1 /*- 2 * Copyright 2021 Intel Corp 3 * Copyright 2021 Rubicon Communications, LLC (Netgate) 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <sys/cdefs.h> 8 __FBSDID("$FreeBSD$"); 9 10 #include "igc_api.h" 11 12 static s32 igc_wait_autoneg(struct igc_hw *hw); 13 14 /** 15 * igc_init_phy_ops_generic - Initialize PHY function pointers 16 * @hw: pointer to the HW structure 17 * 18 * Setups up the function pointers to no-op functions 19 **/ 20 void igc_init_phy_ops_generic(struct igc_hw *hw) 21 { 22 struct igc_phy_info *phy = &hw->phy; 23 DEBUGFUNC("igc_init_phy_ops_generic"); 24 25 /* Initialize function pointers */ 26 phy->ops.init_params = igc_null_ops_generic; 27 phy->ops.acquire = igc_null_ops_generic; 28 phy->ops.check_reset_block = igc_null_ops_generic; 29 phy->ops.commit = igc_null_ops_generic; 30 phy->ops.force_speed_duplex = igc_null_ops_generic; 31 phy->ops.get_info = igc_null_ops_generic; 32 phy->ops.set_page = igc_null_set_page; 33 phy->ops.read_reg = igc_null_read_reg; 34 phy->ops.read_reg_locked = igc_null_read_reg; 35 phy->ops.read_reg_page = igc_null_read_reg; 36 phy->ops.release = igc_null_phy_generic; 37 phy->ops.reset = igc_null_ops_generic; 38 phy->ops.set_d0_lplu_state = igc_null_lplu_state; 39 phy->ops.set_d3_lplu_state = igc_null_lplu_state; 40 phy->ops.write_reg = igc_null_write_reg; 41 phy->ops.write_reg_locked = igc_null_write_reg; 42 phy->ops.write_reg_page = igc_null_write_reg; 43 phy->ops.power_up = igc_null_phy_generic; 44 phy->ops.power_down = igc_null_phy_generic; 45 } 46 47 /** 48 * igc_null_set_page - No-op function, return 0 49 * @hw: pointer to the HW structure 50 * @data: dummy variable 51 **/ 52 s32 igc_null_set_page(struct igc_hw IGC_UNUSEDARG *hw, 53 u16 IGC_UNUSEDARG data) 54 { 55 DEBUGFUNC("igc_null_set_page"); 56 return IGC_SUCCESS; 57 } 58 59 /** 60 * igc_null_read_reg - No-op function, return 0 61 * @hw: pointer to the HW structure 62 * @offset: dummy variable 63 * @data: dummy variable 64 **/ 65 s32 igc_null_read_reg(struct igc_hw IGC_UNUSEDARG *hw, 66 u32 IGC_UNUSEDARG offset, u16 IGC_UNUSEDARG *data) 67 { 68 DEBUGFUNC("igc_null_read_reg"); 69 return IGC_SUCCESS; 70 } 71 72 /** 73 * igc_null_phy_generic - No-op function, return void 74 * @hw: pointer to the HW structure 75 **/ 76 void igc_null_phy_generic(struct igc_hw IGC_UNUSEDARG *hw) 77 { 78 DEBUGFUNC("igc_null_phy_generic"); 79 return; 80 } 81 82 /** 83 * igc_null_lplu_state - No-op function, return 0 84 * @hw: pointer to the HW structure 85 * @active: dummy variable 86 **/ 87 s32 igc_null_lplu_state(struct igc_hw IGC_UNUSEDARG *hw, 88 bool IGC_UNUSEDARG active) 89 { 90 DEBUGFUNC("igc_null_lplu_state"); 91 return IGC_SUCCESS; 92 } 93 94 /** 95 * igc_null_write_reg - No-op function, return 0 96 * @hw: pointer to the HW structure 97 * @offset: dummy variable 98 * @data: dummy variable 99 **/ 100 s32 igc_null_write_reg(struct igc_hw IGC_UNUSEDARG *hw, 101 u32 IGC_UNUSEDARG offset, u16 IGC_UNUSEDARG data) 102 { 103 DEBUGFUNC("igc_null_write_reg"); 104 return IGC_SUCCESS; 105 } 106 107 /** 108 * igc_check_reset_block_generic - Check if PHY reset is blocked 109 * @hw: pointer to the HW structure 110 * 111 * Read the PHY management control register and check whether a PHY reset 112 * is blocked. If a reset is not blocked return IGC_SUCCESS, otherwise 113 * return IGC_BLK_PHY_RESET (12). 114 **/ 115 s32 igc_check_reset_block_generic(struct igc_hw *hw) 116 { 117 u32 manc; 118 119 DEBUGFUNC("igc_check_reset_block"); 120 121 manc = IGC_READ_REG(hw, IGC_MANC); 122 123 return (manc & IGC_MANC_BLK_PHY_RST_ON_IDE) ? 124 IGC_BLK_PHY_RESET : IGC_SUCCESS; 125 } 126 127 /** 128 * igc_get_phy_id - Retrieve the PHY ID and revision 129 * @hw: pointer to the HW structure 130 * 131 * Reads the PHY registers and stores the PHY ID and possibly the PHY 132 * revision in the hardware structure. 133 **/ 134 s32 igc_get_phy_id(struct igc_hw *hw) 135 { 136 struct igc_phy_info *phy = &hw->phy; 137 s32 ret_val = IGC_SUCCESS; 138 u16 phy_id; 139 140 DEBUGFUNC("igc_get_phy_id"); 141 142 if (!phy->ops.read_reg) 143 return IGC_SUCCESS; 144 145 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 146 if (ret_val) 147 return ret_val; 148 149 phy->id = (u32)(phy_id << 16); 150 usec_delay(20); 151 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 152 if (ret_val) 153 return ret_val; 154 155 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 156 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 157 158 159 return IGC_SUCCESS; 160 } 161 162 /** 163 * igc_read_phy_reg_mdic - Read MDI control register 164 * @hw: pointer to the HW structure 165 * @offset: register offset to be read 166 * @data: pointer to the read data 167 * 168 * Reads the MDI control register in the PHY at offset and stores the 169 * information read to data. 170 **/ 171 s32 igc_read_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 *data) 172 { 173 struct igc_phy_info *phy = &hw->phy; 174 u32 i, mdic = 0; 175 176 DEBUGFUNC("igc_read_phy_reg_mdic"); 177 178 if (offset > MAX_PHY_REG_ADDRESS) { 179 DEBUGOUT1("PHY Address %d is out of range\n", offset); 180 return -IGC_ERR_PARAM; 181 } 182 183 /* Set up Op-code, Phy Address, and register offset in the MDI 184 * Control register. The MAC will take care of interfacing with the 185 * PHY to retrieve the desired data. 186 */ 187 mdic = ((offset << IGC_MDIC_REG_SHIFT) | 188 (phy->addr << IGC_MDIC_PHY_SHIFT) | 189 (IGC_MDIC_OP_READ)); 190 191 IGC_WRITE_REG(hw, IGC_MDIC, mdic); 192 193 /* Poll the ready bit to see if the MDI read completed 194 * Increasing the time out as testing showed failures with 195 * the lower time out 196 */ 197 for (i = 0; i < (IGC_GEN_POLL_TIMEOUT * 3); i++) { 198 usec_delay_irq(50); 199 mdic = IGC_READ_REG(hw, IGC_MDIC); 200 if (mdic & IGC_MDIC_READY) 201 break; 202 } 203 if (!(mdic & IGC_MDIC_READY)) { 204 DEBUGOUT("MDI Read did not complete\n"); 205 return -IGC_ERR_PHY; 206 } 207 if (mdic & IGC_MDIC_ERROR) { 208 DEBUGOUT("MDI Error\n"); 209 return -IGC_ERR_PHY; 210 } 211 if (((mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT) != offset) { 212 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n", 213 offset, 214 (mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT); 215 return -IGC_ERR_PHY; 216 } 217 *data = (u16) mdic; 218 219 return IGC_SUCCESS; 220 } 221 222 /** 223 * igc_write_phy_reg_mdic - Write MDI control register 224 * @hw: pointer to the HW structure 225 * @offset: register offset to write to 226 * @data: data to write to register at offset 227 * 228 * Writes data to MDI control register in the PHY at offset. 229 **/ 230 s32 igc_write_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 data) 231 { 232 struct igc_phy_info *phy = &hw->phy; 233 u32 i, mdic = 0; 234 235 DEBUGFUNC("igc_write_phy_reg_mdic"); 236 237 if (offset > MAX_PHY_REG_ADDRESS) { 238 DEBUGOUT1("PHY Address %d is out of range\n", offset); 239 return -IGC_ERR_PARAM; 240 } 241 242 /* Set up Op-code, Phy Address, and register offset in the MDI 243 * Control register. The MAC will take care of interfacing with the 244 * PHY to retrieve the desired data. 245 */ 246 mdic = (((u32)data) | 247 (offset << IGC_MDIC_REG_SHIFT) | 248 (phy->addr << IGC_MDIC_PHY_SHIFT) | 249 (IGC_MDIC_OP_WRITE)); 250 251 IGC_WRITE_REG(hw, IGC_MDIC, mdic); 252 253 /* Poll the ready bit to see if the MDI read completed 254 * Increasing the time out as testing showed failures with 255 * the lower time out 256 */ 257 for (i = 0; i < (IGC_GEN_POLL_TIMEOUT * 3); i++) { 258 usec_delay_irq(50); 259 mdic = IGC_READ_REG(hw, IGC_MDIC); 260 if (mdic & IGC_MDIC_READY) 261 break; 262 } 263 if (!(mdic & IGC_MDIC_READY)) { 264 DEBUGOUT("MDI Write did not complete\n"); 265 return -IGC_ERR_PHY; 266 } 267 if (mdic & IGC_MDIC_ERROR) { 268 DEBUGOUT("MDI Error\n"); 269 return -IGC_ERR_PHY; 270 } 271 if (((mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT) != offset) { 272 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n", 273 offset, 274 (mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT); 275 return -IGC_ERR_PHY; 276 } 277 278 return IGC_SUCCESS; 279 } 280 281 /** 282 * igc_phy_setup_autoneg - Configure PHY for auto-negotiation 283 * @hw: pointer to the HW structure 284 * 285 * Reads the MII auto-neg advertisement register and/or the 1000T control 286 * register and if the PHY is already setup for auto-negotiation, then 287 * return successful. Otherwise, setup advertisement and flow control to 288 * the appropriate values for the wanted auto-negotiation. 289 **/ 290 static s32 igc_phy_setup_autoneg(struct igc_hw *hw) 291 { 292 struct igc_phy_info *phy = &hw->phy; 293 s32 ret_val; 294 u16 mii_autoneg_adv_reg; 295 u16 mii_1000t_ctrl_reg = 0; 296 u16 aneg_multigbt_an_ctrl = 0; 297 298 DEBUGFUNC("igc_phy_setup_autoneg"); 299 300 phy->autoneg_advertised &= phy->autoneg_mask; 301 302 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 303 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 304 if (ret_val) 305 return ret_val; 306 307 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 308 /* Read the MII 1000Base-T Control Register (Address 9). */ 309 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 310 &mii_1000t_ctrl_reg); 311 if (ret_val) 312 return ret_val; 313 } 314 315 if ((phy->autoneg_mask & ADVERTISE_2500_FULL) && 316 hw->phy.id == I225_I_PHY_ID) { 317 /* Read the MULTI GBT AN Control Register - reg 7.32 */ 318 ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK << 319 MMD_DEVADDR_SHIFT) | 320 ANEG_MULTIGBT_AN_CTRL, 321 &aneg_multigbt_an_ctrl); 322 323 if (ret_val) 324 return ret_val; 325 } 326 327 /* Need to parse both autoneg_advertised and fc and set up 328 * the appropriate PHY registers. First we will parse for 329 * autoneg_advertised software override. Since we can advertise 330 * a plethora of combinations, we need to check each bit 331 * individually. 332 */ 333 334 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 335 * Advertisement Register (Address 4) and the 1000 mb speed bits in 336 * the 1000Base-T Control Register (Address 9). 337 */ 338 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 339 NWAY_AR_100TX_HD_CAPS | 340 NWAY_AR_10T_FD_CAPS | 341 NWAY_AR_10T_HD_CAPS); 342 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 343 344 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 345 346 /* Do we want to advertise 10 Mb Half Duplex? */ 347 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 348 DEBUGOUT("Advertise 10mb Half duplex\n"); 349 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 350 } 351 352 /* Do we want to advertise 10 Mb Full Duplex? */ 353 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 354 DEBUGOUT("Advertise 10mb Full duplex\n"); 355 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 356 } 357 358 /* Do we want to advertise 100 Mb Half Duplex? */ 359 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 360 DEBUGOUT("Advertise 100mb Half duplex\n"); 361 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 362 } 363 364 /* Do we want to advertise 100 Mb Full Duplex? */ 365 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 366 DEBUGOUT("Advertise 100mb Full duplex\n"); 367 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 368 } 369 370 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 371 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 372 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 373 374 /* Do we want to advertise 1000 Mb Full Duplex? */ 375 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 376 DEBUGOUT("Advertise 1000mb Full duplex\n"); 377 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 378 } 379 380 /* We do not allow the Phy to advertise 2500 Mb Half Duplex */ 381 if (phy->autoneg_advertised & ADVERTISE_2500_HALF) 382 DEBUGOUT("Advertise 2500mb Half duplex request denied!\n"); 383 384 /* Do we want to advertise 2500 Mb Full Duplex? */ 385 if (phy->autoneg_advertised & ADVERTISE_2500_FULL) { 386 DEBUGOUT("Advertise 2500mb Full duplex\n"); 387 aneg_multigbt_an_ctrl |= CR_2500T_FD_CAPS; 388 } else { 389 aneg_multigbt_an_ctrl &= ~CR_2500T_FD_CAPS; 390 } 391 392 /* Check for a software override of the flow control settings, and 393 * setup the PHY advertisement registers accordingly. If 394 * auto-negotiation is enabled, then software will have to set the 395 * "PAUSE" bits to the correct value in the Auto-Negotiation 396 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 397 * negotiation. 398 * 399 * The possible values of the "fc" parameter are: 400 * 0: Flow control is completely disabled 401 * 1: Rx flow control is enabled (we can receive pause frames 402 * but not send pause frames). 403 * 2: Tx flow control is enabled (we can send pause frames 404 * but we do not support receiving pause frames). 405 * 3: Both Rx and Tx flow control (symmetric) are enabled. 406 * other: No software override. The flow control configuration 407 * in the EEPROM is used. 408 */ 409 switch (hw->fc.current_mode) { 410 case igc_fc_none: 411 /* Flow control (Rx & Tx) is completely disabled by a 412 * software over-ride. 413 */ 414 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 415 break; 416 case igc_fc_rx_pause: 417 /* Rx Flow control is enabled, and Tx Flow control is 418 * disabled, by a software over-ride. 419 * 420 * Since there really isn't a way to advertise that we are 421 * capable of Rx Pause ONLY, we will advertise that we 422 * support both symmetric and asymmetric Rx PAUSE. Later 423 * (in igc_config_fc_after_link_up) we will disable the 424 * hw's ability to send PAUSE frames. 425 */ 426 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 427 break; 428 case igc_fc_tx_pause: 429 /* Tx Flow control is enabled, and Rx Flow control is 430 * disabled, by a software over-ride. 431 */ 432 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 433 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 434 break; 435 case igc_fc_full: 436 /* Flow control (both Rx and Tx) is enabled by a software 437 * over-ride. 438 */ 439 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 440 break; 441 default: 442 DEBUGOUT("Flow control param set incorrectly\n"); 443 return -IGC_ERR_CONFIG; 444 } 445 446 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 447 if (ret_val) 448 return ret_val; 449 450 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 451 452 if (phy->autoneg_mask & ADVERTISE_1000_FULL) 453 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, 454 mii_1000t_ctrl_reg); 455 456 if ((phy->autoneg_mask & ADVERTISE_2500_FULL) && 457 hw->phy.id == I225_I_PHY_ID) 458 ret_val = phy->ops.write_reg(hw, 459 (STANDARD_AN_REG_MASK << 460 MMD_DEVADDR_SHIFT) | 461 ANEG_MULTIGBT_AN_CTRL, 462 aneg_multigbt_an_ctrl); 463 464 return ret_val; 465 } 466 467 /** 468 * igc_copper_link_autoneg - Setup/Enable autoneg for copper link 469 * @hw: pointer to the HW structure 470 * 471 * Performs initial bounds checking on autoneg advertisement parameter, then 472 * configure to advertise the full capability. Setup the PHY to autoneg 473 * and restart the negotiation process between the link partner. If 474 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 475 **/ 476 static s32 igc_copper_link_autoneg(struct igc_hw *hw) 477 { 478 struct igc_phy_info *phy = &hw->phy; 479 s32 ret_val; 480 u16 phy_ctrl; 481 482 DEBUGFUNC("igc_copper_link_autoneg"); 483 484 /* Perform some bounds checking on the autoneg advertisement 485 * parameter. 486 */ 487 phy->autoneg_advertised &= phy->autoneg_mask; 488 489 /* If autoneg_advertised is zero, we assume it was not defaulted 490 * by the calling code so we set to advertise full capability. 491 */ 492 if (!phy->autoneg_advertised) 493 phy->autoneg_advertised = phy->autoneg_mask; 494 495 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 496 ret_val = igc_phy_setup_autoneg(hw); 497 if (ret_val) { 498 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 499 return ret_val; 500 } 501 DEBUGOUT("Restarting Auto-Neg\n"); 502 503 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 504 * the Auto Neg Restart bit in the PHY control register. 505 */ 506 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 507 if (ret_val) 508 return ret_val; 509 510 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 511 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 512 if (ret_val) 513 return ret_val; 514 515 /* Does the user want to wait for Auto-Neg to complete here, or 516 * check at a later time (for example, callback routine). 517 */ 518 if (phy->autoneg_wait_to_complete) { 519 ret_val = igc_wait_autoneg(hw); 520 if (ret_val) { 521 DEBUGOUT("Error while waiting for autoneg to complete\n"); 522 return ret_val; 523 } 524 } 525 526 hw->mac.get_link_status = true; 527 528 return ret_val; 529 } 530 531 /** 532 * igc_setup_copper_link_generic - Configure copper link settings 533 * @hw: pointer to the HW structure 534 * 535 * Calls the appropriate function to configure the link for auto-neg or forced 536 * speed and duplex. Then we check for link, once link is established calls 537 * to configure collision distance and flow control are called. If link is 538 * not established, we return -IGC_ERR_PHY (-2). 539 **/ 540 s32 igc_setup_copper_link_generic(struct igc_hw *hw) 541 { 542 s32 ret_val; 543 bool link; 544 545 DEBUGFUNC("igc_setup_copper_link_generic"); 546 547 if (hw->mac.autoneg) { 548 /* Setup autoneg and flow control advertisement and perform 549 * autonegotiation. 550 */ 551 ret_val = igc_copper_link_autoneg(hw); 552 if (ret_val) 553 return ret_val; 554 } else { 555 /* PHY will be set to 10H, 10F, 100H or 100F 556 * depending on user settings. 557 */ 558 DEBUGOUT("Forcing Speed and Duplex\n"); 559 ret_val = hw->phy.ops.force_speed_duplex(hw); 560 if (ret_val) { 561 DEBUGOUT("Error Forcing Speed and Duplex\n"); 562 return ret_val; 563 } 564 } 565 566 /* Check link status. Wait up to 100 microseconds for link to become 567 * valid. 568 */ 569 ret_val = igc_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, 570 &link); 571 if (ret_val) 572 return ret_val; 573 574 if (link) { 575 DEBUGOUT("Valid link established!!!\n"); 576 hw->mac.ops.config_collision_dist(hw); 577 ret_val = igc_config_fc_after_link_up_generic(hw); 578 } else { 579 DEBUGOUT("Unable to establish link!!!\n"); 580 } 581 582 return ret_val; 583 } 584 585 /** 586 * igc_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 587 * @hw: pointer to the HW structure 588 * @phy_ctrl: pointer to current value of PHY_CONTROL 589 * 590 * Forces speed and duplex on the PHY by doing the following: disable flow 591 * control, force speed/duplex on the MAC, disable auto speed detection, 592 * disable auto-negotiation, configure duplex, configure speed, configure 593 * the collision distance, write configuration to CTRL register. The 594 * caller must write to the PHY_CONTROL register for these settings to 595 * take affect. 596 **/ 597 void igc_phy_force_speed_duplex_setup(struct igc_hw *hw, u16 *phy_ctrl) 598 { 599 struct igc_mac_info *mac = &hw->mac; 600 u32 ctrl; 601 602 DEBUGFUNC("igc_phy_force_speed_duplex_setup"); 603 604 /* Turn off flow control when forcing speed/duplex */ 605 hw->fc.current_mode = igc_fc_none; 606 607 /* Force speed/duplex on the mac */ 608 ctrl = IGC_READ_REG(hw, IGC_CTRL); 609 ctrl |= (IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX); 610 ctrl &= ~IGC_CTRL_SPD_SEL; 611 612 /* Disable Auto Speed Detection */ 613 ctrl &= ~IGC_CTRL_ASDE; 614 615 /* Disable autoneg on the phy */ 616 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 617 618 /* Forcing Full or Half Duplex? */ 619 if (mac->forced_speed_duplex & IGC_ALL_HALF_DUPLEX) { 620 ctrl &= ~IGC_CTRL_FD; 621 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 622 DEBUGOUT("Half Duplex\n"); 623 } else { 624 ctrl |= IGC_CTRL_FD; 625 *phy_ctrl |= MII_CR_FULL_DUPLEX; 626 DEBUGOUT("Full Duplex\n"); 627 } 628 629 /* Forcing 10mb or 100mb? */ 630 if (mac->forced_speed_duplex & IGC_ALL_100_SPEED) { 631 ctrl |= IGC_CTRL_SPD_100; 632 *phy_ctrl |= MII_CR_SPEED_100; 633 *phy_ctrl &= ~MII_CR_SPEED_1000; 634 DEBUGOUT("Forcing 100mb\n"); 635 } else { 636 ctrl &= ~(IGC_CTRL_SPD_1000 | IGC_CTRL_SPD_100); 637 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 638 DEBUGOUT("Forcing 10mb\n"); 639 } 640 641 hw->mac.ops.config_collision_dist(hw); 642 643 IGC_WRITE_REG(hw, IGC_CTRL, ctrl); 644 } 645 646 /** 647 * igc_set_d3_lplu_state_generic - Sets low power link up state for D3 648 * @hw: pointer to the HW structure 649 * @active: boolean used to enable/disable lplu 650 * 651 * Success returns 0, Failure returns 1 652 * 653 * The low power link up (lplu) state is set to the power management level D3 654 * and SmartSpeed is disabled when active is true, else clear lplu for D3 655 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 656 * is used during Dx states where the power conservation is most important. 657 * During driver activity, SmartSpeed should be enabled so performance is 658 * maintained. 659 **/ 660 s32 igc_set_d3_lplu_state_generic(struct igc_hw *hw, bool active) 661 { 662 struct igc_phy_info *phy = &hw->phy; 663 s32 ret_val; 664 u16 data; 665 666 DEBUGFUNC("igc_set_d3_lplu_state_generic"); 667 668 if (!hw->phy.ops.read_reg) 669 return IGC_SUCCESS; 670 671 ret_val = phy->ops.read_reg(hw, IGP02IGC_PHY_POWER_MGMT, &data); 672 if (ret_val) 673 return ret_val; 674 675 if (!active) { 676 data &= ~IGP02IGC_PM_D3_LPLU; 677 ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT, 678 data); 679 if (ret_val) 680 return ret_val; 681 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 682 * during Dx states where the power conservation is most 683 * important. During driver activity we should enable 684 * SmartSpeed, so performance is maintained. 685 */ 686 if (phy->smart_speed == igc_smart_speed_on) { 687 ret_val = phy->ops.read_reg(hw, 688 IGP01IGC_PHY_PORT_CONFIG, 689 &data); 690 if (ret_val) 691 return ret_val; 692 693 data |= IGP01IGC_PSCFR_SMART_SPEED; 694 ret_val = phy->ops.write_reg(hw, 695 IGP01IGC_PHY_PORT_CONFIG, 696 data); 697 if (ret_val) 698 return ret_val; 699 } else if (phy->smart_speed == igc_smart_speed_off) { 700 ret_val = phy->ops.read_reg(hw, 701 IGP01IGC_PHY_PORT_CONFIG, 702 &data); 703 if (ret_val) 704 return ret_val; 705 706 data &= ~IGP01IGC_PSCFR_SMART_SPEED; 707 ret_val = phy->ops.write_reg(hw, 708 IGP01IGC_PHY_PORT_CONFIG, 709 data); 710 if (ret_val) 711 return ret_val; 712 } 713 } else if ((phy->autoneg_advertised == IGC_ALL_SPEED_DUPLEX) || 714 (phy->autoneg_advertised == IGC_ALL_NOT_GIG) || 715 (phy->autoneg_advertised == IGC_ALL_10_SPEED)) { 716 data |= IGP02IGC_PM_D3_LPLU; 717 ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT, 718 data); 719 if (ret_val) 720 return ret_val; 721 722 /* When LPLU is enabled, we should disable SmartSpeed */ 723 ret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_CONFIG, 724 &data); 725 if (ret_val) 726 return ret_val; 727 728 data &= ~IGP01IGC_PSCFR_SMART_SPEED; 729 ret_val = phy->ops.write_reg(hw, IGP01IGC_PHY_PORT_CONFIG, 730 data); 731 } 732 733 return ret_val; 734 } 735 736 /** 737 * igc_check_downshift_generic - Checks whether a downshift in speed occurred 738 * @hw: pointer to the HW structure 739 * 740 * Success returns 0, Failure returns 1 741 * 742 * A downshift is detected by querying the PHY link health. 743 **/ 744 s32 igc_check_downshift_generic(struct igc_hw *hw) 745 { 746 struct igc_phy_info *phy = &hw->phy; 747 s32 ret_val; 748 749 DEBUGFUNC("igc_check_downshift_generic"); 750 751 switch (phy->type) { 752 case igc_phy_i225: 753 default: 754 /* speed downshift not supported */ 755 phy->speed_downgraded = false; 756 return IGC_SUCCESS; 757 } 758 759 return ret_val; 760 } 761 762 /** 763 * igc_wait_autoneg - Wait for auto-neg completion 764 * @hw: pointer to the HW structure 765 * 766 * Waits for auto-negotiation to complete or for the auto-negotiation time 767 * limit to expire, which ever happens first. 768 **/ 769 static s32 igc_wait_autoneg(struct igc_hw *hw) 770 { 771 s32 ret_val = IGC_SUCCESS; 772 u16 i, phy_status; 773 774 DEBUGFUNC("igc_wait_autoneg"); 775 776 if (!hw->phy.ops.read_reg) 777 return IGC_SUCCESS; 778 779 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 780 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 781 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 782 if (ret_val) 783 break; 784 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 785 if (ret_val) 786 break; 787 if (phy_status & MII_SR_AUTONEG_COMPLETE) 788 break; 789 msec_delay(100); 790 } 791 792 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 793 * has completed. 794 */ 795 return ret_val; 796 } 797 798 /** 799 * igc_phy_has_link_generic - Polls PHY for link 800 * @hw: pointer to the HW structure 801 * @iterations: number of times to poll for link 802 * @usec_interval: delay between polling attempts 803 * @success: pointer to whether polling was successful or not 804 * 805 * Polls the PHY status register for link, 'iterations' number of times. 806 **/ 807 s32 igc_phy_has_link_generic(struct igc_hw *hw, u32 iterations, 808 u32 usec_interval, bool *success) 809 { 810 s32 ret_val = IGC_SUCCESS; 811 u16 i, phy_status; 812 813 DEBUGFUNC("igc_phy_has_link_generic"); 814 815 if (!hw->phy.ops.read_reg) 816 return IGC_SUCCESS; 817 818 for (i = 0; i < iterations; i++) { 819 /* Some PHYs require the PHY_STATUS register to be read 820 * twice due to the link bit being sticky. No harm doing 821 * it across the board. 822 */ 823 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 824 if (ret_val) { 825 /* If the first read fails, another entity may have 826 * ownership of the resources, wait and try again to 827 * see if they have relinquished the resources yet. 828 */ 829 if (usec_interval >= 1000) 830 msec_delay(usec_interval/1000); 831 else 832 usec_delay(usec_interval); 833 } 834 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 835 if (ret_val) 836 break; 837 if (phy_status & MII_SR_LINK_STATUS) 838 break; 839 if (usec_interval >= 1000) 840 msec_delay(usec_interval/1000); 841 else 842 usec_delay(usec_interval); 843 } 844 845 *success = (i < iterations); 846 847 return ret_val; 848 } 849 850 /** 851 * igc_phy_sw_reset_generic - PHY software reset 852 * @hw: pointer to the HW structure 853 * 854 * Does a software reset of the PHY by reading the PHY control register and 855 * setting/write the control register reset bit to the PHY. 856 **/ 857 s32 igc_phy_sw_reset_generic(struct igc_hw *hw) 858 { 859 s32 ret_val; 860 u16 phy_ctrl; 861 862 DEBUGFUNC("igc_phy_sw_reset_generic"); 863 864 if (!hw->phy.ops.read_reg) 865 return IGC_SUCCESS; 866 867 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 868 if (ret_val) 869 return ret_val; 870 871 phy_ctrl |= MII_CR_RESET; 872 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 873 if (ret_val) 874 return ret_val; 875 876 usec_delay(1); 877 878 return ret_val; 879 } 880 881 /** 882 * igc_phy_hw_reset_generic - PHY hardware reset 883 * @hw: pointer to the HW structure 884 * 885 * Verify the reset block is not blocking us from resetting. Acquire 886 * semaphore (if necessary) and read/set/write the device control reset 887 * bit in the PHY. Wait the appropriate delay time for the device to 888 * reset and release the semaphore (if necessary). 889 **/ 890 s32 igc_phy_hw_reset_generic(struct igc_hw *hw) 891 { 892 struct igc_phy_info *phy = &hw->phy; 893 s32 ret_val; 894 u32 ctrl, timeout = 10000, phpm = 0; 895 896 DEBUGFUNC("igc_phy_hw_reset_generic"); 897 898 if (phy->ops.check_reset_block) { 899 ret_val = phy->ops.check_reset_block(hw); 900 if (ret_val) 901 return IGC_SUCCESS; 902 } 903 904 ret_val = phy->ops.acquire(hw); 905 if (ret_val) 906 return ret_val; 907 908 phpm = IGC_READ_REG(hw, IGC_I225_PHPM); 909 910 ctrl = IGC_READ_REG(hw, IGC_CTRL); 911 IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_PHY_RST); 912 IGC_WRITE_FLUSH(hw); 913 914 usec_delay(phy->reset_delay_us); 915 916 IGC_WRITE_REG(hw, IGC_CTRL, ctrl); 917 IGC_WRITE_FLUSH(hw); 918 919 usec_delay(150); 920 921 do { 922 phpm = IGC_READ_REG(hw, IGC_I225_PHPM); 923 timeout--; 924 usec_delay(1); 925 } while (!(phpm & IGC_I225_PHPM_RST_COMPL) && timeout); 926 927 if (!timeout) 928 DEBUGOUT("Timeout expired after a phy reset\n"); 929 930 phy->ops.release(hw); 931 932 return ret_val; 933 } 934 935 /** 936 * igc_power_up_phy_copper - Restore copper link in case of PHY power down 937 * @hw: pointer to the HW structure 938 * 939 * In the case of a PHY power down to save power, or to turn off link during a 940 * driver unload, or wake on lan is not enabled, restore the link to previous 941 * settings. 942 **/ 943 void igc_power_up_phy_copper(struct igc_hw *hw) 944 { 945 u16 mii_reg = 0; 946 947 /* The PHY will retain its settings across a power down/up cycle */ 948 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 949 mii_reg &= ~MII_CR_POWER_DOWN; 950 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 951 usec_delay(300); 952 } 953 954 /** 955 * igc_power_down_phy_copper - Restore copper link in case of PHY power down 956 * @hw: pointer to the HW structure 957 * 958 * In the case of a PHY power down to save power, or to turn off link during a 959 * driver unload, or wake on lan is not enabled, restore the link to previous 960 * settings. 961 **/ 962 void igc_power_down_phy_copper(struct igc_hw *hw) 963 { 964 u16 mii_reg = 0; 965 966 /* The PHY will retain its settings across a power down/up cycle */ 967 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 968 mii_reg |= MII_CR_POWER_DOWN; 969 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 970 msec_delay(1); 971 } 972 /** 973 * igc_write_phy_reg_gpy - Write GPY PHY register 974 * @hw: pointer to the HW structure 975 * @offset: register offset to write to 976 * @data: data to write at register offset 977 * 978 * Acquires semaphore, if necessary, then writes the data to PHY register 979 * at the offset. Release any acquired semaphores before exiting. 980 **/ 981 s32 igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data) 982 { 983 s32 ret_val; 984 u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT; 985 986 DEBUGFUNC("igc_write_phy_reg_gpy"); 987 988 offset = offset & GPY_REG_MASK; 989 990 if (!dev_addr) { 991 ret_val = hw->phy.ops.acquire(hw); 992 if (ret_val) 993 return ret_val; 994 ret_val = igc_write_phy_reg_mdic(hw, offset, data); 995 if (ret_val) 996 return ret_val; 997 hw->phy.ops.release(hw); 998 } else { 999 ret_val = igc_write_xmdio_reg(hw, (u16)offset, dev_addr, 1000 data); 1001 } 1002 return ret_val; 1003 } 1004 1005 /** 1006 * igc_read_phy_reg_gpy - Read GPY PHY register 1007 * @hw: pointer to the HW structure 1008 * @offset: lower half is register offset to read to 1009 * upper half is MMD to use. 1010 * @data: data to read at register offset 1011 * 1012 * Acquires semaphore, if necessary, then reads the data in the PHY register 1013 * at the offset. Release any acquired semaphores before exiting. 1014 **/ 1015 s32 igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data) 1016 { 1017 s32 ret_val; 1018 u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT; 1019 1020 DEBUGFUNC("igc_read_phy_reg_gpy"); 1021 1022 offset = offset & GPY_REG_MASK; 1023 1024 if (!dev_addr) { 1025 ret_val = hw->phy.ops.acquire(hw); 1026 if (ret_val) 1027 return ret_val; 1028 ret_val = igc_read_phy_reg_mdic(hw, offset, data); 1029 if (ret_val) 1030 return ret_val; 1031 hw->phy.ops.release(hw); 1032 } else { 1033 ret_val = igc_read_xmdio_reg(hw, (u16)offset, dev_addr, 1034 data); 1035 } 1036 return ret_val; 1037 } 1038 1039 1040 /** 1041 * __igc_access_xmdio_reg - Read/write XMDIO register 1042 * @hw: pointer to the HW structure 1043 * @address: XMDIO address to program 1044 * @dev_addr: device address to program 1045 * @data: pointer to value to read/write from/to the XMDIO address 1046 * @read: boolean flag to indicate read or write 1047 **/ 1048 static s32 __igc_access_xmdio_reg(struct igc_hw *hw, u16 address, 1049 u8 dev_addr, u16 *data, bool read) 1050 { 1051 s32 ret_val; 1052 1053 DEBUGFUNC("__igc_access_xmdio_reg"); 1054 1055 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr); 1056 if (ret_val) 1057 return ret_val; 1058 1059 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address); 1060 if (ret_val) 1061 return ret_val; 1062 1063 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA | 1064 dev_addr); 1065 if (ret_val) 1066 return ret_val; 1067 1068 if (read) 1069 ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data); 1070 else 1071 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data); 1072 if (ret_val) 1073 return ret_val; 1074 1075 /* Recalibrate the device back to 0 */ 1076 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0); 1077 if (ret_val) 1078 return ret_val; 1079 1080 return ret_val; 1081 } 1082 1083 /** 1084 * igc_read_xmdio_reg - Read XMDIO register 1085 * @hw: pointer to the HW structure 1086 * @addr: XMDIO address to program 1087 * @dev_addr: device address to program 1088 * @data: value to be read from the EMI address 1089 **/ 1090 s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr, u16 *data) 1091 { 1092 DEBUGFUNC("igc_read_xmdio_reg"); 1093 1094 return __igc_access_xmdio_reg(hw, addr, dev_addr, data, true); 1095 } 1096 1097 /** 1098 * igc_write_xmdio_reg - Write XMDIO register 1099 * @hw: pointer to the HW structure 1100 * @addr: XMDIO address to program 1101 * @dev_addr: device address to program 1102 * @data: value to be written to the XMDIO address 1103 **/ 1104 s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr, u16 data) 1105 { 1106 DEBUGFUNC("igc_write_xmdio_reg"); 1107 1108 return __igc_access_xmdio_reg(hw, addr, dev_addr, &data, false); 1109 } 1110