1 /*- 2 * Copyright 2021 Intel Corp 3 * Copyright 2021 Rubicon Communications, LLC (Netgate) 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <sys/cdefs.h> 8 #include "igc_api.h" 9 10 static void igc_config_collision_dist_generic(struct igc_hw *hw); 11 12 /** 13 * igc_init_mac_ops_generic - Initialize MAC function pointers 14 * @hw: pointer to the HW structure 15 * 16 * Setups up the function pointers to no-op functions 17 **/ 18 void igc_init_mac_ops_generic(struct igc_hw *hw) 19 { 20 struct igc_mac_info *mac = &hw->mac; 21 DEBUGFUNC("igc_init_mac_ops_generic"); 22 23 /* General Setup */ 24 mac->ops.init_params = igc_null_ops_generic; 25 mac->ops.config_collision_dist = igc_config_collision_dist_generic; 26 mac->ops.rar_set = igc_rar_set_generic; 27 } 28 29 /** 30 * igc_null_ops_generic - No-op function, returns 0 31 * @hw: pointer to the HW structure 32 **/ 33 s32 igc_null_ops_generic(struct igc_hw IGC_UNUSEDARG *hw) 34 { 35 DEBUGFUNC("igc_null_ops_generic"); 36 return IGC_SUCCESS; 37 } 38 39 /** 40 * igc_null_mac_generic - No-op function, return void 41 * @hw: pointer to the HW structure 42 **/ 43 void igc_null_mac_generic(struct igc_hw IGC_UNUSEDARG *hw) 44 { 45 DEBUGFUNC("igc_null_mac_generic"); 46 return; 47 } 48 49 /** 50 * igc_null_link_info - No-op function, return 0 51 * @hw: pointer to the HW structure 52 * @s: dummy variable 53 * @d: dummy variable 54 **/ 55 s32 igc_null_link_info(struct igc_hw IGC_UNUSEDARG *hw, 56 u16 IGC_UNUSEDARG *s, u16 IGC_UNUSEDARG *d) 57 { 58 DEBUGFUNC("igc_null_link_info"); 59 return IGC_SUCCESS; 60 } 61 62 /** 63 * igc_null_mng_mode - No-op function, return false 64 * @hw: pointer to the HW structure 65 **/ 66 bool igc_null_mng_mode(struct igc_hw IGC_UNUSEDARG *hw) 67 { 68 DEBUGFUNC("igc_null_mng_mode"); 69 return false; 70 } 71 72 /** 73 * igc_enable_mng_pass_thru - Check if management passthrough is needed 74 * @hw: pointer to the HW structure 75 * 76 * Verify that the I225/I226 management engine needs the external link. 77 **/ 78 bool 79 igc_enable_mng_pass_thru(struct igc_hw *hw) 80 { 81 u32 manc; 82 83 DEBUGFUNC("igc_enable_mng_pass_thru"); 84 85 if (!hw->mac.asf_firmware_present) 86 return (false); 87 88 manc = IGC_READ_REG(hw, IGC_MANC); 89 return ((manc & IGC_MANC_RCV_TCO_EN) != 0); 90 } 91 92 /** 93 * igc_null_update_mc - No-op function, return void 94 * @hw: pointer to the HW structure 95 * @h: dummy variable 96 * @a: dummy variable 97 **/ 98 void igc_null_update_mc(struct igc_hw IGC_UNUSEDARG *hw, 99 u8 IGC_UNUSEDARG *h, u32 IGC_UNUSEDARG a) 100 { 101 DEBUGFUNC("igc_null_update_mc"); 102 return; 103 } 104 105 /** 106 * igc_null_write_vfta - No-op function, return void 107 * @hw: pointer to the HW structure 108 * @a: dummy variable 109 * @b: dummy variable 110 **/ 111 void igc_null_write_vfta(struct igc_hw IGC_UNUSEDARG *hw, 112 u32 IGC_UNUSEDARG a, u32 IGC_UNUSEDARG b) 113 { 114 DEBUGFUNC("igc_null_write_vfta"); 115 return; 116 } 117 118 /** 119 * igc_null_rar_set - No-op function, return 0 120 * @hw: pointer to the HW structure 121 * @h: dummy variable 122 * @a: dummy variable 123 **/ 124 int igc_null_rar_set(struct igc_hw IGC_UNUSEDARG *hw, 125 u8 IGC_UNUSEDARG *h, u32 IGC_UNUSEDARG a) 126 { 127 DEBUGFUNC("igc_null_rar_set"); 128 return IGC_SUCCESS; 129 } 130 131 /** 132 * igc_set_lan_id_single_port - Set LAN id for a single port device 133 * @hw: pointer to the HW structure 134 * 135 * Sets the LAN function id to zero for a single port device. 136 **/ 137 void igc_set_lan_id_single_port(struct igc_hw *hw) 138 { 139 struct igc_bus_info *bus = &hw->bus; 140 141 bus->func = 0; 142 } 143 144 /** 145 * igc_clear_vfta_generic - Clear VLAN filter table 146 * @hw: pointer to the HW structure 147 * 148 * Clears the register array which contains the VLAN filter table by 149 * setting all the values to 0. 150 **/ 151 void igc_clear_vfta_generic(struct igc_hw *hw) 152 { 153 u32 offset; 154 155 DEBUGFUNC("igc_clear_vfta_generic"); 156 157 for (offset = 0; offset < IGC_VLAN_FILTER_TBL_SIZE; offset++) { 158 IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, 0); 159 IGC_WRITE_FLUSH(hw); 160 } 161 } 162 163 /** 164 * igc_write_vfta_generic - Write value to VLAN filter table 165 * @hw: pointer to the HW structure 166 * @offset: register offset in VLAN filter table 167 * @value: register value written to VLAN filter table 168 * 169 * Writes value at the given offset in the register array which stores 170 * the VLAN filter table. 171 **/ 172 void igc_write_vfta_generic(struct igc_hw *hw, u32 offset, u32 value) 173 { 174 DEBUGFUNC("igc_write_vfta_generic"); 175 176 IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, value); 177 IGC_WRITE_FLUSH(hw); 178 } 179 180 /** 181 * igc_init_rx_addrs_generic - Initialize receive address's 182 * @hw: pointer to the HW structure 183 * @rar_count: receive address registers 184 * 185 * Setup the receive address registers by setting the base receive address 186 * register to the devices MAC address and clearing all the other receive 187 * address registers to 0. 188 **/ 189 void igc_init_rx_addrs_generic(struct igc_hw *hw, u16 rar_count) 190 { 191 u32 i; 192 u8 mac_addr[ETH_ADDR_LEN] = {0}; 193 194 DEBUGFUNC("igc_init_rx_addrs_generic"); 195 196 /* Setup the receive address */ 197 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 198 199 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 200 201 /* Zero out the other (rar_entry_count - 1) receive addresses */ 202 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 203 for (i = 1; i < rar_count; i++) 204 hw->mac.ops.rar_set(hw, mac_addr, i); 205 } 206 207 /** 208 * igc_check_alt_mac_addr_generic - Check for alternate MAC addr 209 * @hw: pointer to the HW structure 210 * 211 * Checks the nvm for an alternate MAC address. An alternate MAC address 212 * can be setup by pre-boot software and must be treated like a permanent 213 * address and must override the actual permanent MAC address. If an 214 * alternate MAC address is found it is programmed into RAR0, replacing 215 * the permanent address that was installed into RAR0 by the Si on reset. 216 * This function will return SUCCESS unless it encounters an error while 217 * reading the EEPROM. 218 **/ 219 s32 igc_check_alt_mac_addr_generic(struct igc_hw *hw) 220 { 221 u32 i; 222 s32 ret_val; 223 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 224 u8 alt_mac_addr[ETH_ADDR_LEN]; 225 226 DEBUGFUNC("igc_check_alt_mac_addr_generic"); 227 228 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); 229 if (ret_val) 230 return ret_val; 231 232 233 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 234 &nvm_alt_mac_addr_offset); 235 if (ret_val) { 236 DEBUGOUT("NVM Read Error\n"); 237 return ret_val; 238 } 239 240 if ((nvm_alt_mac_addr_offset == 0xFFFF) || 241 (nvm_alt_mac_addr_offset == 0x0000)) 242 /* There is no Alternate MAC Address */ 243 return IGC_SUCCESS; 244 245 if (hw->bus.func == IGC_FUNC_1) 246 nvm_alt_mac_addr_offset += IGC_ALT_MAC_ADDRESS_OFFSET_LAN1; 247 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 248 offset = nvm_alt_mac_addr_offset + (i >> 1); 249 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 250 if (ret_val) { 251 DEBUGOUT("NVM Read Error\n"); 252 return ret_val; 253 } 254 255 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 256 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 257 } 258 259 /* if multicast bit is set, the alternate address will not be used */ 260 if (alt_mac_addr[0] & 0x01) { 261 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 262 return IGC_SUCCESS; 263 } 264 265 /* We have a valid alternate MAC address, and we want to treat it the 266 * same as the normal permanent MAC address stored by the HW into the 267 * RAR. Do this by mapping this address into RAR0. 268 */ 269 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 270 271 return IGC_SUCCESS; 272 } 273 274 /** 275 * igc_rar_set_generic - Set receive address register 276 * @hw: pointer to the HW structure 277 * @addr: pointer to the receive address 278 * @index: receive address array register 279 * 280 * Sets the receive address array register at index to the address passed 281 * in by addr. 282 **/ 283 int igc_rar_set_generic(struct igc_hw *hw, u8 *addr, u32 index) 284 { 285 u32 rar_low, rar_high; 286 287 DEBUGFUNC("igc_rar_set_generic"); 288 289 /* HW expects these in little endian so we reverse the byte order 290 * from network order (big endian) to little endian 291 */ 292 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 293 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 294 295 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 296 297 /* If MAC address zero, no need to set the AV bit */ 298 if (rar_low || rar_high) 299 rar_high |= IGC_RAH_AV; 300 301 /* Some bridges will combine consecutive 32-bit writes into 302 * a single burst write, which will malfunction on some parts. 303 * The flushes avoid this. 304 */ 305 IGC_WRITE_REG(hw, IGC_RAL(index), rar_low); 306 IGC_WRITE_FLUSH(hw); 307 IGC_WRITE_REG(hw, IGC_RAH(index), rar_high); 308 IGC_WRITE_FLUSH(hw); 309 310 return IGC_SUCCESS; 311 } 312 313 /** 314 * igc_hash_mc_addr_generic - Generate a multicast hash value 315 * @hw: pointer to the HW structure 316 * @mc_addr: pointer to a multicast address 317 * 318 * Generates a multicast address hash value which is used to determine 319 * the multicast filter table array address and new table value. 320 **/ 321 u32 igc_hash_mc_addr_generic(struct igc_hw *hw, u8 *mc_addr) 322 { 323 u32 hash_value, hash_mask; 324 u8 bit_shift = 1; 325 326 DEBUGFUNC("igc_hash_mc_addr_generic"); 327 328 /* Register count multiplied by bits per register */ 329 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 330 331 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts 332 * where 0xFF would still fall within the hash mask. 333 */ 334 while (bit_shift < 4 && hash_mask >> bit_shift != 0xFF) 335 bit_shift++; 336 337 /* The portion of the address that is used for the hash table 338 * is determined by the mc_filter_type setting. 339 * The algorithm is such that there is a total of 8 bits of shifting. 340 * The bit_shift for a mc_filter_type of 0 represents the number of 341 * left-shifts where the MSB of mc_addr[5] would still fall within 342 * the hash_mask. Case 0 does this exactly. Since there are a total 343 * of 8 bits of shifting, then mc_addr[4] will shift right the 344 * remaining number of bits. Thus 8 - bit_shift. The rest of the 345 * cases are a variation of this algorithm...essentially raising the 346 * number of bits to shift mc_addr[5] left, while still keeping the 347 * 8-bit shifting total. 348 * 349 * For example, given the following Destination MAC Address and an 350 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 351 * we can see that the bit_shift for case 0 is 4. These are the hash 352 * values resulting from each mc_filter_type... 353 * [0] [1] [2] [3] [4] [5] 354 * 01 AA 00 12 34 56 355 * LSB MSB 356 * 357 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 358 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 359 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 360 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 361 */ 362 switch (hw->mac.mc_filter_type) { 363 default: 364 case 0: 365 break; 366 case 1: 367 bit_shift += 1; 368 break; 369 case 2: 370 bit_shift += 2; 371 break; 372 case 3: 373 bit_shift += 4; 374 break; 375 } 376 377 hash_value = (u32)mc_addr[4]; 378 hash_value >>= 8 - bit_shift; 379 hash_value |= (u32)mc_addr[5] << bit_shift; 380 hash_value &= hash_mask; 381 382 return hash_value; 383 } 384 385 /** 386 * igc_update_mc_addr_list_generic - Update Multicast addresses 387 * @hw: pointer to the HW structure 388 * @mc_addr_list: array of multicast addresses to program 389 * @mc_addr_count: number of multicast addresses to program 390 * 391 * Updates entire Multicast Table Array. 392 * The caller must have a packed mc_addr_list of multicast addresses. 393 **/ 394 void igc_update_mc_addr_list_generic(struct igc_hw *hw, 395 u8 *mc_addr_list, u32 mc_addr_count) 396 { 397 u32 hash_value, hash_bit, hash_reg; 398 int i; 399 400 DEBUGFUNC("igc_update_mc_addr_list_generic"); 401 402 /* clear mta_shadow */ 403 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 404 405 /* update mta_shadow from mc_addr_list */ 406 for (i = 0; (u32) i < mc_addr_count; i++) { 407 hash_value = igc_hash_mc_addr_generic(hw, mc_addr_list); 408 409 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 410 hash_bit = hash_value & 0x1F; 411 412 hw->mac.mta_shadow[hash_reg] |= 1U << hash_bit; 413 mc_addr_list += (ETH_ADDR_LEN); 414 } 415 416 /* replace the entire MTA table */ 417 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 418 IGC_WRITE_REG_ARRAY(hw, IGC_MTA, i, hw->mac.mta_shadow[i]); 419 IGC_WRITE_FLUSH(hw); 420 } 421 422 /** 423 * igc_clear_hw_cntrs_base_generic - Clear base hardware counters 424 * @hw: pointer to the HW structure 425 * 426 * Clears the base hardware counters by reading the counter registers. 427 **/ 428 void igc_clear_hw_cntrs_base_generic(struct igc_hw *hw) 429 { 430 DEBUGFUNC("igc_clear_hw_cntrs_base_generic"); 431 432 IGC_READ_REG(hw, IGC_CRCERRS); 433 IGC_READ_REG(hw, IGC_RXERRC); 434 IGC_READ_REG(hw, IGC_MPC); 435 IGC_READ_REG(hw, IGC_SCC); 436 IGC_READ_REG(hw, IGC_ECOL); 437 IGC_READ_REG(hw, IGC_MCC); 438 IGC_READ_REG(hw, IGC_LATECOL); 439 IGC_READ_REG(hw, IGC_COLC); 440 IGC_READ_REG(hw, IGC_RERC); 441 IGC_READ_REG(hw, IGC_DC); 442 IGC_READ_REG(hw, IGC_RLEC); 443 IGC_READ_REG(hw, IGC_XONRXC); 444 IGC_READ_REG(hw, IGC_XONTXC); 445 IGC_READ_REG(hw, IGC_XOFFRXC); 446 IGC_READ_REG(hw, IGC_XOFFTXC); 447 IGC_READ_REG(hw, IGC_FCRUC); 448 IGC_READ_REG(hw, IGC_GPRC); 449 IGC_READ_REG(hw, IGC_BPRC); 450 IGC_READ_REG(hw, IGC_MPRC); 451 IGC_READ_REG(hw, IGC_GPTC); 452 IGC_READ_REG(hw, IGC_GORCL); 453 IGC_READ_REG(hw, IGC_GORCH); 454 IGC_READ_REG(hw, IGC_GOTCL); 455 IGC_READ_REG(hw, IGC_GOTCH); 456 IGC_READ_REG(hw, IGC_RNBC); 457 IGC_READ_REG(hw, IGC_RUC); 458 IGC_READ_REG(hw, IGC_RFC); 459 IGC_READ_REG(hw, IGC_ROC); 460 IGC_READ_REG(hw, IGC_RJC); 461 IGC_READ_REG(hw, IGC_TORL); 462 IGC_READ_REG(hw, IGC_TORH); 463 IGC_READ_REG(hw, IGC_TOTL); 464 IGC_READ_REG(hw, IGC_TOTH); 465 IGC_READ_REG(hw, IGC_TPR); 466 IGC_READ_REG(hw, IGC_TPT); 467 IGC_READ_REG(hw, IGC_MPTC); 468 IGC_READ_REG(hw, IGC_BPTC); 469 IGC_READ_REG(hw, IGC_TLPIC); 470 IGC_READ_REG(hw, IGC_RLPIC); 471 IGC_READ_REG(hw, IGC_RXDMTC); 472 } 473 474 /** 475 * igc_check_for_copper_link_generic - Check for link (Copper) 476 * @hw: pointer to the HW structure 477 * 478 * Checks to see of the link status of the hardware has changed. If a 479 * change in link status has been detected, then we read the PHY registers 480 * to get the current speed/duplex if link exists. 481 **/ 482 s32 igc_check_for_copper_link_generic(struct igc_hw *hw) 483 { 484 struct igc_mac_info *mac = &hw->mac; 485 s32 ret_val; 486 bool link = false; 487 488 DEBUGFUNC("igc_check_for_copper_link"); 489 490 /* We only want to go out to the PHY registers to see if Auto-Neg 491 * has completed and/or if our link status has changed. The 492 * get_link_status flag is set upon receiving a Link Status 493 * Change or Rx Sequence Error interrupt. 494 */ 495 if (!mac->get_link_status) 496 return IGC_SUCCESS; 497 498 /* First we want to see if the MII Status Register reports 499 * link. If so, then we want to get the current speed/duplex 500 * of the PHY. 501 */ 502 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link); 503 if (ret_val) 504 return ret_val; 505 506 if (!link) 507 return IGC_SUCCESS; /* No link detected */ 508 509 mac->get_link_status = false; 510 511 /* Check if there was DownShift, must be checked 512 * immediately after link-up 513 */ 514 igc_check_downshift_generic(hw); 515 516 /* If we are forcing speed/duplex, then we simply return since 517 * we have already determined whether we have link or not. 518 */ 519 if (!mac->autoneg) 520 return -IGC_ERR_CONFIG; 521 522 /* Auto-Neg is enabled. Auto Speed Detection takes care 523 * of MAC speed/duplex configuration. So we only need to 524 * configure Collision Distance in the MAC. 525 */ 526 mac->ops.config_collision_dist(hw); 527 528 /* Configure Flow Control now that Auto-Neg has completed. 529 * First, we need to restore the desired flow control 530 * settings because we may have had to re-autoneg with a 531 * different link partner. 532 */ 533 ret_val = igc_config_fc_after_link_up_generic(hw); 534 if (ret_val) 535 DEBUGOUT("Error configuring flow control\n"); 536 537 return ret_val; 538 } 539 540 /** 541 * igc_setup_link_generic - Setup flow control and link settings 542 * @hw: pointer to the HW structure 543 * 544 * Determines which flow control settings to use, then configures flow 545 * control. Calls the appropriate media-specific link configuration 546 * function. Assuming the adapter has a valid link partner, a valid link 547 * should be established. Assumes the hardware has previously been reset 548 * and the transmitter and receiver are not enabled. 549 **/ 550 s32 igc_setup_link_generic(struct igc_hw *hw) 551 { 552 s32 ret_val; 553 554 DEBUGFUNC("igc_setup_link_generic"); 555 556 /* In the case of the phy reset being blocked, we already have a link. 557 * We do not need to set it up again. 558 */ 559 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 560 return IGC_SUCCESS; 561 562 /* If requested flow control is set to default, set flow control 563 * for both 'rx' and 'tx' pause frames. 564 */ 565 if (hw->fc.requested_mode == igc_fc_default) { 566 hw->fc.requested_mode = igc_fc_full; 567 } 568 569 /* Save off the requested flow control mode for use later. Depending 570 * on the link partner's capabilities, we may or may not use this mode. 571 */ 572 hw->fc.current_mode = hw->fc.requested_mode; 573 574 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 575 hw->fc.current_mode); 576 577 /* Call the necessary media_type subroutine to configure the link. */ 578 ret_val = hw->mac.ops.setup_physical_interface(hw); 579 if (ret_val) 580 return ret_val; 581 582 /* Initialize the flow control address, type, and PAUSE timer 583 * registers to their default values. This is done even if flow 584 * control is disabled, because it does not hurt anything to 585 * initialize these registers. 586 */ 587 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 588 IGC_WRITE_REG(hw, IGC_FCT, FLOW_CONTROL_TYPE); 589 IGC_WRITE_REG(hw, IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 590 IGC_WRITE_REG(hw, IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW); 591 592 IGC_WRITE_REG(hw, IGC_FCTTV, hw->fc.pause_time); 593 594 return igc_set_fc_watermarks_generic(hw); 595 } 596 597 /** 598 * igc_config_collision_dist_generic - Configure collision distance 599 * @hw: pointer to the HW structure 600 * 601 * Configures the collision distance to the default value and is used 602 * during link setup. 603 **/ 604 static void igc_config_collision_dist_generic(struct igc_hw *hw) 605 { 606 u32 tctl; 607 608 DEBUGFUNC("igc_config_collision_dist_generic"); 609 610 tctl = IGC_READ_REG(hw, IGC_TCTL); 611 612 tctl &= ~IGC_TCTL_COLD; 613 tctl |= IGC_COLLISION_DISTANCE << IGC_COLD_SHIFT; 614 615 IGC_WRITE_REG(hw, IGC_TCTL, tctl); 616 IGC_WRITE_FLUSH(hw); 617 } 618 619 /** 620 * igc_set_fc_watermarks_generic - Set flow control high/low watermarks 621 * @hw: pointer to the HW structure 622 * 623 * Sets the flow control high/low threshold (watermark) registers. If 624 * flow control XON frame transmission is enabled, then set XON frame 625 * transmission as well. 626 **/ 627 s32 igc_set_fc_watermarks_generic(struct igc_hw *hw) 628 { 629 u32 fcrtl = 0, fcrth = 0; 630 631 DEBUGFUNC("igc_set_fc_watermarks_generic"); 632 633 /* Set the flow control receive threshold registers. Normally, 634 * these registers will be set to a default threshold that may be 635 * adjusted later by the driver's runtime code. However, if the 636 * ability to transmit pause frames is not enabled, then these 637 * registers will be set to 0. 638 */ 639 if (hw->fc.current_mode & igc_fc_tx_pause) { 640 /* We need to set up the Receive Threshold high and low water 641 * marks as well as (optionally) enabling the transmission of 642 * XON frames. 643 */ 644 fcrtl = hw->fc.low_water; 645 if (hw->fc.send_xon) 646 fcrtl |= IGC_FCRTL_XONE; 647 648 fcrth = hw->fc.high_water; 649 } 650 IGC_WRITE_REG(hw, IGC_FCRTL, fcrtl); 651 IGC_WRITE_REG(hw, IGC_FCRTH, fcrth); 652 653 return IGC_SUCCESS; 654 } 655 656 /** 657 * igc_force_mac_fc_generic - Force the MAC's flow control settings 658 * @hw: pointer to the HW structure 659 * 660 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 661 * device control register to reflect the adapter settings. TFCE and RFCE 662 * need to be explicitly set by software when a copper PHY is used because 663 * autonegotiation is managed by the PHY rather than the MAC. Software must 664 * also configure these bits when link is forced on a fiber connection. 665 **/ 666 s32 igc_force_mac_fc_generic(struct igc_hw *hw) 667 { 668 u32 ctrl; 669 670 DEBUGFUNC("igc_force_mac_fc_generic"); 671 672 ctrl = IGC_READ_REG(hw, IGC_CTRL); 673 674 /* Because we didn't get link via the internal auto-negotiation 675 * mechanism (we either forced link or we got link via PHY 676 * auto-neg), we have to manually enable/disable transmit an 677 * receive flow control. 678 * 679 * The "Case" statement below enables/disable flow control 680 * according to the "hw->fc.current_mode" parameter. 681 * 682 * The possible values of the "fc" parameter are: 683 * 0: Flow control is completely disabled 684 * 1: Rx flow control is enabled (we can receive pause 685 * frames but not send pause frames). 686 * 2: Tx flow control is enabled (we can send pause frames 687 * frames but we do not receive pause frames). 688 * 3: Both Rx and Tx flow control (symmetric) is enabled. 689 * other: No other values should be possible at this point. 690 */ 691 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 692 693 switch (hw->fc.current_mode) { 694 case igc_fc_none: 695 ctrl &= (~(IGC_CTRL_TFCE | IGC_CTRL_RFCE)); 696 break; 697 case igc_fc_rx_pause: 698 ctrl &= (~IGC_CTRL_TFCE); 699 ctrl |= IGC_CTRL_RFCE; 700 break; 701 case igc_fc_tx_pause: 702 ctrl &= (~IGC_CTRL_RFCE); 703 ctrl |= IGC_CTRL_TFCE; 704 break; 705 case igc_fc_full: 706 ctrl |= (IGC_CTRL_TFCE | IGC_CTRL_RFCE); 707 break; 708 default: 709 DEBUGOUT("Flow control param set incorrectly\n"); 710 return -IGC_ERR_CONFIG; 711 } 712 713 IGC_WRITE_REG(hw, IGC_CTRL, ctrl); 714 715 return IGC_SUCCESS; 716 } 717 718 /** 719 * igc_config_fc_after_link_up_generic - Configures flow control after link 720 * @hw: pointer to the HW structure 721 * 722 * Checks the status of auto-negotiation after link up to ensure that the 723 * speed and duplex were not forced. If the link needed to be forced, then 724 * flow control needs to be forced also. If auto-negotiation is enabled 725 * and did not fail, then we configure flow control based on our link 726 * partner. 727 **/ 728 s32 igc_config_fc_after_link_up_generic(struct igc_hw *hw) 729 { 730 struct igc_mac_info *mac = &hw->mac; 731 s32 ret_val = IGC_SUCCESS; 732 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 733 u16 speed, duplex; 734 735 DEBUGFUNC("igc_config_fc_after_link_up_generic"); 736 737 if (ret_val) { 738 DEBUGOUT("Error forcing flow control settings\n"); 739 return ret_val; 740 } 741 742 /* Check for the case where we have copper media and auto-neg is 743 * enabled. In this case, we need to check and see if Auto-Neg 744 * has completed, and if so, how the PHY and link partner has 745 * flow control configured. 746 */ 747 if (mac->autoneg) { 748 /* Read the MII Status Register and check to see if AutoNeg 749 * has completed. We read this twice because this reg has 750 * some "sticky" (latched) bits. 751 */ 752 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 753 if (ret_val) 754 return ret_val; 755 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 756 if (ret_val) 757 return ret_val; 758 759 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 760 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); 761 return ret_val; 762 } 763 764 /* The AutoNeg process has completed, so we now need to 765 * read both the Auto Negotiation Advertisement 766 * Register (Address 4) and the Auto_Negotiation Base 767 * Page Ability Register (Address 5) to determine how 768 * flow control was negotiated. 769 */ 770 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 771 &mii_nway_adv_reg); 772 if (ret_val) 773 return ret_val; 774 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 775 &mii_nway_lp_ability_reg); 776 if (ret_val) 777 return ret_val; 778 779 /* Two bits in the Auto Negotiation Advertisement Register 780 * (Address 4) and two bits in the Auto Negotiation Base 781 * Page Ability Register (Address 5) determine flow control 782 * for both the PHY and the link partner. The following 783 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 784 * 1999, describes these PAUSE resolution bits and how flow 785 * control is determined based upon these settings. 786 * NOTE: DC = Don't Care 787 * 788 * LOCAL DEVICE | LINK PARTNER 789 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 790 *-------|---------|-------|---------|-------------------- 791 * 0 | 0 | DC | DC | igc_fc_none 792 * 0 | 1 | 0 | DC | igc_fc_none 793 * 0 | 1 | 1 | 0 | igc_fc_none 794 * 0 | 1 | 1 | 1 | igc_fc_tx_pause 795 * 1 | 0 | 0 | DC | igc_fc_none 796 * 1 | DC | 1 | DC | igc_fc_full 797 * 1 | 1 | 0 | 0 | igc_fc_none 798 * 1 | 1 | 0 | 1 | igc_fc_rx_pause 799 * 800 * Are both PAUSE bits set to 1? If so, this implies 801 * Symmetric Flow Control is enabled at both ends. The 802 * ASM_DIR bits are irrelevant per the spec. 803 * 804 * For Symmetric Flow Control: 805 * 806 * LOCAL DEVICE | LINK PARTNER 807 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 808 *-------|---------|-------|---------|-------------------- 809 * 1 | DC | 1 | DC | IGC_fc_full 810 * 811 */ 812 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 813 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 814 /* Now we need to check if the user selected Rx ONLY 815 * of pause frames. In this case, we had to advertise 816 * FULL flow control because we could not advertise Rx 817 * ONLY. Hence, we must now check to see if we need to 818 * turn OFF the TRANSMISSION of PAUSE frames. 819 */ 820 if (hw->fc.requested_mode == igc_fc_full) { 821 hw->fc.current_mode = igc_fc_full; 822 DEBUGOUT("Flow Control = FULL.\n"); 823 } else { 824 hw->fc.current_mode = igc_fc_rx_pause; 825 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 826 } 827 } 828 /* For receiving PAUSE frames ONLY. 829 * 830 * LOCAL DEVICE | LINK PARTNER 831 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 832 *-------|---------|-------|---------|-------------------- 833 * 0 | 1 | 1 | 1 | igc_fc_tx_pause 834 */ 835 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 836 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 837 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 838 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 839 hw->fc.current_mode = igc_fc_tx_pause; 840 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 841 } 842 /* For transmitting PAUSE frames ONLY. 843 * 844 * LOCAL DEVICE | LINK PARTNER 845 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 846 *-------|---------|-------|---------|-------------------- 847 * 1 | 1 | 0 | 1 | igc_fc_rx_pause 848 */ 849 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 850 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 851 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 852 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 853 hw->fc.current_mode = igc_fc_rx_pause; 854 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 855 } else { 856 /* Per the IEEE spec, at this point flow control 857 * should be disabled. 858 */ 859 hw->fc.current_mode = igc_fc_none; 860 DEBUGOUT("Flow Control = NONE.\n"); 861 } 862 863 /* Now we need to do one last check... If we auto- 864 * negotiated to HALF DUPLEX, flow control should not be 865 * enabled per IEEE 802.3 spec. 866 */ 867 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 868 if (ret_val) { 869 DEBUGOUT("Error getting link speed and duplex\n"); 870 return ret_val; 871 } 872 873 if (duplex == HALF_DUPLEX) 874 hw->fc.current_mode = igc_fc_none; 875 876 /* Now we call a subroutine to actually force the MAC 877 * controller to use the correct flow control settings. 878 */ 879 ret_val = igc_force_mac_fc_generic(hw); 880 if (ret_val) { 881 DEBUGOUT("Error forcing flow control settings\n"); 882 return ret_val; 883 } 884 } 885 886 return IGC_SUCCESS; 887 } 888 889 /** 890 * igc_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 891 * @hw: pointer to the HW structure 892 * @speed: stores the current speed 893 * @duplex: stores the current duplex 894 * 895 * Read the status register for the current speed/duplex and store the current 896 * speed and duplex for copper connections. 897 **/ 898 s32 igc_get_speed_and_duplex_copper_generic(struct igc_hw *hw, u16 *speed, 899 u16 *duplex) 900 { 901 u32 status; 902 903 DEBUGFUNC("igc_get_speed_and_duplex_copper_generic"); 904 905 status = IGC_READ_REG(hw, IGC_STATUS); 906 if (status & IGC_STATUS_SPEED_1000) { 907 /* For I225, STATUS will indicate 1G speed in both 1 Gbps 908 * and 2.5 Gbps link modes. An additional bit is used 909 * to differentiate between 1 Gbps and 2.5 Gbps. 910 */ 911 if ((hw->mac.type == igc_i225) && 912 (status & IGC_STATUS_SPEED_2500)) { 913 *speed = SPEED_2500; 914 DEBUGOUT("2500 Mbs, "); 915 } else { 916 *speed = SPEED_1000; 917 DEBUGOUT("1000 Mbs, "); 918 } 919 } else if (status & IGC_STATUS_SPEED_100) { 920 *speed = SPEED_100; 921 DEBUGOUT("100 Mbs, "); 922 } else { 923 *speed = SPEED_10; 924 DEBUGOUT("10 Mbs, "); 925 } 926 927 if (status & IGC_STATUS_FD) { 928 *duplex = FULL_DUPLEX; 929 DEBUGOUT("Full Duplex\n"); 930 } else { 931 *duplex = HALF_DUPLEX; 932 DEBUGOUT("Half Duplex\n"); 933 } 934 935 return IGC_SUCCESS; 936 } 937 938 /** 939 * igc_get_hw_semaphore_generic - Acquire hardware semaphore 940 * @hw: pointer to the HW structure 941 * 942 * Acquire the HW semaphore to access the PHY or NVM 943 **/ 944 s32 igc_get_hw_semaphore_generic(struct igc_hw *hw) 945 { 946 u32 swsm; 947 s32 timeout = hw->nvm.word_size + 1; 948 s32 i = 0; 949 950 DEBUGFUNC("igc_get_hw_semaphore_generic"); 951 952 /* Get the SW semaphore */ 953 while (i < timeout) { 954 swsm = IGC_READ_REG(hw, IGC_SWSM); 955 if (!(swsm & IGC_SWSM_SMBI)) 956 break; 957 958 usec_delay(50); 959 i++; 960 } 961 962 if (i == timeout) { 963 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 964 return -IGC_ERR_NVM; 965 } 966 967 /* Get the FW semaphore. */ 968 for (i = 0; i < timeout; i++) { 969 swsm = IGC_READ_REG(hw, IGC_SWSM); 970 IGC_WRITE_REG(hw, IGC_SWSM, swsm | IGC_SWSM_SWESMBI); 971 972 /* Semaphore acquired if bit latched */ 973 if (IGC_READ_REG(hw, IGC_SWSM) & IGC_SWSM_SWESMBI) 974 break; 975 976 usec_delay(50); 977 } 978 979 if (i == timeout) { 980 /* Release semaphores */ 981 igc_put_hw_semaphore_generic(hw); 982 DEBUGOUT("Driver can't access the NVM\n"); 983 return -IGC_ERR_NVM; 984 } 985 986 return IGC_SUCCESS; 987 } 988 989 /** 990 * igc_put_hw_semaphore_generic - Release hardware semaphore 991 * @hw: pointer to the HW structure 992 * 993 * Release hardware semaphore used to access the PHY or NVM 994 **/ 995 void igc_put_hw_semaphore_generic(struct igc_hw *hw) 996 { 997 u32 swsm; 998 999 DEBUGFUNC("igc_put_hw_semaphore_generic"); 1000 1001 swsm = IGC_READ_REG(hw, IGC_SWSM); 1002 1003 swsm &= ~(IGC_SWSM_SMBI | IGC_SWSM_SWESMBI); 1004 1005 IGC_WRITE_REG(hw, IGC_SWSM, swsm); 1006 } 1007 1008 /** 1009 * igc_get_auto_rd_done_generic - Check for auto read completion 1010 * @hw: pointer to the HW structure 1011 * 1012 * Check EEPROM for Auto Read done bit. 1013 **/ 1014 s32 igc_get_auto_rd_done_generic(struct igc_hw *hw) 1015 { 1016 s32 i = 0; 1017 1018 DEBUGFUNC("igc_get_auto_rd_done_generic"); 1019 1020 while (i < AUTO_READ_DONE_TIMEOUT) { 1021 if (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_AUTO_RD) 1022 break; 1023 msec_delay(1); 1024 i++; 1025 } 1026 1027 if (i == AUTO_READ_DONE_TIMEOUT) { 1028 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1029 return -IGC_ERR_RESET; 1030 } 1031 1032 return IGC_SUCCESS; 1033 } 1034 1035 /** 1036 * igc_disable_pcie_master_generic - Disables PCI-express master access 1037 * @hw: pointer to the HW structure 1038 * 1039 * Returns IGC_SUCCESS if successful, else returns -10 1040 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 1041 * the master requests to be disabled. 1042 * 1043 * Disables PCI-Express master access and verifies there are no pending 1044 * requests. 1045 **/ 1046 s32 igc_disable_pcie_master_generic(struct igc_hw *hw) 1047 { 1048 u32 ctrl; 1049 s32 timeout = MASTER_DISABLE_TIMEOUT; 1050 1051 DEBUGFUNC("igc_disable_pcie_master_generic"); 1052 1053 ctrl = IGC_READ_REG(hw, IGC_CTRL); 1054 ctrl |= IGC_CTRL_GIO_MASTER_DISABLE; 1055 IGC_WRITE_REG(hw, IGC_CTRL, ctrl); 1056 1057 while (timeout) { 1058 if (!(IGC_READ_REG(hw, IGC_STATUS) & 1059 IGC_STATUS_GIO_MASTER_ENABLE)) 1060 break; 1061 usec_delay(100); 1062 timeout--; 1063 } 1064 1065 if (!timeout) { 1066 DEBUGOUT("Master requests are pending.\n"); 1067 return -IGC_ERR_MASTER_REQUESTS_PENDING; 1068 } 1069 1070 return IGC_SUCCESS; 1071 } 1072