1 /*- 2 * Copyright 2021 Intel Corp 3 * Copyright 2021 Rubicon Communications, LLC (Netgate) 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <sys/cdefs.h> 8 #include "igc_api.h" 9 10 static void igc_config_collision_dist_generic(struct igc_hw *hw); 11 12 /** 13 * igc_init_mac_ops_generic - Initialize MAC function pointers 14 * @hw: pointer to the HW structure 15 * 16 * Setups up the function pointers to no-op functions 17 **/ 18 void igc_init_mac_ops_generic(struct igc_hw *hw) 19 { 20 struct igc_mac_info *mac = &hw->mac; 21 DEBUGFUNC("igc_init_mac_ops_generic"); 22 23 /* General Setup */ 24 mac->ops.init_params = igc_null_ops_generic; 25 mac->ops.config_collision_dist = igc_config_collision_dist_generic; 26 mac->ops.rar_set = igc_rar_set_generic; 27 } 28 29 /** 30 * igc_null_ops_generic - No-op function, returns 0 31 * @hw: pointer to the HW structure 32 **/ 33 s32 igc_null_ops_generic(struct igc_hw IGC_UNUSEDARG *hw) 34 { 35 DEBUGFUNC("igc_null_ops_generic"); 36 return IGC_SUCCESS; 37 } 38 39 /** 40 * igc_null_mac_generic - No-op function, return void 41 * @hw: pointer to the HW structure 42 **/ 43 void igc_null_mac_generic(struct igc_hw IGC_UNUSEDARG *hw) 44 { 45 DEBUGFUNC("igc_null_mac_generic"); 46 return; 47 } 48 49 /** 50 * igc_null_link_info - No-op function, return 0 51 * @hw: pointer to the HW structure 52 * @s: dummy variable 53 * @d: dummy variable 54 **/ 55 s32 igc_null_link_info(struct igc_hw IGC_UNUSEDARG *hw, 56 u16 IGC_UNUSEDARG *s, u16 IGC_UNUSEDARG *d) 57 { 58 DEBUGFUNC("igc_null_link_info"); 59 return IGC_SUCCESS; 60 } 61 62 /** 63 * igc_null_mng_mode - No-op function, return false 64 * @hw: pointer to the HW structure 65 **/ 66 bool igc_null_mng_mode(struct igc_hw IGC_UNUSEDARG *hw) 67 { 68 DEBUGFUNC("igc_null_mng_mode"); 69 return false; 70 } 71 72 /** 73 * igc_null_update_mc - No-op function, return void 74 * @hw: pointer to the HW structure 75 * @h: dummy variable 76 * @a: dummy variable 77 **/ 78 void igc_null_update_mc(struct igc_hw IGC_UNUSEDARG *hw, 79 u8 IGC_UNUSEDARG *h, u32 IGC_UNUSEDARG a) 80 { 81 DEBUGFUNC("igc_null_update_mc"); 82 return; 83 } 84 85 /** 86 * igc_null_write_vfta - No-op function, return void 87 * @hw: pointer to the HW structure 88 * @a: dummy variable 89 * @b: dummy variable 90 **/ 91 void igc_null_write_vfta(struct igc_hw IGC_UNUSEDARG *hw, 92 u32 IGC_UNUSEDARG a, u32 IGC_UNUSEDARG b) 93 { 94 DEBUGFUNC("igc_null_write_vfta"); 95 return; 96 } 97 98 /** 99 * igc_null_rar_set - No-op function, return 0 100 * @hw: pointer to the HW structure 101 * @h: dummy variable 102 * @a: dummy variable 103 **/ 104 int igc_null_rar_set(struct igc_hw IGC_UNUSEDARG *hw, 105 u8 IGC_UNUSEDARG *h, u32 IGC_UNUSEDARG a) 106 { 107 DEBUGFUNC("igc_null_rar_set"); 108 return IGC_SUCCESS; 109 } 110 111 /** 112 * igc_set_lan_id_single_port - Set LAN id for a single port device 113 * @hw: pointer to the HW structure 114 * 115 * Sets the LAN function id to zero for a single port device. 116 **/ 117 void igc_set_lan_id_single_port(struct igc_hw *hw) 118 { 119 struct igc_bus_info *bus = &hw->bus; 120 121 bus->func = 0; 122 } 123 124 /** 125 * igc_clear_vfta_generic - Clear VLAN filter table 126 * @hw: pointer to the HW structure 127 * 128 * Clears the register array which contains the VLAN filter table by 129 * setting all the values to 0. 130 **/ 131 void igc_clear_vfta_generic(struct igc_hw *hw) 132 { 133 u32 offset; 134 135 DEBUGFUNC("igc_clear_vfta_generic"); 136 137 for (offset = 0; offset < IGC_VLAN_FILTER_TBL_SIZE; offset++) { 138 IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, 0); 139 IGC_WRITE_FLUSH(hw); 140 } 141 } 142 143 /** 144 * igc_write_vfta_generic - Write value to VLAN filter table 145 * @hw: pointer to the HW structure 146 * @offset: register offset in VLAN filter table 147 * @value: register value written to VLAN filter table 148 * 149 * Writes value at the given offset in the register array which stores 150 * the VLAN filter table. 151 **/ 152 void igc_write_vfta_generic(struct igc_hw *hw, u32 offset, u32 value) 153 { 154 DEBUGFUNC("igc_write_vfta_generic"); 155 156 IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, value); 157 IGC_WRITE_FLUSH(hw); 158 } 159 160 /** 161 * igc_init_rx_addrs_generic - Initialize receive address's 162 * @hw: pointer to the HW structure 163 * @rar_count: receive address registers 164 * 165 * Setup the receive address registers by setting the base receive address 166 * register to the devices MAC address and clearing all the other receive 167 * address registers to 0. 168 **/ 169 void igc_init_rx_addrs_generic(struct igc_hw *hw, u16 rar_count) 170 { 171 u32 i; 172 u8 mac_addr[ETH_ADDR_LEN] = {0}; 173 174 DEBUGFUNC("igc_init_rx_addrs_generic"); 175 176 /* Setup the receive address */ 177 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 178 179 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 180 181 /* Zero out the other (rar_entry_count - 1) receive addresses */ 182 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 183 for (i = 1; i < rar_count; i++) 184 hw->mac.ops.rar_set(hw, mac_addr, i); 185 } 186 187 /** 188 * igc_check_alt_mac_addr_generic - Check for alternate MAC addr 189 * @hw: pointer to the HW structure 190 * 191 * Checks the nvm for an alternate MAC address. An alternate MAC address 192 * can be setup by pre-boot software and must be treated like a permanent 193 * address and must override the actual permanent MAC address. If an 194 * alternate MAC address is found it is programmed into RAR0, replacing 195 * the permanent address that was installed into RAR0 by the Si on reset. 196 * This function will return SUCCESS unless it encounters an error while 197 * reading the EEPROM. 198 **/ 199 s32 igc_check_alt_mac_addr_generic(struct igc_hw *hw) 200 { 201 u32 i; 202 s32 ret_val; 203 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 204 u8 alt_mac_addr[ETH_ADDR_LEN]; 205 206 DEBUGFUNC("igc_check_alt_mac_addr_generic"); 207 208 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); 209 if (ret_val) 210 return ret_val; 211 212 213 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 214 &nvm_alt_mac_addr_offset); 215 if (ret_val) { 216 DEBUGOUT("NVM Read Error\n"); 217 return ret_val; 218 } 219 220 if ((nvm_alt_mac_addr_offset == 0xFFFF) || 221 (nvm_alt_mac_addr_offset == 0x0000)) 222 /* There is no Alternate MAC Address */ 223 return IGC_SUCCESS; 224 225 if (hw->bus.func == IGC_FUNC_1) 226 nvm_alt_mac_addr_offset += IGC_ALT_MAC_ADDRESS_OFFSET_LAN1; 227 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 228 offset = nvm_alt_mac_addr_offset + (i >> 1); 229 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 230 if (ret_val) { 231 DEBUGOUT("NVM Read Error\n"); 232 return ret_val; 233 } 234 235 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 236 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 237 } 238 239 /* if multicast bit is set, the alternate address will not be used */ 240 if (alt_mac_addr[0] & 0x01) { 241 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 242 return IGC_SUCCESS; 243 } 244 245 /* We have a valid alternate MAC address, and we want to treat it the 246 * same as the normal permanent MAC address stored by the HW into the 247 * RAR. Do this by mapping this address into RAR0. 248 */ 249 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 250 251 return IGC_SUCCESS; 252 } 253 254 /** 255 * igc_rar_set_generic - Set receive address register 256 * @hw: pointer to the HW structure 257 * @addr: pointer to the receive address 258 * @index: receive address array register 259 * 260 * Sets the receive address array register at index to the address passed 261 * in by addr. 262 **/ 263 int igc_rar_set_generic(struct igc_hw *hw, u8 *addr, u32 index) 264 { 265 u32 rar_low, rar_high; 266 267 DEBUGFUNC("igc_rar_set_generic"); 268 269 /* HW expects these in little endian so we reverse the byte order 270 * from network order (big endian) to little endian 271 */ 272 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 273 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 274 275 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 276 277 /* If MAC address zero, no need to set the AV bit */ 278 if (rar_low || rar_high) 279 rar_high |= IGC_RAH_AV; 280 281 /* Some bridges will combine consecutive 32-bit writes into 282 * a single burst write, which will malfunction on some parts. 283 * The flushes avoid this. 284 */ 285 IGC_WRITE_REG(hw, IGC_RAL(index), rar_low); 286 IGC_WRITE_FLUSH(hw); 287 IGC_WRITE_REG(hw, IGC_RAH(index), rar_high); 288 IGC_WRITE_FLUSH(hw); 289 290 return IGC_SUCCESS; 291 } 292 293 /** 294 * igc_hash_mc_addr_generic - Generate a multicast hash value 295 * @hw: pointer to the HW structure 296 * @mc_addr: pointer to a multicast address 297 * 298 * Generates a multicast address hash value which is used to determine 299 * the multicast filter table array address and new table value. 300 **/ 301 u32 igc_hash_mc_addr_generic(struct igc_hw *hw, u8 *mc_addr) 302 { 303 u32 hash_value, hash_mask; 304 u8 bit_shift = 1; 305 306 DEBUGFUNC("igc_hash_mc_addr_generic"); 307 308 /* Register count multiplied by bits per register */ 309 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 310 311 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts 312 * where 0xFF would still fall within the hash mask. 313 */ 314 while (bit_shift < 4 && hash_mask >> bit_shift != 0xFF) 315 bit_shift++; 316 317 /* The portion of the address that is used for the hash table 318 * is determined by the mc_filter_type setting. 319 * The algorithm is such that there is a total of 8 bits of shifting. 320 * The bit_shift for a mc_filter_type of 0 represents the number of 321 * left-shifts where the MSB of mc_addr[5] would still fall within 322 * the hash_mask. Case 0 does this exactly. Since there are a total 323 * of 8 bits of shifting, then mc_addr[4] will shift right the 324 * remaining number of bits. Thus 8 - bit_shift. The rest of the 325 * cases are a variation of this algorithm...essentially raising the 326 * number of bits to shift mc_addr[5] left, while still keeping the 327 * 8-bit shifting total. 328 * 329 * For example, given the following Destination MAC Address and an 330 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 331 * we can see that the bit_shift for case 0 is 4. These are the hash 332 * values resulting from each mc_filter_type... 333 * [0] [1] [2] [3] [4] [5] 334 * 01 AA 00 12 34 56 335 * LSB MSB 336 * 337 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 338 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 339 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 340 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 341 */ 342 switch (hw->mac.mc_filter_type) { 343 default: 344 case 0: 345 break; 346 case 1: 347 bit_shift += 1; 348 break; 349 case 2: 350 bit_shift += 2; 351 break; 352 case 3: 353 bit_shift += 4; 354 break; 355 } 356 357 hash_value = (u32)mc_addr[4]; 358 hash_value >>= 8 - bit_shift; 359 hash_value |= (u32)mc_addr[5] << bit_shift; 360 hash_value &= hash_mask; 361 362 return hash_value; 363 } 364 365 /** 366 * igc_update_mc_addr_list_generic - Update Multicast addresses 367 * @hw: pointer to the HW structure 368 * @mc_addr_list: array of multicast addresses to program 369 * @mc_addr_count: number of multicast addresses to program 370 * 371 * Updates entire Multicast Table Array. 372 * The caller must have a packed mc_addr_list of multicast addresses. 373 **/ 374 void igc_update_mc_addr_list_generic(struct igc_hw *hw, 375 u8 *mc_addr_list, u32 mc_addr_count) 376 { 377 u32 hash_value, hash_bit, hash_reg; 378 int i; 379 380 DEBUGFUNC("igc_update_mc_addr_list_generic"); 381 382 /* clear mta_shadow */ 383 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 384 385 /* update mta_shadow from mc_addr_list */ 386 for (i = 0; (u32) i < mc_addr_count; i++) { 387 hash_value = igc_hash_mc_addr_generic(hw, mc_addr_list); 388 389 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 390 hash_bit = hash_value & 0x1F; 391 392 hw->mac.mta_shadow[hash_reg] |= 1U << hash_bit; 393 mc_addr_list += (ETH_ADDR_LEN); 394 } 395 396 /* replace the entire MTA table */ 397 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 398 IGC_WRITE_REG_ARRAY(hw, IGC_MTA, i, hw->mac.mta_shadow[i]); 399 IGC_WRITE_FLUSH(hw); 400 } 401 402 /** 403 * igc_clear_hw_cntrs_base_generic - Clear base hardware counters 404 * @hw: pointer to the HW structure 405 * 406 * Clears the base hardware counters by reading the counter registers. 407 **/ 408 void igc_clear_hw_cntrs_base_generic(struct igc_hw *hw) 409 { 410 DEBUGFUNC("igc_clear_hw_cntrs_base_generic"); 411 412 IGC_READ_REG(hw, IGC_CRCERRS); 413 IGC_READ_REG(hw, IGC_RXERRC); 414 IGC_READ_REG(hw, IGC_MPC); 415 IGC_READ_REG(hw, IGC_SCC); 416 IGC_READ_REG(hw, IGC_ECOL); 417 IGC_READ_REG(hw, IGC_MCC); 418 IGC_READ_REG(hw, IGC_LATECOL); 419 IGC_READ_REG(hw, IGC_COLC); 420 IGC_READ_REG(hw, IGC_RERC); 421 IGC_READ_REG(hw, IGC_DC); 422 IGC_READ_REG(hw, IGC_RLEC); 423 IGC_READ_REG(hw, IGC_XONRXC); 424 IGC_READ_REG(hw, IGC_XONTXC); 425 IGC_READ_REG(hw, IGC_XOFFRXC); 426 IGC_READ_REG(hw, IGC_XOFFTXC); 427 IGC_READ_REG(hw, IGC_FCRUC); 428 IGC_READ_REG(hw, IGC_GPRC); 429 IGC_READ_REG(hw, IGC_BPRC); 430 IGC_READ_REG(hw, IGC_MPRC); 431 IGC_READ_REG(hw, IGC_GPTC); 432 IGC_READ_REG(hw, IGC_GORCL); 433 IGC_READ_REG(hw, IGC_GORCH); 434 IGC_READ_REG(hw, IGC_GOTCL); 435 IGC_READ_REG(hw, IGC_GOTCH); 436 IGC_READ_REG(hw, IGC_RNBC); 437 IGC_READ_REG(hw, IGC_RUC); 438 IGC_READ_REG(hw, IGC_RFC); 439 IGC_READ_REG(hw, IGC_ROC); 440 IGC_READ_REG(hw, IGC_RJC); 441 IGC_READ_REG(hw, IGC_TORL); 442 IGC_READ_REG(hw, IGC_TORH); 443 IGC_READ_REG(hw, IGC_TOTL); 444 IGC_READ_REG(hw, IGC_TOTH); 445 IGC_READ_REG(hw, IGC_TPR); 446 IGC_READ_REG(hw, IGC_TPT); 447 IGC_READ_REG(hw, IGC_MPTC); 448 IGC_READ_REG(hw, IGC_BPTC); 449 IGC_READ_REG(hw, IGC_TLPIC); 450 IGC_READ_REG(hw, IGC_RLPIC); 451 IGC_READ_REG(hw, IGC_RXDMTC); 452 } 453 454 /** 455 * igc_check_for_copper_link_generic - Check for link (Copper) 456 * @hw: pointer to the HW structure 457 * 458 * Checks to see of the link status of the hardware has changed. If a 459 * change in link status has been detected, then we read the PHY registers 460 * to get the current speed/duplex if link exists. 461 **/ 462 s32 igc_check_for_copper_link_generic(struct igc_hw *hw) 463 { 464 struct igc_mac_info *mac = &hw->mac; 465 s32 ret_val; 466 bool link = false; 467 468 DEBUGFUNC("igc_check_for_copper_link"); 469 470 /* We only want to go out to the PHY registers to see if Auto-Neg 471 * has completed and/or if our link status has changed. The 472 * get_link_status flag is set upon receiving a Link Status 473 * Change or Rx Sequence Error interrupt. 474 */ 475 if (!mac->get_link_status) 476 return IGC_SUCCESS; 477 478 /* First we want to see if the MII Status Register reports 479 * link. If so, then we want to get the current speed/duplex 480 * of the PHY. 481 */ 482 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link); 483 if (ret_val) 484 return ret_val; 485 486 if (!link) 487 return IGC_SUCCESS; /* No link detected */ 488 489 mac->get_link_status = false; 490 491 /* Check if there was DownShift, must be checked 492 * immediately after link-up 493 */ 494 igc_check_downshift_generic(hw); 495 496 /* If we are forcing speed/duplex, then we simply return since 497 * we have already determined whether we have link or not. 498 */ 499 if (!mac->autoneg) 500 return -IGC_ERR_CONFIG; 501 502 /* Auto-Neg is enabled. Auto Speed Detection takes care 503 * of MAC speed/duplex configuration. So we only need to 504 * configure Collision Distance in the MAC. 505 */ 506 mac->ops.config_collision_dist(hw); 507 508 /* Configure Flow Control now that Auto-Neg has completed. 509 * First, we need to restore the desired flow control 510 * settings because we may have had to re-autoneg with a 511 * different link partner. 512 */ 513 ret_val = igc_config_fc_after_link_up_generic(hw); 514 if (ret_val) 515 DEBUGOUT("Error configuring flow control\n"); 516 517 return ret_val; 518 } 519 520 /** 521 * igc_setup_link_generic - Setup flow control and link settings 522 * @hw: pointer to the HW structure 523 * 524 * Determines which flow control settings to use, then configures flow 525 * control. Calls the appropriate media-specific link configuration 526 * function. Assuming the adapter has a valid link partner, a valid link 527 * should be established. Assumes the hardware has previously been reset 528 * and the transmitter and receiver are not enabled. 529 **/ 530 s32 igc_setup_link_generic(struct igc_hw *hw) 531 { 532 s32 ret_val; 533 534 DEBUGFUNC("igc_setup_link_generic"); 535 536 /* In the case of the phy reset being blocked, we already have a link. 537 * We do not need to set it up again. 538 */ 539 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 540 return IGC_SUCCESS; 541 542 /* If requested flow control is set to default, set flow control 543 * for both 'rx' and 'tx' pause frames. 544 */ 545 if (hw->fc.requested_mode == igc_fc_default) { 546 hw->fc.requested_mode = igc_fc_full; 547 } 548 549 /* Save off the requested flow control mode for use later. Depending 550 * on the link partner's capabilities, we may or may not use this mode. 551 */ 552 hw->fc.current_mode = hw->fc.requested_mode; 553 554 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 555 hw->fc.current_mode); 556 557 /* Call the necessary media_type subroutine to configure the link. */ 558 ret_val = hw->mac.ops.setup_physical_interface(hw); 559 if (ret_val) 560 return ret_val; 561 562 /* Initialize the flow control address, type, and PAUSE timer 563 * registers to their default values. This is done even if flow 564 * control is disabled, because it does not hurt anything to 565 * initialize these registers. 566 */ 567 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 568 IGC_WRITE_REG(hw, IGC_FCT, FLOW_CONTROL_TYPE); 569 IGC_WRITE_REG(hw, IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 570 IGC_WRITE_REG(hw, IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW); 571 572 IGC_WRITE_REG(hw, IGC_FCTTV, hw->fc.pause_time); 573 574 return igc_set_fc_watermarks_generic(hw); 575 } 576 577 /** 578 * igc_config_collision_dist_generic - Configure collision distance 579 * @hw: pointer to the HW structure 580 * 581 * Configures the collision distance to the default value and is used 582 * during link setup. 583 **/ 584 static void igc_config_collision_dist_generic(struct igc_hw *hw) 585 { 586 u32 tctl; 587 588 DEBUGFUNC("igc_config_collision_dist_generic"); 589 590 tctl = IGC_READ_REG(hw, IGC_TCTL); 591 592 tctl &= ~IGC_TCTL_COLD; 593 tctl |= IGC_COLLISION_DISTANCE << IGC_COLD_SHIFT; 594 595 IGC_WRITE_REG(hw, IGC_TCTL, tctl); 596 IGC_WRITE_FLUSH(hw); 597 } 598 599 /** 600 * igc_set_fc_watermarks_generic - Set flow control high/low watermarks 601 * @hw: pointer to the HW structure 602 * 603 * Sets the flow control high/low threshold (watermark) registers. If 604 * flow control XON frame transmission is enabled, then set XON frame 605 * transmission as well. 606 **/ 607 s32 igc_set_fc_watermarks_generic(struct igc_hw *hw) 608 { 609 u32 fcrtl = 0, fcrth = 0; 610 611 DEBUGFUNC("igc_set_fc_watermarks_generic"); 612 613 /* Set the flow control receive threshold registers. Normally, 614 * these registers will be set to a default threshold that may be 615 * adjusted later by the driver's runtime code. However, if the 616 * ability to transmit pause frames is not enabled, then these 617 * registers will be set to 0. 618 */ 619 if (hw->fc.current_mode & igc_fc_tx_pause) { 620 /* We need to set up the Receive Threshold high and low water 621 * marks as well as (optionally) enabling the transmission of 622 * XON frames. 623 */ 624 fcrtl = hw->fc.low_water; 625 if (hw->fc.send_xon) 626 fcrtl |= IGC_FCRTL_XONE; 627 628 fcrth = hw->fc.high_water; 629 } 630 IGC_WRITE_REG(hw, IGC_FCRTL, fcrtl); 631 IGC_WRITE_REG(hw, IGC_FCRTH, fcrth); 632 633 return IGC_SUCCESS; 634 } 635 636 /** 637 * igc_force_mac_fc_generic - Force the MAC's flow control settings 638 * @hw: pointer to the HW structure 639 * 640 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 641 * device control register to reflect the adapter settings. TFCE and RFCE 642 * need to be explicitly set by software when a copper PHY is used because 643 * autonegotiation is managed by the PHY rather than the MAC. Software must 644 * also configure these bits when link is forced on a fiber connection. 645 **/ 646 s32 igc_force_mac_fc_generic(struct igc_hw *hw) 647 { 648 u32 ctrl; 649 650 DEBUGFUNC("igc_force_mac_fc_generic"); 651 652 ctrl = IGC_READ_REG(hw, IGC_CTRL); 653 654 /* Because we didn't get link via the internal auto-negotiation 655 * mechanism (we either forced link or we got link via PHY 656 * auto-neg), we have to manually enable/disable transmit an 657 * receive flow control. 658 * 659 * The "Case" statement below enables/disable flow control 660 * according to the "hw->fc.current_mode" parameter. 661 * 662 * The possible values of the "fc" parameter are: 663 * 0: Flow control is completely disabled 664 * 1: Rx flow control is enabled (we can receive pause 665 * frames but not send pause frames). 666 * 2: Tx flow control is enabled (we can send pause frames 667 * frames but we do not receive pause frames). 668 * 3: Both Rx and Tx flow control (symmetric) is enabled. 669 * other: No other values should be possible at this point. 670 */ 671 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 672 673 switch (hw->fc.current_mode) { 674 case igc_fc_none: 675 ctrl &= (~(IGC_CTRL_TFCE | IGC_CTRL_RFCE)); 676 break; 677 case igc_fc_rx_pause: 678 ctrl &= (~IGC_CTRL_TFCE); 679 ctrl |= IGC_CTRL_RFCE; 680 break; 681 case igc_fc_tx_pause: 682 ctrl &= (~IGC_CTRL_RFCE); 683 ctrl |= IGC_CTRL_TFCE; 684 break; 685 case igc_fc_full: 686 ctrl |= (IGC_CTRL_TFCE | IGC_CTRL_RFCE); 687 break; 688 default: 689 DEBUGOUT("Flow control param set incorrectly\n"); 690 return -IGC_ERR_CONFIG; 691 } 692 693 IGC_WRITE_REG(hw, IGC_CTRL, ctrl); 694 695 return IGC_SUCCESS; 696 } 697 698 /** 699 * igc_config_fc_after_link_up_generic - Configures flow control after link 700 * @hw: pointer to the HW structure 701 * 702 * Checks the status of auto-negotiation after link up to ensure that the 703 * speed and duplex were not forced. If the link needed to be forced, then 704 * flow control needs to be forced also. If auto-negotiation is enabled 705 * and did not fail, then we configure flow control based on our link 706 * partner. 707 **/ 708 s32 igc_config_fc_after_link_up_generic(struct igc_hw *hw) 709 { 710 struct igc_mac_info *mac = &hw->mac; 711 s32 ret_val = IGC_SUCCESS; 712 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 713 u16 speed, duplex; 714 715 DEBUGFUNC("igc_config_fc_after_link_up_generic"); 716 717 if (ret_val) { 718 DEBUGOUT("Error forcing flow control settings\n"); 719 return ret_val; 720 } 721 722 /* Check for the case where we have copper media and auto-neg is 723 * enabled. In this case, we need to check and see if Auto-Neg 724 * has completed, and if so, how the PHY and link partner has 725 * flow control configured. 726 */ 727 if (mac->autoneg) { 728 /* Read the MII Status Register and check to see if AutoNeg 729 * has completed. We read this twice because this reg has 730 * some "sticky" (latched) bits. 731 */ 732 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 733 if (ret_val) 734 return ret_val; 735 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 736 if (ret_val) 737 return ret_val; 738 739 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 740 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); 741 return ret_val; 742 } 743 744 /* The AutoNeg process has completed, so we now need to 745 * read both the Auto Negotiation Advertisement 746 * Register (Address 4) and the Auto_Negotiation Base 747 * Page Ability Register (Address 5) to determine how 748 * flow control was negotiated. 749 */ 750 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 751 &mii_nway_adv_reg); 752 if (ret_val) 753 return ret_val; 754 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 755 &mii_nway_lp_ability_reg); 756 if (ret_val) 757 return ret_val; 758 759 /* Two bits in the Auto Negotiation Advertisement Register 760 * (Address 4) and two bits in the Auto Negotiation Base 761 * Page Ability Register (Address 5) determine flow control 762 * for both the PHY and the link partner. The following 763 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 764 * 1999, describes these PAUSE resolution bits and how flow 765 * control is determined based upon these settings. 766 * NOTE: DC = Don't Care 767 * 768 * LOCAL DEVICE | LINK PARTNER 769 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 770 *-------|---------|-------|---------|-------------------- 771 * 0 | 0 | DC | DC | igc_fc_none 772 * 0 | 1 | 0 | DC | igc_fc_none 773 * 0 | 1 | 1 | 0 | igc_fc_none 774 * 0 | 1 | 1 | 1 | igc_fc_tx_pause 775 * 1 | 0 | 0 | DC | igc_fc_none 776 * 1 | DC | 1 | DC | igc_fc_full 777 * 1 | 1 | 0 | 0 | igc_fc_none 778 * 1 | 1 | 0 | 1 | igc_fc_rx_pause 779 * 780 * Are both PAUSE bits set to 1? If so, this implies 781 * Symmetric Flow Control is enabled at both ends. The 782 * ASM_DIR bits are irrelevant per the spec. 783 * 784 * For Symmetric Flow Control: 785 * 786 * LOCAL DEVICE | LINK PARTNER 787 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 788 *-------|---------|-------|---------|-------------------- 789 * 1 | DC | 1 | DC | IGC_fc_full 790 * 791 */ 792 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 793 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 794 /* Now we need to check if the user selected Rx ONLY 795 * of pause frames. In this case, we had to advertise 796 * FULL flow control because we could not advertise Rx 797 * ONLY. Hence, we must now check to see if we need to 798 * turn OFF the TRANSMISSION of PAUSE frames. 799 */ 800 if (hw->fc.requested_mode == igc_fc_full) { 801 hw->fc.current_mode = igc_fc_full; 802 DEBUGOUT("Flow Control = FULL.\n"); 803 } else { 804 hw->fc.current_mode = igc_fc_rx_pause; 805 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 806 } 807 } 808 /* For receiving PAUSE frames ONLY. 809 * 810 * LOCAL DEVICE | LINK PARTNER 811 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 812 *-------|---------|-------|---------|-------------------- 813 * 0 | 1 | 1 | 1 | igc_fc_tx_pause 814 */ 815 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 816 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 817 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 818 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 819 hw->fc.current_mode = igc_fc_tx_pause; 820 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 821 } 822 /* For transmitting PAUSE frames ONLY. 823 * 824 * LOCAL DEVICE | LINK PARTNER 825 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 826 *-------|---------|-------|---------|-------------------- 827 * 1 | 1 | 0 | 1 | igc_fc_rx_pause 828 */ 829 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 830 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 831 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 832 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 833 hw->fc.current_mode = igc_fc_rx_pause; 834 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 835 } else { 836 /* Per the IEEE spec, at this point flow control 837 * should be disabled. 838 */ 839 hw->fc.current_mode = igc_fc_none; 840 DEBUGOUT("Flow Control = NONE.\n"); 841 } 842 843 /* Now we need to do one last check... If we auto- 844 * negotiated to HALF DUPLEX, flow control should not be 845 * enabled per IEEE 802.3 spec. 846 */ 847 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 848 if (ret_val) { 849 DEBUGOUT("Error getting link speed and duplex\n"); 850 return ret_val; 851 } 852 853 if (duplex == HALF_DUPLEX) 854 hw->fc.current_mode = igc_fc_none; 855 856 /* Now we call a subroutine to actually force the MAC 857 * controller to use the correct flow control settings. 858 */ 859 ret_val = igc_force_mac_fc_generic(hw); 860 if (ret_val) { 861 DEBUGOUT("Error forcing flow control settings\n"); 862 return ret_val; 863 } 864 } 865 866 return IGC_SUCCESS; 867 } 868 869 /** 870 * igc_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 871 * @hw: pointer to the HW structure 872 * @speed: stores the current speed 873 * @duplex: stores the current duplex 874 * 875 * Read the status register for the current speed/duplex and store the current 876 * speed and duplex for copper connections. 877 **/ 878 s32 igc_get_speed_and_duplex_copper_generic(struct igc_hw *hw, u16 *speed, 879 u16 *duplex) 880 { 881 u32 status; 882 883 DEBUGFUNC("igc_get_speed_and_duplex_copper_generic"); 884 885 status = IGC_READ_REG(hw, IGC_STATUS); 886 if (status & IGC_STATUS_SPEED_1000) { 887 /* For I225, STATUS will indicate 1G speed in both 1 Gbps 888 * and 2.5 Gbps link modes. An additional bit is used 889 * to differentiate between 1 Gbps and 2.5 Gbps. 890 */ 891 if ((hw->mac.type == igc_i225) && 892 (status & IGC_STATUS_SPEED_2500)) { 893 *speed = SPEED_2500; 894 DEBUGOUT("2500 Mbs, "); 895 } else { 896 *speed = SPEED_1000; 897 DEBUGOUT("1000 Mbs, "); 898 } 899 } else if (status & IGC_STATUS_SPEED_100) { 900 *speed = SPEED_100; 901 DEBUGOUT("100 Mbs, "); 902 } else { 903 *speed = SPEED_10; 904 DEBUGOUT("10 Mbs, "); 905 } 906 907 if (status & IGC_STATUS_FD) { 908 *duplex = FULL_DUPLEX; 909 DEBUGOUT("Full Duplex\n"); 910 } else { 911 *duplex = HALF_DUPLEX; 912 DEBUGOUT("Half Duplex\n"); 913 } 914 915 return IGC_SUCCESS; 916 } 917 918 /** 919 * igc_get_hw_semaphore_generic - Acquire hardware semaphore 920 * @hw: pointer to the HW structure 921 * 922 * Acquire the HW semaphore to access the PHY or NVM 923 **/ 924 s32 igc_get_hw_semaphore_generic(struct igc_hw *hw) 925 { 926 u32 swsm; 927 s32 timeout = hw->nvm.word_size + 1; 928 s32 i = 0; 929 930 DEBUGFUNC("igc_get_hw_semaphore_generic"); 931 932 /* Get the SW semaphore */ 933 while (i < timeout) { 934 swsm = IGC_READ_REG(hw, IGC_SWSM); 935 if (!(swsm & IGC_SWSM_SMBI)) 936 break; 937 938 usec_delay(50); 939 i++; 940 } 941 942 if (i == timeout) { 943 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 944 return -IGC_ERR_NVM; 945 } 946 947 /* Get the FW semaphore. */ 948 for (i = 0; i < timeout; i++) { 949 swsm = IGC_READ_REG(hw, IGC_SWSM); 950 IGC_WRITE_REG(hw, IGC_SWSM, swsm | IGC_SWSM_SWESMBI); 951 952 /* Semaphore acquired if bit latched */ 953 if (IGC_READ_REG(hw, IGC_SWSM) & IGC_SWSM_SWESMBI) 954 break; 955 956 usec_delay(50); 957 } 958 959 if (i == timeout) { 960 /* Release semaphores */ 961 igc_put_hw_semaphore_generic(hw); 962 DEBUGOUT("Driver can't access the NVM\n"); 963 return -IGC_ERR_NVM; 964 } 965 966 return IGC_SUCCESS; 967 } 968 969 /** 970 * igc_put_hw_semaphore_generic - Release hardware semaphore 971 * @hw: pointer to the HW structure 972 * 973 * Release hardware semaphore used to access the PHY or NVM 974 **/ 975 void igc_put_hw_semaphore_generic(struct igc_hw *hw) 976 { 977 u32 swsm; 978 979 DEBUGFUNC("igc_put_hw_semaphore_generic"); 980 981 swsm = IGC_READ_REG(hw, IGC_SWSM); 982 983 swsm &= ~(IGC_SWSM_SMBI | IGC_SWSM_SWESMBI); 984 985 IGC_WRITE_REG(hw, IGC_SWSM, swsm); 986 } 987 988 /** 989 * igc_get_auto_rd_done_generic - Check for auto read completion 990 * @hw: pointer to the HW structure 991 * 992 * Check EEPROM for Auto Read done bit. 993 **/ 994 s32 igc_get_auto_rd_done_generic(struct igc_hw *hw) 995 { 996 s32 i = 0; 997 998 DEBUGFUNC("igc_get_auto_rd_done_generic"); 999 1000 while (i < AUTO_READ_DONE_TIMEOUT) { 1001 if (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_AUTO_RD) 1002 break; 1003 msec_delay(1); 1004 i++; 1005 } 1006 1007 if (i == AUTO_READ_DONE_TIMEOUT) { 1008 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1009 return -IGC_ERR_RESET; 1010 } 1011 1012 return IGC_SUCCESS; 1013 } 1014 1015 /** 1016 * igc_disable_pcie_master_generic - Disables PCI-express master access 1017 * @hw: pointer to the HW structure 1018 * 1019 * Returns IGC_SUCCESS if successful, else returns -10 1020 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 1021 * the master requests to be disabled. 1022 * 1023 * Disables PCI-Express master access and verifies there are no pending 1024 * requests. 1025 **/ 1026 s32 igc_disable_pcie_master_generic(struct igc_hw *hw) 1027 { 1028 u32 ctrl; 1029 s32 timeout = MASTER_DISABLE_TIMEOUT; 1030 1031 DEBUGFUNC("igc_disable_pcie_master_generic"); 1032 1033 ctrl = IGC_READ_REG(hw, IGC_CTRL); 1034 ctrl |= IGC_CTRL_GIO_MASTER_DISABLE; 1035 IGC_WRITE_REG(hw, IGC_CTRL, ctrl); 1036 1037 while (timeout) { 1038 if (!(IGC_READ_REG(hw, IGC_STATUS) & 1039 IGC_STATUS_GIO_MASTER_ENABLE)) 1040 break; 1041 usec_delay(100); 1042 timeout--; 1043 } 1044 1045 if (!timeout) { 1046 DEBUGOUT("Master requests are pending.\n"); 1047 return -IGC_ERR_MASTER_REQUESTS_PENDING; 1048 } 1049 1050 return IGC_SUCCESS; 1051 } 1052