1 /*- 2 * Copyright 2021 Intel Corp 3 * Copyright 2021 Rubicon Communications, LLC (Netgate) 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <sys/cdefs.h> 8 #include "igc_api.h" 9 10 static void igc_config_collision_dist_generic(struct igc_hw *hw); 11 12 /** 13 * igc_init_mac_ops_generic - Initialize MAC function pointers 14 * @hw: pointer to the HW structure 15 * 16 * Setups up the function pointers to no-op functions 17 **/ 18 void igc_init_mac_ops_generic(struct igc_hw *hw) 19 { 20 struct igc_mac_info *mac = &hw->mac; 21 DEBUGFUNC("igc_init_mac_ops_generic"); 22 23 /* General Setup */ 24 mac->ops.init_params = igc_null_ops_generic; 25 mac->ops.config_collision_dist = igc_config_collision_dist_generic; 26 mac->ops.rar_set = igc_rar_set_generic; 27 } 28 29 /** 30 * igc_null_ops_generic - No-op function, returns 0 31 * @hw: pointer to the HW structure 32 **/ 33 s32 igc_null_ops_generic(struct igc_hw IGC_UNUSEDARG *hw) 34 { 35 DEBUGFUNC("igc_null_ops_generic"); 36 return IGC_SUCCESS; 37 } 38 39 /** 40 * igc_null_mac_generic - No-op function, return void 41 * @hw: pointer to the HW structure 42 **/ 43 void igc_null_mac_generic(struct igc_hw IGC_UNUSEDARG *hw) 44 { 45 DEBUGFUNC("igc_null_mac_generic"); 46 return; 47 } 48 49 /** 50 * igc_null_link_info - No-op function, return 0 51 * @hw: pointer to the HW structure 52 * @s: dummy variable 53 * @d: dummy variable 54 **/ 55 s32 igc_null_link_info(struct igc_hw IGC_UNUSEDARG *hw, 56 u16 IGC_UNUSEDARG *s, u16 IGC_UNUSEDARG *d) 57 { 58 DEBUGFUNC("igc_null_link_info"); 59 return IGC_SUCCESS; 60 } 61 62 /** 63 * igc_null_mng_mode - No-op function, return false 64 * @hw: pointer to the HW structure 65 **/ 66 bool igc_null_mng_mode(struct igc_hw IGC_UNUSEDARG *hw) 67 { 68 DEBUGFUNC("igc_null_mng_mode"); 69 return false; 70 } 71 72 /** 73 * igc_null_update_mc - No-op function, return void 74 * @hw: pointer to the HW structure 75 * @h: dummy variable 76 * @a: dummy variable 77 **/ 78 void igc_null_update_mc(struct igc_hw IGC_UNUSEDARG *hw, 79 u8 IGC_UNUSEDARG *h, u32 IGC_UNUSEDARG a) 80 { 81 DEBUGFUNC("igc_null_update_mc"); 82 return; 83 } 84 85 /** 86 * igc_null_write_vfta - No-op function, return void 87 * @hw: pointer to the HW structure 88 * @a: dummy variable 89 * @b: dummy variable 90 **/ 91 void igc_null_write_vfta(struct igc_hw IGC_UNUSEDARG *hw, 92 u32 IGC_UNUSEDARG a, u32 IGC_UNUSEDARG b) 93 { 94 DEBUGFUNC("igc_null_write_vfta"); 95 return; 96 } 97 98 /** 99 * igc_null_rar_set - No-op function, return 0 100 * @hw: pointer to the HW structure 101 * @h: dummy variable 102 * @a: dummy variable 103 **/ 104 int igc_null_rar_set(struct igc_hw IGC_UNUSEDARG *hw, 105 u8 IGC_UNUSEDARG *h, u32 IGC_UNUSEDARG a) 106 { 107 DEBUGFUNC("igc_null_rar_set"); 108 return IGC_SUCCESS; 109 } 110 111 /** 112 * igc_set_lan_id_single_port - Set LAN id for a single port device 113 * @hw: pointer to the HW structure 114 * 115 * Sets the LAN function id to zero for a single port device. 116 **/ 117 void igc_set_lan_id_single_port(struct igc_hw *hw) 118 { 119 struct igc_bus_info *bus = &hw->bus; 120 121 bus->func = 0; 122 } 123 124 /** 125 * igc_clear_vfta_generic - Clear VLAN filter table 126 * @hw: pointer to the HW structure 127 * 128 * Clears the register array which contains the VLAN filter table by 129 * setting all the values to 0. 130 **/ 131 void igc_clear_vfta_generic(struct igc_hw *hw) 132 { 133 u32 offset; 134 135 DEBUGFUNC("igc_clear_vfta_generic"); 136 137 for (offset = 0; offset < IGC_VLAN_FILTER_TBL_SIZE; offset++) { 138 IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, 0); 139 IGC_WRITE_FLUSH(hw); 140 } 141 } 142 143 /** 144 * igc_write_vfta_generic - Write value to VLAN filter table 145 * @hw: pointer to the HW structure 146 * @offset: register offset in VLAN filter table 147 * @value: register value written to VLAN filter table 148 * 149 * Writes value at the given offset in the register array which stores 150 * the VLAN filter table. 151 **/ 152 void igc_write_vfta_generic(struct igc_hw *hw, u32 offset, u32 value) 153 { 154 DEBUGFUNC("igc_write_vfta_generic"); 155 156 IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, value); 157 IGC_WRITE_FLUSH(hw); 158 } 159 160 /** 161 * igc_init_rx_addrs_generic - Initialize receive address's 162 * @hw: pointer to the HW structure 163 * @rar_count: receive address registers 164 * 165 * Setup the receive address registers by setting the base receive address 166 * register to the devices MAC address and clearing all the other receive 167 * address registers to 0. 168 **/ 169 void igc_init_rx_addrs_generic(struct igc_hw *hw, u16 rar_count) 170 { 171 u32 i; 172 u8 mac_addr[ETH_ADDR_LEN] = {0}; 173 174 DEBUGFUNC("igc_init_rx_addrs_generic"); 175 176 /* Setup the receive address */ 177 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 178 179 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 180 181 /* Zero out the other (rar_entry_count - 1) receive addresses */ 182 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 183 for (i = 1; i < rar_count; i++) 184 hw->mac.ops.rar_set(hw, mac_addr, i); 185 } 186 187 /** 188 * igc_check_alt_mac_addr_generic - Check for alternate MAC addr 189 * @hw: pointer to the HW structure 190 * 191 * Checks the nvm for an alternate MAC address. An alternate MAC address 192 * can be setup by pre-boot software and must be treated like a permanent 193 * address and must override the actual permanent MAC address. If an 194 * alternate MAC address is found it is programmed into RAR0, replacing 195 * the permanent address that was installed into RAR0 by the Si on reset. 196 * This function will return SUCCESS unless it encounters an error while 197 * reading the EEPROM. 198 **/ 199 s32 igc_check_alt_mac_addr_generic(struct igc_hw *hw) 200 { 201 u32 i; 202 s32 ret_val; 203 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 204 u8 alt_mac_addr[ETH_ADDR_LEN]; 205 206 DEBUGFUNC("igc_check_alt_mac_addr_generic"); 207 208 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); 209 if (ret_val) 210 return ret_val; 211 212 213 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 214 &nvm_alt_mac_addr_offset); 215 if (ret_val) { 216 DEBUGOUT("NVM Read Error\n"); 217 return ret_val; 218 } 219 220 if ((nvm_alt_mac_addr_offset == 0xFFFF) || 221 (nvm_alt_mac_addr_offset == 0x0000)) 222 /* There is no Alternate MAC Address */ 223 return IGC_SUCCESS; 224 225 if (hw->bus.func == IGC_FUNC_1) 226 nvm_alt_mac_addr_offset += IGC_ALT_MAC_ADDRESS_OFFSET_LAN1; 227 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 228 offset = nvm_alt_mac_addr_offset + (i >> 1); 229 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 230 if (ret_val) { 231 DEBUGOUT("NVM Read Error\n"); 232 return ret_val; 233 } 234 235 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 236 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 237 } 238 239 /* if multicast bit is set, the alternate address will not be used */ 240 if (alt_mac_addr[0] & 0x01) { 241 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 242 return IGC_SUCCESS; 243 } 244 245 /* We have a valid alternate MAC address, and we want to treat it the 246 * same as the normal permanent MAC address stored by the HW into the 247 * RAR. Do this by mapping this address into RAR0. 248 */ 249 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 250 251 return IGC_SUCCESS; 252 } 253 254 /** 255 * igc_rar_set_generic - Set receive address register 256 * @hw: pointer to the HW structure 257 * @addr: pointer to the receive address 258 * @index: receive address array register 259 * 260 * Sets the receive address array register at index to the address passed 261 * in by addr. 262 **/ 263 int igc_rar_set_generic(struct igc_hw *hw, u8 *addr, u32 index) 264 { 265 u32 rar_low, rar_high; 266 267 DEBUGFUNC("igc_rar_set_generic"); 268 269 /* HW expects these in little endian so we reverse the byte order 270 * from network order (big endian) to little endian 271 */ 272 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 273 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 274 275 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 276 277 /* If MAC address zero, no need to set the AV bit */ 278 if (rar_low || rar_high) 279 rar_high |= IGC_RAH_AV; 280 281 /* Some bridges will combine consecutive 32-bit writes into 282 * a single burst write, which will malfunction on some parts. 283 * The flushes avoid this. 284 */ 285 IGC_WRITE_REG(hw, IGC_RAL(index), rar_low); 286 IGC_WRITE_FLUSH(hw); 287 IGC_WRITE_REG(hw, IGC_RAH(index), rar_high); 288 IGC_WRITE_FLUSH(hw); 289 290 return IGC_SUCCESS; 291 } 292 293 /** 294 * igc_hash_mc_addr_generic - Generate a multicast hash value 295 * @hw: pointer to the HW structure 296 * @mc_addr: pointer to a multicast address 297 * 298 * Generates a multicast address hash value which is used to determine 299 * the multicast filter table array address and new table value. 300 **/ 301 u32 igc_hash_mc_addr_generic(struct igc_hw *hw, u8 *mc_addr) 302 { 303 u32 hash_value, hash_mask; 304 u8 bit_shift = 0; 305 306 DEBUGFUNC("igc_hash_mc_addr_generic"); 307 308 /* Register count multiplied by bits per register */ 309 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 310 311 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts 312 * where 0xFF would still fall within the hash mask. 313 */ 314 while (hash_mask >> bit_shift != 0xFF) 315 bit_shift++; 316 317 /* The portion of the address that is used for the hash table 318 * is determined by the mc_filter_type setting. 319 * The algorithm is such that there is a total of 8 bits of shifting. 320 * The bit_shift for a mc_filter_type of 0 represents the number of 321 * left-shifts where the MSB of mc_addr[5] would still fall within 322 * the hash_mask. Case 0 does this exactly. Since there are a total 323 * of 8 bits of shifting, then mc_addr[4] will shift right the 324 * remaining number of bits. Thus 8 - bit_shift. The rest of the 325 * cases are a variation of this algorithm...essentially raising the 326 * number of bits to shift mc_addr[5] left, while still keeping the 327 * 8-bit shifting total. 328 * 329 * For example, given the following Destination MAC Address and an 330 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 331 * we can see that the bit_shift for case 0 is 4. These are the hash 332 * values resulting from each mc_filter_type... 333 * [0] [1] [2] [3] [4] [5] 334 * 01 AA 00 12 34 56 335 * LSB MSB 336 * 337 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 338 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 339 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 340 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 341 */ 342 switch (hw->mac.mc_filter_type) { 343 default: 344 case 0: 345 break; 346 case 1: 347 bit_shift += 1; 348 break; 349 case 2: 350 bit_shift += 2; 351 break; 352 case 3: 353 bit_shift += 4; 354 break; 355 } 356 357 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 358 (((u16) mc_addr[5]) << bit_shift))); 359 360 return hash_value; 361 } 362 363 /** 364 * igc_update_mc_addr_list_generic - Update Multicast addresses 365 * @hw: pointer to the HW structure 366 * @mc_addr_list: array of multicast addresses to program 367 * @mc_addr_count: number of multicast addresses to program 368 * 369 * Updates entire Multicast Table Array. 370 * The caller must have a packed mc_addr_list of multicast addresses. 371 **/ 372 void igc_update_mc_addr_list_generic(struct igc_hw *hw, 373 u8 *mc_addr_list, u32 mc_addr_count) 374 { 375 u32 hash_value, hash_bit, hash_reg; 376 int i; 377 378 DEBUGFUNC("igc_update_mc_addr_list_generic"); 379 380 /* clear mta_shadow */ 381 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 382 383 /* update mta_shadow from mc_addr_list */ 384 for (i = 0; (u32) i < mc_addr_count; i++) { 385 hash_value = igc_hash_mc_addr_generic(hw, mc_addr_list); 386 387 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 388 hash_bit = hash_value & 0x1F; 389 390 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 391 mc_addr_list += (ETH_ADDR_LEN); 392 } 393 394 /* replace the entire MTA table */ 395 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 396 IGC_WRITE_REG_ARRAY(hw, IGC_MTA, i, hw->mac.mta_shadow[i]); 397 IGC_WRITE_FLUSH(hw); 398 } 399 400 /** 401 * igc_clear_hw_cntrs_base_generic - Clear base hardware counters 402 * @hw: pointer to the HW structure 403 * 404 * Clears the base hardware counters by reading the counter registers. 405 **/ 406 void igc_clear_hw_cntrs_base_generic(struct igc_hw *hw) 407 { 408 DEBUGFUNC("igc_clear_hw_cntrs_base_generic"); 409 410 IGC_READ_REG(hw, IGC_CRCERRS); 411 IGC_READ_REG(hw, IGC_RXERRC); 412 IGC_READ_REG(hw, IGC_MPC); 413 IGC_READ_REG(hw, IGC_SCC); 414 IGC_READ_REG(hw, IGC_ECOL); 415 IGC_READ_REG(hw, IGC_MCC); 416 IGC_READ_REG(hw, IGC_LATECOL); 417 IGC_READ_REG(hw, IGC_COLC); 418 IGC_READ_REG(hw, IGC_RERC); 419 IGC_READ_REG(hw, IGC_DC); 420 IGC_READ_REG(hw, IGC_RLEC); 421 IGC_READ_REG(hw, IGC_XONRXC); 422 IGC_READ_REG(hw, IGC_XONTXC); 423 IGC_READ_REG(hw, IGC_XOFFRXC); 424 IGC_READ_REG(hw, IGC_XOFFTXC); 425 IGC_READ_REG(hw, IGC_FCRUC); 426 IGC_READ_REG(hw, IGC_GPRC); 427 IGC_READ_REG(hw, IGC_BPRC); 428 IGC_READ_REG(hw, IGC_MPRC); 429 IGC_READ_REG(hw, IGC_GPTC); 430 IGC_READ_REG(hw, IGC_GORCL); 431 IGC_READ_REG(hw, IGC_GORCH); 432 IGC_READ_REG(hw, IGC_GOTCL); 433 IGC_READ_REG(hw, IGC_GOTCH); 434 IGC_READ_REG(hw, IGC_RNBC); 435 IGC_READ_REG(hw, IGC_RUC); 436 IGC_READ_REG(hw, IGC_RFC); 437 IGC_READ_REG(hw, IGC_ROC); 438 IGC_READ_REG(hw, IGC_RJC); 439 IGC_READ_REG(hw, IGC_TORL); 440 IGC_READ_REG(hw, IGC_TORH); 441 IGC_READ_REG(hw, IGC_TOTL); 442 IGC_READ_REG(hw, IGC_TOTH); 443 IGC_READ_REG(hw, IGC_TPR); 444 IGC_READ_REG(hw, IGC_TPT); 445 IGC_READ_REG(hw, IGC_MPTC); 446 IGC_READ_REG(hw, IGC_BPTC); 447 IGC_READ_REG(hw, IGC_TLPIC); 448 IGC_READ_REG(hw, IGC_RLPIC); 449 IGC_READ_REG(hw, IGC_RXDMTC); 450 } 451 452 /** 453 * igc_check_for_copper_link_generic - Check for link (Copper) 454 * @hw: pointer to the HW structure 455 * 456 * Checks to see of the link status of the hardware has changed. If a 457 * change in link status has been detected, then we read the PHY registers 458 * to get the current speed/duplex if link exists. 459 **/ 460 s32 igc_check_for_copper_link_generic(struct igc_hw *hw) 461 { 462 struct igc_mac_info *mac = &hw->mac; 463 s32 ret_val; 464 bool link = false; 465 466 DEBUGFUNC("igc_check_for_copper_link"); 467 468 /* We only want to go out to the PHY registers to see if Auto-Neg 469 * has completed and/or if our link status has changed. The 470 * get_link_status flag is set upon receiving a Link Status 471 * Change or Rx Sequence Error interrupt. 472 */ 473 if (!mac->get_link_status) 474 return IGC_SUCCESS; 475 476 /* First we want to see if the MII Status Register reports 477 * link. If so, then we want to get the current speed/duplex 478 * of the PHY. 479 */ 480 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link); 481 if (ret_val) 482 return ret_val; 483 484 if (!link) 485 return IGC_SUCCESS; /* No link detected */ 486 487 mac->get_link_status = false; 488 489 /* Check if there was DownShift, must be checked 490 * immediately after link-up 491 */ 492 igc_check_downshift_generic(hw); 493 494 /* If we are forcing speed/duplex, then we simply return since 495 * we have already determined whether we have link or not. 496 */ 497 if (!mac->autoneg) 498 return -IGC_ERR_CONFIG; 499 500 /* Auto-Neg is enabled. Auto Speed Detection takes care 501 * of MAC speed/duplex configuration. So we only need to 502 * configure Collision Distance in the MAC. 503 */ 504 mac->ops.config_collision_dist(hw); 505 506 /* Configure Flow Control now that Auto-Neg has completed. 507 * First, we need to restore the desired flow control 508 * settings because we may have had to re-autoneg with a 509 * different link partner. 510 */ 511 ret_val = igc_config_fc_after_link_up_generic(hw); 512 if (ret_val) 513 DEBUGOUT("Error configuring flow control\n"); 514 515 return ret_val; 516 } 517 518 /** 519 * igc_setup_link_generic - Setup flow control and link settings 520 * @hw: pointer to the HW structure 521 * 522 * Determines which flow control settings to use, then configures flow 523 * control. Calls the appropriate media-specific link configuration 524 * function. Assuming the adapter has a valid link partner, a valid link 525 * should be established. Assumes the hardware has previously been reset 526 * and the transmitter and receiver are not enabled. 527 **/ 528 s32 igc_setup_link_generic(struct igc_hw *hw) 529 { 530 s32 ret_val; 531 532 DEBUGFUNC("igc_setup_link_generic"); 533 534 /* In the case of the phy reset being blocked, we already have a link. 535 * We do not need to set it up again. 536 */ 537 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 538 return IGC_SUCCESS; 539 540 /* If requested flow control is set to default, set flow control 541 * for both 'rx' and 'tx' pause frames. 542 */ 543 if (hw->fc.requested_mode == igc_fc_default) { 544 hw->fc.requested_mode = igc_fc_full; 545 } 546 547 /* Save off the requested flow control mode for use later. Depending 548 * on the link partner's capabilities, we may or may not use this mode. 549 */ 550 hw->fc.current_mode = hw->fc.requested_mode; 551 552 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 553 hw->fc.current_mode); 554 555 /* Call the necessary media_type subroutine to configure the link. */ 556 ret_val = hw->mac.ops.setup_physical_interface(hw); 557 if (ret_val) 558 return ret_val; 559 560 /* Initialize the flow control address, type, and PAUSE timer 561 * registers to their default values. This is done even if flow 562 * control is disabled, because it does not hurt anything to 563 * initialize these registers. 564 */ 565 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 566 IGC_WRITE_REG(hw, IGC_FCT, FLOW_CONTROL_TYPE); 567 IGC_WRITE_REG(hw, IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 568 IGC_WRITE_REG(hw, IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW); 569 570 IGC_WRITE_REG(hw, IGC_FCTTV, hw->fc.pause_time); 571 572 return igc_set_fc_watermarks_generic(hw); 573 } 574 575 /** 576 * igc_config_collision_dist_generic - Configure collision distance 577 * @hw: pointer to the HW structure 578 * 579 * Configures the collision distance to the default value and is used 580 * during link setup. 581 **/ 582 static void igc_config_collision_dist_generic(struct igc_hw *hw) 583 { 584 u32 tctl; 585 586 DEBUGFUNC("igc_config_collision_dist_generic"); 587 588 tctl = IGC_READ_REG(hw, IGC_TCTL); 589 590 tctl &= ~IGC_TCTL_COLD; 591 tctl |= IGC_COLLISION_DISTANCE << IGC_COLD_SHIFT; 592 593 IGC_WRITE_REG(hw, IGC_TCTL, tctl); 594 IGC_WRITE_FLUSH(hw); 595 } 596 597 /** 598 * igc_set_fc_watermarks_generic - Set flow control high/low watermarks 599 * @hw: pointer to the HW structure 600 * 601 * Sets the flow control high/low threshold (watermark) registers. If 602 * flow control XON frame transmission is enabled, then set XON frame 603 * transmission as well. 604 **/ 605 s32 igc_set_fc_watermarks_generic(struct igc_hw *hw) 606 { 607 u32 fcrtl = 0, fcrth = 0; 608 609 DEBUGFUNC("igc_set_fc_watermarks_generic"); 610 611 /* Set the flow control receive threshold registers. Normally, 612 * these registers will be set to a default threshold that may be 613 * adjusted later by the driver's runtime code. However, if the 614 * ability to transmit pause frames is not enabled, then these 615 * registers will be set to 0. 616 */ 617 if (hw->fc.current_mode & igc_fc_tx_pause) { 618 /* We need to set up the Receive Threshold high and low water 619 * marks as well as (optionally) enabling the transmission of 620 * XON frames. 621 */ 622 fcrtl = hw->fc.low_water; 623 if (hw->fc.send_xon) 624 fcrtl |= IGC_FCRTL_XONE; 625 626 fcrth = hw->fc.high_water; 627 } 628 IGC_WRITE_REG(hw, IGC_FCRTL, fcrtl); 629 IGC_WRITE_REG(hw, IGC_FCRTH, fcrth); 630 631 return IGC_SUCCESS; 632 } 633 634 /** 635 * igc_force_mac_fc_generic - Force the MAC's flow control settings 636 * @hw: pointer to the HW structure 637 * 638 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 639 * device control register to reflect the adapter settings. TFCE and RFCE 640 * need to be explicitly set by software when a copper PHY is used because 641 * autonegotiation is managed by the PHY rather than the MAC. Software must 642 * also configure these bits when link is forced on a fiber connection. 643 **/ 644 s32 igc_force_mac_fc_generic(struct igc_hw *hw) 645 { 646 u32 ctrl; 647 648 DEBUGFUNC("igc_force_mac_fc_generic"); 649 650 ctrl = IGC_READ_REG(hw, IGC_CTRL); 651 652 /* Because we didn't get link via the internal auto-negotiation 653 * mechanism (we either forced link or we got link via PHY 654 * auto-neg), we have to manually enable/disable transmit an 655 * receive flow control. 656 * 657 * The "Case" statement below enables/disable flow control 658 * according to the "hw->fc.current_mode" parameter. 659 * 660 * The possible values of the "fc" parameter are: 661 * 0: Flow control is completely disabled 662 * 1: Rx flow control is enabled (we can receive pause 663 * frames but not send pause frames). 664 * 2: Tx flow control is enabled (we can send pause frames 665 * frames but we do not receive pause frames). 666 * 3: Both Rx and Tx flow control (symmetric) is enabled. 667 * other: No other values should be possible at this point. 668 */ 669 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 670 671 switch (hw->fc.current_mode) { 672 case igc_fc_none: 673 ctrl &= (~(IGC_CTRL_TFCE | IGC_CTRL_RFCE)); 674 break; 675 case igc_fc_rx_pause: 676 ctrl &= (~IGC_CTRL_TFCE); 677 ctrl |= IGC_CTRL_RFCE; 678 break; 679 case igc_fc_tx_pause: 680 ctrl &= (~IGC_CTRL_RFCE); 681 ctrl |= IGC_CTRL_TFCE; 682 break; 683 case igc_fc_full: 684 ctrl |= (IGC_CTRL_TFCE | IGC_CTRL_RFCE); 685 break; 686 default: 687 DEBUGOUT("Flow control param set incorrectly\n"); 688 return -IGC_ERR_CONFIG; 689 } 690 691 IGC_WRITE_REG(hw, IGC_CTRL, ctrl); 692 693 return IGC_SUCCESS; 694 } 695 696 /** 697 * igc_config_fc_after_link_up_generic - Configures flow control after link 698 * @hw: pointer to the HW structure 699 * 700 * Checks the status of auto-negotiation after link up to ensure that the 701 * speed and duplex were not forced. If the link needed to be forced, then 702 * flow control needs to be forced also. If auto-negotiation is enabled 703 * and did not fail, then we configure flow control based on our link 704 * partner. 705 **/ 706 s32 igc_config_fc_after_link_up_generic(struct igc_hw *hw) 707 { 708 struct igc_mac_info *mac = &hw->mac; 709 s32 ret_val = IGC_SUCCESS; 710 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 711 u16 speed, duplex; 712 713 DEBUGFUNC("igc_config_fc_after_link_up_generic"); 714 715 if (ret_val) { 716 DEBUGOUT("Error forcing flow control settings\n"); 717 return ret_val; 718 } 719 720 /* Check for the case where we have copper media and auto-neg is 721 * enabled. In this case, we need to check and see if Auto-Neg 722 * has completed, and if so, how the PHY and link partner has 723 * flow control configured. 724 */ 725 if (mac->autoneg) { 726 /* Read the MII Status Register and check to see if AutoNeg 727 * has completed. We read this twice because this reg has 728 * some "sticky" (latched) bits. 729 */ 730 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 731 if (ret_val) 732 return ret_val; 733 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 734 if (ret_val) 735 return ret_val; 736 737 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 738 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); 739 return ret_val; 740 } 741 742 /* The AutoNeg process has completed, so we now need to 743 * read both the Auto Negotiation Advertisement 744 * Register (Address 4) and the Auto_Negotiation Base 745 * Page Ability Register (Address 5) to determine how 746 * flow control was negotiated. 747 */ 748 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 749 &mii_nway_adv_reg); 750 if (ret_val) 751 return ret_val; 752 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 753 &mii_nway_lp_ability_reg); 754 if (ret_val) 755 return ret_val; 756 757 /* Two bits in the Auto Negotiation Advertisement Register 758 * (Address 4) and two bits in the Auto Negotiation Base 759 * Page Ability Register (Address 5) determine flow control 760 * for both the PHY and the link partner. The following 761 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 762 * 1999, describes these PAUSE resolution bits and how flow 763 * control is determined based upon these settings. 764 * NOTE: DC = Don't Care 765 * 766 * LOCAL DEVICE | LINK PARTNER 767 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 768 *-------|---------|-------|---------|-------------------- 769 * 0 | 0 | DC | DC | igc_fc_none 770 * 0 | 1 | 0 | DC | igc_fc_none 771 * 0 | 1 | 1 | 0 | igc_fc_none 772 * 0 | 1 | 1 | 1 | igc_fc_tx_pause 773 * 1 | 0 | 0 | DC | igc_fc_none 774 * 1 | DC | 1 | DC | igc_fc_full 775 * 1 | 1 | 0 | 0 | igc_fc_none 776 * 1 | 1 | 0 | 1 | igc_fc_rx_pause 777 * 778 * Are both PAUSE bits set to 1? If so, this implies 779 * Symmetric Flow Control is enabled at both ends. The 780 * ASM_DIR bits are irrelevant per the spec. 781 * 782 * For Symmetric Flow Control: 783 * 784 * LOCAL DEVICE | LINK PARTNER 785 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 786 *-------|---------|-------|---------|-------------------- 787 * 1 | DC | 1 | DC | IGC_fc_full 788 * 789 */ 790 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 791 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 792 /* Now we need to check if the user selected Rx ONLY 793 * of pause frames. In this case, we had to advertise 794 * FULL flow control because we could not advertise Rx 795 * ONLY. Hence, we must now check to see if we need to 796 * turn OFF the TRANSMISSION of PAUSE frames. 797 */ 798 if (hw->fc.requested_mode == igc_fc_full) { 799 hw->fc.current_mode = igc_fc_full; 800 DEBUGOUT("Flow Control = FULL.\n"); 801 } else { 802 hw->fc.current_mode = igc_fc_rx_pause; 803 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 804 } 805 } 806 /* For receiving PAUSE frames ONLY. 807 * 808 * LOCAL DEVICE | LINK PARTNER 809 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 810 *-------|---------|-------|---------|-------------------- 811 * 0 | 1 | 1 | 1 | igc_fc_tx_pause 812 */ 813 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 814 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 815 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 816 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 817 hw->fc.current_mode = igc_fc_tx_pause; 818 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); 819 } 820 /* For transmitting PAUSE frames ONLY. 821 * 822 * LOCAL DEVICE | LINK PARTNER 823 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 824 *-------|---------|-------|---------|-------------------- 825 * 1 | 1 | 0 | 1 | igc_fc_rx_pause 826 */ 827 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 828 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 829 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 830 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 831 hw->fc.current_mode = igc_fc_rx_pause; 832 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); 833 } else { 834 /* Per the IEEE spec, at this point flow control 835 * should be disabled. 836 */ 837 hw->fc.current_mode = igc_fc_none; 838 DEBUGOUT("Flow Control = NONE.\n"); 839 } 840 841 /* Now we need to do one last check... If we auto- 842 * negotiated to HALF DUPLEX, flow control should not be 843 * enabled per IEEE 802.3 spec. 844 */ 845 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 846 if (ret_val) { 847 DEBUGOUT("Error getting link speed and duplex\n"); 848 return ret_val; 849 } 850 851 if (duplex == HALF_DUPLEX) 852 hw->fc.current_mode = igc_fc_none; 853 854 /* Now we call a subroutine to actually force the MAC 855 * controller to use the correct flow control settings. 856 */ 857 ret_val = igc_force_mac_fc_generic(hw); 858 if (ret_val) { 859 DEBUGOUT("Error forcing flow control settings\n"); 860 return ret_val; 861 } 862 } 863 864 return IGC_SUCCESS; 865 } 866 867 /** 868 * igc_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 869 * @hw: pointer to the HW structure 870 * @speed: stores the current speed 871 * @duplex: stores the current duplex 872 * 873 * Read the status register for the current speed/duplex and store the current 874 * speed and duplex for copper connections. 875 **/ 876 s32 igc_get_speed_and_duplex_copper_generic(struct igc_hw *hw, u16 *speed, 877 u16 *duplex) 878 { 879 u32 status; 880 881 DEBUGFUNC("igc_get_speed_and_duplex_copper_generic"); 882 883 status = IGC_READ_REG(hw, IGC_STATUS); 884 if (status & IGC_STATUS_SPEED_1000) { 885 /* For I225, STATUS will indicate 1G speed in both 1 Gbps 886 * and 2.5 Gbps link modes. An additional bit is used 887 * to differentiate between 1 Gbps and 2.5 Gbps. 888 */ 889 if ((hw->mac.type == igc_i225) && 890 (status & IGC_STATUS_SPEED_2500)) { 891 *speed = SPEED_2500; 892 DEBUGOUT("2500 Mbs, "); 893 } else { 894 *speed = SPEED_1000; 895 DEBUGOUT("1000 Mbs, "); 896 } 897 } else if (status & IGC_STATUS_SPEED_100) { 898 *speed = SPEED_100; 899 DEBUGOUT("100 Mbs, "); 900 } else { 901 *speed = SPEED_10; 902 DEBUGOUT("10 Mbs, "); 903 } 904 905 if (status & IGC_STATUS_FD) { 906 *duplex = FULL_DUPLEX; 907 DEBUGOUT("Full Duplex\n"); 908 } else { 909 *duplex = HALF_DUPLEX; 910 DEBUGOUT("Half Duplex\n"); 911 } 912 913 return IGC_SUCCESS; 914 } 915 916 /** 917 * igc_get_hw_semaphore_generic - Acquire hardware semaphore 918 * @hw: pointer to the HW structure 919 * 920 * Acquire the HW semaphore to access the PHY or NVM 921 **/ 922 s32 igc_get_hw_semaphore_generic(struct igc_hw *hw) 923 { 924 u32 swsm; 925 s32 timeout = hw->nvm.word_size + 1; 926 s32 i = 0; 927 928 DEBUGFUNC("igc_get_hw_semaphore_generic"); 929 930 /* Get the SW semaphore */ 931 while (i < timeout) { 932 swsm = IGC_READ_REG(hw, IGC_SWSM); 933 if (!(swsm & IGC_SWSM_SMBI)) 934 break; 935 936 usec_delay(50); 937 i++; 938 } 939 940 if (i == timeout) { 941 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 942 return -IGC_ERR_NVM; 943 } 944 945 /* Get the FW semaphore. */ 946 for (i = 0; i < timeout; i++) { 947 swsm = IGC_READ_REG(hw, IGC_SWSM); 948 IGC_WRITE_REG(hw, IGC_SWSM, swsm | IGC_SWSM_SWESMBI); 949 950 /* Semaphore acquired if bit latched */ 951 if (IGC_READ_REG(hw, IGC_SWSM) & IGC_SWSM_SWESMBI) 952 break; 953 954 usec_delay(50); 955 } 956 957 if (i == timeout) { 958 /* Release semaphores */ 959 igc_put_hw_semaphore_generic(hw); 960 DEBUGOUT("Driver can't access the NVM\n"); 961 return -IGC_ERR_NVM; 962 } 963 964 return IGC_SUCCESS; 965 } 966 967 /** 968 * igc_put_hw_semaphore_generic - Release hardware semaphore 969 * @hw: pointer to the HW structure 970 * 971 * Release hardware semaphore used to access the PHY or NVM 972 **/ 973 void igc_put_hw_semaphore_generic(struct igc_hw *hw) 974 { 975 u32 swsm; 976 977 DEBUGFUNC("igc_put_hw_semaphore_generic"); 978 979 swsm = IGC_READ_REG(hw, IGC_SWSM); 980 981 swsm &= ~(IGC_SWSM_SMBI | IGC_SWSM_SWESMBI); 982 983 IGC_WRITE_REG(hw, IGC_SWSM, swsm); 984 } 985 986 /** 987 * igc_get_auto_rd_done_generic - Check for auto read completion 988 * @hw: pointer to the HW structure 989 * 990 * Check EEPROM for Auto Read done bit. 991 **/ 992 s32 igc_get_auto_rd_done_generic(struct igc_hw *hw) 993 { 994 s32 i = 0; 995 996 DEBUGFUNC("igc_get_auto_rd_done_generic"); 997 998 while (i < AUTO_READ_DONE_TIMEOUT) { 999 if (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_AUTO_RD) 1000 break; 1001 msec_delay(1); 1002 i++; 1003 } 1004 1005 if (i == AUTO_READ_DONE_TIMEOUT) { 1006 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1007 return -IGC_ERR_RESET; 1008 } 1009 1010 return IGC_SUCCESS; 1011 } 1012 1013 /** 1014 * igc_disable_pcie_master_generic - Disables PCI-express master access 1015 * @hw: pointer to the HW structure 1016 * 1017 * Returns IGC_SUCCESS if successful, else returns -10 1018 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 1019 * the master requests to be disabled. 1020 * 1021 * Disables PCI-Express master access and verifies there are no pending 1022 * requests. 1023 **/ 1024 s32 igc_disable_pcie_master_generic(struct igc_hw *hw) 1025 { 1026 u32 ctrl; 1027 s32 timeout = MASTER_DISABLE_TIMEOUT; 1028 1029 DEBUGFUNC("igc_disable_pcie_master_generic"); 1030 1031 ctrl = IGC_READ_REG(hw, IGC_CTRL); 1032 ctrl |= IGC_CTRL_GIO_MASTER_DISABLE; 1033 IGC_WRITE_REG(hw, IGC_CTRL, ctrl); 1034 1035 while (timeout) { 1036 if (!(IGC_READ_REG(hw, IGC_STATUS) & 1037 IGC_STATUS_GIO_MASTER_ENABLE)) 1038 break; 1039 usec_delay(100); 1040 timeout--; 1041 } 1042 1043 if (!timeout) { 1044 DEBUGOUT("Master requests are pending.\n"); 1045 return -IGC_ERR_MASTER_REQUESTS_PENDING; 1046 } 1047 1048 return IGC_SUCCESS; 1049 } 1050