1 /*- 2 * Copyright 2021 Intel Corp 3 * Copyright 2021 Rubicon Communications, LLC (Netgate) 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * $FreeBSD$ 7 */ 8 9 #ifndef _IGC_HW_H_ 10 #define _IGC_HW_H_ 11 12 #include "igc_osdep.h" 13 #include "igc_regs.h" 14 #include "igc_defines.h" 15 16 struct igc_hw; 17 18 #define IGC_DEV_ID_I225_LM 0x15F2 19 #define IGC_DEV_ID_I225_V 0x15F3 20 #define IGC_DEV_ID_I225_K 0x3100 21 #define IGC_DEV_ID_I225_I 0x15F8 22 #define IGC_DEV_ID_I220_V 0x15F7 23 #define IGC_DEV_ID_I225_K2 0x3101 24 #define IGC_DEV_ID_I225_LMVP 0x5502 25 #define IGC_DEV_ID_I226_K 0x3102 26 #define IGC_DEV_ID_I226_LMVP 0x5503 27 #define IGC_DEV_ID_I225_IT 0x0D9F 28 #define IGC_DEV_ID_I226_LM 0x125B 29 #define IGC_DEV_ID_I226_V 0x125C 30 #define IGC_DEV_ID_I226_IT 0x125D 31 #define IGC_DEV_ID_I221_V 0x125E 32 #define IGC_DEV_ID_I226_BLANK_NVM 0x125F 33 #define IGC_DEV_ID_I225_BLANK_NVM 0x15FD 34 35 #define IGC_REVISION_0 0 36 #define IGC_REVISION_1 1 37 #define IGC_REVISION_2 2 38 #define IGC_REVISION_3 3 39 #define IGC_REVISION_4 4 40 41 #define IGC_FUNC_1 1 42 43 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN0 0 44 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN1 3 45 46 enum igc_mac_type { 47 igc_undefined = 0, 48 igc_i225, 49 igc_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 50 }; 51 52 enum igc_media_type { 53 igc_media_type_unknown = 0, 54 igc_media_type_copper = 1, 55 igc_num_media_types 56 }; 57 58 enum igc_nvm_type { 59 igc_nvm_unknown = 0, 60 igc_nvm_eeprom_spi, 61 igc_nvm_flash_hw, 62 igc_nvm_invm, 63 }; 64 65 enum igc_phy_type { 66 igc_phy_unknown = 0, 67 igc_phy_none, 68 igc_phy_i225, 69 }; 70 71 enum igc_bus_type { 72 igc_bus_type_unknown = 0, 73 igc_bus_type_pci, 74 igc_bus_type_pcix, 75 igc_bus_type_pci_express, 76 igc_bus_type_reserved 77 }; 78 79 enum igc_bus_speed { 80 igc_bus_speed_unknown = 0, 81 igc_bus_speed_33, 82 igc_bus_speed_66, 83 igc_bus_speed_100, 84 igc_bus_speed_120, 85 igc_bus_speed_133, 86 igc_bus_speed_2500, 87 igc_bus_speed_5000, 88 igc_bus_speed_reserved 89 }; 90 91 enum igc_bus_width { 92 igc_bus_width_unknown = 0, 93 igc_bus_width_pcie_x1, 94 igc_bus_width_pcie_x2, 95 igc_bus_width_pcie_x4 = 4, 96 igc_bus_width_pcie_x8 = 8, 97 igc_bus_width_32, 98 igc_bus_width_64, 99 igc_bus_width_reserved 100 }; 101 102 enum igc_fc_mode { 103 igc_fc_none = 0, 104 igc_fc_rx_pause, 105 igc_fc_tx_pause, 106 igc_fc_full, 107 igc_fc_default = 0xFF 108 }; 109 110 enum igc_ms_type { 111 igc_ms_hw_default = 0, 112 igc_ms_force_master, 113 igc_ms_force_slave, 114 igc_ms_auto 115 }; 116 117 enum igc_smart_speed { 118 igc_smart_speed_default = 0, 119 igc_smart_speed_on, 120 igc_smart_speed_off 121 }; 122 123 #define __le16 u16 124 #define __le32 u32 125 #define __le64 u64 126 /* Receive Descriptor */ 127 struct igc_rx_desc { 128 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 129 __le16 length; /* Length of data DMAed into data buffer */ 130 __le16 csum; /* Packet checksum */ 131 u8 status; /* Descriptor status */ 132 u8 errors; /* Descriptor Errors */ 133 __le16 special; 134 }; 135 136 /* Receive Descriptor - Extended */ 137 union igc_rx_desc_extended { 138 struct { 139 __le64 buffer_addr; 140 __le64 reserved; 141 } read; 142 struct { 143 struct { 144 __le32 mrq; /* Multiple Rx Queues */ 145 union { 146 __le32 rss; /* RSS Hash */ 147 struct { 148 __le16 ip_id; /* IP id */ 149 __le16 csum; /* Packet Checksum */ 150 } csum_ip; 151 } hi_dword; 152 } lower; 153 struct { 154 __le32 status_error; /* ext status/error */ 155 __le16 length; 156 __le16 vlan; /* VLAN tag */ 157 } upper; 158 } wb; /* writeback */ 159 }; 160 161 #define MAX_PS_BUFFERS 4 162 163 /* Number of packet split data buffers (not including the header buffer) */ 164 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 165 166 /* Receive Descriptor - Packet Split */ 167 union igc_rx_desc_packet_split { 168 struct { 169 /* one buffer for protocol header(s), three data buffers */ 170 __le64 buffer_addr[MAX_PS_BUFFERS]; 171 } read; 172 struct { 173 struct { 174 __le32 mrq; /* Multiple Rx Queues */ 175 union { 176 __le32 rss; /* RSS Hash */ 177 struct { 178 __le16 ip_id; /* IP id */ 179 __le16 csum; /* Packet Checksum */ 180 } csum_ip; 181 } hi_dword; 182 } lower; 183 struct { 184 __le32 status_error; /* ext status/error */ 185 __le16 length0; /* length of buffer 0 */ 186 __le16 vlan; /* VLAN tag */ 187 } middle; 188 struct { 189 __le16 header_status; 190 /* length of buffers 1-3 */ 191 __le16 length[PS_PAGE_BUFFERS]; 192 } upper; 193 __le64 reserved; 194 } wb; /* writeback */ 195 }; 196 197 /* Transmit Descriptor */ 198 struct igc_tx_desc { 199 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 200 union { 201 __le32 data; 202 struct { 203 __le16 length; /* Data buffer length */ 204 u8 cso; /* Checksum offset */ 205 u8 cmd; /* Descriptor control */ 206 } flags; 207 } lower; 208 union { 209 __le32 data; 210 struct { 211 u8 status; /* Descriptor status */ 212 u8 css; /* Checksum start */ 213 __le16 special; 214 } fields; 215 } upper; 216 }; 217 218 /* Offload Context Descriptor */ 219 struct igc_context_desc { 220 union { 221 __le32 ip_config; 222 struct { 223 u8 ipcss; /* IP checksum start */ 224 u8 ipcso; /* IP checksum offset */ 225 __le16 ipcse; /* IP checksum end */ 226 } ip_fields; 227 } lower_setup; 228 union { 229 __le32 tcp_config; 230 struct { 231 u8 tucss; /* TCP checksum start */ 232 u8 tucso; /* TCP checksum offset */ 233 __le16 tucse; /* TCP checksum end */ 234 } tcp_fields; 235 } upper_setup; 236 __le32 cmd_and_length; 237 union { 238 __le32 data; 239 struct { 240 u8 status; /* Descriptor status */ 241 u8 hdr_len; /* Header length */ 242 __le16 mss; /* Maximum segment size */ 243 } fields; 244 } tcp_seg_setup; 245 }; 246 247 /* Offload data descriptor */ 248 struct igc_data_desc { 249 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 250 union { 251 __le32 data; 252 struct { 253 __le16 length; /* Data buffer length */ 254 u8 typ_len_ext; 255 u8 cmd; 256 } flags; 257 } lower; 258 union { 259 __le32 data; 260 struct { 261 u8 status; /* Descriptor status */ 262 u8 popts; /* Packet Options */ 263 __le16 special; 264 } fields; 265 } upper; 266 }; 267 268 /* Statistics counters collected by the MAC */ 269 struct igc_hw_stats { 270 u64 crcerrs; 271 u64 algnerrc; 272 u64 symerrs; 273 u64 rxerrc; 274 u64 mpc; 275 u64 scc; 276 u64 ecol; 277 u64 mcc; 278 u64 latecol; 279 u64 colc; 280 u64 dc; 281 u64 tncrs; 282 u64 sec; 283 u64 rlec; 284 u64 xonrxc; 285 u64 xontxc; 286 u64 xoffrxc; 287 u64 xofftxc; 288 u64 fcruc; 289 u64 prc64; 290 u64 prc127; 291 u64 prc255; 292 u64 prc511; 293 u64 prc1023; 294 u64 prc1522; 295 u64 tlpic; 296 u64 rlpic; 297 u64 gprc; 298 u64 bprc; 299 u64 mprc; 300 u64 gptc; 301 u64 gorc; 302 u64 gotc; 303 u64 rnbc; 304 u64 ruc; 305 u64 rfc; 306 u64 roc; 307 u64 rjc; 308 u64 mgprc; 309 u64 mgpdc; 310 u64 mgptc; 311 u64 tor; 312 u64 tot; 313 u64 tpr; 314 u64 tpt; 315 u64 ptc64; 316 u64 ptc127; 317 u64 ptc255; 318 u64 ptc511; 319 u64 ptc1023; 320 u64 ptc1522; 321 u64 mptc; 322 u64 bptc; 323 u64 tsctc; 324 u64 iac; 325 u64 rxdmtc; 326 u64 htdpmc; 327 u64 rpthc; 328 u64 hgptc; 329 u64 hgorc; 330 u64 hgotc; 331 u64 lenerrs; 332 u64 scvpc; 333 u64 hrmpc; 334 u64 doosync; 335 u64 o2bgptc; 336 u64 o2bspc; 337 u64 b2ospc; 338 u64 b2ogprc; 339 }; 340 341 #include "igc_mac.h" 342 #include "igc_phy.h" 343 #include "igc_nvm.h" 344 345 /* Function pointers for the MAC. */ 346 struct igc_mac_operations { 347 s32 (*init_params)(struct igc_hw *); 348 s32 (*check_for_link)(struct igc_hw *); 349 void (*clear_hw_cntrs)(struct igc_hw *); 350 void (*clear_vfta)(struct igc_hw *); 351 s32 (*get_bus_info)(struct igc_hw *); 352 void (*set_lan_id)(struct igc_hw *); 353 s32 (*get_link_up_info)(struct igc_hw *, u16 *, u16 *); 354 void (*update_mc_addr_list)(struct igc_hw *, u8 *, u32); 355 s32 (*reset_hw)(struct igc_hw *); 356 s32 (*init_hw)(struct igc_hw *); 357 s32 (*setup_link)(struct igc_hw *); 358 s32 (*setup_physical_interface)(struct igc_hw *); 359 void (*write_vfta)(struct igc_hw *, u32, u32); 360 void (*config_collision_dist)(struct igc_hw *); 361 int (*rar_set)(struct igc_hw *, u8*, u32); 362 s32 (*read_mac_addr)(struct igc_hw *); 363 s32 (*validate_mdi_setting)(struct igc_hw *); 364 s32 (*acquire_swfw_sync)(struct igc_hw *, u16); 365 void (*release_swfw_sync)(struct igc_hw *, u16); 366 }; 367 368 /* When to use various PHY register access functions: 369 * 370 * Func Caller 371 * Function Does Does When to use 372 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 373 * X_reg L,P,A n/a for simple PHY reg accesses 374 * X_reg_locked P,A L for multiple accesses of different regs 375 * on different pages 376 * X_reg_page A L,P for multiple accesses of different regs 377 * on the same page 378 * 379 * Where X=[read|write], L=locking, P=sets page, A=register access 380 * 381 */ 382 struct igc_phy_operations { 383 s32 (*init_params)(struct igc_hw *); 384 s32 (*acquire)(struct igc_hw *); 385 s32 (*check_reset_block)(struct igc_hw *); 386 s32 (*force_speed_duplex)(struct igc_hw *); 387 s32 (*get_info)(struct igc_hw *); 388 s32 (*set_page)(struct igc_hw *, u16); 389 s32 (*read_reg)(struct igc_hw *, u32, u16 *); 390 s32 (*read_reg_locked)(struct igc_hw *, u32, u16 *); 391 s32 (*read_reg_page)(struct igc_hw *, u32, u16 *); 392 void (*release)(struct igc_hw *); 393 s32 (*reset)(struct igc_hw *); 394 s32 (*set_d0_lplu_state)(struct igc_hw *, bool); 395 s32 (*set_d3_lplu_state)(struct igc_hw *, bool); 396 s32 (*write_reg)(struct igc_hw *, u32, u16); 397 s32 (*write_reg_locked)(struct igc_hw *, u32, u16); 398 s32 (*write_reg_page)(struct igc_hw *, u32, u16); 399 void (*power_up)(struct igc_hw *); 400 void (*power_down)(struct igc_hw *); 401 }; 402 403 /* Function pointers for the NVM. */ 404 struct igc_nvm_operations { 405 s32 (*init_params)(struct igc_hw *); 406 s32 (*acquire)(struct igc_hw *); 407 s32 (*read)(struct igc_hw *, u16, u16, u16 *); 408 void (*release)(struct igc_hw *); 409 void (*reload)(struct igc_hw *); 410 s32 (*update)(struct igc_hw *); 411 s32 (*validate)(struct igc_hw *); 412 s32 (*write)(struct igc_hw *, u16, u16, u16 *); 413 }; 414 415 struct igc_info { 416 s32 (*get_invariants)(struct igc_hw *hw); 417 struct igc_mac_operations *mac_ops; 418 const struct igc_phy_operations *phy_ops; 419 struct igc_nvm_operations *nvm_ops; 420 }; 421 422 extern const struct igc_info igc_i225_info; 423 424 struct igc_mac_info { 425 struct igc_mac_operations ops; 426 u8 addr[ETH_ADDR_LEN]; 427 u8 perm_addr[ETH_ADDR_LEN]; 428 429 enum igc_mac_type type; 430 431 u32 mc_filter_type; 432 433 u16 current_ifs_val; 434 u16 ifs_max_val; 435 u16 ifs_min_val; 436 u16 ifs_ratio; 437 u16 ifs_step_size; 438 u16 mta_reg_count; 439 u16 uta_reg_count; 440 441 /* Maximum size of the MTA register table in all supported adapters */ 442 #define MAX_MTA_REG 128 443 u32 mta_shadow[MAX_MTA_REG]; 444 u16 rar_entry_count; 445 446 u8 forced_speed_duplex; 447 448 bool asf_firmware_present; 449 bool autoneg; 450 bool get_link_status; 451 u32 max_frame_size; 452 }; 453 454 struct igc_phy_info { 455 struct igc_phy_operations ops; 456 enum igc_phy_type type; 457 458 enum igc_smart_speed smart_speed; 459 460 u32 addr; 461 u32 id; 462 u32 reset_delay_us; /* in usec */ 463 u32 revision; 464 465 enum igc_media_type media_type; 466 467 u16 autoneg_advertised; 468 u16 autoneg_mask; 469 470 u8 mdix; 471 472 bool polarity_correction; 473 bool speed_downgraded; 474 bool autoneg_wait_to_complete; 475 }; 476 477 struct igc_nvm_info { 478 struct igc_nvm_operations ops; 479 enum igc_nvm_type type; 480 481 u16 word_size; 482 u16 delay_usec; 483 u16 address_bits; 484 u16 opcode_bits; 485 u16 page_size; 486 }; 487 488 struct igc_bus_info { 489 enum igc_bus_type type; 490 enum igc_bus_speed speed; 491 enum igc_bus_width width; 492 493 u16 func; 494 u16 pci_cmd_word; 495 }; 496 497 struct igc_fc_info { 498 u32 high_water; /* Flow control high-water mark */ 499 u32 low_water; /* Flow control low-water mark */ 500 u16 pause_time; /* Flow control pause timer */ 501 u16 refresh_time; /* Flow control refresh timer */ 502 bool send_xon; /* Flow control send XON */ 503 bool strict_ieee; /* Strict IEEE mode */ 504 enum igc_fc_mode current_mode; /* FC mode in effect */ 505 enum igc_fc_mode requested_mode; /* FC mode requested by caller */ 506 }; 507 508 struct igc_dev_spec_i225 { 509 bool eee_disable; 510 bool clear_semaphore_once; 511 u32 mtu; 512 }; 513 514 struct igc_hw { 515 void *back; 516 517 u8 *hw_addr; 518 u8 *flash_address; 519 unsigned long io_base; 520 521 struct igc_mac_info mac; 522 struct igc_fc_info fc; 523 struct igc_phy_info phy; 524 struct igc_nvm_info nvm; 525 struct igc_bus_info bus; 526 527 union { 528 struct igc_dev_spec_i225 _i225; 529 } dev_spec; 530 531 u16 device_id; 532 u16 subsystem_vendor_id; 533 u16 subsystem_device_id; 534 u16 vendor_id; 535 536 u8 revision_id; 537 }; 538 539 #include "igc_i225.h" 540 #include "igc_base.h" 541 542 /* These functions must be implemented by drivers */ 543 s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); 544 s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); 545 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); 546 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); 547 548 #endif 549