1 /*- 2 * Copyright 2021 Intel Corp 3 * Copyright 2021 Rubicon Communications, LLC (Netgate) 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef _IGC_BASE_H_ 8 #define _IGC_BASE_H_ 9 10 /* forward declaration */ 11 s32 igc_init_hw_base(struct igc_hw *hw); 12 void igc_power_down_phy_copper_base(struct igc_hw *hw); 13 extern void igc_rx_fifo_flush_base(struct igc_hw *hw); 14 s32 igc_acquire_phy_base(struct igc_hw *hw); 15 void igc_release_phy_base(struct igc_hw *hw); 16 17 /* Transmit Descriptor - Advanced */ 18 union igc_adv_tx_desc { 19 struct { 20 __le64 buffer_addr; /* Address of descriptor's data buf */ 21 __le32 cmd_type_len; 22 __le32 olinfo_status; 23 } read; 24 struct { 25 __le64 rsvd; /* Reserved */ 26 __le32 nxtseq_seed; 27 __le32 status; 28 } wb; 29 }; 30 31 /* Context descriptors */ 32 struct igc_adv_tx_context_desc { 33 __le32 vlan_macip_lens; 34 union { 35 __le32 launch_time; 36 __le32 seqnum_seed; 37 }; 38 __le32 type_tucmd_mlhl; 39 __le32 mss_l4len_idx; 40 }; 41 42 /* Adv Transmit Descriptor Config Masks */ 43 #define IGC_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ 44 #define IGC_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 45 #define IGC_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ 46 #define IGC_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 47 #define IGC_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ 48 #define IGC_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ 49 #define IGC_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ 50 #define IGC_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ 51 #define IGC_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 52 #define IGC_ADVTXD_MAC_LINKSEC 0x00040000 /* Apply LinkSec on pkt */ 53 #define IGC_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp pkt */ 54 #define IGC_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED prsnt in WB */ 55 #define IGC_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 56 #define IGC_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ 57 #define IGC_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ 58 #define IGC_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ 59 /* 1st & Last TSO-full iSCSI PDU*/ 60 #define IGC_ADVTXD_POPTS_ISCO_FULL 0x00001800 61 #define IGC_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ 62 #define IGC_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 63 64 /* Advanced Transmit Context Descriptor Config */ 65 #define IGC_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 66 #define IGC_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 67 #define IGC_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 68 #define IGC_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 69 #define IGC_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 70 #define IGC_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 71 #define IGC_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ 72 #define IGC_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ 73 /* IPSec Encrypt Enable for ESP */ 74 #define IGC_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000 75 /* Req requires Markers and CRC */ 76 #define IGC_ADVTXD_TUCMD_MKRREQ 0x00002000 77 #define IGC_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 78 #define IGC_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 79 /* Adv ctxt IPSec SA IDX mask */ 80 #define IGC_ADVTXD_IPSEC_SA_INDEX_MASK 0x000000FF 81 /* Adv ctxt IPSec ESP len mask */ 82 #define IGC_ADVTXD_IPSEC_ESP_LEN_MASK 0x000000FF 83 84 #define IGC_RAR_ENTRIES_BASE 16 85 86 /* Receive Descriptor - Advanced */ 87 union igc_adv_rx_desc { 88 struct { 89 __le64 pkt_addr; /* Packet buffer address */ 90 __le64 hdr_addr; /* Header buffer address */ 91 } read; 92 struct { 93 struct { 94 union { 95 __le32 data; 96 struct { 97 __le16 pkt_info; /*RSS type, Pkt type*/ 98 /* Split Header, header buffer len */ 99 __le16 hdr_info; 100 } hs_rss; 101 } lo_dword; 102 union { 103 __le32 rss; /* RSS Hash */ 104 struct { 105 __le16 ip_id; /* IP id */ 106 __le16 csum; /* Packet Checksum */ 107 } csum_ip; 108 } hi_dword; 109 } lower; 110 struct { 111 __le32 status_error; /* ext status/error */ 112 __le16 length; /* Packet length */ 113 __le16 vlan; /* VLAN tag */ 114 } upper; 115 } wb; /* writeback */ 116 }; 117 118 /* Additional Transmit Descriptor Control definitions */ 119 #define IGC_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */ 120 121 /* Additional Receive Descriptor Control definitions */ 122 #define IGC_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */ 123 124 /* SRRCTL bit definitions */ 125 #define IGC_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 126 #define IGC_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 127 #define IGC_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 128 129 #endif /* _IGC_BASE_H_ */ 130