1 /*- 2 * Copyright 2021 Intel Corp 3 * Copyright 2021 Rubicon Communications, LLC (Netgate) 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <sys/cdefs.h> 8 #include "igc_hw.h" 9 #include "igc_i225.h" 10 #include "igc_mac.h" 11 #include "igc_base.h" 12 13 /** 14 * igc_acquire_phy_base - Acquire rights to access PHY 15 * @hw: pointer to the HW structure 16 * 17 * Acquire access rights to the correct PHY. 18 **/ 19 s32 igc_acquire_phy_base(struct igc_hw *hw) 20 { 21 u16 mask = IGC_SWFW_PHY0_SM; 22 23 DEBUGFUNC("igc_acquire_phy_base"); 24 25 if (hw->bus.func == IGC_FUNC_1) 26 mask = IGC_SWFW_PHY1_SM; 27 28 return hw->mac.ops.acquire_swfw_sync(hw, mask); 29 } 30 31 /** 32 * igc_release_phy_base - Release rights to access PHY 33 * @hw: pointer to the HW structure 34 * 35 * A wrapper to release access rights to the correct PHY. 36 **/ 37 void igc_release_phy_base(struct igc_hw *hw) 38 { 39 u16 mask = IGC_SWFW_PHY0_SM; 40 41 DEBUGFUNC("igc_release_phy_base"); 42 43 if (hw->bus.func == IGC_FUNC_1) 44 mask = IGC_SWFW_PHY1_SM; 45 46 hw->mac.ops.release_swfw_sync(hw, mask); 47 } 48 49 /** 50 * igc_init_hw_base - Initialize hardware 51 * @hw: pointer to the HW structure 52 * 53 * This inits the hardware readying it for operation. 54 **/ 55 s32 igc_init_hw_base(struct igc_hw *hw) 56 { 57 struct igc_mac_info *mac = &hw->mac; 58 s32 ret_val; 59 u16 i, rar_count = mac->rar_entry_count; 60 61 DEBUGFUNC("igc_init_hw_base"); 62 63 /* Setup the receive address */ 64 igc_init_rx_addrs_generic(hw, rar_count); 65 66 /* Zero out the Multicast HASH table */ 67 DEBUGOUT("Zeroing the MTA\n"); 68 for (i = 0; i < mac->mta_reg_count; i++) 69 IGC_WRITE_REG_ARRAY(hw, IGC_MTA, i, 0); 70 71 /* Zero out the Unicast HASH table */ 72 DEBUGOUT("Zeroing the UTA\n"); 73 for (i = 0; i < mac->uta_reg_count; i++) 74 IGC_WRITE_REG_ARRAY(hw, IGC_UTA, i, 0); 75 76 /* Setup link and flow control */ 77 ret_val = mac->ops.setup_link(hw); 78 /* 79 * Clear all of the statistics registers (clear on read). It is 80 * important that we do this after we have tried to establish link 81 * because the symbol error count will increment wildly if there 82 * is no link. 83 */ 84 igc_clear_hw_cntrs_base_generic(hw); 85 86 return ret_val; 87 } 88 89 /** 90 * igc_power_down_phy_copper_base - Remove link during PHY power down 91 * @hw: pointer to the HW structure 92 * 93 * In the case of a PHY power down to save power, or to turn off link during a 94 * driver unload, or wake on lan is not enabled, remove the link. 95 **/ 96 void igc_power_down_phy_copper_base(struct igc_hw *hw) 97 { 98 struct igc_phy_info *phy = &hw->phy; 99 100 if (!(phy->ops.check_reset_block)) 101 return; 102 103 /* If the management interface is not enabled, then power down. */ 104 if (!(igc_enable_mng_pass_thru(hw) || 105 phy->ops.check_reset_block(hw))) 106 igc_power_down_phy_copper(hw); 107 } 108 109 /** 110 * igc_rx_fifo_flush_base - Clean Rx FIFO after Rx enable 111 * @hw: pointer to the HW structure 112 * 113 * After Rx enable, if manageability is enabled then there is likely some 114 * bad data at the start of the FIFO and possibly in the DMA FIFO. This 115 * function clears the FIFOs and flushes any packets that came in as Rx was 116 * being enabled. 117 **/ 118 void igc_rx_fifo_flush_base(struct igc_hw *hw) 119 { 120 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 121 int i, ms_wait; 122 123 DEBUGFUNC("igc_rx_fifo_flush_base"); 124 125 /* disable IPv6 options as per hardware errata */ 126 rfctl = IGC_READ_REG(hw, IGC_RFCTL); 127 rfctl |= IGC_RFCTL_IPV6_EX_DIS; 128 IGC_WRITE_REG(hw, IGC_RFCTL, rfctl); 129 130 if (!(IGC_READ_REG(hw, IGC_MANC) & IGC_MANC_RCV_TCO_EN)) 131 return; 132 133 /* Disable all Rx queues */ 134 for (i = 0; i < 4; i++) { 135 rxdctl[i] = IGC_READ_REG(hw, IGC_RXDCTL(i)); 136 IGC_WRITE_REG(hw, IGC_RXDCTL(i), 137 rxdctl[i] & ~IGC_RXDCTL_QUEUE_ENABLE); 138 } 139 /* Poll all queues to verify they have shut down */ 140 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 141 msec_delay(1); 142 rx_enabled = 0; 143 for (i = 0; i < 4; i++) 144 rx_enabled |= IGC_READ_REG(hw, IGC_RXDCTL(i)); 145 if (!(rx_enabled & IGC_RXDCTL_QUEUE_ENABLE)) 146 break; 147 } 148 149 if (ms_wait == 10) 150 DEBUGOUT("Queue disable timed out after 10ms\n"); 151 152 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 153 * incoming packets are rejected. Set enable and wait 2ms so that 154 * any packet that was coming in as RCTL.EN was set is flushed 155 */ 156 IGC_WRITE_REG(hw, IGC_RFCTL, rfctl & ~IGC_RFCTL_LEF); 157 158 rlpml = IGC_READ_REG(hw, IGC_RLPML); 159 IGC_WRITE_REG(hw, IGC_RLPML, 0); 160 161 rctl = IGC_READ_REG(hw, IGC_RCTL); 162 temp_rctl = rctl & ~(IGC_RCTL_EN | IGC_RCTL_SBP); 163 temp_rctl |= IGC_RCTL_LPE; 164 165 IGC_WRITE_REG(hw, IGC_RCTL, temp_rctl); 166 IGC_WRITE_REG(hw, IGC_RCTL, temp_rctl | IGC_RCTL_EN); 167 IGC_WRITE_FLUSH(hw); 168 msec_delay(2); 169 170 /* Enable Rx queues that were previously enabled and restore our 171 * previous state 172 */ 173 for (i = 0; i < 4; i++) 174 IGC_WRITE_REG(hw, IGC_RXDCTL(i), rxdctl[i]); 175 IGC_WRITE_REG(hw, IGC_RCTL, rctl); 176 IGC_WRITE_FLUSH(hw); 177 178 IGC_WRITE_REG(hw, IGC_RLPML, rlpml); 179 IGC_WRITE_REG(hw, IGC_RFCTL, rfctl); 180 181 /* Flush receive errors generated by workaround */ 182 IGC_READ_REG(hw, IGC_ROC); 183 IGC_READ_REG(hw, IGC_RNBC); 184 IGC_READ_REG(hw, IGC_MPC); 185 } 186 187 /** 188 * igc_is_device_id_i225 - Check whether the device is I225 silicon 189 * @hw: pointer to the HW structure 190 * 191 * I225 and I226 share the same mac.type, so this checks the PCI 192 * device ID directly to distinguish I225 parts, e.g. for erratum 193 * workarounds that apply only to that silicon. 194 * 195 * I225_BLANK_NVM is absent from the equivalent Linux helper. I220 is 196 * kept separate because Intel's I225 specification update does not 197 * identify it as affected. 198 **/ 199 bool igc_is_device_id_i225(struct igc_hw *hw) 200 { 201 switch (hw->device_id) { 202 case IGC_DEV_ID_I225_LM: 203 case IGC_DEV_ID_I225_V: 204 case IGC_DEV_ID_I225_K: 205 case IGC_DEV_ID_I225_I: 206 case IGC_DEV_ID_I225_K2: 207 case IGC_DEV_ID_I225_LMVP: 208 case IGC_DEV_ID_I225_IT: 209 case IGC_DEV_ID_I225_BLANK_NVM: 210 return true; 211 default: 212 return false; 213 } 214 } 215 216 /** 217 * igc_is_device_id_i226 - Check whether the device is I226 silicon 218 * @hw: pointer to the HW structure 219 * 220 * I225 and I226 share the same mac.type, so this checks the PCI 221 * device ID directly to distinguish I226 parts, e.g. for erratum 222 * workarounds that apply only to that silicon. 223 * 224 * I226_LMVP and I226_BLANK_NVM are absent from the equivalent Linux 225 * errata; keep them listed here so a future resync does not drop them. 226 **/ 227 bool igc_is_device_id_i226(struct igc_hw *hw) 228 { 229 switch (hw->device_id) { 230 case IGC_DEV_ID_I226_LM: 231 case IGC_DEV_ID_I226_V: 232 case IGC_DEV_ID_I226_K: 233 case IGC_DEV_ID_I226_IT: 234 case IGC_DEV_ID_I226_LMVP: 235 case IGC_DEV_ID_I226_BLANK_NVM: 236 return true; 237 default: 238 return false; 239 } 240 } 241