1517904deSPeter Grehan /*- 2517904deSPeter Grehan * SPDX-License-Identifier: BSD-2-Clause 3517904deSPeter Grehan * 4*bc9402abSKevin Bowling * Copyright (c) 2001-2024, Intel Corporation 5517904deSPeter Grehan * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 6517904deSPeter Grehan * Copyright (c) 2021 Rubicon Communications, LLC (Netgate) 7517904deSPeter Grehan * 8517904deSPeter Grehan * Redistribution and use in source and binary forms, with or without 9517904deSPeter Grehan * modification, are permitted provided that the following conditions 10517904deSPeter Grehan * are met: 11517904deSPeter Grehan * 1. Redistributions of source code must retain the above copyright 12517904deSPeter Grehan * notice, this list of conditions and the following disclaimer. 13517904deSPeter Grehan * 2. Redistributions in binary form must reproduce the above copyright 14517904deSPeter Grehan * notice, this list of conditions and the following disclaimer in the 15517904deSPeter Grehan * documentation and/or other materials provided with the distribution. 16517904deSPeter Grehan * 17517904deSPeter Grehan * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18517904deSPeter Grehan * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19517904deSPeter Grehan * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20517904deSPeter Grehan * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21517904deSPeter Grehan * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22517904deSPeter Grehan * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23517904deSPeter Grehan * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24517904deSPeter Grehan * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25517904deSPeter Grehan * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26517904deSPeter Grehan * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27517904deSPeter Grehan * SUCH DAMAGE. 28517904deSPeter Grehan */ 29517904deSPeter Grehan 30517904deSPeter Grehan #include "opt_ddb.h" 31517904deSPeter Grehan #include "opt_inet.h" 32517904deSPeter Grehan #include "opt_inet6.h" 33517904deSPeter Grehan #include "opt_rss.h" 34517904deSPeter Grehan 35517904deSPeter Grehan #ifdef HAVE_KERNEL_OPTION_HEADERS 36517904deSPeter Grehan #include "opt_device_polling.h" 37517904deSPeter Grehan #endif 38517904deSPeter Grehan 39517904deSPeter Grehan #include <sys/param.h> 40517904deSPeter Grehan #include <sys/systm.h> 41517904deSPeter Grehan #ifdef DDB 42517904deSPeter Grehan #include <sys/types.h> 43517904deSPeter Grehan #include <ddb/ddb.h> 44517904deSPeter Grehan #endif 45517904deSPeter Grehan #include <sys/buf_ring.h> 46517904deSPeter Grehan #include <sys/bus.h> 47517904deSPeter Grehan #include <sys/endian.h> 48517904deSPeter Grehan #include <sys/kernel.h> 49517904deSPeter Grehan #include <sys/kthread.h> 50517904deSPeter Grehan #include <sys/malloc.h> 51517904deSPeter Grehan #include <sys/mbuf.h> 52517904deSPeter Grehan #include <sys/module.h> 53517904deSPeter Grehan #include <sys/rman.h> 54517904deSPeter Grehan #include <sys/smp.h> 55517904deSPeter Grehan #include <sys/socket.h> 56517904deSPeter Grehan #include <sys/sockio.h> 57517904deSPeter Grehan #include <sys/sysctl.h> 58517904deSPeter Grehan #include <sys/taskqueue.h> 59517904deSPeter Grehan #include <sys/eventhandler.h> 60517904deSPeter Grehan #include <machine/bus.h> 61517904deSPeter Grehan #include <machine/resource.h> 62517904deSPeter Grehan 63517904deSPeter Grehan #include <net/bpf.h> 64517904deSPeter Grehan #include <net/ethernet.h> 65517904deSPeter Grehan #include <net/if.h> 66517904deSPeter Grehan #include <net/if_var.h> 67517904deSPeter Grehan #include <net/if_arp.h> 68517904deSPeter Grehan #include <net/if_dl.h> 69517904deSPeter Grehan #include <net/if_media.h> 70517904deSPeter Grehan #include <net/iflib.h> 71517904deSPeter Grehan 72517904deSPeter Grehan #include <net/if_types.h> 73517904deSPeter Grehan #include <net/if_vlan_var.h> 74517904deSPeter Grehan 75517904deSPeter Grehan #include <netinet/in_systm.h> 76517904deSPeter Grehan #include <netinet/in.h> 77517904deSPeter Grehan #include <netinet/if_ether.h> 78517904deSPeter Grehan #include <netinet/ip.h> 79517904deSPeter Grehan #include <netinet/ip6.h> 80517904deSPeter Grehan #include <netinet/tcp.h> 81517904deSPeter Grehan #include <netinet/udp.h> 82517904deSPeter Grehan 83517904deSPeter Grehan #include <machine/in_cksum.h> 84517904deSPeter Grehan #include <dev/led/led.h> 85517904deSPeter Grehan #include <dev/pci/pcivar.h> 86517904deSPeter Grehan #include <dev/pci/pcireg.h> 87517904deSPeter Grehan 88517904deSPeter Grehan #include "igc_api.h" 89517904deSPeter Grehan #include "igc_i225.h" 90517904deSPeter Grehan #include "ifdi_if.h" 91517904deSPeter Grehan 92517904deSPeter Grehan 93517904deSPeter Grehan #ifndef _IGC_H_DEFINED_ 94517904deSPeter Grehan #define _IGC_H_DEFINED_ 95517904deSPeter Grehan 96517904deSPeter Grehan 97517904deSPeter Grehan /* Tunables */ 98517904deSPeter Grehan 99517904deSPeter Grehan /* 100517904deSPeter Grehan * IGC_MAX_TXD: Maximum number of Transmit Descriptors 101517904deSPeter Grehan * Valid Range: 128-4096 102517904deSPeter Grehan * Default Value: 1024 103517904deSPeter Grehan * This value is the number of transmit descriptors allocated by the driver. 104517904deSPeter Grehan * Increasing this value allows the driver to queue more transmits. Each 105517904deSPeter Grehan * descriptor is 16 bytes. 106517904deSPeter Grehan * Since TDLEN should be multiple of 128bytes, the number of transmit 107517904deSPeter Grehan * desscriptors should meet the following condition. 108517904deSPeter Grehan * (num_tx_desc * sizeof(struct igc_tx_desc)) % 128 == 0 109517904deSPeter Grehan */ 110517904deSPeter Grehan #define IGC_MIN_TXD 128 111517904deSPeter Grehan #define IGC_MAX_TXD 4096 112517904deSPeter Grehan #define IGC_DEFAULT_TXD 1024 113517904deSPeter Grehan #define IGC_DEFAULT_MULTI_TXD 4096 114517904deSPeter Grehan #define IGC_MAX_TXD 4096 115517904deSPeter Grehan 116517904deSPeter Grehan /* 117517904deSPeter Grehan * IGC_MAX_RXD - Maximum number of receive Descriptors 118517904deSPeter Grehan * Valid Range: 128-4096 119517904deSPeter Grehan * Default Value: 1024 120517904deSPeter Grehan * This value is the number of receive descriptors allocated by the driver. 121517904deSPeter Grehan * Increasing this value allows the driver to buffer more incoming packets. 122517904deSPeter Grehan * Each descriptor is 16 bytes. A receive buffer is also allocated for each 123517904deSPeter Grehan * descriptor. The maximum MTU size is 16110. 124517904deSPeter Grehan * Since TDLEN should be multiple of 128bytes, the number of transmit 125517904deSPeter Grehan * desscriptors should meet the following condition. 126517904deSPeter Grehan * (num_tx_desc * sizeof(struct igc_tx_desc)) % 128 == 0 127517904deSPeter Grehan */ 128517904deSPeter Grehan #define IGC_MIN_RXD 128 129517904deSPeter Grehan #define IGC_MAX_RXD 4096 130517904deSPeter Grehan #define IGC_DEFAULT_RXD 1024 131517904deSPeter Grehan #define IGC_DEFAULT_MULTI_RXD 4096 132517904deSPeter Grehan #define IGC_MAX_RXD 4096 133517904deSPeter Grehan 134517904deSPeter Grehan /* 135517904deSPeter Grehan * This parameter controls whether or not autonegotation is enabled. 136517904deSPeter Grehan * 0 - Disable autonegotiation 137517904deSPeter Grehan * 1 - Enable autonegotiation 138517904deSPeter Grehan */ 139517904deSPeter Grehan #define DO_AUTO_NEG true 140517904deSPeter Grehan 141517904deSPeter Grehan /* Tunables -- End */ 142517904deSPeter Grehan 143517904deSPeter Grehan #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 144517904deSPeter Grehan ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 145517904deSPeter Grehan ADVERTISE_1000_FULL | ADVERTISE_2500_FULL) 146517904deSPeter Grehan 147517904deSPeter Grehan #define AUTO_ALL_MODES 0 148517904deSPeter Grehan 149517904deSPeter Grehan /* 150517904deSPeter Grehan * Micellaneous constants 151517904deSPeter Grehan */ 152517904deSPeter Grehan #define MAX_NUM_MULTICAST_ADDRESSES 128 153517904deSPeter Grehan #define IGC_FC_PAUSE_TIME 0x0680 154517904deSPeter Grehan 155517904deSPeter Grehan #define IGC_TXPBSIZE 20408 156517904deSPeter Grehan #define IGC_PKTTYPE_MASK 0x0000FFF0 157517904deSPeter Grehan #define IGC_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */ 158517904deSPeter Grehan 159517904deSPeter Grehan #define IGC_RX_PTHRESH 8 160517904deSPeter Grehan #define IGC_RX_HTHRESH 8 161517904deSPeter Grehan #define IGC_RX_WTHRESH 4 162517904deSPeter Grehan 163517904deSPeter Grehan #define IGC_TX_PTHRESH 8 164517904deSPeter Grehan #define IGC_TX_HTHRESH 1 165517904deSPeter Grehan 166*bc9402abSKevin Bowling /* Define the interrupt rates and EITR helpers */ 167*bc9402abSKevin Bowling #define IGC_INTS_4K 4000 168*bc9402abSKevin Bowling #define IGC_INTS_20K 20000 169*bc9402abSKevin Bowling #define IGC_INTS_70K 70000 170*bc9402abSKevin Bowling #define IGC_INTS_DEFAULT 8000 171*bc9402abSKevin Bowling #define IGC_EITR_DIVIDEND 1000000 172*bc9402abSKevin Bowling #define IGC_EITR_SHIFT 2 173*bc9402abSKevin Bowling #define IGC_QVECTOR_MASK 0x7FFC 174*bc9402abSKevin Bowling #define IGC_INTS_TO_EITR(i) (((IGC_EITR_DIVIDEND/i) & IGC_QVECTOR_MASK) << \ 175*bc9402abSKevin Bowling IGC_EITR_SHIFT) 176*bc9402abSKevin Bowling 177517904deSPeter Grehan /* 178517904deSPeter Grehan * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 179517904deSPeter Grehan * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 180517904deSPeter Grehan * also optimize cache line size effect. H/W supports up to cache line size 128. 181517904deSPeter Grehan */ 182517904deSPeter Grehan #define IGC_DBA_ALIGN 128 183517904deSPeter Grehan 184517904deSPeter Grehan #define IGC_MSIX_BAR 3 185517904deSPeter Grehan 186517904deSPeter Grehan /* Defines for printing debug information */ 187517904deSPeter Grehan #define DEBUG_INIT 0 188517904deSPeter Grehan #define DEBUG_IOCTL 0 189517904deSPeter Grehan #define DEBUG_HW 0 190517904deSPeter Grehan 191517904deSPeter Grehan #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 192517904deSPeter Grehan #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 193517904deSPeter Grehan #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 194517904deSPeter Grehan #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 195517904deSPeter Grehan #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 196517904deSPeter Grehan #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 197517904deSPeter Grehan #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 198517904deSPeter Grehan #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 199517904deSPeter Grehan #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 200517904deSPeter Grehan 201517904deSPeter Grehan #define IGC_MAX_SCATTER 40 202517904deSPeter Grehan #define IGC_VFTA_SIZE 128 203517904deSPeter Grehan #define IGC_TSO_SIZE 65535 204517904deSPeter Grehan #define IGC_TSO_SEG_SIZE 4096 /* Max dma segment size */ 205517904deSPeter Grehan #define IGC_CSUM_OFFLOAD (CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | \ 206517904deSPeter Grehan CSUM_IP_SCTP | CSUM_IP6_UDP | CSUM_IP6_TCP | \ 207517904deSPeter Grehan CSUM_IP6_SCTP) /* Offload bits in mbuf flag */ 208517904deSPeter Grehan 209517904deSPeter Grehan struct igc_adapter; 210517904deSPeter Grehan 211517904deSPeter Grehan struct igc_int_delay_info { 212517904deSPeter Grehan struct igc_adapter *adapter; /* Back-pointer to the adapter struct */ 213517904deSPeter Grehan int offset; /* Register offset to read/write */ 214517904deSPeter Grehan int value; /* Current value in usecs */ 215517904deSPeter Grehan }; 216517904deSPeter Grehan 217517904deSPeter Grehan /* 218517904deSPeter Grehan * The transmit ring, one per tx queue 219517904deSPeter Grehan */ 220517904deSPeter Grehan struct tx_ring { 221517904deSPeter Grehan struct igc_adapter *adapter; 222517904deSPeter Grehan struct igc_tx_desc *tx_base; 223517904deSPeter Grehan uint64_t tx_paddr; 224517904deSPeter Grehan qidx_t *tx_rsq; 225517904deSPeter Grehan uint8_t me; 226517904deSPeter Grehan qidx_t tx_rs_cidx; 227517904deSPeter Grehan qidx_t tx_rs_pidx; 228517904deSPeter Grehan qidx_t tx_cidx_processed; 229517904deSPeter Grehan /* Interrupt resources */ 230517904deSPeter Grehan void *tag; 231517904deSPeter Grehan struct resource *res; 232*bc9402abSKevin Bowling 233*bc9402abSKevin Bowling /* Soft stats */ 234517904deSPeter Grehan unsigned long tx_irq; 235*bc9402abSKevin Bowling unsigned long tx_packets; 236*bc9402abSKevin Bowling unsigned long tx_bytes; 237*bc9402abSKevin Bowling 238517904deSPeter Grehan 239517904deSPeter Grehan /* Saved csum offloading context information */ 240517904deSPeter Grehan int csum_flags; 241517904deSPeter Grehan int csum_lhlen; 242517904deSPeter Grehan int csum_iphlen; 243517904deSPeter Grehan 244517904deSPeter Grehan int csum_thlen; 245517904deSPeter Grehan int csum_mss; 246517904deSPeter Grehan int csum_pktlen; 247517904deSPeter Grehan 248517904deSPeter Grehan uint32_t csum_txd_upper; 249517904deSPeter Grehan uint32_t csum_txd_lower; /* last field */ 250517904deSPeter Grehan }; 251517904deSPeter Grehan 252517904deSPeter Grehan /* 253517904deSPeter Grehan * The Receive ring, one per rx queue 254517904deSPeter Grehan */ 255517904deSPeter Grehan struct rx_ring { 256517904deSPeter Grehan struct igc_adapter *adapter; 257517904deSPeter Grehan struct igc_rx_queue *que; 258517904deSPeter Grehan u32 me; 259517904deSPeter Grehan u32 payload; 260517904deSPeter Grehan union igc_rx_desc_extended *rx_base; 261517904deSPeter Grehan uint64_t rx_paddr; 262517904deSPeter Grehan 263517904deSPeter Grehan /* Interrupt resources */ 264517904deSPeter Grehan void *tag; 265517904deSPeter Grehan struct resource *res; 266517904deSPeter Grehan 267517904deSPeter Grehan /* Soft stats */ 268517904deSPeter Grehan unsigned long rx_irq; 269517904deSPeter Grehan unsigned long rx_discarded; 270517904deSPeter Grehan unsigned long rx_packets; 271517904deSPeter Grehan unsigned long rx_bytes; 272*bc9402abSKevin Bowling 273*bc9402abSKevin Bowling /* Next requested ITR latency */ 274*bc9402abSKevin Bowling u8 rx_nextlatency; 275517904deSPeter Grehan }; 276517904deSPeter Grehan 277517904deSPeter Grehan struct igc_tx_queue { 278517904deSPeter Grehan struct igc_adapter *adapter; 279517904deSPeter Grehan u32 msix; 280517904deSPeter Grehan u32 eims; /* This queue's EIMS bit */ 281517904deSPeter Grehan u32 me; 282517904deSPeter Grehan struct tx_ring txr; 283517904deSPeter Grehan }; 284517904deSPeter Grehan 285517904deSPeter Grehan struct igc_rx_queue { 286517904deSPeter Grehan struct igc_adapter *adapter; 287517904deSPeter Grehan u32 me; 288517904deSPeter Grehan u32 msix; 289517904deSPeter Grehan u32 eims; 290*bc9402abSKevin Bowling u32 eitr_setting; 291517904deSPeter Grehan struct rx_ring rxr; 292517904deSPeter Grehan u64 irqs; 293517904deSPeter Grehan struct if_irq que_irq; 294517904deSPeter Grehan }; 295517904deSPeter Grehan 296517904deSPeter Grehan /* Our adapter structure */ 297517904deSPeter Grehan struct igc_adapter { 298ec22a3a2SJustin Hibbits if_t ifp; 299517904deSPeter Grehan struct igc_hw hw; 300517904deSPeter Grehan 301517904deSPeter Grehan if_softc_ctx_t shared; 302517904deSPeter Grehan if_ctx_t ctx; 303517904deSPeter Grehan #define tx_num_queues shared->isc_ntxqsets 304517904deSPeter Grehan #define rx_num_queues shared->isc_nrxqsets 305517904deSPeter Grehan #define intr_type shared->isc_intr 306517904deSPeter Grehan /* FreeBSD operating-system-specific structures. */ 307517904deSPeter Grehan struct igc_osdep osdep; 308517904deSPeter Grehan device_t dev; 309517904deSPeter Grehan struct cdev *led_dev; 310517904deSPeter Grehan 311517904deSPeter Grehan struct igc_tx_queue *tx_queues; 312517904deSPeter Grehan struct igc_rx_queue *rx_queues; 313517904deSPeter Grehan struct if_irq irq; 314517904deSPeter Grehan 315517904deSPeter Grehan struct resource *memory; 316517904deSPeter Grehan struct resource *flash; 317517904deSPeter Grehan struct resource *ioport; 318517904deSPeter Grehan 319517904deSPeter Grehan struct resource *res; 320517904deSPeter Grehan void *tag; 321517904deSPeter Grehan u32 linkvec; 322517904deSPeter Grehan u32 ivars; 323517904deSPeter Grehan 324517904deSPeter Grehan struct ifmedia *media; 325517904deSPeter Grehan int msix; 326517904deSPeter Grehan int if_flags; 327517904deSPeter Grehan int igc_insert_vlan_header; 328517904deSPeter Grehan u32 ims; 329517904deSPeter Grehan 330517904deSPeter Grehan u32 flags; 331517904deSPeter Grehan /* Task for FAST handling */ 332517904deSPeter Grehan struct grouptask link_task; 333517904deSPeter Grehan 334517904deSPeter Grehan u32 txd_cmd; 335517904deSPeter Grehan 336517904deSPeter Grehan u32 rx_mbuf_sz; 337517904deSPeter Grehan 338*bc9402abSKevin Bowling int enable_aim; 339*bc9402abSKevin Bowling 340517904deSPeter Grehan /* Management and WOL features */ 341517904deSPeter Grehan u32 wol; 342517904deSPeter Grehan 343517904deSPeter Grehan /* Multicast array memory */ 344517904deSPeter Grehan u8 *mta; 345517904deSPeter Grehan 346517904deSPeter Grehan /* Info about the interface */ 347517904deSPeter Grehan u16 link_active; 348517904deSPeter Grehan u16 fc; 349517904deSPeter Grehan u16 link_speed; 350517904deSPeter Grehan u16 link_duplex; 351517904deSPeter Grehan u32 smartspeed; 352517904deSPeter Grehan u32 dmac; 353*bc9402abSKevin Bowling u32 pba; 354517904deSPeter Grehan int link_mask; 355517904deSPeter Grehan 356517904deSPeter Grehan u64 que_mask; 357517904deSPeter Grehan 35833ed9bdcSKevin Bowling struct igc_fw_version fw_ver; 35933ed9bdcSKevin Bowling 360517904deSPeter Grehan struct igc_int_delay_info tx_int_delay; 361517904deSPeter Grehan struct igc_int_delay_info tx_abs_int_delay; 362517904deSPeter Grehan struct igc_int_delay_info rx_int_delay; 363517904deSPeter Grehan struct igc_int_delay_info rx_abs_int_delay; 364517904deSPeter Grehan struct igc_int_delay_info tx_itr; 365517904deSPeter Grehan 366517904deSPeter Grehan /* Misc stats maintained by the driver */ 367517904deSPeter Grehan unsigned long dropped_pkts; 368517904deSPeter Grehan unsigned long link_irq; 369517904deSPeter Grehan unsigned long rx_overruns; 370517904deSPeter Grehan unsigned long watchdog_events; 371517904deSPeter Grehan 372517904deSPeter Grehan struct igc_hw_stats stats; 373517904deSPeter Grehan u16 vf_ifp; 374517904deSPeter Grehan }; 375517904deSPeter Grehan 376517904deSPeter Grehan void igc_dump_rs(struct igc_adapter *); 377517904deSPeter Grehan 378517904deSPeter Grehan #define IGC_RSSRK_SIZE 4 379517904deSPeter Grehan #define IGC_RSSRK_VAL(key, i) (key[(i) * IGC_RSSRK_SIZE] | \ 380517904deSPeter Grehan key[(i) * IGC_RSSRK_SIZE + 1] << 8 | \ 381517904deSPeter Grehan key[(i) * IGC_RSSRK_SIZE + 2] << 16 | \ 382517904deSPeter Grehan key[(i) * IGC_RSSRK_SIZE + 3] << 24) 383517904deSPeter Grehan #endif /* _IGC_H_DEFINED_ */ 384