1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2001-2024, Intel Corporation 5 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 6 * Copyright (c) 2021-2024 Rubicon Communications, LLC (Netgate) 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 #include "if_igc.h" 32 #include <sys/sbuf.h> 33 #include <machine/_inttypes.h> 34 35 #include <net/rss_config.h> 36 #include <netinet/in_rss.h> 37 38 39 /********************************************************************* 40 * PCI Device ID Table 41 * 42 * Used by probe to select devices to load on 43 * Last entry must be all 0s 44 * 45 * { Vendor ID, Device ID, String } 46 *********************************************************************/ 47 48 static const pci_vendor_info_t igc_vendor_info_array[] = 49 { 50 /* Intel(R) PRO/1000 Network Connection - igc */ 51 PVID(0x8086, IGC_DEV_ID_I225_LM, 52 "Intel(R) Ethernet Controller I225-LM"), 53 PVID(0x8086, IGC_DEV_ID_I225_V, 54 "Intel(R) Ethernet Controller I225-V"), 55 PVID(0x8086, IGC_DEV_ID_I225_K, 56 "Intel(R) Ethernet Controller I225-K"), 57 PVID(0x8086, IGC_DEV_ID_I225_I, 58 "Intel(R) Ethernet Controller I225-IT"), 59 PVID(0x8086, IGC_DEV_ID_I220_V, 60 "Intel(R) Ethernet Controller I220-V"), 61 PVID(0x8086, IGC_DEV_ID_I225_K2, 62 "Intel(R) Ethernet Controller I225-K(2)"), 63 PVID(0x8086, IGC_DEV_ID_I225_LMVP, 64 "Intel(R) Ethernet Controller I225-LMvP(2)"), 65 PVID(0x8086, IGC_DEV_ID_I226_K, 66 "Intel(R) Ethernet Controller I226-K"), 67 PVID(0x8086, IGC_DEV_ID_I226_LMVP, 68 "Intel(R) Ethernet Controller I226-LMvP"), 69 PVID(0x8086, IGC_DEV_ID_I225_IT, 70 "Intel(R) Ethernet Controller I225-IT(2)"), 71 PVID(0x8086, IGC_DEV_ID_I226_LM, 72 "Intel(R) Ethernet Controller I226-LM"), 73 PVID(0x8086, IGC_DEV_ID_I226_V, 74 "Intel(R) Ethernet Controller I226-V"), 75 PVID(0x8086, IGC_DEV_ID_I226_IT, 76 "Intel(R) Ethernet Controller I226-IT"), 77 PVID(0x8086, IGC_DEV_ID_I221_V, 78 "Intel(R) Ethernet Controller I221-V"), 79 PVID(0x8086, IGC_DEV_ID_I226_BLANK_NVM, 80 "Intel(R) Ethernet Controller I226(blankNVM)"), 81 PVID(0x8086, IGC_DEV_ID_I225_BLANK_NVM, 82 "Intel(R) Ethernet Controller I225(blankNVM)"), 83 /* required last entry */ 84 PVID_END 85 }; 86 87 /********************************************************************* 88 * Function prototypes 89 *********************************************************************/ 90 static void *igc_register(device_t); 91 static int igc_if_attach_pre(if_ctx_t); 92 static int igc_if_attach_post(if_ctx_t); 93 static int igc_if_detach(if_ctx_t); 94 static int igc_if_shutdown(if_ctx_t); 95 static int igc_if_suspend(if_ctx_t); 96 static int igc_if_resume(if_ctx_t); 97 98 static int igc_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, 99 int); 100 static int igc_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, 101 int); 102 static void igc_if_queues_free(if_ctx_t); 103 104 static uint64_t igc_if_get_counter(if_ctx_t, ift_counter); 105 static void igc_if_init(if_ctx_t); 106 static void igc_if_stop(if_ctx_t); 107 static void igc_if_media_status(if_ctx_t, struct ifmediareq *); 108 static int igc_if_media_change(if_ctx_t); 109 static int igc_if_mtu_set(if_ctx_t, uint32_t); 110 static void igc_if_timer(if_ctx_t, uint16_t); 111 static void igc_if_vlan_register(if_ctx_t, u16); 112 static void igc_if_vlan_unregister(if_ctx_t, u16); 113 static bool igc_if_needs_restart(if_ctx_t, enum iflib_restart_event); 114 115 static void igc_identify_hardware(if_ctx_t); 116 static int igc_allocate_pci_resources(if_ctx_t); 117 static void igc_free_pci_resources(if_ctx_t); 118 static void igc_disable_broken_l1_2(if_ctx_t); 119 static int igc_reset(if_ctx_t); 120 static int igc_setup_interface(if_ctx_t); 121 static int igc_setup_msix(if_ctx_t); 122 123 static void igc_initialize_transmit_unit(if_ctx_t); 124 static void igc_initialize_receive_unit(if_ctx_t); 125 126 static void igc_if_intr_enable(if_ctx_t); 127 static void igc_if_intr_disable(if_ctx_t); 128 static int igc_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 129 static int igc_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 130 static void igc_handle_fatal_error_intr(struct igc_softc *, u32); 131 static bool igc_handle_fatal_error_admin(struct igc_softc *); 132 static void igc_prepare_fatal_error_reset(struct igc_softc *); 133 static void igc_finish_fatal_error_reset(struct igc_softc *); 134 static void igc_if_multi_set(if_ctx_t); 135 static void igc_if_update_admin_status(if_ctx_t); 136 static void igc_apply_i225_ipg_workaround(struct igc_softc *); 137 static void igc_if_debug(if_ctx_t); 138 static void igc_update_ecc_stats(struct igc_softc *); 139 static void igc_update_stats_counters(struct igc_softc *); 140 static void igc_add_hw_stats(struct igc_softc *); 141 static int igc_if_set_promisc(if_ctx_t, int); 142 static bool igc_if_vlan_filter_capable(if_ctx_t); 143 static bool igc_if_vlan_filter_used(if_ctx_t); 144 static void igc_if_vlan_filter_enable(struct igc_softc *); 145 static void igc_if_vlan_filter_disable(struct igc_softc *); 146 static void igc_setup_vlan_hw_support(if_ctx_t); 147 static void igc_if_led_func(if_ctx_t, int); 148 static void igc_led_restore(struct igc_softc *); 149 static void igc_fw_version(struct igc_softc *); 150 static void igc_sbuf_fw_version(struct igc_fw_version *, struct sbuf *); 151 static void igc_print_fw_version(struct igc_softc *); 152 static int igc_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 153 static int igc_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 154 static void igc_print_nvm_info(struct igc_softc *); 155 static int igc_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 156 static int igc_get_rs(SYSCTL_HANDLER_ARGS); 157 static void igc_print_debug_info(struct igc_softc *); 158 static int igc_is_valid_ether_addr(u8 *); 159 static void igc_neweitr(struct igc_softc *, struct igc_rx_queue *, 160 struct rx_ring *); 161 static int igc_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS); 162 /* Management and WOL Support */ 163 static void igc_get_hw_control(struct igc_softc *); 164 static void igc_release_hw_control(struct igc_softc *); 165 static int igc_enable_pci_busmaster(struct igc_softc *); 166 static void igc_configure_wakeup(if_ctx_t); 167 static int igc_enable_wakeup(if_ctx_t); 168 static void igc_power_up_wakeup_link(struct igc_softc *); 169 170 int igc_intr(void *); 171 172 enum igc_fatal_error_state { 173 IGC_FATAL_ERROR_NONE, 174 IGC_FATAL_ERROR_CAPTURING, 175 IGC_FATAL_ERROR_DETECTED, 176 IGC_FATAL_ERROR_RESET_REQUESTED, 177 }; 178 179 /* MSI-X handlers */ 180 static int igc_if_msix_intr_assign(if_ctx_t, int); 181 static int igc_msix_link(void *); 182 static void igc_handle_link(void *context); 183 184 static void igc_sysctl_request_reinit(struct igc_softc *); 185 static int igc_set_flowcntl(SYSCTL_HANDLER_ARGS); 186 static int igc_sysctl_dmac(SYSCTL_HANDLER_ARGS); 187 static int igc_sysctl_eee(SYSCTL_HANDLER_ARGS); 188 189 static int igc_get_regs(SYSCTL_HANDLER_ARGS); 190 191 static void igc_configure_queues(struct igc_softc *); 192 static void igc_initialize_interrupt_rate(struct igc_softc *); 193 194 195 /********************************************************************* 196 * FreeBSD Device Interface Entry Points 197 *********************************************************************/ 198 static device_method_t igc_methods[] = { 199 /* Device interface */ 200 DEVMETHOD(device_register, igc_register), 201 DEVMETHOD(device_probe, iflib_device_probe), 202 DEVMETHOD(device_attach, iflib_device_attach), 203 DEVMETHOD(device_detach, iflib_device_detach), 204 DEVMETHOD(device_shutdown, iflib_device_shutdown), 205 DEVMETHOD(device_suspend, iflib_device_suspend), 206 DEVMETHOD(device_resume, iflib_device_resume), 207 DEVMETHOD_END 208 }; 209 210 static driver_t igc_driver = { 211 "igc", igc_methods, sizeof(struct igc_softc), 212 }; 213 214 DRIVER_MODULE(igc, pci, igc_driver, 0, 0); 215 216 MODULE_DEPEND(igc, pci, 1, 1, 1); 217 MODULE_DEPEND(igc, ether, 1, 1, 1); 218 MODULE_DEPEND(igc, iflib, 1, 1, 1); 219 220 IFLIB_PNP_INFO(pci, igc, igc_vendor_info_array); 221 222 static device_method_t igc_if_methods[] = { 223 DEVMETHOD(ifdi_attach_pre, igc_if_attach_pre), 224 DEVMETHOD(ifdi_attach_post, igc_if_attach_post), 225 DEVMETHOD(ifdi_detach, igc_if_detach), 226 DEVMETHOD(ifdi_shutdown, igc_if_shutdown), 227 DEVMETHOD(ifdi_suspend, igc_if_suspend), 228 DEVMETHOD(ifdi_resume, igc_if_resume), 229 DEVMETHOD(ifdi_init, igc_if_init), 230 DEVMETHOD(ifdi_stop, igc_if_stop), 231 DEVMETHOD(ifdi_msix_intr_assign, igc_if_msix_intr_assign), 232 DEVMETHOD(ifdi_intr_enable, igc_if_intr_enable), 233 DEVMETHOD(ifdi_intr_disable, igc_if_intr_disable), 234 DEVMETHOD(ifdi_tx_queues_alloc, igc_if_tx_queues_alloc), 235 DEVMETHOD(ifdi_rx_queues_alloc, igc_if_rx_queues_alloc), 236 DEVMETHOD(ifdi_queues_free, igc_if_queues_free), 237 DEVMETHOD(ifdi_update_admin_status, igc_if_update_admin_status), 238 DEVMETHOD(ifdi_multi_set, igc_if_multi_set), 239 DEVMETHOD(ifdi_media_status, igc_if_media_status), 240 DEVMETHOD(ifdi_media_change, igc_if_media_change), 241 DEVMETHOD(ifdi_mtu_set, igc_if_mtu_set), 242 DEVMETHOD(ifdi_promisc_set, igc_if_set_promisc), 243 DEVMETHOD(ifdi_timer, igc_if_timer), 244 DEVMETHOD(ifdi_vlan_register, igc_if_vlan_register), 245 DEVMETHOD(ifdi_vlan_unregister, igc_if_vlan_unregister), 246 DEVMETHOD(ifdi_get_counter, igc_if_get_counter), 247 DEVMETHOD(ifdi_rx_queue_intr_enable, igc_if_rx_queue_intr_enable), 248 DEVMETHOD(ifdi_tx_queue_intr_enable, igc_if_tx_queue_intr_enable), 249 DEVMETHOD(ifdi_debug, igc_if_debug), 250 DEVMETHOD(ifdi_needs_restart, igc_if_needs_restart), 251 DEVMETHOD(ifdi_led_func, igc_if_led_func), 252 DEVMETHOD_END 253 }; 254 255 static driver_t igc_if_driver = { 256 "igc_if", igc_if_methods, sizeof(struct igc_softc) 257 }; 258 259 /********************************************************************* 260 * Tunable default values. 261 *********************************************************************/ 262 263 /* Allow common code without TSO */ 264 #ifndef CSUM_TSO 265 #define CSUM_TSO 0 266 #endif 267 268 static SYSCTL_NODE(_hw, OID_AUTO, igc, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 269 "igc driver parameters"); 270 271 static int igc_disable_crc_stripping = 0; 272 SYSCTL_INT(_hw_igc, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 273 &igc_disable_crc_stripping, 0, "Disable CRC Stripping"); 274 275 static int igc_smart_pwr_down = false; 276 SYSCTL_INT(_hw_igc, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, 277 &igc_smart_pwr_down, 278 0, "Set to true to leave smart power down enabled on newer adapters"); 279 280 /* Controls whether promiscuous also shows bad packets */ 281 static int igc_debug_sbp = false; 282 SYSCTL_INT(_hw_igc, OID_AUTO, sbp, CTLFLAG_RDTUN, &igc_debug_sbp, 0, 283 "Show bad packets in promiscuous mode"); 284 285 /* Energy efficient ethernet - default to OFF */ 286 static int igc_eee_setting = 1; 287 SYSCTL_INT(_hw_igc, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &igc_eee_setting, 0, 288 "Enable Energy Efficient Ethernet"); 289 290 /* 291 * AIM: Adaptive Interrupt Moderation 292 * which means that the interrupt rate is varied over time based on the 293 * traffic for that interrupt vector 294 */ 295 static int igc_enable_aim = 1; 296 SYSCTL_INT(_hw_igc, OID_AUTO, enable_aim, CTLFLAG_RWTUN, &igc_enable_aim, 297 0, "Enable adaptive interrupt moderation (1=normal, 2=lowlatency)"); 298 299 /* 300 ** Tuneable Interrupt rate 301 */ 302 static int igc_max_interrupt_rate = IGC_INTS_DEFAULT; 303 SYSCTL_INT(_hw_igc, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 304 &igc_max_interrupt_rate, 0, "Maximum interrupts per second"); 305 306 extern struct if_txrx igc_txrx; 307 308 static struct if_shared_ctx igc_sctx_init = { 309 .isc_magic = IFLIB_MAGIC, 310 .isc_q_align = PAGE_SIZE, 311 .isc_tx_maxsize = IGC_TSO_SIZE + sizeof(struct ether_vlan_header), 312 .isc_tx_maxsegsize = PAGE_SIZE, 313 .isc_tso_maxsize = IGC_TSO_SIZE + sizeof(struct ether_vlan_header), 314 .isc_tso_maxsegsize = IGC_TSO_SEG_SIZE, 315 .isc_rx_maxsize = MAX_JUMBO_FRAME_SIZE, 316 .isc_rx_nsegments = 1, 317 .isc_rx_maxsegsize = MJUM9BYTES, 318 .isc_nfl = 1, 319 .isc_nrxqs = 1, 320 .isc_ntxqs = 1, 321 .isc_admin_intrcnt = 1, 322 .isc_vendor_info = igc_vendor_info_array, 323 .isc_driver_version = "1", 324 .isc_driver = &igc_if_driver, 325 .isc_flags = 326 IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 327 328 .isc_nrxd_min = {IGC_MIN_RXD}, 329 .isc_ntxd_min = {IGC_MIN_TXD}, 330 .isc_nrxd_max = {IGC_MAX_RXD}, 331 .isc_ntxd_max = {IGC_MAX_TXD}, 332 .isc_nrxd_default = {IGC_DEFAULT_RXD}, 333 .isc_ntxd_default = {IGC_DEFAULT_TXD}, 334 }; 335 336 /***************************************************************** 337 * 338 * Dump Registers 339 * 340 ****************************************************************/ 341 #define IGC_REGS_LEN 739 342 343 static int igc_get_regs(SYSCTL_HANDLER_ARGS) 344 { 345 struct igc_softc *sc = (struct igc_softc *)arg1; 346 struct igc_hw *hw = &sc->hw; 347 struct sbuf *sb; 348 u32 *regs_buff; 349 int rc; 350 351 regs_buff = malloc(sizeof(u32) * IGC_REGS_LEN, M_DEVBUF, M_WAITOK); 352 memset(regs_buff, 0, IGC_REGS_LEN * sizeof(u32)); 353 354 rc = sysctl_wire_old_buffer(req, 0); 355 MPASS(rc == 0); 356 if (rc != 0) { 357 free(regs_buff, M_DEVBUF); 358 return (rc); 359 } 360 361 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 362 MPASS(sb != NULL); 363 if (sb == NULL) { 364 free(regs_buff, M_DEVBUF); 365 return (ENOMEM); 366 } 367 368 /* General Registers */ 369 regs_buff[0] = IGC_READ_REG(hw, IGC_CTRL); 370 regs_buff[1] = IGC_READ_REG(hw, IGC_STATUS); 371 regs_buff[2] = IGC_READ_REG(hw, IGC_CTRL_EXT); 372 regs_buff[3] = IGC_READ_REG(hw, IGC_ICR); 373 regs_buff[4] = IGC_READ_REG(hw, IGC_RCTL); 374 regs_buff[5] = IGC_READ_REG(hw, IGC_RDLEN(0)); 375 regs_buff[6] = IGC_READ_REG(hw, IGC_RDH(0)); 376 regs_buff[7] = IGC_READ_REG(hw, IGC_RDT(0)); 377 regs_buff[8] = IGC_READ_REG(hw, IGC_RXDCTL(0)); 378 regs_buff[9] = IGC_READ_REG(hw, IGC_RDBAL(0)); 379 regs_buff[10] = IGC_READ_REG(hw, IGC_RDBAH(0)); 380 regs_buff[11] = IGC_READ_REG(hw, IGC_TCTL); 381 regs_buff[12] = IGC_READ_REG(hw, IGC_TDBAL(0)); 382 regs_buff[13] = IGC_READ_REG(hw, IGC_TDBAH(0)); 383 regs_buff[14] = IGC_READ_REG(hw, IGC_TDLEN(0)); 384 regs_buff[15] = IGC_READ_REG(hw, IGC_TDH(0)); 385 regs_buff[16] = IGC_READ_REG(hw, IGC_TDT(0)); 386 regs_buff[17] = IGC_READ_REG(hw, IGC_TXDCTL(0)); 387 388 sbuf_printf(sb, "General Registers\n"); 389 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 390 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 391 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 392 393 sbuf_printf(sb, "Interrupt Registers\n"); 394 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 395 396 sbuf_printf(sb, "RX Registers\n"); 397 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 398 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 399 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 400 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 401 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 402 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 403 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 404 405 sbuf_printf(sb, "TX Registers\n"); 406 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 407 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 408 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 409 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 410 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 411 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 412 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 413 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 414 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 415 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 416 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 417 418 free(regs_buff, M_DEVBUF); 419 420 #ifdef DUMP_DESCS 421 { 422 if_softc_ctx_t scctx = sc->shared; 423 struct rx_ring *rxr = &rx_que->rxr; 424 struct tx_ring *txr = &tx_que->txr; 425 int ntxd = scctx->isc_ntxd[0]; 426 int nrxd = scctx->isc_nrxd[0]; 427 int j; 428 429 for (j = 0; j < nrxd; j++) { 430 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 431 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 432 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" 433 PRIx64 " Error:%d Length:%d\n", 434 j, rxr->rx_base[j].read.buffer_addr, staterr, length); 435 } 436 437 for (j = 0; j < min(ntxd, 256); j++) { 438 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 439 440 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x" 441 "[3]: %08x eop: %d DD=%d\n", 442 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 443 buf->eop != -1 ? 444 txr->tx_base[buf->eop].upper.fields.status & 445 IGC_TXD_STAT_DD : 0); 446 447 } 448 } 449 #endif 450 451 rc = sbuf_finish(sb); 452 sbuf_delete(sb); 453 return(rc); 454 } 455 456 static void * 457 igc_register(device_t dev) 458 { 459 return (&igc_sctx_init); 460 } 461 462 static int 463 igc_set_num_queues(if_ctx_t ctx) 464 { 465 int maxqueues; 466 467 maxqueues = 4; 468 469 return (maxqueues); 470 } 471 472 #define IGC_CAPS \ 473 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 474 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL | IFCAP_TSO4 | \ 475 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | \ 476 IFCAP_HWCSUM_IPV6 | IFCAP_TSO6 477 478 /********************************************************************* 479 * Device initialization routine 480 * 481 * The attach entry point is called when the driver is being loaded. 482 * This routine identifies the type of hardware, allocates all resources 483 * and initializes the hardware. 484 * 485 * return 0 on success, positive on failure 486 *********************************************************************/ 487 static int 488 igc_if_attach_pre(if_ctx_t ctx) 489 { 490 struct igc_softc *sc; 491 if_softc_ctx_t scctx; 492 device_t dev; 493 struct igc_hw *hw; 494 int error = 0; 495 496 INIT_DEBUGOUT("igc_if_attach_pre: begin"); 497 dev = iflib_get_dev(ctx); 498 sc = iflib_get_softc(ctx); 499 500 if (igc_max_interrupt_rate <= 0) { 501 device_printf(dev, 502 "Invalid max_interrupt_rate %d; using default %d\n", 503 igc_max_interrupt_rate, IGC_INTS_DEFAULT); 504 igc_max_interrupt_rate = IGC_INTS_DEFAULT; 505 } 506 507 sc->ctx = sc->osdep.ctx = ctx; 508 sc->dev = sc->osdep.dev = dev; 509 scctx = sc->shared = iflib_get_softc_ctx(ctx); 510 sc->media = iflib_get_media(ctx); 511 hw = &sc->hw; 512 513 /* SYSCTL stuff */ 514 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 515 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 516 OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 517 sc, 0, igc_sysctl_nvm_info, "I", "NVM Information"); 518 519 sc->enable_aim = igc_enable_aim; 520 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 521 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 522 OID_AUTO, "enable_aim", CTLFLAG_RW, 523 &sc->enable_aim, 0, 524 "Interrupt Moderation (1=normal, 2=lowlatency)"); 525 526 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 527 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 528 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, 529 sc, 0, igc_sysctl_print_fw_version, "A", 530 "Prints FW/NVM Versions"); 531 532 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 533 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 534 OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 535 sc, 0, igc_sysctl_debug_info, "I", "Debug Information"); 536 537 sc->fc = igc_fc_full; 538 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 539 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 540 OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 541 sc, 0, igc_set_flowcntl, "I", "Flow Control"); 542 543 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 544 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 545 OID_AUTO, "reg_dump", 546 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 547 igc_get_regs, "A", "Dump Registers"); 548 549 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 550 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 551 OID_AUTO, "rs_dump", 552 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 553 igc_get_rs, "I", "Dump RS indexes"); 554 555 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 556 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 557 OID_AUTO, "dmac", 558 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 559 igc_sysctl_dmac, "I", "DMA Coalesce"); 560 561 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 562 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 563 OID_AUTO, "tso_tcp_flags_mask_first_segment", 564 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 565 sc, 0, igc_sysctl_tso_tcp_flags_mask, "IU", 566 "TSO TCP flags mask for first segment"); 567 568 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 569 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 570 OID_AUTO, "tso_tcp_flags_mask_middle_segment", 571 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 572 sc, 1, igc_sysctl_tso_tcp_flags_mask, "IU", 573 "TSO TCP flags mask for middle segment"); 574 575 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 576 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 577 OID_AUTO, "tso_tcp_flags_mask_last_segment", 578 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 579 sc, 2, igc_sysctl_tso_tcp_flags_mask, "IU", 580 "TSO TCP flags mask for last segment"); 581 582 /* Determine hardware and mac info */ 583 igc_identify_hardware(ctx); 584 585 /* Apply device-specific PCIe L1.2 errata workarounds. */ 586 igc_disable_broken_l1_2(ctx); 587 588 scctx->isc_tx_nsegments = IGC_MAX_SCATTER; 589 scctx->isc_nrxqsets_max = 590 scctx->isc_ntxqsets_max = igc_set_num_queues(ctx); 591 if (bootverbose) 592 device_printf(dev, "attach_pre capping queues at %d\n", 593 scctx->isc_ntxqsets_max); 594 595 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * 596 sizeof(union igc_adv_tx_desc), IGC_DBA_ALIGN); 597 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * 598 sizeof(union igc_adv_rx_desc), IGC_DBA_ALIGN); 599 scctx->isc_txd_size[0] = sizeof(union igc_adv_tx_desc); 600 scctx->isc_rxd_size[0] = sizeof(union igc_adv_rx_desc); 601 scctx->isc_txrx = &igc_txrx; 602 scctx->isc_tx_tso_segments_max = IGC_MAX_SCATTER; 603 scctx->isc_tx_tso_size_max = IGC_TSO_SIZE; 604 scctx->isc_tx_tso_segsize_max = IGC_TSO_SEG_SIZE; 605 scctx->isc_capabilities = scctx->isc_capenable = IGC_CAPS; 606 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 607 CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_SCTP | CSUM_IP6_SCTP; 608 609 /* 610 ** Some new devices, as with ixgbe, now may 611 ** use a different BAR, so we need to keep 612 ** track of which is used. 613 */ 614 scctx->isc_msix_bar = PCIR_BAR(IGC_MSIX_BAR); 615 if (pci_read_config(dev, scctx->isc_msix_bar, 4) == 0) 616 scctx->isc_msix_bar += 4; 617 618 /* Setup PCI resources */ 619 if (igc_allocate_pci_resources(ctx)) { 620 device_printf(dev, "Allocation of PCI resources failed\n"); 621 error = ENXIO; 622 goto err_pci; 623 } 624 625 /* Do Shared Code initialization */ 626 error = igc_setup_init_funcs(hw, true); 627 if (error) { 628 device_printf(dev, "Setup of Shared code failed, error %d\n", 629 error); 630 error = ENXIO; 631 goto err_pci; 632 } 633 634 igc_setup_msix(ctx); 635 igc_get_bus_info(hw); 636 637 hw->mac.autoneg = DO_AUTO_NEG; 638 hw->phy.autoneg_wait_to_complete = false; 639 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 640 641 /* Copper options */ 642 if (hw->phy.media_type == igc_media_type_copper) { 643 hw->phy.mdix = AUTO_ALL_MODES; 644 } 645 646 /* 647 * Set the frame limits assuming 648 * standard ethernet sized frames. 649 */ 650 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 651 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 652 653 /* Allocate multicast array memory. */ 654 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 655 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 656 if (sc->mta == NULL) { 657 device_printf(dev, 658 "Can not allocate multicast setup array\n"); 659 error = ENOMEM; 660 goto err_late; 661 } 662 663 /* Check SOL/IDER usage */ 664 if (igc_check_reset_block(hw)) 665 device_printf(dev, "PHY reset is blocked" 666 " due to SOL/IDER session.\n"); 667 668 /* Sysctl for setting Energy Efficient Ethernet */ 669 sc->hw.dev_spec._i225.eee_disable = igc_eee_setting; 670 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 671 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 672 OID_AUTO, "eee_control", 673 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 674 sc, 0, igc_sysctl_eee, "I", 675 "Disable Energy Efficient Ethernet"); 676 677 /* 678 ** Start from a known state, this is 679 ** important in reading the nvm and 680 ** mac from that. 681 */ 682 error = igc_reset_hw(hw); 683 if (error != IGC_SUCCESS) { 684 device_printf(dev, "Hardware reset failed: %d\n", error); 685 error = EIO; 686 goto err_late; 687 } 688 689 /* Make sure we have a good EEPROM before we read from it */ 690 if (igc_validate_nvm_checksum(hw) < 0) { 691 /* 692 ** Some PCI-E parts fail the first check due to 693 ** the link being in sleep state, call it again, 694 ** if it fails a second time its a real issue. 695 */ 696 if (igc_validate_nvm_checksum(hw) < 0) { 697 device_printf(dev, 698 "The EEPROM Checksum Is Not Valid\n"); 699 error = EIO; 700 goto err_late; 701 } 702 } 703 704 /* Copy the permanent MAC address out of the EEPROM */ 705 if (igc_read_mac_addr(hw) < 0) { 706 device_printf(dev, "EEPROM read error while reading MAC" 707 " address\n"); 708 error = EIO; 709 goto err_late; 710 } 711 712 if (!igc_is_valid_ether_addr(hw->mac.addr)) { 713 device_printf(dev, "Invalid MAC address\n"); 714 error = EIO; 715 goto err_late; 716 } 717 718 /* Save the EEPROM/NVM versions */ 719 igc_fw_version(sc); 720 721 igc_print_fw_version(sc); 722 723 /* 724 * Get Wake-on-Lan and Management info for later use 725 */ 726 igc_configure_wakeup(ctx); 727 728 iflib_set_mac(ctx, hw->mac.addr); 729 730 return (0); 731 732 err_late: 733 igc_release_hw_control(sc); 734 err_pci: 735 igc_free_pci_resources(ctx); 736 free(sc->mta, M_DEVBUF); 737 738 return (error); 739 } 740 741 static int 742 igc_if_attach_post(if_ctx_t ctx) 743 { 744 struct igc_softc *sc = iflib_get_softc(ctx); 745 struct igc_hw *hw = &sc->hw; 746 int error = 0; 747 748 /* Setup OS specific network interface */ 749 error = igc_setup_interface(ctx); 750 if (error != 0) 751 return (error); 752 753 if (igc_reset(ctx) != IGC_SUCCESS) 754 return (EIO); 755 756 /* Initialize statistics */ 757 igc_update_stats_counters(sc); 758 hw->mac.get_link_status = true; 759 igc_if_update_admin_status(ctx); 760 igc_add_hw_stats(sc); 761 762 /* the driver can now take control from firmware */ 763 igc_get_hw_control(sc); 764 765 INIT_DEBUGOUT("igc_if_attach_post: end"); 766 767 return (error); 768 } 769 770 /********************************************************************* 771 * Device removal routine 772 * 773 * The detach entry point is called when the driver is being removed. 774 * This routine stops the adapter and deallocates all the resources 775 * that were allocated for driver operation. 776 * 777 * return 0 on success, positive on failure 778 *********************************************************************/ 779 static int 780 igc_if_detach(if_ctx_t ctx) 781 { 782 struct igc_softc *sc = iflib_get_softc(ctx); 783 784 INIT_DEBUGOUT("igc_if_detach: begin"); 785 786 igc_phy_hw_reset(&sc->hw); 787 788 igc_release_hw_control(sc); 789 igc_free_pci_resources(ctx); 790 791 return (0); 792 } 793 794 /********************************************************************* 795 * 796 * Shutdown entry point 797 * 798 **********************************************************************/ 799 800 static int 801 igc_if_shutdown(if_ctx_t ctx) 802 { 803 int error; 804 805 error = igc_if_suspend(ctx); 806 if (error != 0) 807 device_printf(iflib_get_dev(ctx), 808 "Wake configuration failed during shutdown: %d\n", error); 809 return (0); 810 } 811 812 /* 813 * Suspend/resume device methods. 814 */ 815 static int 816 igc_if_suspend(if_ctx_t ctx) 817 { 818 struct igc_softc *sc = iflib_get_softc(ctx); 819 int error; 820 821 error = igc_enable_wakeup(ctx); 822 igc_release_hw_control(sc); 823 return (error); 824 } 825 826 static int 827 igc_if_resume(if_ctx_t ctx) 828 { 829 struct igc_softc *sc = iflib_get_softc(ctx); 830 u32 wus, wus_ext; 831 832 /* 833 * PCIe config space, and with it L1.2, may have been reset 834 * across the suspend/resume cycle. 835 */ 836 igc_disable_broken_l1_2(ctx); 837 wus = IGC_READ_REG(&sc->hw, IGC_WUS); 838 wus_ext = IGC_READ_REG(&sc->hw, IGC_WUS_EXT); 839 if (wus != 0 || wus_ext != 0) 840 device_printf(sc->dev, 841 "Wakeup status: %#010x, extended %#010x\n", wus, wus_ext); 842 IGC_WRITE_REG(&sc->hw, IGC_WUFC, 0); 843 IGC_WRITE_REG(&sc->hw, IGC_WUFC_EXT, 0); 844 IGC_WRITE_REG(&sc->hw, IGC_WUC, 0); 845 IGC_WRITE_REG(&sc->hw, IGC_WUS, ~0U); 846 IGC_WRITE_REG(&sc->hw, IGC_WUS_EXT, ~0U); 847 /* Clear PME after its MAC wake source has been removed. */ 848 pci_clear_pme(sc->dev); 849 850 return (0); 851 } 852 853 static int 854 igc_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 855 { 856 int max_frame_size; 857 struct igc_softc *sc = iflib_get_softc(ctx); 858 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 859 860 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 861 862 /* 9K Jumbo Frame size */ 863 max_frame_size = 9234; 864 865 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 866 return (EINVAL); 867 } 868 869 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 870 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 871 return (0); 872 } 873 874 /********************************************************************* 875 * Init entry point 876 * 877 * This routine is used in two ways. It is used by the stack as 878 * init entry point in network interface structure. It is also used 879 * by the driver as a hw/sw initialization routine to get to a 880 * consistent state. 881 * 882 **********************************************************************/ 883 static void 884 igc_if_init(if_ctx_t ctx) 885 { 886 struct igc_softc *sc = iflib_get_softc(ctx); 887 if_softc_ctx_t scctx = sc->shared; 888 if_t ifp = iflib_get_ifp(ctx); 889 struct igc_tx_queue *tx_que; 890 int i; 891 892 INIT_DEBUGOUT("igc_if_init: begin"); 893 894 if (igc_enable_pci_busmaster(sc) != 0) { 895 device_printf(sc->dev, "Could not enable PCI bus mastering\n"); 896 iflib_init_failed(ctx); 897 return; 898 } 899 if (sc->suspend_link_powered_down) 900 igc_power_up_wakeup_link(sc); 901 902 /* Get the latest mac address, User can use a LAA */ 903 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, 904 ETHER_ADDR_LEN); 905 906 /* Initialize the hardware */ 907 if (igc_reset(ctx) != IGC_SUCCESS) { 908 iflib_init_failed(ctx); 909 return; 910 } 911 igc_if_update_admin_status(ctx); 912 913 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; 914 i++, tx_que++) { 915 struct tx_ring *txr = &tx_que->txr; 916 917 txr->tx_rs_cidx = txr->tx_rs_pidx; 918 919 /* Initialize the last processed descriptor to be the end of 920 * the ring, rather than the start, so that we avoid an 921 * off-by-one error when calculating how many descriptors are 922 * done in the credits_update function. 923 */ 924 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 925 } 926 927 /* Setup VLAN support, basic and offload if available */ 928 IGC_WRITE_REG(&sc->hw, IGC_VET, ETHERTYPE_VLAN); 929 930 /* Prepare transmit descriptors and buffers */ 931 igc_initialize_transmit_unit(ctx); 932 933 /* Setup Multicast table */ 934 igc_if_multi_set(ctx); 935 936 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 937 igc_initialize_receive_unit(ctx); 938 939 /* Set up VLAN support */ 940 igc_setup_vlan_hw_support(ctx); 941 942 /* Don't lose promiscuous settings */ 943 igc_if_set_promisc(ctx, if_getflags(ifp)); 944 igc_clear_hw_cntrs_base_generic(&sc->hw); 945 946 if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 947 igc_configure_queues(sc); 948 igc_initialize_interrupt_rate(sc); 949 950 /* this clears any pending interrupts */ 951 IGC_READ_REG(&sc->hw, IGC_ICR); 952 IGC_WRITE_REG(&sc->hw, IGC_ICS, IGC_ICS_LSC); 953 954 /* the driver can now take control from firmware */ 955 igc_get_hw_control(sc); 956 957 /* Set Energy Efficient Ethernet */ 958 igc_set_eee_i225(&sc->hw, true, true, true); 959 } 960 961 /* 962 * RX publishes its byte and packet counters as one snapshot when iflib 963 * returns descriptors to hardware. This also covers watchdog-driven RX 964 * processing, which can run while the interrupt vector is unmasked. 965 */ 966 static __inline void 967 igc_aim_rx_delta(struct rx_ring *rxr, u32 *bytes, u32 *packets) 968 { 969 uint64_t snapshot; 970 u32 now_bytes, now_packets; 971 972 snapshot = atomic_load_acq_64(&rxr->rx_aim_snapshot); 973 now_bytes = snapshot >> 32; 974 now_packets = (u32)snapshot; 975 *bytes = now_bytes - rxr->rx_bytes_last; 976 *packets = now_packets - rxr->rx_packets_last; 977 rxr->rx_bytes_last = now_bytes; 978 rxr->rx_packets_last = now_packets; 979 } 980 981 /* 982 * TX publishes its byte and packet counters as one snapshot at the doorbell, 983 * because encapsulation can overlap the interrupt filter. The two halves 984 * remain independent free running u32 counters, so their deltas are correct 985 * across wrap. 986 */ 987 static __inline void 988 igc_aim_tx_delta(struct tx_ring *txr, u32 *bytes, u32 *packets) 989 { 990 uint64_t snapshot; 991 u32 now_bytes, now_packets; 992 993 snapshot = atomic_load_acq_64(&txr->tx_aim_snapshot); 994 now_bytes = snapshot >> 32; 995 now_packets = (u32)snapshot; 996 *bytes = now_bytes - txr->tx_bytes_last; 997 *packets = now_packets - txr->tx_packets_last; 998 txr->tx_bytes_last = now_bytes; 999 txr->tx_packets_last = now_packets; 1000 } 1001 1002 /********************************************************************* 1003 * 1004 * Do Adaptive Interrupt Moderation: 1005 * - Calculate based on average size over the last interval 1006 * 1007 * Returns interrupts per second rather than a register value, so that the 1008 * caller's IGC_INTS_TO_EITR() conversion applies, or zero if the interval 1009 * carried no packet to measure. 1010 * 1011 *********************************************************************/ 1012 static u32 1013 igc_ring_itr(struct igc_softc *sc, u32 rxbytes, u32 rxpackets, u32 txbytes, 1014 u32 txpackets) 1015 { 1016 u32 newitr = 0; 1017 1018 if (txbytes && txpackets) 1019 newitr = txbytes / txpackets; 1020 if (rxbytes && rxpackets) 1021 newitr = max(newitr, rxbytes / rxpackets); 1022 1023 /* 1024 * No packet was observed, so there is no size to work from. Report no 1025 * observation and let the caller keep the rate it already has. 1026 */ 1027 if (newitr == 0) 1028 return (0); 1029 1030 newitr += 24; /* account for hardware frame, crc */ 1031 /* set an upper boundary */ 1032 newitr = min(newitr, 3000); 1033 /* Be nice to the mid range */ 1034 if ((newitr > 300) && (newitr < 1200)) 1035 newitr = (newitr / 3); 1036 else 1037 newitr = (newitr / 2); 1038 1039 /* The value above was written straight to EITR; make it a rate */ 1040 newitr = IGC_AIM_DIVIDEND / newitr; 1041 1042 /* 1043 * Cap the rate: enable_aim=1 is the normal setting, enable_aim=2 opts 1044 * into the low latency end. The original was unbounded and would ask 1045 * for ~95k ints/s on minimum sized frames. There is deliberately no 1046 * floor, so jumbo traffic settles near 2.7k ints/s. 1047 */ 1048 if (sc->enable_aim == 1) 1049 newitr = min(newitr, IGC_INTS_20K); 1050 else 1051 newitr = min(newitr, IGC_INTS_70K); 1052 1053 return (newitr); 1054 } 1055 1056 /********************************************************************* 1057 * 1058 * Helper to calculate next EITR value for AIM 1059 * 1060 *********************************************************************/ 1061 static void 1062 igc_neweitr(struct igc_softc *sc, struct igc_rx_queue *que, 1063 struct rx_ring *rxr) 1064 { 1065 struct igc_hw *hw = &sc->hw; 1066 struct igc_tx_queue *tx_que; 1067 u32 ringbytes, ringpackets, rxbytes, rxpackets, txbytes, txpackets; 1068 u32 neweitr; 1069 int i; 1070 1071 igc_aim_rx_delta(rxr, &rxbytes, &rxpackets); 1072 1073 /* 1074 * A vector can service more than one TX ring when iflib is configured 1075 * with unequal RX and TX queue counts. Sample every ring routed to 1076 * this vector rather than treating the vector as a TX queue index. 1077 */ 1078 txbytes = txpackets = 0; 1079 for (i = 0; i < sc->tx_num_queues; i++) { 1080 tx_que = &sc->tx_queues[i]; 1081 if (tx_que->msix != que->msix) 1082 continue; 1083 igc_aim_tx_delta(&tx_que->txr, &ringbytes, &ringpackets); 1084 txbytes += ringbytes; 1085 txpackets += ringpackets; 1086 } 1087 1088 /* Idle, do nothing */ 1089 if (txbytes == 0 && rxbytes == 0) 1090 return; 1091 1092 if (sc->enable_aim == 0) { 1093 neweitr = igc_max_interrupt_rate; 1094 } else if (sc->link_speed < SPEED_1000) { 1095 /* Use half default (4K) ITR if sub-gig */ 1096 neweitr = IGC_INTS_4K; 1097 } else if (sc->shared->isc_max_frame_size * 2 > (sc->pba << 10)) { 1098 /* Want at least enough packet buffer for two frames to AIM */ 1099 neweitr = igc_max_interrupt_rate; 1100 } else { 1101 neweitr = igc_ring_itr(sc, rxbytes, rxpackets, txbytes, 1102 txpackets); 1103 /* No usable observation; leave the rate where it is */ 1104 if (neweitr == 0) 1105 return; 1106 } 1107 1108 neweitr = IGC_INTS_TO_EITR(neweitr); 1109 1110 neweitr |= IGC_EITR_CNT_IGNR; 1111 1112 if (neweitr != que->eitr_setting) { 1113 que->eitr_setting = neweitr; 1114 IGC_WRITE_REG(hw, IGC_EITR(que->msix), que->eitr_setting); 1115 } 1116 } 1117 1118 /********************************************************************* 1119 * 1120 * Fast Legacy/MSI Combined Interrupt Service routine 1121 * 1122 *********************************************************************/ 1123 int 1124 igc_intr(void *arg) 1125 { 1126 struct igc_softc *sc = arg; 1127 struct igc_hw *hw = &sc->hw; 1128 struct igc_rx_queue *que = &sc->rx_queues[0]; 1129 struct rx_ring *rxr = &que->rxr; 1130 if_ctx_t ctx = sc->ctx; 1131 u32 reg_icr; 1132 1133 reg_icr = IGC_READ_REG(hw, IGC_ICR); 1134 1135 /* Hot eject? */ 1136 if (reg_icr == 0xffffffff) 1137 return FILTER_STRAY; 1138 1139 /* Definitely not our interrupt. */ 1140 if (reg_icr == 0x0) 1141 return FILTER_STRAY; 1142 1143 if ((reg_icr & IGC_ICR_INT_ASSERTED) == 0) 1144 return FILTER_STRAY; 1145 1146 /* 1147 * Only MSI-X interrupts have one-shot behavior by taking advantage 1148 * of the EIAC register. Thus, explicitly disable interrupts. This 1149 * also works around the MSI message reordering errata on certain 1150 * systems. 1151 */ 1152 IFDI_INTR_DISABLE(ctx); 1153 1154 /* Link status change */ 1155 if (reg_icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) 1156 igc_handle_link(ctx); 1157 1158 if (reg_icr & IGC_ICR_RXO) 1159 sc->rx_overruns++; 1160 1161 igc_handle_fatal_error_intr(sc, reg_icr); 1162 1163 igc_neweitr(sc, que, rxr); 1164 1165 return (FILTER_SCHEDULE_THREAD); 1166 } 1167 1168 static int 1169 igc_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1170 { 1171 struct igc_softc *sc = iflib_get_softc(ctx); 1172 struct igc_rx_queue *rxq = &sc->rx_queues[rxqid]; 1173 1174 IGC_WRITE_REG(&sc->hw, IGC_EIMS, rxq->eims); 1175 return (0); 1176 } 1177 1178 static int 1179 igc_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1180 { 1181 struct igc_softc *sc = iflib_get_softc(ctx); 1182 struct igc_tx_queue *txq = &sc->tx_queues[txqid]; 1183 1184 IGC_WRITE_REG(&sc->hw, IGC_EIMS, txq->eims); 1185 return (0); 1186 } 1187 1188 /********************************************************************* 1189 * 1190 * MSI-X RX Interrupt Service routine 1191 * 1192 **********************************************************************/ 1193 static int 1194 igc_msix_que(void *arg) 1195 { 1196 struct igc_rx_queue *que = arg; 1197 struct igc_softc *sc = que->sc; 1198 struct rx_ring *rxr = &que->rxr; 1199 1200 ++que->irqs; 1201 1202 igc_neweitr(sc, que, rxr); 1203 1204 return (FILTER_SCHEDULE_THREAD); 1205 } 1206 1207 /********************************************************************* 1208 * 1209 * MSI-X Link Fast Interrupt Service routine 1210 * 1211 **********************************************************************/ 1212 static int 1213 igc_msix_link(void *arg) 1214 { 1215 struct igc_softc *sc = arg; 1216 u32 reg_icr; 1217 1218 ++sc->link_irq; 1219 MPASS(sc->hw.back != NULL); 1220 reg_icr = IGC_READ_REG(&sc->hw, IGC_ICR); 1221 1222 if (reg_icr & IGC_ICR_RXO) 1223 sc->rx_overruns++; 1224 1225 if (reg_icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) { 1226 igc_handle_link(sc->ctx); 1227 } 1228 igc_handle_fatal_error_intr(sc, reg_icr); 1229 1230 reg_icr = IGC_IMS_LSC; 1231 if (atomic_load_acq_32(&sc->fatal_error_state) == 1232 IGC_FATAL_ERROR_NONE) 1233 reg_icr |= IGC_IMS_FER; 1234 IGC_WRITE_REG(&sc->hw, IGC_IMS, reg_icr); 1235 IGC_WRITE_REG(&sc->hw, IGC_EIMS, sc->link_mask); 1236 1237 return (FILTER_HANDLED); 1238 } 1239 1240 static void 1241 igc_handle_link(void *context) 1242 { 1243 if_ctx_t ctx = context; 1244 struct igc_softc *sc = iflib_get_softc(ctx); 1245 1246 sc->hw.mac.get_link_status = true; 1247 iflib_admin_intr_deferred(ctx); 1248 } 1249 1250 /* 1251 * Fatal internal memory errors stop some or all device traffic. Capture the 1252 * read-clear indication before handing recovery to the iflib admin task. 1253 */ 1254 static void 1255 igc_handle_fatal_error_intr(struct igc_softc *sc, u32 icr) 1256 { 1257 struct igc_hw *hw; 1258 u32 lanerr, mngerr, pcieerr, peind; 1259 1260 if ((icr & IGC_ICR_FER) == 0) 1261 return; 1262 1263 hw = &sc->hw; 1264 IGC_WRITE_REG(hw, IGC_IMC, IGC_IMS_FER); 1265 if (!atomic_cmpset_32(&sc->fatal_error_state, 1266 IGC_FATAL_ERROR_NONE, IGC_FATAL_ERROR_CAPTURING)) 1267 return; 1268 1269 peind = IGC_READ_REG(hw, IGC_PEIND) & IGC_PEIND_FATAL_MASK; 1270 pcieerr = IGC_READ_REG(hw, IGC_PCIEERRSTS) & 1271 IGC_PCIEERRSTS_FATAL_MASK; 1272 lanerr = IGC_READ_REG(hw, IGC_LANPERRSTS) & 1273 IGC_LANPERRSTS_RETX_BUF; 1274 mngerr = IGC_READ_REG(hw, IGC_MNGPARSTS) & 1275 IGC_MNGPARSTS_FATAL_MASK; 1276 if (pcieerr != 0) 1277 peind |= IGC_PEIND_PCIE_PARITY_FATAL; 1278 if (lanerr != 0) 1279 peind |= IGC_PEIND_LANPORT_PARITY_FATAL; 1280 1281 sc->fatal_error_peind = peind; 1282 sc->fatal_error_pcie = pcieerr; 1283 sc->fatal_error_lan = lanerr; 1284 sc->fatal_error_mng = mngerr; 1285 atomic_store_rel_32(&sc->fatal_error_state, 1286 IGC_FATAL_ERROR_DETECTED); 1287 iflib_admin_intr_deferred(sc->ctx); 1288 } 1289 1290 static bool 1291 igc_handle_fatal_error_admin(struct igc_softc *sc) 1292 { 1293 u32 peind; 1294 1295 if (!atomic_cmpset_acq_32(&sc->fatal_error_state, 1296 IGC_FATAL_ERROR_DETECTED, IGC_FATAL_ERROR_RESET_REQUESTED)) 1297 return (atomic_load_acq_32(&sc->fatal_error_state) != 1298 IGC_FATAL_ERROR_NONE); 1299 1300 peind = sc->fatal_error_peind; 1301 if (peind & IGC_PEIND_LANPORT_PARITY_FATAL) 1302 sc->fatal_error_lan_count++; 1303 if (peind & IGC_PEIND_MNG_PARITY_FATAL) 1304 sc->fatal_error_mng_count++; 1305 if (peind & IGC_PEIND_PCIE_PARITY_FATAL) 1306 sc->fatal_error_pcie_count++; 1307 if (peind & IGC_PEIND_DMA_PARITY_FATAL) 1308 sc->fatal_error_dma_count++; 1309 if (peind == 0) 1310 sc->fatal_error_unknown_count++; 1311 1312 device_printf(sc->dev, 1313 "fatal internal memory error: PEIND %#x, PCIEERRSTS %#x, " 1314 "LANPERRSTS %#x, MNGPARSTS %#x\n", 1315 peind, sc->fatal_error_pcie, sc->fatal_error_lan, 1316 sc->fatal_error_mng); 1317 /* Management-memory recovery is owned by management firmware. */ 1318 if (peind != 0 && (peind & IGC_PEIND_HOST_FATAL_MASK) == 0) { 1319 sc->fatal_error_peind = 0; 1320 sc->fatal_error_pcie = 0; 1321 sc->fatal_error_lan = 0; 1322 sc->fatal_error_mng = 0; 1323 atomic_store_rel_32(&sc->fatal_error_state, 1324 IGC_FATAL_ERROR_NONE); 1325 IGC_WRITE_REG(&sc->hw, IGC_IMS, IGC_IMS_FER); 1326 IGC_WRITE_FLUSH(&sc->hw); 1327 return (true); 1328 } 1329 1330 device_printf(sc->dev, "requesting reset after memory error\n"); 1331 iflib_request_reset(sc->ctx); 1332 /* Re-enter the admin task so it observes the reset request. */ 1333 iflib_admin_intr_deferred(sc->ctx); 1334 return (true); 1335 } 1336 1337 /********************************************************************* 1338 * 1339 * Media Ioctl callback 1340 * 1341 * This routine is called whenever the user queries the status of 1342 * the interface using ifconfig. 1343 * 1344 **********************************************************************/ 1345 static void 1346 igc_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1347 { 1348 struct igc_softc *sc = iflib_get_softc(ctx); 1349 1350 INIT_DEBUGOUT("igc_if_media_status: begin"); 1351 1352 iflib_admin_intr_deferred(ctx); 1353 1354 ifmr->ifm_status = IFM_AVALID; 1355 ifmr->ifm_active = IFM_ETHER; 1356 1357 if (!sc->link_active) { 1358 return; 1359 } 1360 1361 ifmr->ifm_status |= IFM_ACTIVE; 1362 1363 switch (sc->link_speed) { 1364 case 10: 1365 ifmr->ifm_active |= IFM_10_T; 1366 break; 1367 case 100: 1368 ifmr->ifm_active |= IFM_100_TX; 1369 break; 1370 case 1000: 1371 ifmr->ifm_active |= IFM_1000_T; 1372 break; 1373 case 2500: 1374 ifmr->ifm_active |= IFM_2500_T; 1375 break; 1376 } 1377 1378 if (sc->link_duplex == FULL_DUPLEX) 1379 ifmr->ifm_active |= IFM_FDX; 1380 else 1381 ifmr->ifm_active |= IFM_HDX; 1382 } 1383 1384 /********************************************************************* 1385 * 1386 * Media Ioctl callback 1387 * 1388 * This routine is called when the user changes speed/duplex using 1389 * media/mediopt option with ifconfig. 1390 * 1391 **********************************************************************/ 1392 static int 1393 igc_if_media_change(if_ctx_t ctx) 1394 { 1395 struct igc_softc *sc = iflib_get_softc(ctx); 1396 struct ifmedia *ifm = iflib_get_media(ctx); 1397 1398 INIT_DEBUGOUT("igc_if_media_change: begin"); 1399 1400 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1401 return (EINVAL); 1402 1403 sc->hw.mac.autoneg = DO_AUTO_NEG; 1404 1405 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1406 case IFM_AUTO: 1407 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1408 break; 1409 case IFM_2500_T: 1410 sc->hw.phy.autoneg_advertised = ADVERTISE_2500_FULL; 1411 break; 1412 case IFM_1000_T: 1413 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1414 break; 1415 case IFM_100_TX: 1416 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1417 sc->hw.phy.autoneg_advertised = ADVERTISE_100_FULL; 1418 else 1419 sc->hw.phy.autoneg_advertised = ADVERTISE_100_HALF; 1420 break; 1421 case IFM_10_T: 1422 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1423 sc->hw.phy.autoneg_advertised = ADVERTISE_10_FULL; 1424 else 1425 sc->hw.phy.autoneg_advertised = ADVERTISE_10_HALF; 1426 break; 1427 default: 1428 device_printf(sc->dev, "Unsupported media type\n"); 1429 } 1430 1431 return (0); 1432 } 1433 1434 static int 1435 igc_if_set_promisc(if_ctx_t ctx, int flags) 1436 { 1437 struct igc_softc *sc = iflib_get_softc(ctx); 1438 if_t ifp = iflib_get_ifp(ctx); 1439 u32 reg_rctl; 1440 int mcnt = 0; 1441 1442 reg_rctl = IGC_READ_REG(&sc->hw, IGC_RCTL); 1443 reg_rctl &= ~(IGC_RCTL_SBP | IGC_RCTL_UPE); 1444 if (flags & IFF_ALLMULTI) 1445 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1446 else 1447 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1448 1449 /* Don't disable if in MAX groups */ 1450 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1451 reg_rctl &= ~IGC_RCTL_MPE; 1452 1453 if (flags & IFF_PROMISC) { 1454 reg_rctl |= (IGC_RCTL_UPE | IGC_RCTL_MPE); 1455 /* Turn this on if you want to see bad packets */ 1456 if (igc_debug_sbp) 1457 reg_rctl |= IGC_RCTL_SBP; 1458 } else if (flags & IFF_ALLMULTI) { 1459 reg_rctl |= IGC_RCTL_MPE; 1460 reg_rctl &= ~IGC_RCTL_UPE; 1461 } 1462 1463 if ((flags & IFF_PROMISC) || !igc_if_vlan_filter_used(ctx)) 1464 reg_rctl &= ~IGC_RCTL_VFE; 1465 else 1466 reg_rctl |= IGC_RCTL_VFE; 1467 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg_rctl); 1468 1469 return (0); 1470 } 1471 1472 static u_int 1473 igc_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1474 { 1475 u8 *mta = arg; 1476 1477 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1478 return (0); 1479 1480 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1481 1482 return (1); 1483 } 1484 1485 /********************************************************************* 1486 * Multicast Update 1487 * 1488 * This routine is called whenever multicast address list is updated. 1489 * 1490 **********************************************************************/ 1491 1492 static void 1493 igc_if_multi_set(if_ctx_t ctx) 1494 { 1495 struct igc_softc *sc = iflib_get_softc(ctx); 1496 if_t ifp = iflib_get_ifp(ctx); 1497 u8 *mta; /* Multicast array memory */ 1498 u32 reg_rctl = 0; 1499 int mcnt = 0; 1500 1501 IOCTL_DEBUGOUT("igc_set_multi: begin"); 1502 1503 mta = sc->mta; 1504 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1505 1506 mcnt = if_foreach_llmaddr(ifp, igc_copy_maddr, mta); 1507 1508 reg_rctl = IGC_READ_REG(&sc->hw, IGC_RCTL); 1509 1510 if (if_getflags(ifp) & IFF_PROMISC) { 1511 reg_rctl |= (IGC_RCTL_UPE | IGC_RCTL_MPE); 1512 /* Turn this on if you want to see bad packets */ 1513 if (igc_debug_sbp) 1514 reg_rctl |= IGC_RCTL_SBP; 1515 } else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1516 if_getflags(ifp) & IFF_ALLMULTI) { 1517 reg_rctl |= IGC_RCTL_MPE; 1518 reg_rctl &= ~IGC_RCTL_UPE; 1519 } else 1520 reg_rctl &= ~(IGC_RCTL_UPE | IGC_RCTL_MPE); 1521 1522 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1523 igc_update_mc_addr_list(&sc->hw, mta, mcnt); 1524 1525 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg_rctl); 1526 } 1527 1528 /********************************************************************* 1529 * Timer routine 1530 * 1531 * This routine schedules igc_if_update_admin_status() to check for 1532 * link status and to gather statistics as well as to perform some 1533 * controller-specific hardware patting. 1534 * 1535 **********************************************************************/ 1536 static void 1537 igc_if_timer(if_ctx_t ctx, uint16_t qid) 1538 { 1539 1540 if (qid != 0) 1541 return; 1542 1543 iflib_admin_intr_deferred(ctx); 1544 } 1545 1546 static void 1547 igc_apply_i225_ipg_workaround(struct igc_softc *sc) 1548 { 1549 struct igc_hw *hw = &sc->hw; 1550 u32 ipgt, tipg; 1551 1552 /* 1553 * I225 v1 cannot receive the minimum IPG required at 2.5 Gb/s. 1554 * Intel's documented back-to-back workaround is for the transmitter 1555 * to use a 15-byte IPG instead of 12 bytes. I225 v2 and later have 1556 * the receive-side fix and should retain the standard IPG. 1557 */ 1558 if (!igc_is_device_id_i225(hw) || 1559 hw->revision_id >= IGC_REVISION_2) 1560 return; 1561 1562 ipgt = sc->link_speed == SPEED_2500 ? IGC_I225_TIPG_IPGT_2P5 : 1563 DEFAULT_82543_TIPG_IPGT_COPPER; 1564 tipg = IGC_READ_REG(hw, IGC_TIPG); 1565 if ((tipg & IGC_TIPG_IPGT_MASK) == ipgt) 1566 return; 1567 1568 tipg &= ~IGC_TIPG_IPGT_MASK; 1569 tipg |= ipgt; 1570 IGC_WRITE_REG(hw, IGC_TIPG, tipg); 1571 } 1572 1573 static void 1574 igc_if_update_admin_status(if_ctx_t ctx) 1575 { 1576 struct igc_softc *sc = iflib_get_softc(ctx); 1577 struct igc_hw *hw = &sc->hw; 1578 device_t dev = iflib_get_dev(ctx); 1579 u32 link_check, thstat, ctrl; 1580 1581 if (igc_handle_fatal_error_admin(sc)) 1582 return; 1583 1584 link_check = thstat = ctrl = 0; 1585 /* Get the cached link value or read phy for real */ 1586 switch (hw->phy.media_type) { 1587 case igc_media_type_copper: 1588 if (hw->mac.get_link_status == true) { 1589 /* Do the work to read phy */ 1590 igc_check_for_link(hw); 1591 link_check = !hw->mac.get_link_status; 1592 } else 1593 link_check = true; 1594 break; 1595 case igc_media_type_unknown: 1596 igc_check_for_link(hw); 1597 link_check = !hw->mac.get_link_status; 1598 /* FALLTHROUGH */ 1599 default: 1600 break; 1601 } 1602 1603 /* Now check for a transition */ 1604 if (link_check && (sc->link_active == 0)) { 1605 igc_get_speed_and_duplex(hw, &sc->link_speed, 1606 &sc->link_duplex); 1607 if (bootverbose) 1608 device_printf(dev, "Link is up %d Mbps %s\n", 1609 sc->link_speed, 1610 ((sc->link_duplex == FULL_DUPLEX) ? 1611 "Full Duplex" : "Half Duplex")); 1612 sc->link_active = 1; 1613 iflib_link_state_change(ctx, LINK_STATE_UP, 1614 IF_Mbps(sc->link_speed)); 1615 } else if (!link_check && (sc->link_active == 1)) { 1616 sc->link_speed = 0; 1617 sc->link_duplex = 0; 1618 sc->link_active = 0; 1619 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1620 } 1621 igc_apply_i225_ipg_workaround(sc); 1622 igc_update_stats_counters(sc); 1623 } 1624 1625 /********************************************************************* 1626 * 1627 * This routine disables all traffic on the adapter by issuing a 1628 * global reset on the MAC. 1629 * 1630 **********************************************************************/ 1631 static void 1632 igc_if_stop(if_ctx_t ctx) 1633 { 1634 struct igc_softc *sc = iflib_get_softc(ctx); 1635 s32 error; 1636 1637 INIT_DEBUGOUT("igc_if_stop: begin"); 1638 1639 igc_led_restore(sc); 1640 igc_prepare_fatal_error_reset(sc); 1641 error = igc_reset_hw(&sc->hw); 1642 if (error != IGC_SUCCESS) { 1643 device_printf(sc->dev, "Hardware reset failed while stopping: " 1644 "%d\n", error); 1645 return; 1646 } 1647 igc_finish_fatal_error_reset(sc); 1648 IGC_WRITE_REG(&sc->hw, IGC_WUC, 0); 1649 } 1650 1651 /* 1652 * A PCIe-region parity failure stops PCIe and DMA traffic. Intel requires a 1653 * device reset before master disable in this case, unlike the normal reset 1654 * path, which disables the bus master first. 1655 */ 1656 static void 1657 igc_prepare_fatal_error_reset(struct igc_softc *sc) 1658 { 1659 struct igc_hw *hw; 1660 s32 error; 1661 u32 ctrl, pcieerr; 1662 int i; 1663 1664 if (atomic_load_acq_32(&sc->fatal_error_state) == 1665 IGC_FATAL_ERROR_NONE) 1666 return; 1667 1668 hw = &sc->hw; 1669 pcieerr = sc->fatal_error_pcie | 1670 (IGC_READ_REG(hw, IGC_PCIEERRSTS) & IGC_PCIEERRSTS_FATAL_MASK); 1671 if ((sc->fatal_error_peind & IGC_PEIND_PCIE_PARITY_FATAL) == 0 && 1672 pcieerr == 0) 1673 return; 1674 1675 ctrl = IGC_READ_REG(hw, IGC_CTRL); 1676 IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_DEV_RST); 1677 /* Do not access device registers for at least 3 ms after DEV_RST. */ 1678 msec_delay(3); 1679 for (i = 0; i < AUTO_READ_DONE_TIMEOUT; i++) { 1680 if ((IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_AUTO_RD) != 0 && 1681 (IGC_READ_REG(hw, IGC_STATUS) & IGC_STATUS_RST_DONE) != 0) 1682 break; 1683 msec_delay(1); 1684 } 1685 if (i == AUTO_READ_DONE_TIMEOUT) 1686 device_printf(sc->dev, 1687 "device reset did not complete during parity recovery\n"); 1688 error = igc_disable_pcie_master_generic(hw); 1689 if (error != IGC_SUCCESS) 1690 device_printf(sc->dev, 1691 "PCIe master disable failed during parity recovery: %d\n", 1692 error); 1693 pcieerr |= IGC_READ_REG(hw, IGC_PCIEERRSTS) & 1694 IGC_PCIEERRSTS_FATAL_MASK; 1695 if (pcieerr != 0) 1696 IGC_WRITE_REG(hw, IGC_PCIEERRSTS, pcieerr); 1697 } 1698 1699 static void 1700 igc_finish_fatal_error_reset(struct igc_softc *sc) 1701 { 1702 struct igc_hw *hw; 1703 u32 lanerr, pcieerr; 1704 1705 if (atomic_load_acq_32(&sc->fatal_error_state) == 1706 IGC_FATAL_ERROR_NONE) 1707 return; 1708 1709 hw = &sc->hw; 1710 pcieerr = sc->fatal_error_pcie | 1711 (IGC_READ_REG(hw, IGC_PCIEERRSTS) & IGC_PCIEERRSTS_FATAL_MASK); 1712 if (pcieerr != 0) 1713 IGC_WRITE_REG(hw, IGC_PCIEERRSTS, pcieerr); 1714 lanerr = sc->fatal_error_lan | 1715 (IGC_READ_REG(hw, IGC_LANPERRSTS) & IGC_LANPERRSTS_RETX_BUF); 1716 if (lanerr != 0) 1717 IGC_WRITE_REG(hw, IGC_LANPERRSTS, lanerr); 1718 /* 1719 * DEV_RST can relatch PEIND from a subordinate status register 1720 * before that register is cleared. Drain the recovered indication 1721 * before unmasking FER so a later error is not misattributed. 1722 */ 1723 (void)IGC_READ_REG(hw, IGC_PEIND); 1724 1725 sc->fatal_error_peind = 0; 1726 sc->fatal_error_pcie = 0; 1727 sc->fatal_error_lan = 0; 1728 sc->fatal_error_mng = 0; 1729 atomic_store_rel_32(&sc->fatal_error_state, IGC_FATAL_ERROR_NONE); 1730 } 1731 1732 /* 1733 * I225/I226 have three configurable LED outputs. DPDK uses LED1 for 1734 * adapter identification; retain that convention and preserve the OEM's 1735 * configuration for normal link and activity indication. 1736 */ 1737 static void 1738 igc_if_led_func(if_ctx_t ctx, int onoff) 1739 { 1740 struct igc_softc *sc; 1741 struct igc_hw *hw; 1742 u32 ledctl; 1743 1744 sc = iflib_get_softc(ctx); 1745 hw = &sc->hw; 1746 if (onoff) { 1747 if (!sc->led_active) { 1748 sc->ledctl_default = IGC_READ_REG(hw, IGC_LEDCTL); 1749 sc->led_active = true; 1750 } 1751 ledctl = sc->ledctl_default; 1752 ledctl &= ~(IGC_LEDCTL_LED1_MODE_MASK | 1753 IGC_LEDCTL_LED1_BLINK); 1754 ledctl |= IGC_LEDCTL_MODE_LED_ON << 1755 IGC_LEDCTL_LED1_MODE_SHIFT; 1756 IGC_WRITE_REG(hw, IGC_LEDCTL, ledctl); 1757 } else { 1758 igc_led_restore(sc); 1759 } 1760 } 1761 1762 static void 1763 igc_led_restore(struct igc_softc *sc) 1764 { 1765 1766 if (!sc->led_active) 1767 return; 1768 IGC_WRITE_REG(&sc->hw, IGC_LEDCTL, sc->ledctl_default); 1769 sc->led_active = false; 1770 } 1771 1772 /********************************************************************* 1773 * 1774 * Determine hardware revision. 1775 * 1776 **********************************************************************/ 1777 static void 1778 igc_identify_hardware(if_ctx_t ctx) 1779 { 1780 device_t dev = iflib_get_dev(ctx); 1781 struct igc_softc *sc = iflib_get_softc(ctx); 1782 1783 /* Make sure our PCI config space has the necessary stuff set */ 1784 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1785 1786 /* Save off the information about this board */ 1787 sc->hw.vendor_id = pci_get_vendor(dev); 1788 sc->hw.device_id = pci_get_device(dev); 1789 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1790 sc->hw.subsystem_vendor_id = 1791 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1792 sc->hw.subsystem_device_id = 1793 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1794 1795 /* Do Shared Code Init and Setup */ 1796 if (igc_set_mac_type(&sc->hw)) { 1797 device_printf(dev, "Setup init failure\n"); 1798 return; 1799 } 1800 } 1801 1802 /********************************************************************* 1803 * 1804 * Intel's I225/I226 Specification Update, erratum 2, states that I225 1805 * devices can incorrectly enter L1 substates while CLKREQ# is asserted, 1806 * causing repeated L1-substate entry and exit. Disable both ASPM and 1807 * PCI-PM L1.2, as the erratum can occur while idle or in D3. 1808 * 1809 * I226 devices have a separate erratum where ASPM L1.2 exit latency can 1810 * exceed what the packet buffer can tolerate under load. Disabling ASPM 1811 * L1.2 on the device itself works around the issue. 1812 * 1813 **********************************************************************/ 1814 static void 1815 igc_disable_broken_l1_2(if_ctx_t ctx) 1816 { 1817 device_t dev = iflib_get_dev(ctx); 1818 struct igc_softc *sc = iflib_get_softc(ctx); 1819 int cap; 1820 uint32_t ctl1, mask; 1821 1822 if (igc_is_device_id_i225(&sc->hw)) 1823 mask = PCIM_L1PM_CTL1_ASPM_L1_2 | 1824 PCIM_L1PM_CTL1_PCIPM_L1_2; 1825 else if (igc_is_device_id_i226(&sc->hw)) 1826 mask = PCIM_L1PM_CTL1_ASPM_L1_2; 1827 else 1828 return; 1829 1830 if (pci_find_extcap(dev, PCIZ_L1PM, &cap) != 0) 1831 return; 1832 1833 ctl1 = pci_read_config(dev, cap + PCIR_L1PM_CTL1, 4); 1834 ctl1 &= ~mask; 1835 pci_write_config(dev, cap + PCIR_L1PM_CTL1, ctl1, 4); 1836 } 1837 1838 static int 1839 igc_allocate_pci_resources(if_ctx_t ctx) 1840 { 1841 struct igc_softc *sc = iflib_get_softc(ctx); 1842 device_t dev = iflib_get_dev(ctx); 1843 int rid; 1844 1845 rid = PCIR_BAR(0); 1846 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1847 &rid, RF_ACTIVE); 1848 if (sc->memory == NULL) { 1849 device_printf(dev, 1850 "Unable to allocate bus resource: memory\n"); 1851 return (ENXIO); 1852 } 1853 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 1854 sc->osdep.mem_bus_space_handle = 1855 rman_get_bushandle(sc->memory); 1856 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 1857 1858 sc->hw.back = &sc->osdep; 1859 1860 return (0); 1861 } 1862 1863 /********************************************************************* 1864 * 1865 * Set up the MSI-X Interrupt handlers 1866 * 1867 **********************************************************************/ 1868 static int 1869 igc_if_msix_intr_assign(if_ctx_t ctx, int msix) 1870 { 1871 struct igc_softc *sc = iflib_get_softc(ctx); 1872 struct igc_rx_queue *rx_que = sc->rx_queues; 1873 struct igc_tx_queue *tx_que = sc->tx_queues; 1874 int error, rid, i, vector = 0, rx_vectors; 1875 char buf[16]; 1876 1877 /* First set up ring resources */ 1878 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { 1879 rid = vector + 1; 1880 snprintf(buf, sizeof(buf), "rxq%d", i); 1881 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, 1882 IFLIB_INTR_RXTX, igc_msix_que, rx_que, rx_que->me, buf); 1883 if (error) { 1884 device_printf(iflib_get_dev(ctx), 1885 "Failed to allocate que int %d err: %d", 1886 i, error); 1887 sc->rx_num_queues = i + 1; 1888 goto fail; 1889 } 1890 1891 rx_que->msix = vector; 1892 1893 /* 1894 * Set the bit to enable interrupt 1895 * in IGC_IMS -- bits 20 and 21 1896 * are for RX0 and RX1, note this has 1897 * NOTHING to do with the MSI-X vector 1898 */ 1899 rx_que->eims = 1 << vector; 1900 } 1901 rx_vectors = vector; 1902 1903 vector = 0; 1904 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { 1905 snprintf(buf, sizeof(buf), "txq%d", i); 1906 tx_que = &sc->tx_queues[i]; 1907 iflib_softirq_alloc_generic(ctx, 1908 &sc->rx_queues[i % sc->rx_num_queues].que_irq, 1909 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 1910 1911 tx_que->msix = (vector % sc->rx_num_queues); 1912 1913 /* 1914 * Set the bit to enable interrupt 1915 * in IGC_IMS -- bits 22 and 23 1916 * are for TX0 and TX1, note this has 1917 * NOTHING to do with the MSI-X vector 1918 */ 1919 tx_que->eims = 1 << i; 1920 } 1921 1922 /* Link interrupt */ 1923 rid = rx_vectors + 1; 1924 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, 1925 igc_msix_link, sc, 0, "aq"); 1926 1927 if (error) { 1928 device_printf(iflib_get_dev(ctx), 1929 "Failed to register admin handler"); 1930 goto fail; 1931 } 1932 sc->linkvec = rx_vectors; 1933 return (0); 1934 fail: 1935 iflib_irq_free(ctx, &sc->irq); 1936 rx_que = sc->rx_queues; 1937 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) 1938 iflib_irq_free(ctx, &rx_que->que_irq); 1939 return (error); 1940 } 1941 1942 static void 1943 igc_configure_queues(struct igc_softc *sc) 1944 { 1945 struct igc_hw *hw = &sc->hw; 1946 struct igc_rx_queue *rx_que; 1947 struct igc_tx_queue *tx_que; 1948 u32 ivar = 0; 1949 1950 /* First turn on RSS capability */ 1951 IGC_WRITE_REG(hw, IGC_GPIE, 1952 IGC_GPIE_MSIX_MODE | IGC_GPIE_EIAME | IGC_GPIE_PBA | 1953 IGC_GPIE_NSICR); 1954 1955 /* Turn on MSI-X */ 1956 /* RX entries */ 1957 for (int i = 0; i < sc->rx_num_queues; i++) { 1958 u32 index = i >> 1; 1959 ivar = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, index); 1960 rx_que = &sc->rx_queues[i]; 1961 if (i & 1) { 1962 ivar &= 0xFF00FFFF; 1963 ivar |= (rx_que->msix | IGC_IVAR_VALID) << 16; 1964 } else { 1965 ivar &= 0xFFFFFF00; 1966 ivar |= rx_que->msix | IGC_IVAR_VALID; 1967 } 1968 IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, index, ivar); 1969 } 1970 /* TX entries */ 1971 for (int i = 0; i < sc->tx_num_queues; i++) { 1972 u32 index = i >> 1; 1973 ivar = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, index); 1974 tx_que = &sc->tx_queues[i]; 1975 if (i & 1) { 1976 ivar &= 0x00FFFFFF; 1977 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 24; 1978 } else { 1979 ivar &= 0xFFFF00FF; 1980 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 8; 1981 } 1982 IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, index, ivar); 1983 sc->que_mask |= tx_que->eims; 1984 } 1985 1986 /* And for the link interrupt */ 1987 ivar = (sc->linkvec | IGC_IVAR_VALID) << 8; 1988 sc->link_mask = 1 << sc->linkvec; 1989 IGC_WRITE_REG(hw, IGC_IVAR_MISC, ivar); 1990 1991 return; 1992 } 1993 1994 static void 1995 igc_initialize_interrupt_rate(struct igc_softc *sc) 1996 { 1997 struct igc_hw *hw = &sc->hw; 1998 struct igc_rx_queue *rx_que; 1999 u32 newitr; 2000 2001 newitr = IGC_INTS_TO_EITR(igc_max_interrupt_rate); 2002 newitr |= IGC_EITR_CNT_IGNR; 2003 2004 for (int i = 0; i < sc->rx_num_queues; i++) { 2005 rx_que = &sc->rx_queues[i]; 2006 rx_que->eitr_setting = newitr; 2007 IGC_WRITE_REG(hw, IGC_EITR(rx_que->msix), 2008 rx_que->eitr_setting); 2009 } 2010 } 2011 2012 static void 2013 igc_free_pci_resources(if_ctx_t ctx) 2014 { 2015 struct igc_softc *sc = iflib_get_softc(ctx); 2016 struct igc_rx_queue *que = sc->rx_queues; 2017 device_t dev = iflib_get_dev(ctx); 2018 2019 /* Release all MSI-X queue resources */ 2020 if (sc->intr_type == IFLIB_INTR_MSIX) 2021 iflib_irq_free(ctx, &sc->irq); 2022 2023 if (que != NULL) { 2024 for (int i = 0; i < sc->rx_num_queues; i++, que++) 2025 iflib_irq_free(ctx, &que->que_irq); 2026 } 2027 2028 if (sc->memory != NULL) { 2029 bus_release_resource(dev, SYS_RES_MEMORY, 2030 rman_get_rid(sc->memory), sc->memory); 2031 sc->memory = NULL; 2032 } 2033 2034 if (sc->flash != NULL) { 2035 bus_release_resource(dev, SYS_RES_MEMORY, 2036 rman_get_rid(sc->flash), sc->flash); 2037 sc->flash = NULL; 2038 } 2039 2040 if (sc->ioport != NULL) { 2041 bus_release_resource(dev, SYS_RES_IOPORT, 2042 rman_get_rid(sc->ioport), sc->ioport); 2043 sc->ioport = NULL; 2044 } 2045 } 2046 2047 /* Set up MSI or MSI-X */ 2048 static int 2049 igc_setup_msix(if_ctx_t ctx) 2050 { 2051 return (0); 2052 } 2053 2054 /********************************************************************* 2055 * 2056 * Initialize the DMA Coalescing feature 2057 * 2058 **********************************************************************/ 2059 static void 2060 igc_init_dmac(struct igc_softc *sc, u32 pba) 2061 { 2062 device_t dev = sc->dev; 2063 struct igc_hw *hw = &sc->hw; 2064 u32 dmac, reg = ~IGC_DMACR_DMAC_EN; 2065 u16 hwm; 2066 u16 max_frame_size; 2067 int status; 2068 2069 max_frame_size = sc->shared->isc_max_frame_size; 2070 2071 if (sc->dmac == 0) { /* Disabling it */ 2072 IGC_WRITE_REG(hw, IGC_DMACR, reg); 2073 return; 2074 } else 2075 device_printf(dev, "DMA Coalescing enabled\n"); 2076 2077 /* Set starting threshold */ 2078 IGC_WRITE_REG(hw, IGC_DMCTXTH, 0); 2079 2080 hwm = 64 * pba - max_frame_size / 16; 2081 if (hwm < 64 * (pba - 6)) 2082 hwm = 64 * (pba - 6); 2083 reg = IGC_READ_REG(hw, IGC_FCRTC); 2084 reg &= ~IGC_FCRTC_RTH_COAL_MASK; 2085 reg |= ((hwm << IGC_FCRTC_RTH_COAL_SHIFT) 2086 & IGC_FCRTC_RTH_COAL_MASK); 2087 IGC_WRITE_REG(hw, IGC_FCRTC, reg); 2088 2089 dmac = pba - max_frame_size / 512; 2090 if (dmac < pba - 10) 2091 dmac = pba - 10; 2092 reg = IGC_READ_REG(hw, IGC_DMACR); 2093 reg &= ~IGC_DMACR_DMACTHR_MASK; 2094 reg |= ((dmac << IGC_DMACR_DMACTHR_SHIFT) 2095 & IGC_DMACR_DMACTHR_MASK); 2096 2097 /* transition to L0x or L1 if available..*/ 2098 reg |= (IGC_DMACR_DMAC_EN | IGC_DMACR_DMAC_LX_MASK); 2099 2100 /* Check if status is 2.5Gb backplane connection 2101 * before configuration of watchdog timer, which is 2102 * in msec values in 12.8usec intervals 2103 * watchdog timer= msec values in 32usec intervals 2104 * for non 2.5Gb connection 2105 */ 2106 status = IGC_READ_REG(hw, IGC_STATUS); 2107 if ((status & IGC_STATUS_2P5_SKU) && 2108 (!(status & IGC_STATUS_2P5_SKU_OVER))) 2109 reg |= ((sc->dmac * 5) >> 6); 2110 else 2111 reg |= (sc->dmac >> 5); 2112 2113 IGC_WRITE_REG(hw, IGC_DMACR, reg); 2114 2115 IGC_WRITE_REG(hw, IGC_DMCRTRH, 0); 2116 2117 /* Set the interval before transition */ 2118 reg = IGC_READ_REG(hw, IGC_DMCTLX); 2119 reg |= IGC_DMCTLX_DCFLUSH_DIS; 2120 2121 /* 2122 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2123 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2124 */ 2125 status = IGC_READ_REG(hw, IGC_STATUS); 2126 if ((status & IGC_STATUS_2P5_SKU) && 2127 (!(status & IGC_STATUS_2P5_SKU_OVER))) 2128 reg |= 0xA; 2129 else 2130 reg |= 0x4; 2131 2132 IGC_WRITE_REG(hw, IGC_DMCTLX, reg); 2133 2134 /* free space in tx packet buffer to wake from DMA coal */ 2135 IGC_WRITE_REG(hw, IGC_DMCTXTH, (IGC_TXPBSIZE - 2136 (2 * max_frame_size)) >> 6); 2137 2138 /* make low power state decision controlled by DMA coal */ 2139 reg = IGC_READ_REG(hw, IGC_PCIEMISC); 2140 reg &= ~IGC_PCIEMISC_LX_DECISION; 2141 IGC_WRITE_REG(hw, IGC_PCIEMISC, reg); 2142 } 2143 2144 /********************************************************************* 2145 * 2146 * Initialize the hardware to a configuration as specified by the 2147 * softc structure. 2148 * 2149 **********************************************************************/ 2150 static int 2151 igc_reset(if_ctx_t ctx) 2152 { 2153 device_t dev = iflib_get_dev(ctx); 2154 struct igc_softc *sc = iflib_get_softc(ctx); 2155 struct igc_hw *hw = &sc->hw; 2156 u32 rx_buffer_size; 2157 u32 pba; 2158 s32 error; 2159 2160 INIT_DEBUGOUT("igc_reset: begin"); 2161 igc_led_restore(sc); 2162 /* Let the firmware know the OS is in control */ 2163 igc_get_hw_control(sc); 2164 2165 /* 2166 * Packet Buffer Allocation (PBA) 2167 * Writing PBA sets the receive portion of the buffer 2168 * the remainder is used for the transmit buffer. 2169 */ 2170 pba = IGC_PBA_34K; 2171 2172 INIT_DEBUGOUT1("igc_reset: pba=%dK",pba); 2173 2174 /* 2175 * These parameters control the automatic generation (Tx) and 2176 * response (Rx) to Ethernet PAUSE frames. 2177 * - High water mark should allow for at least two frames to be 2178 * received after sending an XOFF. 2179 * - Low water mark works best when it is very near the high water 2180 * mark. 2181 * This allows the receiver to restart by sending XON when it has 2182 * drained a bit. Here we use an arbitrary value of 1500 which will 2183 * restart after one full frame is pulled from the buffer. There 2184 * could be several smaller frames in the buffer and if so they will 2185 * not trigger the XON until their total number reduces the buffer 2186 * by 1500. 2187 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2188 */ 2189 rx_buffer_size = (pba & 0xffff) << 10; 2190 hw->fc.high_water = rx_buffer_size - 2191 roundup2(sc->hw.mac.max_frame_size, 1024); 2192 /* 16-byte granularity */ 2193 hw->fc.low_water = hw->fc.high_water - 16; 2194 2195 hw->fc.requested_mode = sc->fc; 2196 2197 hw->fc.pause_time = IGC_FC_PAUSE_TIME; 2198 2199 hw->fc.send_xon = true; 2200 2201 /* Issue a global reset */ 2202 error = igc_reset_hw(hw); 2203 if (error != IGC_SUCCESS) { 2204 device_printf(dev, "Hardware reset failed: %d\n", error); 2205 return (error); 2206 } 2207 IGC_WRITE_REG(hw, IGC_WUC, 0); 2208 2209 /* and a re-init */ 2210 error = igc_init_hw(hw); 2211 if (error != IGC_SUCCESS) { 2212 device_printf(dev, "Hardware initialization failed: %d\n", 2213 error); 2214 return (error); 2215 } 2216 igc_finish_fatal_error_reset(sc); 2217 2218 /* Setup DMA Coalescing */ 2219 igc_init_dmac(sc, pba); 2220 2221 /* Save the final PBA off if it needs to be used elsewhere i.e. AIM */ 2222 sc->pba = pba; 2223 2224 IGC_WRITE_REG(hw, IGC_VET, ETHERTYPE_VLAN); 2225 igc_get_phy_info(hw); 2226 igc_check_for_link(hw); 2227 2228 return (IGC_SUCCESS); 2229 } 2230 2231 /* 2232 * Initialise the RSS mapping for NICs that support multiple transmit/ 2233 * receive rings. 2234 */ 2235 2236 #define RSSKEYLEN 10 2237 static void 2238 igc_initialize_rss_mapping(struct igc_softc *sc) 2239 { 2240 struct igc_hw *hw = &sc->hw; 2241 int i; 2242 int queue_id; 2243 u32 reta; 2244 u32 rss_key[RSSKEYLEN], mrqc, shift = 0; 2245 u32 rss_hash_config; 2246 2247 /* 2248 * The redirection table controls which destination 2249 * queue each bucket redirects traffic to. 2250 * Each DWORD represents four queues, with the LSB 2251 * being the first queue in the DWORD. 2252 * 2253 * This just allocates buckets to queues using round-robin 2254 * allocation. 2255 * 2256 * NOTE: It Just Happens to line up with the default 2257 * RSS allocation method. 2258 */ 2259 2260 /* Warning FM follows */ 2261 reta = 0; 2262 for (i = 0; i < 128; i++) { 2263 #ifdef RSS 2264 queue_id = rss_get_indirection_to_bucket(i); 2265 /* 2266 * If we have more queues than buckets, we'll 2267 * end up mapping buckets to a subset of the 2268 * queues. 2269 * 2270 * If we have more buckets than queues, we'll 2271 * end up instead assigning multiple buckets 2272 * to queues. 2273 * 2274 * Both are suboptimal, but we need to handle 2275 * the case so we don't go out of bounds 2276 * indexing arrays and such. 2277 */ 2278 queue_id = queue_id % sc->rx_num_queues; 2279 #else 2280 queue_id = (i % sc->rx_num_queues); 2281 #endif 2282 /* Adjust if required */ 2283 queue_id = queue_id << shift; 2284 2285 /* 2286 * The low 8 bits are for hash value (n+0); 2287 * The next 8 bits are for hash value (n+1), etc. 2288 */ 2289 reta = reta >> 8; 2290 reta = reta | ( ((uint32_t) queue_id) << 24); 2291 if ((i & 3) == 3) { 2292 IGC_WRITE_REG(hw, IGC_RETA(i >> 2), reta); 2293 reta = 0; 2294 } 2295 } 2296 2297 /* Now fill in hash table */ 2298 2299 /* 2300 * MRQC: Multiple Receive Queues Command 2301 * Set queuing to RSS control, number depends on the device. 2302 */ 2303 mrqc = IGC_MRQC_ENABLE_RSS_4Q; 2304 2305 /* XXX ew typecasting */ 2306 rss_getkey((uint8_t *) &rss_key); 2307 for (i = 0; i < RSSKEYLEN; i++) 2308 IGC_WRITE_REG_ARRAY(hw, IGC_RSSRK(0), i, rss_key[i]); 2309 2310 /* 2311 * Configure the RSS fields to hash upon. Hash exactly what the 2312 * stack hashes, so that hardware and software agree on the hash 2313 * of a flow. 2314 */ 2315 rss_hash_config = rss_gethashconfig(); 2316 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV4) 2317 mrqc |= IGC_MRQC_RSS_FIELD_IPV4; 2318 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV4) 2319 mrqc |= IGC_MRQC_RSS_FIELD_IPV4_TCP; 2320 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6) 2321 mrqc |= IGC_MRQC_RSS_FIELD_IPV6; 2322 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV6) 2323 mrqc |= IGC_MRQC_RSS_FIELD_IPV6_TCP; 2324 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV6_EX) 2325 mrqc |= IGC_MRQC_RSS_FIELD_IPV6_TCP_EX; 2326 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV4) 2327 mrqc |= IGC_MRQC_RSS_FIELD_IPV4_UDP; 2328 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV6) 2329 mrqc |= IGC_MRQC_RSS_FIELD_IPV6_UDP; 2330 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV6_EX) 2331 mrqc |= IGC_MRQC_RSS_FIELD_IPV6_UDP_EX; 2332 2333 IGC_WRITE_REG(hw, IGC_MRQC, mrqc); 2334 } 2335 2336 /********************************************************************* 2337 * 2338 * Setup networking device structure and register interface media. 2339 * 2340 **********************************************************************/ 2341 static int 2342 igc_setup_interface(if_ctx_t ctx) 2343 { 2344 if_t ifp = iflib_get_ifp(ctx); 2345 struct igc_softc *sc = iflib_get_softc(ctx); 2346 if_softc_ctx_t scctx = sc->shared; 2347 2348 INIT_DEBUGOUT("igc_setup_interface: begin"); 2349 2350 /* Single Queue */ 2351 if (sc->tx_num_queues == 1) { 2352 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2353 if_setsendqready(ifp); 2354 } 2355 2356 /* 2357 * Specify the media types supported by this adapter and register 2358 * callbacks to update media and link information 2359 */ 2360 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 2361 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2362 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2363 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2364 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2365 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2366 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_T, 0, NULL); 2367 2368 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2369 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 2370 return (0); 2371 } 2372 2373 static int 2374 igc_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 2375 int ntxqs, int ntxqsets) 2376 { 2377 struct igc_softc *sc = iflib_get_softc(ctx); 2378 if_softc_ctx_t scctx = sc->shared; 2379 int error = IGC_SUCCESS; 2380 struct igc_tx_queue *que; 2381 int i, j; 2382 2383 MPASS(sc->tx_num_queues > 0); 2384 MPASS(sc->tx_num_queues == ntxqsets); 2385 2386 /* First allocate the top level queue structs */ 2387 if (!(sc->tx_queues = 2388 (struct igc_tx_queue *) malloc(sizeof(struct igc_tx_queue) * 2389 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2390 device_printf(iflib_get_dev(ctx), 2391 "Unable to allocate queue memory\n"); 2392 return(ENOMEM); 2393 } 2394 2395 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { 2396 /* Set up some basics */ 2397 2398 struct tx_ring *txr = &que->txr; 2399 KASSERT(__is_aligned(&txr->tx_aim_snapshot, sizeof(uint64_t)), 2400 ("%s: misaligned TX AIM snapshot %p", __func__, 2401 &txr->tx_aim_snapshot)); 2402 txr->sc = que->sc = sc; 2403 que->me = txr->me = i; 2404 2405 /* Allocate report status array */ 2406 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * 2407 scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2408 device_printf(iflib_get_dev(ctx), 2409 "failed to allocate rs_idxs memory\n"); 2410 error = ENOMEM; 2411 goto fail; 2412 } 2413 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2414 txr->tx_rsq[j] = QIDX_INVALID; 2415 /* get virtual and physical address of the hardware queues */ 2416 txr->tx_base = (struct igc_tx_desc *)vaddrs[i*ntxqs]; 2417 txr->tx_paddr = paddrs[i*ntxqs]; 2418 } 2419 2420 if (bootverbose) 2421 device_printf(iflib_get_dev(ctx), 2422 "allocated for %d tx_queues\n", sc->tx_num_queues); 2423 return (0); 2424 fail: 2425 igc_if_queues_free(ctx); 2426 return (error); 2427 } 2428 2429 static int 2430 igc_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 2431 int nrxqs, int nrxqsets) 2432 { 2433 struct igc_softc *sc = iflib_get_softc(ctx); 2434 int error = IGC_SUCCESS; 2435 struct igc_rx_queue *que; 2436 int i; 2437 2438 MPASS(sc->rx_num_queues > 0); 2439 MPASS(sc->rx_num_queues == nrxqsets); 2440 2441 /* First allocate the top level queue structs */ 2442 if (!(sc->rx_queues = 2443 (struct igc_rx_queue *) malloc(sizeof(struct igc_rx_queue) * 2444 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2445 device_printf(iflib_get_dev(ctx), 2446 "Unable to allocate queue memory\n"); 2447 error = ENOMEM; 2448 goto fail; 2449 } 2450 2451 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 2452 /* Set up some basics */ 2453 struct rx_ring *rxr = &que->rxr; 2454 KASSERT(__is_aligned(&rxr->rx_aim_snapshot, sizeof(uint64_t)), 2455 ("%s: misaligned RX AIM snapshot %p", __func__, 2456 &rxr->rx_aim_snapshot)); 2457 rxr->sc = que->sc = sc; 2458 rxr->que = que; 2459 que->me = rxr->me = i; 2460 2461 /* get virtual and physical address of the hardware queues */ 2462 rxr->rx_base = (union igc_rx_desc_extended *)vaddrs[i*nrxqs]; 2463 rxr->rx_paddr = paddrs[i*nrxqs]; 2464 } 2465 2466 if (bootverbose) 2467 device_printf(iflib_get_dev(ctx), 2468 "allocated for %d rx_queues\n", sc->rx_num_queues); 2469 2470 return (0); 2471 fail: 2472 igc_if_queues_free(ctx); 2473 return (error); 2474 } 2475 2476 static void 2477 igc_if_queues_free(if_ctx_t ctx) 2478 { 2479 struct igc_softc *sc = iflib_get_softc(ctx); 2480 struct igc_tx_queue *tx_que = sc->tx_queues; 2481 struct igc_rx_queue *rx_que = sc->rx_queues; 2482 2483 if (tx_que != NULL) { 2484 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 2485 struct tx_ring *txr = &tx_que->txr; 2486 if (txr->tx_rsq == NULL) 2487 break; 2488 2489 free(txr->tx_rsq, M_DEVBUF); 2490 txr->tx_rsq = NULL; 2491 } 2492 free(sc->tx_queues, M_DEVBUF); 2493 sc->tx_queues = NULL; 2494 } 2495 2496 if (rx_que != NULL) { 2497 free(sc->rx_queues, M_DEVBUF); 2498 sc->rx_queues = NULL; 2499 } 2500 2501 if (sc->mta != NULL) { 2502 free(sc->mta, M_DEVBUF); 2503 sc->mta = NULL; 2504 } 2505 } 2506 2507 /********************************************************************* 2508 * 2509 * Enable transmit unit. 2510 * 2511 **********************************************************************/ 2512 static void 2513 igc_initialize_transmit_unit(if_ctx_t ctx) 2514 { 2515 struct igc_softc *sc = iflib_get_softc(ctx); 2516 if_softc_ctx_t scctx = sc->shared; 2517 struct igc_tx_queue *que; 2518 struct tx_ring *txr; 2519 struct igc_hw *hw = &sc->hw; 2520 u32 tctl, txdctl = 0; 2521 2522 INIT_DEBUGOUT("igc_initialize_transmit_unit: begin"); 2523 2524 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 2525 u64 bus_addr; 2526 caddr_t offp, endp; 2527 2528 que = &sc->tx_queues[i]; 2529 txr = &que->txr; 2530 bus_addr = txr->tx_paddr; 2531 2532 /* Clear checksum offload context. */ 2533 offp = (caddr_t)&txr->csum_flags; 2534 endp = (caddr_t)(txr + 1); 2535 bzero(offp, endp - offp); 2536 2537 /* Base and Len of TX Ring */ 2538 IGC_WRITE_REG(hw, IGC_TDLEN(i), 2539 scctx->isc_ntxd[0] * sizeof(struct igc_tx_desc)); 2540 IGC_WRITE_REG(hw, IGC_TDBAH(i), 2541 (u32)(bus_addr >> 32)); 2542 IGC_WRITE_REG(hw, IGC_TDBAL(i), 2543 (u32)bus_addr); 2544 /* Init the HEAD/TAIL indices */ 2545 IGC_WRITE_REG(hw, IGC_TDT(i), 0); 2546 IGC_WRITE_REG(hw, IGC_TDH(i), 0); 2547 2548 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2549 IGC_READ_REG(&sc->hw, IGC_TDBAL(i)), 2550 IGC_READ_REG(&sc->hw, IGC_TDLEN(i))); 2551 2552 /* WTHRESH must be zero when iflib uses sparse RS. */ 2553 txdctl = IGC_TX_PTHRESH | (IGC_TX_HTHRESH << 8) | 2554 IGC_TXDCTL_QUEUE_ENABLE; 2555 2556 IGC_WRITE_REG(hw, IGC_TXDCTL(i), txdctl); 2557 } 2558 2559 /* Program the Transmit Control Register */ 2560 tctl = IGC_READ_REG(&sc->hw, IGC_TCTL); 2561 tctl &= ~IGC_TCTL_CT; 2562 tctl |= (IGC_TCTL_PSP | IGC_TCTL_RTLC | IGC_TCTL_EN | 2563 (IGC_COLLISION_THRESHOLD << IGC_CT_SHIFT)); 2564 2565 /* This write will effectively turn on the transmit unit. */ 2566 IGC_WRITE_REG(&sc->hw, IGC_TCTL, tctl); 2567 } 2568 2569 /********************************************************************* 2570 * 2571 * Enable receive unit. 2572 * 2573 **********************************************************************/ 2574 #define BSIZEPKT_ROUNDUP ((1<<IGC_SRRCTL_BSIZEPKT_SHIFT)-1) 2575 2576 static void 2577 igc_initialize_receive_unit(if_ctx_t ctx) 2578 { 2579 struct igc_softc *sc = iflib_get_softc(ctx); 2580 if_softc_ctx_t scctx = sc->shared; 2581 if_t ifp = iflib_get_ifp(ctx); 2582 struct igc_hw *hw = &sc->hw; 2583 struct igc_rx_queue *que; 2584 int i; 2585 u32 psize, rctl, rxcsum, srrctl = 0; 2586 2587 INIT_DEBUGOUT("igc_initialize_receive_units: begin"); 2588 2589 /* 2590 * Make sure receives are disabled while setting 2591 * up the descriptor ring 2592 */ 2593 rctl = IGC_READ_REG(hw, IGC_RCTL); 2594 IGC_WRITE_REG(hw, IGC_RCTL, rctl & ~IGC_RCTL_EN); 2595 2596 /* Setup the Receive Control Register */ 2597 rctl &= ~(3 << IGC_RCTL_MO_SHIFT); 2598 rctl |= IGC_RCTL_EN | IGC_RCTL_BAM | 2599 IGC_RCTL_LBM_NO | IGC_RCTL_RDMTS_HALF | 2600 (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT); 2601 2602 /* Do not store bad packets */ 2603 rctl &= ~IGC_RCTL_SBP; 2604 2605 /* Enable Long Packet receive */ 2606 if (if_getmtu(ifp) > ETHERMTU) 2607 rctl |= IGC_RCTL_LPE; 2608 else 2609 rctl &= ~IGC_RCTL_LPE; 2610 2611 /* Strip the CRC */ 2612 if (!igc_disable_crc_stripping) 2613 rctl |= IGC_RCTL_SECRC; 2614 2615 rxcsum = IGC_READ_REG(hw, IGC_RXCSUM); 2616 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 2617 rxcsum |= IGC_RXCSUM_CRCOFL; 2618 if (sc->tx_num_queues > 1) 2619 rxcsum |= IGC_RXCSUM_PCSD; 2620 else 2621 rxcsum |= IGC_RXCSUM_IPPCSE; 2622 } else { 2623 if (sc->tx_num_queues > 1) 2624 rxcsum |= IGC_RXCSUM_PCSD; 2625 else 2626 rxcsum &= ~IGC_RXCSUM_TUOFL; 2627 } 2628 IGC_WRITE_REG(hw, IGC_RXCSUM, rxcsum); 2629 2630 if (sc->rx_num_queues > 1) 2631 igc_initialize_rss_mapping(sc); 2632 2633 if (if_getmtu(ifp) > ETHERMTU) { 2634 psize = scctx->isc_max_frame_size; 2635 /* are we on a vlan? */ 2636 if (if_vlantrunkinuse(ifp)) 2637 psize += VLAN_TAG_SIZE; 2638 IGC_WRITE_REG(&sc->hw, IGC_RLPML, psize); 2639 } 2640 2641 /* Set maximum packet buffer len */ 2642 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 2643 IGC_SRRCTL_BSIZEPKT_SHIFT; 2644 /* srrctl above overrides this but set the register to a sane value */ 2645 rctl |= IGC_RCTL_SZ_2048; 2646 2647 /* 2648 * If TX flow control is disabled and there's >1 queue defined, 2649 * enable DROP. 2650 * 2651 * This drops frames rather than hanging the RX MAC for all queues. 2652 */ 2653 if ((sc->rx_num_queues > 1) && 2654 (sc->fc == igc_fc_none || 2655 sc->fc == igc_fc_rx_pause)) { 2656 srrctl |= IGC_SRRCTL_DROP_EN; 2657 } 2658 2659 /* Setup the Base and Length of the Rx Descriptor Rings */ 2660 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 2661 struct rx_ring *rxr = &que->rxr; 2662 u64 bus_addr = rxr->rx_paddr; 2663 u32 rxdctl; 2664 2665 #ifdef notyet 2666 /* Configure for header split? -- ignore for now */ 2667 rxr->hdr_split = igc_header_split; 2668 #else 2669 srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF; 2670 #endif 2671 2672 IGC_WRITE_REG(hw, IGC_RDLEN(i), 2673 scctx->isc_nrxd[0] * sizeof(struct igc_rx_desc)); 2674 IGC_WRITE_REG(hw, IGC_RDBAH(i), (uint32_t)(bus_addr >> 32)); 2675 IGC_WRITE_REG(hw, IGC_RDBAL(i), (uint32_t)bus_addr); 2676 IGC_WRITE_REG(hw, IGC_SRRCTL(i), srrctl); 2677 /* Setup the Head and Tail Descriptor Pointers */ 2678 IGC_WRITE_REG(hw, IGC_RDH(i), 0); 2679 IGC_WRITE_REG(hw, IGC_RDT(i), 0); 2680 /* Enable this Queue */ 2681 rxdctl = IGC_READ_REG(hw, IGC_RXDCTL(i)); 2682 rxdctl &= ~(IGC_RXDCTL_PTHRESH | IGC_RXDCTL_HTHRESH | 2683 IGC_RXDCTL_WTHRESH); 2684 rxdctl |= IGC_RX_PTHRESH | (IGC_RX_HTHRESH << 8) | 2685 (IGC_RX_WTHRESH << 16) | IGC_RXDCTL_QUEUE_ENABLE; 2686 IGC_WRITE_REG(hw, IGC_RXDCTL(i), rxdctl); 2687 } 2688 2689 /* Make sure VLAN Filters are off */ 2690 rctl &= ~IGC_RCTL_VFE; 2691 2692 /* Write out the settings */ 2693 IGC_WRITE_REG(hw, IGC_RCTL, rctl); 2694 2695 return; 2696 } 2697 2698 static void 2699 igc_if_vlan_register(if_ctx_t ctx, u16 vtag) 2700 { 2701 struct igc_softc *sc = iflib_get_softc(ctx); 2702 u32 index, mask; 2703 2704 index = (vtag >> 5) & 0x7f; 2705 mask = 1U << (vtag & 0x1f); 2706 if ((sc->shadow_vfta[index] & mask) != 0) 2707 return; 2708 sc->shadow_vfta[index] |= mask; 2709 igc_write_vfta(&sc->hw, index, sc->shadow_vfta[index]); 2710 } 2711 2712 static void 2713 igc_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 2714 { 2715 struct igc_softc *sc = iflib_get_softc(ctx); 2716 u32 index, mask; 2717 2718 index = (vtag >> 5) & 0x7f; 2719 mask = 1U << (vtag & 0x1f); 2720 if ((sc->shadow_vfta[index] & mask) == 0) 2721 return; 2722 sc->shadow_vfta[index] &= ~mask; 2723 igc_write_vfta(&sc->hw, index, sc->shadow_vfta[index]); 2724 } 2725 2726 static bool 2727 igc_if_vlan_filter_capable(if_ctx_t ctx) 2728 { 2729 if_t ifp = iflib_get_ifp(ctx); 2730 2731 return ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) != 0 && 2732 !igc_disable_crc_stripping); 2733 } 2734 2735 static bool 2736 igc_if_vlan_filter_used(if_ctx_t ctx) 2737 { 2738 struct igc_softc *sc = iflib_get_softc(ctx); 2739 2740 if (!igc_if_vlan_filter_capable(ctx)) 2741 return (false); 2742 2743 for (int i = 0; i < IGC_VFTA_SIZE; i++) 2744 if (sc->shadow_vfta[i] != 0) 2745 return (true); 2746 2747 return (false); 2748 } 2749 2750 static void 2751 igc_if_vlan_filter_enable(struct igc_softc *sc) 2752 { 2753 u32 reg; 2754 2755 reg = IGC_READ_REG(&sc->hw, IGC_RCTL); 2756 reg &= ~IGC_RCTL_CFIEN; 2757 reg |= IGC_RCTL_VFE; 2758 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg); 2759 } 2760 2761 static void 2762 igc_if_vlan_filter_disable(struct igc_softc *sc) 2763 { 2764 u32 reg; 2765 2766 reg = IGC_READ_REG(&sc->hw, IGC_RCTL); 2767 reg &= ~(IGC_RCTL_VFE | IGC_RCTL_CFIEN); 2768 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg); 2769 } 2770 2771 static void 2772 igc_setup_vlan_hw_support(if_ctx_t ctx) 2773 { 2774 struct igc_softc *sc = iflib_get_softc(ctx); 2775 struct igc_hw *hw = &sc->hw; 2776 if_t ifp = iflib_get_ifp(ctx); 2777 u32 reg; 2778 2779 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 2780 !igc_disable_crc_stripping) { 2781 reg = IGC_READ_REG(hw, IGC_CTRL); 2782 reg |= IGC_CTRL_VME; 2783 IGC_WRITE_REG(hw, IGC_CTRL, reg); 2784 } else { 2785 reg = IGC_READ_REG(hw, IGC_CTRL); 2786 reg &= ~IGC_CTRL_VME; 2787 IGC_WRITE_REG(hw, IGC_CTRL, reg); 2788 } 2789 2790 if (!igc_if_vlan_filter_capable(ctx)) { 2791 igc_if_vlan_filter_disable(sc); 2792 return; 2793 } 2794 2795 /* Always admit priority-tagged frames. */ 2796 sc->shadow_vfta[0] |= 1U; 2797 2798 /* A reset may clear the VFTA, so restore the complete desired table. */ 2799 for (int i = 0; i < IGC_VFTA_SIZE; i++) 2800 igc_write_vfta(hw, i, sc->shadow_vfta[i]); 2801 2802 igc_if_vlan_filter_enable(sc); 2803 } 2804 2805 static void 2806 igc_if_intr_enable(if_ctx_t ctx) 2807 { 2808 struct igc_softc *sc = iflib_get_softc(ctx); 2809 struct igc_hw *hw = &sc->hw; 2810 u32 mask; 2811 2812 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 2813 mask = (sc->que_mask | sc->link_mask); 2814 IGC_WRITE_REG(hw, IGC_EIAC, mask); 2815 IGC_WRITE_REG(hw, IGC_EIAM, mask); 2816 IGC_WRITE_REG(hw, IGC_EIMS, mask); 2817 mask = IGC_IMS_LSC; 2818 } else 2819 mask = IMS_ENABLE_MASK; 2820 if (atomic_load_acq_32(&sc->fatal_error_state) == 2821 IGC_FATAL_ERROR_NONE) 2822 mask |= IGC_IMS_FER; 2823 IGC_WRITE_REG(hw, IGC_IMS, mask); 2824 IGC_WRITE_FLUSH(hw); 2825 } 2826 2827 static void 2828 igc_if_intr_disable(if_ctx_t ctx) 2829 { 2830 struct igc_softc *sc = iflib_get_softc(ctx); 2831 struct igc_hw *hw = &sc->hw; 2832 2833 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 2834 IGC_WRITE_REG(hw, IGC_EIMC, 0xffffffff); 2835 IGC_WRITE_REG(hw, IGC_EIAC, 0); 2836 } 2837 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff); 2838 IGC_WRITE_FLUSH(hw); 2839 } 2840 2841 /* 2842 * igc_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 2843 * For ASF and Pass Through versions of f/w this means 2844 * that the driver is loaded. For AMT version type f/w 2845 * this means that the network i/f is open. 2846 */ 2847 static void 2848 igc_get_hw_control(struct igc_softc *sc) 2849 { 2850 u32 ctrl_ext; 2851 2852 if (sc->vf_ifp) 2853 return; 2854 2855 ctrl_ext = IGC_READ_REG(&sc->hw, IGC_CTRL_EXT); 2856 IGC_WRITE_REG(&sc->hw, IGC_CTRL_EXT, 2857 ctrl_ext | IGC_CTRL_EXT_DRV_LOAD); 2858 } 2859 2860 /* 2861 * igc_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 2862 * For ASF and Pass Through versions of f/w this means that 2863 * the driver is no longer loaded. For AMT versions of the 2864 * f/w this means that the network i/f is closed. 2865 */ 2866 static void 2867 igc_release_hw_control(struct igc_softc *sc) 2868 { 2869 u32 ctrl_ext; 2870 2871 ctrl_ext = IGC_READ_REG(&sc->hw, IGC_CTRL_EXT); 2872 IGC_WRITE_REG(&sc->hw, IGC_CTRL_EXT, 2873 ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD); 2874 return; 2875 } 2876 2877 static int 2878 igc_enable_pci_busmaster(struct igc_softc *sc) 2879 { 2880 device_t dev; 2881 u16 command; 2882 int error; 2883 2884 dev = sc->dev; 2885 command = pci_read_config(dev, PCIR_COMMAND, 2); 2886 if (command == 0xffff) 2887 return (ENXIO); 2888 if ((command & PCIM_CMD_BUSMASTEREN) != 0) 2889 return (0); 2890 2891 error = pci_enable_busmaster(dev); 2892 command = pci_read_config(dev, PCIR_COMMAND, 2); 2893 if (command == 0xffff) 2894 return (ENXIO); 2895 if ((command & PCIM_CMD_BUSMASTEREN) == 0) 2896 return (error != 0 ? error : EIO); 2897 return (0); 2898 } 2899 2900 static int 2901 igc_is_valid_ether_addr(u8 *addr) 2902 { 2903 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 2904 2905 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 2906 return (false); 2907 } 2908 2909 return (true); 2910 } 2911 2912 /* Advertise the wake modes supported by I225/I226 physical functions. */ 2913 static void 2914 igc_configure_wakeup(if_ctx_t ctx) 2915 { 2916 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 2917 device_t dev = iflib_get_dev(ctx); 2918 int capabilities; 2919 2920 capabilities = pci_has_pme(dev, PCI_POWERSTATE_D3_HOT) ? 2921 IFCAP_WOL : 0; 2922 scctx->isc_capabilities &= ~IFCAP_WOL; 2923 scctx->isc_capabilities |= capabilities; 2924 scctx->isc_capenable &= ~IFCAP_WOL; 2925 if (capabilities != 0) 2926 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 2927 } 2928 2929 /* Configure the requested PCI Wake-on-LAN filters for suspend. */ 2930 static int 2931 igc_enable_wakeup(if_ctx_t ctx) 2932 { 2933 struct igc_softc *sc = iflib_get_softc(ctx); 2934 device_t dev = iflib_get_dev(ctx); 2935 if_t ifp = iflib_get_ifp(ctx); 2936 int enabled, error = 0, master_error, mcnt; 2937 u32 ctrl, rctl, wufc; 2938 bool manage; 2939 2940 if (!pci_has_pme(dev, PCI_POWERSTATE_D3_HOT)) 2941 return (0); 2942 2943 enabled = if_getcapenable(ifp) & if_getcapabilities(ifp) & IFCAP_WOL; 2944 manage = igc_enable_mng_pass_thru(&sc->hw); 2945 wufc = 0; 2946 if ((enabled & IFCAP_WOL_MAGIC) != 0) 2947 wufc |= IGC_WUFC_MAG; 2948 if ((enabled & IFCAP_WOL_UCAST) != 0) 2949 wufc |= IGC_WUFC_EX; 2950 if ((enabled & IFCAP_WOL_MCAST) != 0) { 2951 wufc |= IGC_WUFC_MC; 2952 bzero(sc->mta, ETHER_ADDR_LEN * 2953 MAX_NUM_MULTICAST_ADDRESSES); 2954 mcnt = if_foreach_llmaddr(ifp, igc_copy_maddr, sc->mta); 2955 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 2956 igc_update_mc_addr_list(&sc->hw, sc->mta, mcnt); 2957 } 2958 2959 IGC_WRITE_REG(&sc->hw, IGC_WUFC, 0); 2960 IGC_WRITE_REG(&sc->hw, IGC_WUFC_EXT, 0); 2961 IGC_WRITE_REG(&sc->hw, IGC_WUC, 0); 2962 IGC_WRITE_REG(&sc->hw, IGC_WUS, ~0U); 2963 IGC_WRITE_REG(&sc->hw, IGC_WUS_EXT, ~0U); 2964 2965 if (wufc == 0) { 2966 if (manage) { 2967 if (sc->suspend_link_powered_down) 2968 igc_power_up_wakeup_link(sc); 2969 pci_enable_pme(dev); 2970 } else { 2971 igc_power_down_phy(&sc->hw); 2972 sc->suspend_link_powered_down = true; 2973 pci_clear_pme(dev); 2974 } 2975 goto master_disable; 2976 } 2977 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN); 2978 error = igc_rar_set(&sc->hw, sc->hw.mac.addr, 0); 2979 if (error != IGC_SUCCESS) { 2980 device_printf(dev, 2981 "Could not restore unicast wake address: %d\n", error); 2982 goto pme; 2983 } 2984 rctl = IGC_READ_REG(&sc->hw, IGC_RCTL); 2985 rctl &= ~(IGC_RCTL_UPE | IGC_RCTL_MPE | IGC_RCTL_MO_3); 2986 rctl |= IGC_RCTL_EN | IGC_RCTL_BAM | 2987 (sc->hw.mac.mc_filter_type << IGC_RCTL_MO_SHIFT); 2988 if ((wufc & IGC_WUFC_MC) != 0) 2989 rctl |= IGC_RCTL_MPE; 2990 IGC_WRITE_REG(&sc->hw, IGC_RCTL, rctl); 2991 2992 /* Advertise the wakeup capability */ 2993 ctrl = IGC_READ_REG(&sc->hw, IGC_CTRL); 2994 ctrl |= IGC_CTRL_ADVD3WUC; 2995 IGC_WRITE_REG(&sc->hw, IGC_CTRL, ctrl); 2996 igc_power_up_wakeup_link(sc); 2997 2998 /* Enable wakeup by the MAC */ 2999 IGC_WRITE_REG(&sc->hw, IGC_WUC, IGC_WUC_PME_EN); 3000 IGC_WRITE_REG(&sc->hw, IGC_WUFC, wufc); 3001 3002 pme: 3003 if (error == IGC_SUCCESS) 3004 pci_enable_pme(dev); 3005 else { 3006 IGC_WRITE_REG(&sc->hw, IGC_WUFC, 0); 3007 IGC_WRITE_REG(&sc->hw, IGC_WUFC_EXT, 0); 3008 IGC_WRITE_REG(&sc->hw, IGC_WUC, 0); 3009 pci_clear_pme(dev); 3010 } 3011 3012 master_disable: 3013 master_error = igc_disable_pcie_master(&sc->hw); 3014 if (master_error != IGC_SUCCESS) 3015 device_printf(dev, "PCIe master disable timed out: %d\n", 3016 master_error); 3017 master_error = pci_disable_busmaster(dev); 3018 if (master_error != 0) 3019 device_printf(dev, "PCI bus-master disable failed: %d\n", 3020 master_error); 3021 3022 return (error == IGC_SUCCESS ? 0 : EIO); 3023 } 3024 3025 static void 3026 igc_power_up_wakeup_link(struct igc_softc *sc) 3027 { 3028 igc_power_up_phy(&sc->hw); 3029 sc->suspend_link_powered_down = false; 3030 } 3031 3032 /********************************************************************** 3033 * 3034 * Update the board statistics counters. 3035 * 3036 **********************************************************************/ 3037 static void 3038 igc_update_ecc_stats(struct igc_softc *sc) 3039 { 3040 struct igc_hw *hw; 3041 u32 pbeccsts, pcieeccsts; 3042 3043 hw = &sc->hw; 3044 pbeccsts = IGC_READ_REG(hw, IGC_PBECCSTS); 3045 if (pbeccsts & IGC_PBECCSTS_CORR_ERR) { 3046 sc->corrected_error_dma_count++; 3047 /* Preserve the enable bit while clearing the RW1C status. */ 3048 IGC_WRITE_REG(hw, IGC_PBECCSTS, 3049 pbeccsts & (IGC_PBECCSTS_ECC_ENABLE | 3050 IGC_PBECCSTS_CORR_ERR)); 3051 } 3052 3053 pcieeccsts = IGC_READ_REG(hw, IGC_PCIEECCSTS) & 3054 IGC_PCIEECCSTS_CORR_MASK; 3055 if (pcieeccsts & IGC_PCIEECCSTS_TX_WR_DATA) 3056 sc->corrected_error_pcie_tx_data_count++; 3057 if (pcieeccsts & IGC_PCIEECCSTS_RETRY_BUF) 3058 sc->corrected_error_pcie_retry_count++; 3059 if (pcieeccsts != 0) 3060 IGC_WRITE_REG(hw, IGC_PCIEECCSTS, pcieeccsts); 3061 } 3062 3063 static void 3064 igc_update_stats_counters(struct igc_softc *sc) 3065 { 3066 u64 prev_xoffrxc = sc->stats.xoffrxc; 3067 3068 sc->stats.crcerrs += IGC_READ_REG(&sc->hw, IGC_CRCERRS); 3069 sc->stats.rxerrc += IGC_READ_REG(&sc->hw, IGC_RXERRC); 3070 sc->stats.mpc += IGC_READ_REG(&sc->hw, IGC_MPC); 3071 sc->stats.scc += IGC_READ_REG(&sc->hw, IGC_SCC); 3072 sc->stats.ecol += IGC_READ_REG(&sc->hw, IGC_ECOL); 3073 3074 sc->stats.mcc += IGC_READ_REG(&sc->hw, IGC_MCC); 3075 sc->stats.latecol += IGC_READ_REG(&sc->hw, IGC_LATECOL); 3076 sc->stats.colc += IGC_READ_REG(&sc->hw, IGC_COLC); 3077 sc->stats.rerc += IGC_READ_REG(&sc->hw, IGC_RERC); 3078 sc->stats.dc += IGC_READ_REG(&sc->hw, IGC_DC); 3079 sc->stats.rlec += IGC_READ_REG(&sc->hw, IGC_RLEC); 3080 sc->stats.xonrxc += IGC_READ_REG(&sc->hw, IGC_XONRXC); 3081 sc->stats.xontxc += IGC_READ_REG(&sc->hw, IGC_XONTXC); 3082 sc->stats.xoffrxc += IGC_READ_REG(&sc->hw, IGC_XOFFRXC); 3083 /* 3084 * For watchdog management we need to know if we have been 3085 * paused during the last interval, so capture that here. 3086 */ 3087 if (sc->stats.xoffrxc != prev_xoffrxc) 3088 sc->shared->isc_pause_frames = 1; 3089 sc->stats.xofftxc += IGC_READ_REG(&sc->hw, IGC_XOFFTXC); 3090 sc->stats.fcruc += IGC_READ_REG(&sc->hw, IGC_FCRUC); 3091 sc->stats.prc64 += IGC_READ_REG(&sc->hw, IGC_PRC64); 3092 sc->stats.prc127 += IGC_READ_REG(&sc->hw, IGC_PRC127); 3093 sc->stats.prc255 += IGC_READ_REG(&sc->hw, IGC_PRC255); 3094 sc->stats.prc511 += IGC_READ_REG(&sc->hw, IGC_PRC511); 3095 sc->stats.prc1023 += IGC_READ_REG(&sc->hw, IGC_PRC1023); 3096 sc->stats.prc1522 += IGC_READ_REG(&sc->hw, IGC_PRC1522); 3097 sc->stats.tlpic += IGC_READ_REG(&sc->hw, IGC_TLPIC); 3098 sc->stats.rlpic += IGC_READ_REG(&sc->hw, IGC_RLPIC); 3099 sc->stats.gprc += IGC_READ_REG(&sc->hw, IGC_GPRC); 3100 sc->stats.bprc += IGC_READ_REG(&sc->hw, IGC_BPRC); 3101 sc->stats.mprc += IGC_READ_REG(&sc->hw, IGC_MPRC); 3102 sc->stats.gptc += IGC_READ_REG(&sc->hw, IGC_GPTC); 3103 3104 /* For the 64-bit byte counters the low dword must be read first. */ 3105 /* Both registers clear on the read of the high dword */ 3106 3107 sc->stats.gorc += IGC_READ_REG(&sc->hw, IGC_GORCL) + 3108 ((u64)IGC_READ_REG(&sc->hw, IGC_GORCH) << 32); 3109 sc->stats.gotc += IGC_READ_REG(&sc->hw, IGC_GOTCL) + 3110 ((u64)IGC_READ_REG(&sc->hw, IGC_GOTCH) << 32); 3111 3112 sc->stats.rnbc += IGC_READ_REG(&sc->hw, IGC_RNBC); 3113 sc->stats.ruc += IGC_READ_REG(&sc->hw, IGC_RUC); 3114 sc->stats.rfc += IGC_READ_REG(&sc->hw, IGC_RFC); 3115 sc->stats.roc += IGC_READ_REG(&sc->hw, IGC_ROC); 3116 sc->stats.rjc += IGC_READ_REG(&sc->hw, IGC_RJC); 3117 3118 sc->stats.mgprc += IGC_READ_REG(&sc->hw, IGC_MGTPRC); 3119 sc->stats.mgpdc += IGC_READ_REG(&sc->hw, IGC_MGTPDC); 3120 sc->stats.mgptc += IGC_READ_REG(&sc->hw, IGC_MGTPTC); 3121 3122 sc->stats.tor += IGC_READ_REG(&sc->hw, IGC_TORH); 3123 sc->stats.tot += IGC_READ_REG(&sc->hw, IGC_TOTH); 3124 3125 sc->stats.tpr += IGC_READ_REG(&sc->hw, IGC_TPR); 3126 sc->stats.tpt += IGC_READ_REG(&sc->hw, IGC_TPT); 3127 sc->stats.ptc64 += IGC_READ_REG(&sc->hw, IGC_PTC64); 3128 sc->stats.ptc127 += IGC_READ_REG(&sc->hw, IGC_PTC127); 3129 sc->stats.ptc255 += IGC_READ_REG(&sc->hw, IGC_PTC255); 3130 sc->stats.ptc511 += IGC_READ_REG(&sc->hw, IGC_PTC511); 3131 sc->stats.ptc1023 += IGC_READ_REG(&sc->hw, IGC_PTC1023); 3132 sc->stats.ptc1522 += IGC_READ_REG(&sc->hw, IGC_PTC1522); 3133 sc->stats.mptc += IGC_READ_REG(&sc->hw, IGC_MPTC); 3134 sc->stats.bptc += IGC_READ_REG(&sc->hw, IGC_BPTC); 3135 3136 /* Interrupt Counts */ 3137 sc->stats.iac += IGC_READ_REG(&sc->hw, IGC_IAC); 3138 sc->stats.rxdmtc += IGC_READ_REG(&sc->hw, IGC_RXDMTC); 3139 3140 sc->stats.algnerrc += IGC_READ_REG(&sc->hw, IGC_ALGNERRC); 3141 sc->stats.tncrs += IGC_READ_REG(&sc->hw, IGC_TNCRS); 3142 sc->stats.htdpmc += IGC_READ_REG(&sc->hw, IGC_HTDPMC); 3143 sc->stats.tsctc += IGC_READ_REG(&sc->hw, IGC_TSCTC); 3144 3145 igc_update_ecc_stats(sc); 3146 } 3147 3148 static uint64_t 3149 igc_if_get_counter(if_ctx_t ctx, ift_counter cnt) 3150 { 3151 struct igc_softc *sc = iflib_get_softc(ctx); 3152 if_t ifp = iflib_get_ifp(ctx); 3153 3154 switch (cnt) { 3155 case IFCOUNTER_COLLISIONS: 3156 return (sc->stats.colc); 3157 case IFCOUNTER_IERRORS: 3158 /* 3159 * RERC overlaps the counters below and, on I225, omits length 3160 * errors. RFC covers bad-CRC runts that CRCERRS does not count. 3161 */ 3162 return (sc->dropped_pkts + sc->stats.rxerrc + 3163 sc->stats.crcerrs + sc->stats.algnerrc + 3164 sc->stats.ruc + sc->stats.rfc + sc->stats.roc + 3165 sc->stats.mpc); 3166 case IFCOUNTER_OERRORS: 3167 return (if_get_counter_default(ifp, cnt) + 3168 sc->stats.ecol + sc->stats.latecol); 3169 default: 3170 return (if_get_counter_default(ifp, cnt)); 3171 } 3172 } 3173 3174 /* igc_if_needs_restart - Tell iflib when the driver needs to be reinitialized 3175 * @ctx: iflib context 3176 * @event: event code to check 3177 * 3178 * Defaults to returning false for unknown events. 3179 * 3180 * @returns true if iflib needs to reinit the interface 3181 */ 3182 static bool 3183 igc_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 3184 { 3185 switch (event) { 3186 case IFLIB_RESTART_VLAN_CONFIG: 3187 default: 3188 return (false); 3189 } 3190 } 3191 3192 /* Export a single 32-bit register via a read-only sysctl. */ 3193 static int 3194 igc_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 3195 { 3196 struct igc_softc *sc; 3197 u_int val; 3198 3199 sc = oidp->oid_arg1; 3200 val = IGC_READ_REG(&sc->hw, oidp->oid_arg2); 3201 return (sysctl_handle_int(oidp, &val, 0, req)); 3202 } 3203 3204 /* Per queue holdoff interrupt rate handler */ 3205 static int 3206 igc_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS) 3207 { 3208 struct igc_rx_queue *rque; 3209 struct igc_tx_queue *tque; 3210 struct igc_hw *hw; 3211 int error; 3212 u32 reg, usec, rate; 3213 3214 bool tx = oidp->oid_arg2; 3215 3216 if (tx) { 3217 tque = oidp->oid_arg1; 3218 hw = &tque->sc->hw; 3219 reg = IGC_READ_REG(hw, IGC_EITR(tque->msix)); 3220 } else { 3221 rque = oidp->oid_arg1; 3222 hw = &rque->sc->hw; 3223 reg = IGC_READ_REG(hw, IGC_EITR(rque->msix)); 3224 } 3225 3226 usec = (reg & IGC_QVECTOR_MASK); 3227 if (usec > 0) 3228 rate = IGC_EITR_TO_INTS(usec); 3229 else 3230 rate = 0; 3231 3232 error = sysctl_handle_int(oidp, &rate, 0, req); 3233 if (error || !req->newptr) 3234 return error; 3235 return 0; 3236 } 3237 3238 /* 3239 * Add sysctl variables, one per statistic, to the system. 3240 */ 3241 static void 3242 igc_add_hw_stats(struct igc_softc *sc) 3243 { 3244 device_t dev = iflib_get_dev(sc->ctx); 3245 struct igc_tx_queue *tx_que = sc->tx_queues; 3246 struct igc_rx_queue *rx_que = sc->rx_queues; 3247 3248 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 3249 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 3250 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 3251 struct igc_hw_stats *stats = &sc->stats; 3252 3253 struct sysctl_oid *eee_node, *memerr_node, *stat_node, *queue_node, 3254 *int_node; 3255 struct sysctl_oid_list *eee_list, *memerr_list, *stat_list, *queue_list, 3256 *int_list; 3257 3258 #define QUEUE_NAME_LEN 32 3259 char namebuf[QUEUE_NAME_LEN]; 3260 3261 /* Driver Statistics */ 3262 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 3263 CTLFLAG_RD, &sc->dropped_pkts, 3264 "Driver dropped packets"); 3265 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 3266 CTLFLAG_RD, &sc->link_irq, 3267 "Link MSI-X IRQ Handled"); 3268 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 3269 CTLFLAG_RD, &sc->rx_overruns, 3270 "RX overruns"); 3271 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 3272 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 3273 sc, IGC_CTRL, igc_sysctl_reg_handler, "IU", 3274 "Device Control Register"); 3275 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 3276 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 3277 sc, IGC_RCTL, igc_sysctl_reg_handler, "IU", 3278 "Receiver Control Register"); 3279 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 3280 CTLFLAG_RD, &sc->hw.fc.high_water, 0, 3281 "Flow Control High Watermark"); 3282 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 3283 CTLFLAG_RD, &sc->hw.fc.low_water, 0, 3284 "Flow Control Low Watermark"); 3285 memerr_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "memory_errors", 3286 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 3287 "Internal memory error indications"); 3288 memerr_list = SYSCTL_CHILDREN(memerr_node); 3289 SYSCTL_ADD_UQUAD(ctx, memerr_list, OID_AUTO, "fatal_lan", 3290 CTLFLAG_RD, &sc->fatal_error_lan_count, 3291 "Fatal LAN-port memory error indications"); 3292 SYSCTL_ADD_UQUAD(ctx, memerr_list, OID_AUTO, "fatal_management", 3293 CTLFLAG_RD, &sc->fatal_error_mng_count, 3294 "Fatal management-memory error indications"); 3295 SYSCTL_ADD_UQUAD(ctx, memerr_list, OID_AUTO, "fatal_pcie", 3296 CTLFLAG_RD, &sc->fatal_error_pcie_count, 3297 "Fatal PCIe memory error indications"); 3298 SYSCTL_ADD_UQUAD(ctx, memerr_list, OID_AUTO, "fatal_dma", 3299 CTLFLAG_RD, &sc->fatal_error_dma_count, 3300 "Fatal DMA memory error indications"); 3301 SYSCTL_ADD_UQUAD(ctx, memerr_list, OID_AUTO, "fatal_unknown", 3302 CTLFLAG_RD, &sc->fatal_error_unknown_count, 3303 "Fatal memory errors without a reported region"); 3304 SYSCTL_ADD_UQUAD(ctx, memerr_list, OID_AUTO, "corrected_dma", 3305 CTLFLAG_RD, &sc->corrected_error_dma_count, 3306 "Corrected DMA memory error indications"); 3307 SYSCTL_ADD_UQUAD(ctx, memerr_list, OID_AUTO, 3308 "corrected_pcie_tx_data", CTLFLAG_RD, 3309 &sc->corrected_error_pcie_tx_data_count, 3310 "Corrected PCIe transmit-data memory error indications"); 3311 SYSCTL_ADD_UQUAD(ctx, memerr_list, OID_AUTO, 3312 "corrected_pcie_retry", CTLFLAG_RD, 3313 &sc->corrected_error_pcie_retry_count, 3314 "Corrected PCIe retry-buffer memory error indications"); 3315 eee_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "eee", 3316 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 3317 "Energy Efficient Ethernet statistics"); 3318 eee_list = SYSCTL_CHILDREN(eee_node); 3319 SYSCTL_ADD_UQUAD(ctx, eee_list, OID_AUTO, "tx_lpi_count", 3320 CTLFLAG_RD, &stats->tlpic, "TX LPI event count"); 3321 SYSCTL_ADD_UQUAD(ctx, eee_list, OID_AUTO, "rx_lpi_count", 3322 CTLFLAG_RD, &stats->rlpic, "RX LPI event count"); 3323 3324 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 3325 struct tx_ring *txr = &tx_que->txr; 3326 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 3327 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 3328 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 3329 queue_list = SYSCTL_CHILDREN(queue_node); 3330 3331 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 3332 CTLTYPE_UINT | CTLFLAG_RD, tx_que, 3333 true, igc_sysctl_interrupt_rate_handler, "IU", 3334 "Interrupt Rate"); 3335 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 3336 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 3337 IGC_TDH(txr->me), igc_sysctl_reg_handler, "IU", 3338 "Transmit Descriptor Head"); 3339 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 3340 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 3341 IGC_TDT(txr->me), igc_sysctl_reg_handler, "IU", 3342 "Transmit Descriptor Tail"); 3343 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 3344 CTLFLAG_RD, &txr->tx_irq, 3345 "Queue MSI-X Transmit Interrupts"); 3346 } 3347 3348 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { 3349 struct rx_ring *rxr = &rx_que->rxr; 3350 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 3351 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 3352 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 3353 queue_list = SYSCTL_CHILDREN(queue_node); 3354 3355 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 3356 CTLTYPE_UINT | CTLFLAG_RD, rx_que, 3357 false, igc_sysctl_interrupt_rate_handler, "IU", 3358 "Interrupt Rate"); 3359 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 3360 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 3361 IGC_RDH(rxr->me), igc_sysctl_reg_handler, "IU", 3362 "Receive Descriptor Head"); 3363 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 3364 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 3365 IGC_RDT(rxr->me), igc_sysctl_reg_handler, "IU", 3366 "Receive Descriptor Tail"); 3367 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 3368 CTLFLAG_RD, &rxr->rx_irq, 3369 "Queue MSI-X Receive Interrupts"); 3370 } 3371 3372 /* MAC stats get their own sub node */ 3373 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 3374 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 3375 stat_list = SYSCTL_CHILDREN(stat_node); 3376 3377 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 3378 CTLFLAG_RD, &stats->ecol, 3379 "Excessive collisions"); 3380 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 3381 CTLFLAG_RD, &stats->scc, 3382 "Single collisions"); 3383 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 3384 CTLFLAG_RD, &stats->mcc, 3385 "Multiple collisions"); 3386 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 3387 CTLFLAG_RD, &stats->latecol, 3388 "Late collisions"); 3389 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 3390 CTLFLAG_RD, &stats->colc, 3391 "Collision Count"); 3392 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 3393 CTLFLAG_RD, &sc->stats.symerrs, 3394 "Symbol Errors"); 3395 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 3396 CTLFLAG_RD, &sc->stats.sec, 3397 "Sequence Errors"); 3398 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 3399 CTLFLAG_RD, &sc->stats.dc, 3400 "Defer Count"); 3401 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 3402 CTLFLAG_RD, &sc->stats.mpc, 3403 "Missed Packets"); 3404 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_length_errors", 3405 CTLFLAG_RD, &sc->stats.rlec, 3406 "Receive Length Errors"); 3407 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 3408 CTLFLAG_RD, &sc->stats.rnbc, 3409 "Receive No Buffers"); 3410 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 3411 CTLFLAG_RD, &sc->stats.ruc, 3412 "Receive Undersize"); 3413 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 3414 CTLFLAG_RD, &sc->stats.rfc, 3415 "Fragmented Packets Received "); 3416 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 3417 CTLFLAG_RD, &sc->stats.roc, 3418 "Oversized Packets Received"); 3419 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 3420 CTLFLAG_RD, &sc->stats.rjc, 3421 "Received Jabber"); 3422 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 3423 CTLFLAG_RD, &sc->stats.rxerrc, 3424 "Receive Errors"); 3425 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_error_count", 3426 CTLFLAG_RD, &sc->stats.rerc, 3427 "Receive Error Count (RERC)"); 3428 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 3429 CTLFLAG_RD, &sc->stats.crcerrs, 3430 "CRC errors"); 3431 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 3432 CTLFLAG_RD, &sc->stats.algnerrc, 3433 "Alignment Errors"); 3434 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 3435 CTLFLAG_RD, &sc->stats.xonrxc, 3436 "XON Received"); 3437 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 3438 CTLFLAG_RD, &sc->stats.xontxc, 3439 "XON Transmitted"); 3440 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 3441 CTLFLAG_RD, &sc->stats.xoffrxc, 3442 "XOFF Received"); 3443 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 3444 CTLFLAG_RD, &sc->stats.xofftxc, 3445 "XOFF Transmitted"); 3446 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "unsupported_fc_recvd", 3447 CTLFLAG_RD, &sc->stats.fcruc, 3448 "Unsupported Flow Control Received"); 3449 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_recvd", 3450 CTLFLAG_RD, &sc->stats.mgprc, 3451 "Management Packets Received"); 3452 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_drop", 3453 CTLFLAG_RD, &sc->stats.mgpdc, 3454 "Management Packets Dropped"); 3455 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_txd", 3456 CTLFLAG_RD, &sc->stats.mgptc, 3457 "Management Packets Transmitted"); 3458 3459 /* Packet Reception Stats */ 3460 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 3461 CTLFLAG_RD, &sc->stats.tpr, 3462 "Total Packets Received "); 3463 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 3464 CTLFLAG_RD, &sc->stats.gprc, 3465 "Good Packets Received"); 3466 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 3467 CTLFLAG_RD, &sc->stats.bprc, 3468 "Broadcast Packets Received"); 3469 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 3470 CTLFLAG_RD, &sc->stats.mprc, 3471 "Multicast Packets Received"); 3472 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 3473 CTLFLAG_RD, &sc->stats.prc64, 3474 "64 byte frames received "); 3475 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 3476 CTLFLAG_RD, &sc->stats.prc127, 3477 "65-127 byte frames received"); 3478 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 3479 CTLFLAG_RD, &sc->stats.prc255, 3480 "128-255 byte frames received"); 3481 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 3482 CTLFLAG_RD, &sc->stats.prc511, 3483 "256-511 byte frames received"); 3484 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 3485 CTLFLAG_RD, &sc->stats.prc1023, 3486 "512-1023 byte frames received"); 3487 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 3488 CTLFLAG_RD, &sc->stats.prc1522, 3489 "1023-1522 byte frames received"); 3490 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 3491 CTLFLAG_RD, &sc->stats.gorc, 3492 "Good Octets Received"); 3493 3494 /* Packet Transmission Stats */ 3495 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 3496 CTLFLAG_RD, &sc->stats.gotc, 3497 "Good Octets Transmitted"); 3498 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 3499 CTLFLAG_RD, &sc->stats.tpt, 3500 "Total Packets Transmitted"); 3501 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 3502 CTLFLAG_RD, &sc->stats.gptc, 3503 "Good Packets Transmitted"); 3504 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "host_tx_discarded", 3505 CTLFLAG_RD, &sc->stats.htdpmc, 3506 "Host Packets Discarded by Transmit MAC"); 3507 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 3508 CTLFLAG_RD, &sc->stats.bptc, 3509 "Broadcast Packets Transmitted"); 3510 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 3511 CTLFLAG_RD, &sc->stats.mptc, 3512 "Multicast Packets Transmitted"); 3513 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 3514 CTLFLAG_RD, &sc->stats.ptc64, 3515 "64 byte frames transmitted "); 3516 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 3517 CTLFLAG_RD, &sc->stats.ptc127, 3518 "65-127 byte frames transmitted"); 3519 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 3520 CTLFLAG_RD, &sc->stats.ptc255, 3521 "128-255 byte frames transmitted"); 3522 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 3523 CTLFLAG_RD, &sc->stats.ptc511, 3524 "256-511 byte frames transmitted"); 3525 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 3526 CTLFLAG_RD, &sc->stats.ptc1023, 3527 "512-1023 byte frames transmitted"); 3528 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 3529 CTLFLAG_RD, &sc->stats.ptc1522, 3530 "1024-1522 byte frames transmitted"); 3531 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 3532 CTLFLAG_RD, &sc->stats.tsctc, 3533 "TSO Contexts Transmitted"); 3534 3535 /* Interrupt Stats */ 3536 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 3537 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 3538 int_list = SYSCTL_CHILDREN(int_node); 3539 3540 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 3541 CTLFLAG_RD, &sc->stats.iac, 3542 "Interrupt Assertion Count"); 3543 3544 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 3545 CTLFLAG_RD, &sc->stats.rxdmtc, 3546 "Rx Desc Min Thresh Count"); 3547 } 3548 3549 static void 3550 igc_fw_version(struct igc_softc *sc) 3551 { 3552 struct igc_hw *hw = &sc->hw; 3553 struct igc_fw_version *fw_ver = &sc->fw_ver; 3554 3555 *fw_ver = (struct igc_fw_version){0}; 3556 3557 igc_get_fw_version(hw, fw_ver); 3558 } 3559 3560 static void 3561 igc_sbuf_fw_version(struct igc_fw_version *fw_ver, struct sbuf *buf) 3562 { 3563 const char *space = ""; 3564 3565 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { 3566 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, 3567 fw_ver->eep_minor, fw_ver->eep_build); 3568 space = " "; 3569 } 3570 3571 if (fw_ver->invm_major || fw_ver->invm_minor || 3572 fw_ver->invm_img_type) { 3573 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d", 3574 space, fw_ver->invm_major, fw_ver->invm_minor, 3575 fw_ver->invm_img_type); 3576 space = " "; 3577 } 3578 3579 if (fw_ver->or_valid) { 3580 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 3581 space, fw_ver->or_major, fw_ver->or_build, 3582 fw_ver->or_patch); 3583 space = " "; 3584 } 3585 3586 if (fw_ver->etrack_id) 3587 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); 3588 } 3589 3590 static void 3591 igc_print_fw_version(struct igc_softc *sc ) 3592 { 3593 device_t dev = sc->dev; 3594 struct sbuf *buf; 3595 int error = 0; 3596 3597 buf = sbuf_new_auto(); 3598 if (!buf) { 3599 device_printf(dev, "Could not allocate sbuf for output.\n"); 3600 return; 3601 } 3602 3603 igc_sbuf_fw_version(&sc->fw_ver, buf); 3604 3605 error = sbuf_finish(buf); 3606 if (error) 3607 device_printf(dev, "Error finishing sbuf: %d\n", error); 3608 else if (sbuf_len(buf)) 3609 device_printf(dev, "%s\n", sbuf_data(buf)); 3610 3611 sbuf_delete(buf); 3612 } 3613 3614 static int 3615 igc_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 3616 { 3617 struct igc_softc *sc = (struct igc_softc *)arg1; 3618 device_t dev = sc->dev; 3619 struct sbuf *buf; 3620 int error = 0; 3621 3622 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 3623 if (!buf) { 3624 device_printf(dev, "Could not allocate sbuf for output.\n"); 3625 return (ENOMEM); 3626 } 3627 3628 igc_sbuf_fw_version(&sc->fw_ver, buf); 3629 3630 error = sbuf_finish(buf); 3631 if (error) 3632 device_printf(dev, "Error finishing sbuf: %d\n", error); 3633 3634 sbuf_delete(buf); 3635 3636 return (0); 3637 } 3638 3639 /********************************************************************** 3640 * 3641 * This routine provides a way to dump out the adapter eeprom, 3642 * often a useful debug/service tool. This only dumps the first 3643 * 32 words, stuff that matters is in that extent. 3644 * 3645 **********************************************************************/ 3646 static int 3647 igc_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 3648 { 3649 struct igc_softc *sc = (struct igc_softc *)arg1; 3650 int error; 3651 int result; 3652 3653 result = -1; 3654 error = sysctl_handle_int(oidp, &result, 0, req); 3655 3656 if (error || !req->newptr) 3657 return (error); 3658 3659 /* 3660 * This value will cause a hex dump of the 3661 * first 32 16-bit words of the EEPROM to 3662 * the screen. 3663 */ 3664 if (result == 1) 3665 igc_print_nvm_info(sc); 3666 3667 return (error); 3668 } 3669 3670 static void 3671 igc_print_nvm_info(struct igc_softc *sc) 3672 { 3673 u16 eeprom_data; 3674 int i, j, row = 0; 3675 3676 /* Its a bit crude, but it gets the job done */ 3677 printf("\nInterface EEPROM Dump:\n"); 3678 printf("Offset\n0x0000 "); 3679 for (i = 0, j = 0; i < 32; i++, j++) { 3680 if (j == 8) { /* Make the offset block */ 3681 j = 0; ++row; 3682 printf("\n0x00%x0 ",row); 3683 } 3684 igc_read_nvm(&sc->hw, i, 1, &eeprom_data); 3685 printf("%04x ", eeprom_data); 3686 } 3687 printf("\n"); 3688 } 3689 3690 static int 3691 igc_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS) 3692 { 3693 struct igc_softc *sc; 3694 u32 reg, val, shift; 3695 int error, mask; 3696 3697 sc = oidp->oid_arg1; 3698 switch (oidp->oid_arg2) { 3699 case 0: 3700 reg = IGC_DTXTCPFLGL; 3701 shift = 0; 3702 break; 3703 case 1: 3704 reg = IGC_DTXTCPFLGL; 3705 shift = 16; 3706 break; 3707 case 2: 3708 reg = IGC_DTXTCPFLGH; 3709 shift = 0; 3710 break; 3711 default: 3712 return (EINVAL); 3713 break; 3714 } 3715 val = IGC_READ_REG(&sc->hw, reg); 3716 mask = (val >> shift) & 0xfff; 3717 error = sysctl_handle_int(oidp, &mask, 0, req); 3718 if (error != 0 || req->newptr == NULL) 3719 return (error); 3720 if (mask < 0 || mask > 0xfff) 3721 return (EINVAL); 3722 val = (val & ~(0xfff << shift)) | (mask << shift); 3723 IGC_WRITE_REG(&sc->hw, reg, val); 3724 return (0); 3725 } 3726 3727 /* 3728 * Set flow control using sysctl: 3729 * Flow control values: 3730 * 0 - off 3731 * 1 - rx pause 3732 * 2 - tx pause 3733 * 3 - full 3734 */ 3735 static int 3736 igc_set_flowcntl(SYSCTL_HANDLER_ARGS) 3737 { 3738 int error, input; 3739 struct igc_softc *sc = (struct igc_softc *) arg1; 3740 3741 input = sc->fc; 3742 error = sysctl_handle_int(oidp, &input, 0, req); 3743 3744 if ((error) || (req->newptr == NULL)) 3745 return (error); 3746 3747 switch (input) { 3748 case igc_fc_rx_pause: 3749 case igc_fc_tx_pause: 3750 case igc_fc_full: 3751 case igc_fc_none: 3752 break; 3753 default: 3754 return (EINVAL); 3755 } 3756 3757 if (input == sc->fc) /* no change? */ 3758 return (0); 3759 3760 /* 3761 * The mode is advertised to the link partner and also decides the 3762 * pause thresholds and per-queue drop, so it takes a reinit to apply. 3763 */ 3764 sc->fc = input; 3765 igc_sysctl_request_reinit(sc); 3766 return (0); 3767 } 3768 3769 static void 3770 igc_sysctl_request_reinit(struct igc_softc *sc) 3771 { 3772 if ((if_getflags(iflib_get_ifp(sc->ctx)) & IFF_UP) == 0) 3773 return; 3774 3775 iflib_request_reset(sc->ctx); 3776 iflib_admin_intr_deferred(sc->ctx); 3777 } 3778 3779 /* 3780 * Manage DMA Coalesce: 3781 * Control values: 3782 * 0/1 - off/on 3783 * Legal timer values are: 3784 * 250,500,1000-10000 in thousands 3785 */ 3786 static int 3787 igc_sysctl_dmac(SYSCTL_HANDLER_ARGS) 3788 { 3789 struct igc_softc *sc = (struct igc_softc *) arg1; 3790 int error; 3791 3792 error = sysctl_handle_int(oidp, &sc->dmac, 0, req); 3793 3794 if ((error) || (req->newptr == NULL)) 3795 return (error); 3796 3797 switch (sc->dmac) { 3798 case 0: 3799 /* Disabling */ 3800 break; 3801 case 1: /* Just enable and use default */ 3802 sc->dmac = 1000; 3803 break; 3804 case 250: 3805 case 500: 3806 case 1000: 3807 case 2000: 3808 case 3000: 3809 case 4000: 3810 case 5000: 3811 case 6000: 3812 case 7000: 3813 case 8000: 3814 case 9000: 3815 case 10000: 3816 /* Legal values - allow */ 3817 break; 3818 default: 3819 /* Do nothing, illegal value */ 3820 sc->dmac = 0; 3821 return (EINVAL); 3822 } 3823 /* Reinit the interface */ 3824 igc_sysctl_request_reinit(sc); 3825 return (error); 3826 } 3827 3828 /* 3829 * Manage Energy Efficient Ethernet: 3830 * Control values: 3831 * 0/1 - enabled/disabled 3832 */ 3833 static int 3834 igc_sysctl_eee(SYSCTL_HANDLER_ARGS) 3835 { 3836 struct igc_softc *sc = (struct igc_softc *) arg1; 3837 int error, value; 3838 3839 value = sc->hw.dev_spec._i225.eee_disable; 3840 error = sysctl_handle_int(oidp, &value, 0, req); 3841 if (error || req->newptr == NULL) 3842 return (error); 3843 3844 sc->hw.dev_spec._i225.eee_disable = (value != 0); 3845 igc_sysctl_request_reinit(sc); 3846 3847 return (0); 3848 } 3849 3850 static int 3851 igc_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3852 { 3853 struct igc_softc *sc; 3854 int error; 3855 int result; 3856 3857 result = -1; 3858 error = sysctl_handle_int(oidp, &result, 0, req); 3859 3860 if (error || !req->newptr) 3861 return (error); 3862 3863 if (result == 1) { 3864 sc = (struct igc_softc *) arg1; 3865 igc_print_debug_info(sc); 3866 } 3867 3868 return (error); 3869 } 3870 3871 static int 3872 igc_get_rs(SYSCTL_HANDLER_ARGS) 3873 { 3874 struct igc_softc *sc = (struct igc_softc *) arg1; 3875 int error; 3876 int result; 3877 3878 result = 0; 3879 error = sysctl_handle_int(oidp, &result, 0, req); 3880 3881 if (error || !req->newptr || result != 1) 3882 return (error); 3883 igc_dump_rs(sc); 3884 3885 return (error); 3886 } 3887 3888 static void 3889 igc_if_debug(if_ctx_t ctx) 3890 { 3891 igc_dump_rs(iflib_get_softc(ctx)); 3892 } 3893 3894 /* 3895 * This routine is meant to be fluid, add whatever is 3896 * needed for debugging a problem. -jfv 3897 */ 3898 static void 3899 igc_print_debug_info(struct igc_softc *sc) 3900 { 3901 device_t dev = iflib_get_dev(sc->ctx); 3902 3903 device_printf(dev, "iflib software admission: %s\n", 3904 iflib_is_running(sc->ctx) ? "open" : "closed"); 3905 3906 for (int i = 0; i < sc->tx_num_queues; i++) { 3907 device_printf(dev, "TX Queue %d ------\n", i); 3908 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3909 IGC_READ_REG(&sc->hw, IGC_TDH(i)), 3910 IGC_READ_REG(&sc->hw, IGC_TDT(i))); 3911 3912 } 3913 for (int j = 0; j < sc->rx_num_queues; j++) { 3914 device_printf(dev, "RX Queue %d ------\n", j); 3915 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 3916 IGC_READ_REG(&sc->hw, IGC_RDH(j)), 3917 IGC_READ_REG(&sc->hw, IGC_RDT(j))); 3918 } 3919 } 3920