1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * Copyright (c) 2021 Rubicon Communications, LLC (Netgate) 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 #include "if_igc.h" 32 #include <sys/sbuf.h> 33 #include <machine/_inttypes.h> 34 35 #ifdef RSS 36 #include <net/rss_config.h> 37 #include <netinet/in_rss.h> 38 #endif 39 40 /********************************************************************* 41 * PCI Device ID Table 42 * 43 * Used by probe to select devices to load on 44 * Last entry must be all 0s 45 * 46 * { Vendor ID, Device ID, String } 47 *********************************************************************/ 48 49 static const pci_vendor_info_t igc_vendor_info_array[] = 50 { 51 /* Intel(R) PRO/1000 Network Connection - igc */ 52 PVID(0x8086, IGC_DEV_ID_I225_LM, "Intel(R) Ethernet Controller I225-LM"), 53 PVID(0x8086, IGC_DEV_ID_I225_V, "Intel(R) Ethernet Controller I225-V"), 54 PVID(0x8086, IGC_DEV_ID_I225_K, "Intel(R) Ethernet Controller I225-K"), 55 PVID(0x8086, IGC_DEV_ID_I225_I, "Intel(R) Ethernet Controller I225-I"), 56 PVID(0x8086, IGC_DEV_ID_I220_V, "Intel(R) Ethernet Controller I220-V"), 57 PVID(0x8086, IGC_DEV_ID_I225_K2, "Intel(R) Ethernet Controller I225-K(2)"), 58 PVID(0x8086, IGC_DEV_ID_I225_LMVP, "Intel(R) Ethernet Controller I225-LMvP(2)"), 59 PVID(0x8086, IGC_DEV_ID_I226_K, "Intel(R) Ethernet Controller I226-K"), 60 PVID(0x8086, IGC_DEV_ID_I226_LMVP, "Intel(R) Ethernet Controller I226-LMvP"), 61 PVID(0x8086, IGC_DEV_ID_I225_IT, "Intel(R) Ethernet Controller I225-IT(2)"), 62 PVID(0x8086, IGC_DEV_ID_I226_LM, "Intel(R) Ethernet Controller I226-LM"), 63 PVID(0x8086, IGC_DEV_ID_I226_V, "Intel(R) Ethernet Controller I226-V"), 64 PVID(0x8086, IGC_DEV_ID_I226_IT, "Intel(R) Ethernet Controller I226-IT"), 65 PVID(0x8086, IGC_DEV_ID_I221_V, "Intel(R) Ethernet Controller I221-V"), 66 PVID(0x8086, IGC_DEV_ID_I226_BLANK_NVM, "Intel(R) Ethernet Controller I226(blankNVM)"), 67 PVID(0x8086, IGC_DEV_ID_I225_BLANK_NVM, "Intel(R) Ethernet Controller I225(blankNVM)"), 68 /* required last entry */ 69 PVID_END 70 }; 71 72 /********************************************************************* 73 * Function prototypes 74 *********************************************************************/ 75 static void *igc_register(device_t dev); 76 static int igc_if_attach_pre(if_ctx_t ctx); 77 static int igc_if_attach_post(if_ctx_t ctx); 78 static int igc_if_detach(if_ctx_t ctx); 79 static int igc_if_shutdown(if_ctx_t ctx); 80 static int igc_if_suspend(if_ctx_t ctx); 81 static int igc_if_resume(if_ctx_t ctx); 82 83 static int igc_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 84 static int igc_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 85 static void igc_if_queues_free(if_ctx_t ctx); 86 87 static uint64_t igc_if_get_counter(if_ctx_t, ift_counter); 88 static void igc_if_init(if_ctx_t ctx); 89 static void igc_if_stop(if_ctx_t ctx); 90 static void igc_if_media_status(if_ctx_t, struct ifmediareq *); 91 static int igc_if_media_change(if_ctx_t ctx); 92 static int igc_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 93 static void igc_if_timer(if_ctx_t ctx, uint16_t qid); 94 static void igc_if_watchdog_reset(if_ctx_t ctx); 95 static bool igc_if_needs_restart(if_ctx_t ctx, enum iflib_restart_event event); 96 97 static void igc_identify_hardware(if_ctx_t ctx); 98 static int igc_allocate_pci_resources(if_ctx_t ctx); 99 static void igc_free_pci_resources(if_ctx_t ctx); 100 static void igc_reset(if_ctx_t ctx); 101 static int igc_setup_interface(if_ctx_t ctx); 102 static int igc_setup_msix(if_ctx_t ctx); 103 104 static void igc_initialize_transmit_unit(if_ctx_t ctx); 105 static void igc_initialize_receive_unit(if_ctx_t ctx); 106 107 static void igc_if_intr_enable(if_ctx_t ctx); 108 static void igc_if_intr_disable(if_ctx_t ctx); 109 static int igc_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 110 static int igc_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 111 static void igc_if_multi_set(if_ctx_t ctx); 112 static void igc_if_update_admin_status(if_ctx_t ctx); 113 static void igc_if_debug(if_ctx_t ctx); 114 static void igc_update_stats_counters(struct igc_adapter *); 115 static void igc_add_hw_stats(struct igc_adapter *adapter); 116 static int igc_if_set_promisc(if_ctx_t ctx, int flags); 117 static void igc_setup_vlan_hw_support(if_ctx_t ctx); 118 static int igc_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 119 static void igc_print_nvm_info(struct igc_adapter *); 120 static int igc_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 121 static int igc_get_rs(SYSCTL_HANDLER_ARGS); 122 static void igc_print_debug_info(struct igc_adapter *); 123 static int igc_is_valid_ether_addr(u8 *); 124 /* Management and WOL Support */ 125 static void igc_get_hw_control(struct igc_adapter *); 126 static void igc_release_hw_control(struct igc_adapter *); 127 static void igc_get_wakeup(if_ctx_t ctx); 128 static void igc_enable_wakeup(if_ctx_t ctx); 129 130 int igc_intr(void *arg); 131 132 /* MSI-X handlers */ 133 static int igc_if_msix_intr_assign(if_ctx_t, int); 134 static int igc_msix_link(void *); 135 static void igc_handle_link(void *context); 136 137 static int igc_set_flowcntl(SYSCTL_HANDLER_ARGS); 138 static int igc_sysctl_eee(SYSCTL_HANDLER_ARGS); 139 140 static int igc_get_regs(SYSCTL_HANDLER_ARGS); 141 142 static void igc_configure_queues(struct igc_adapter *adapter); 143 144 145 /********************************************************************* 146 * FreeBSD Device Interface Entry Points 147 *********************************************************************/ 148 static device_method_t igc_methods[] = { 149 /* Device interface */ 150 DEVMETHOD(device_register, igc_register), 151 DEVMETHOD(device_probe, iflib_device_probe), 152 DEVMETHOD(device_attach, iflib_device_attach), 153 DEVMETHOD(device_detach, iflib_device_detach), 154 DEVMETHOD(device_shutdown, iflib_device_shutdown), 155 DEVMETHOD(device_suspend, iflib_device_suspend), 156 DEVMETHOD(device_resume, iflib_device_resume), 157 DEVMETHOD_END 158 }; 159 160 static driver_t igc_driver = { 161 "igc", igc_methods, sizeof(struct igc_adapter), 162 }; 163 164 DRIVER_MODULE(igc, pci, igc_driver, 0, 0); 165 166 MODULE_DEPEND(igc, pci, 1, 1, 1); 167 MODULE_DEPEND(igc, ether, 1, 1, 1); 168 MODULE_DEPEND(igc, iflib, 1, 1, 1); 169 170 IFLIB_PNP_INFO(pci, igc, igc_vendor_info_array); 171 172 static device_method_t igc_if_methods[] = { 173 DEVMETHOD(ifdi_attach_pre, igc_if_attach_pre), 174 DEVMETHOD(ifdi_attach_post, igc_if_attach_post), 175 DEVMETHOD(ifdi_detach, igc_if_detach), 176 DEVMETHOD(ifdi_shutdown, igc_if_shutdown), 177 DEVMETHOD(ifdi_suspend, igc_if_suspend), 178 DEVMETHOD(ifdi_resume, igc_if_resume), 179 DEVMETHOD(ifdi_init, igc_if_init), 180 DEVMETHOD(ifdi_stop, igc_if_stop), 181 DEVMETHOD(ifdi_msix_intr_assign, igc_if_msix_intr_assign), 182 DEVMETHOD(ifdi_intr_enable, igc_if_intr_enable), 183 DEVMETHOD(ifdi_intr_disable, igc_if_intr_disable), 184 DEVMETHOD(ifdi_tx_queues_alloc, igc_if_tx_queues_alloc), 185 DEVMETHOD(ifdi_rx_queues_alloc, igc_if_rx_queues_alloc), 186 DEVMETHOD(ifdi_queues_free, igc_if_queues_free), 187 DEVMETHOD(ifdi_update_admin_status, igc_if_update_admin_status), 188 DEVMETHOD(ifdi_multi_set, igc_if_multi_set), 189 DEVMETHOD(ifdi_media_status, igc_if_media_status), 190 DEVMETHOD(ifdi_media_change, igc_if_media_change), 191 DEVMETHOD(ifdi_mtu_set, igc_if_mtu_set), 192 DEVMETHOD(ifdi_promisc_set, igc_if_set_promisc), 193 DEVMETHOD(ifdi_timer, igc_if_timer), 194 DEVMETHOD(ifdi_watchdog_reset, igc_if_watchdog_reset), 195 DEVMETHOD(ifdi_get_counter, igc_if_get_counter), 196 DEVMETHOD(ifdi_rx_queue_intr_enable, igc_if_rx_queue_intr_enable), 197 DEVMETHOD(ifdi_tx_queue_intr_enable, igc_if_tx_queue_intr_enable), 198 DEVMETHOD(ifdi_debug, igc_if_debug), 199 DEVMETHOD(ifdi_needs_restart, igc_if_needs_restart), 200 DEVMETHOD_END 201 }; 202 203 static driver_t igc_if_driver = { 204 "igc_if", igc_if_methods, sizeof(struct igc_adapter) 205 }; 206 207 /********************************************************************* 208 * Tunable default values. 209 *********************************************************************/ 210 211 /* Allow common code without TSO */ 212 #ifndef CSUM_TSO 213 #define CSUM_TSO 0 214 #endif 215 216 static SYSCTL_NODE(_hw, OID_AUTO, igc, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 217 "igc driver parameters"); 218 219 static int igc_disable_crc_stripping = 0; 220 SYSCTL_INT(_hw_igc, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 221 &igc_disable_crc_stripping, 0, "Disable CRC Stripping"); 222 223 static int igc_smart_pwr_down = false; 224 SYSCTL_INT(_hw_igc, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &igc_smart_pwr_down, 225 0, "Set to true to leave smart power down enabled on newer adapters"); 226 227 /* Controls whether promiscuous also shows bad packets */ 228 static int igc_debug_sbp = true; 229 SYSCTL_INT(_hw_igc, OID_AUTO, sbp, CTLFLAG_RDTUN, &igc_debug_sbp, 0, 230 "Show bad packets in promiscuous mode"); 231 232 /* Energy efficient ethernet - default to OFF */ 233 static int igc_eee_setting = 1; 234 SYSCTL_INT(_hw_igc, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &igc_eee_setting, 0, 235 "Enable Energy Efficient Ethernet"); 236 237 /* 238 ** Tuneable Interrupt rate 239 */ 240 static int igc_max_interrupt_rate = 20000; 241 SYSCTL_INT(_hw_igc, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 242 &igc_max_interrupt_rate, 0, "Maximum interrupts per second"); 243 244 extern struct if_txrx igc_txrx; 245 246 static struct if_shared_ctx igc_sctx_init = { 247 .isc_magic = IFLIB_MAGIC, 248 .isc_q_align = PAGE_SIZE, 249 .isc_tx_maxsize = IGC_TSO_SIZE + sizeof(struct ether_vlan_header), 250 .isc_tx_maxsegsize = PAGE_SIZE, 251 .isc_tso_maxsize = IGC_TSO_SIZE + sizeof(struct ether_vlan_header), 252 .isc_tso_maxsegsize = IGC_TSO_SEG_SIZE, 253 .isc_rx_maxsize = MAX_JUMBO_FRAME_SIZE, 254 .isc_rx_nsegments = 1, 255 .isc_rx_maxsegsize = MJUM9BYTES, 256 .isc_nfl = 1, 257 .isc_nrxqs = 1, 258 .isc_ntxqs = 1, 259 .isc_admin_intrcnt = 1, 260 .isc_vendor_info = igc_vendor_info_array, 261 .isc_driver_version = "1", 262 .isc_driver = &igc_if_driver, 263 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 264 265 .isc_nrxd_min = {IGC_MIN_RXD}, 266 .isc_ntxd_min = {IGC_MIN_TXD}, 267 .isc_nrxd_max = {IGC_MAX_RXD}, 268 .isc_ntxd_max = {IGC_MAX_TXD}, 269 .isc_nrxd_default = {IGC_DEFAULT_RXD}, 270 .isc_ntxd_default = {IGC_DEFAULT_TXD}, 271 }; 272 273 /***************************************************************** 274 * 275 * Dump Registers 276 * 277 ****************************************************************/ 278 #define IGC_REGS_LEN 739 279 280 static int igc_get_regs(SYSCTL_HANDLER_ARGS) 281 { 282 struct igc_adapter *adapter = (struct igc_adapter *)arg1; 283 struct igc_hw *hw = &adapter->hw; 284 struct sbuf *sb; 285 u32 *regs_buff; 286 int rc; 287 288 regs_buff = malloc(sizeof(u32) * IGC_REGS_LEN, M_DEVBUF, M_WAITOK); 289 memset(regs_buff, 0, IGC_REGS_LEN * sizeof(u32)); 290 291 rc = sysctl_wire_old_buffer(req, 0); 292 MPASS(rc == 0); 293 if (rc != 0) { 294 free(regs_buff, M_DEVBUF); 295 return (rc); 296 } 297 298 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 299 MPASS(sb != NULL); 300 if (sb == NULL) { 301 free(regs_buff, M_DEVBUF); 302 return (ENOMEM); 303 } 304 305 /* General Registers */ 306 regs_buff[0] = IGC_READ_REG(hw, IGC_CTRL); 307 regs_buff[1] = IGC_READ_REG(hw, IGC_STATUS); 308 regs_buff[2] = IGC_READ_REG(hw, IGC_CTRL_EXT); 309 regs_buff[3] = IGC_READ_REG(hw, IGC_ICR); 310 regs_buff[4] = IGC_READ_REG(hw, IGC_RCTL); 311 regs_buff[5] = IGC_READ_REG(hw, IGC_RDLEN(0)); 312 regs_buff[6] = IGC_READ_REG(hw, IGC_RDH(0)); 313 regs_buff[7] = IGC_READ_REG(hw, IGC_RDT(0)); 314 regs_buff[8] = IGC_READ_REG(hw, IGC_RXDCTL(0)); 315 regs_buff[9] = IGC_READ_REG(hw, IGC_RDBAL(0)); 316 regs_buff[10] = IGC_READ_REG(hw, IGC_RDBAH(0)); 317 regs_buff[11] = IGC_READ_REG(hw, IGC_TCTL); 318 regs_buff[12] = IGC_READ_REG(hw, IGC_TDBAL(0)); 319 regs_buff[13] = IGC_READ_REG(hw, IGC_TDBAH(0)); 320 regs_buff[14] = IGC_READ_REG(hw, IGC_TDLEN(0)); 321 regs_buff[15] = IGC_READ_REG(hw, IGC_TDH(0)); 322 regs_buff[16] = IGC_READ_REG(hw, IGC_TDT(0)); 323 regs_buff[17] = IGC_READ_REG(hw, IGC_TXDCTL(0)); 324 325 sbuf_printf(sb, "General Registers\n"); 326 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 327 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 328 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 329 330 sbuf_printf(sb, "Interrupt Registers\n"); 331 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 332 333 sbuf_printf(sb, "RX Registers\n"); 334 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 335 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 336 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 337 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 338 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 339 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 340 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 341 342 sbuf_printf(sb, "TX Registers\n"); 343 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 344 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 345 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 346 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 347 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 348 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 349 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 350 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 351 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 352 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 353 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 354 355 free(regs_buff, M_DEVBUF); 356 357 #ifdef DUMP_DESCS 358 { 359 if_softc_ctx_t scctx = adapter->shared; 360 struct rx_ring *rxr = &rx_que->rxr; 361 struct tx_ring *txr = &tx_que->txr; 362 int ntxd = scctx->isc_ntxd[0]; 363 int nrxd = scctx->isc_nrxd[0]; 364 int j; 365 366 for (j = 0; j < nrxd; j++) { 367 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 368 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 369 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 370 } 371 372 for (j = 0; j < min(ntxd, 256); j++) { 373 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 374 375 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 376 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 377 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & IGC_TXD_STAT_DD : 0); 378 379 } 380 } 381 #endif 382 383 rc = sbuf_finish(sb); 384 sbuf_delete(sb); 385 return(rc); 386 } 387 388 static void * 389 igc_register(device_t dev) 390 { 391 return (&igc_sctx_init); 392 } 393 394 static int 395 igc_set_num_queues(if_ctx_t ctx) 396 { 397 int maxqueues; 398 399 maxqueues = 4; 400 401 return (maxqueues); 402 } 403 404 #define IGC_CAPS \ 405 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 406 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_TSO4 | IFCAP_LRO | \ 407 IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | IFCAP_TSO6 408 409 /********************************************************************* 410 * Device initialization routine 411 * 412 * The attach entry point is called when the driver is being loaded. 413 * This routine identifies the type of hardware, allocates all resources 414 * and initializes the hardware. 415 * 416 * return 0 on success, positive on failure 417 *********************************************************************/ 418 static int 419 igc_if_attach_pre(if_ctx_t ctx) 420 { 421 struct igc_adapter *adapter; 422 if_softc_ctx_t scctx; 423 device_t dev; 424 struct igc_hw *hw; 425 int error = 0; 426 427 INIT_DEBUGOUT("igc_if_attach_pre: begin"); 428 dev = iflib_get_dev(ctx); 429 adapter = iflib_get_softc(ctx); 430 431 adapter->ctx = adapter->osdep.ctx = ctx; 432 adapter->dev = adapter->osdep.dev = dev; 433 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 434 adapter->media = iflib_get_media(ctx); 435 hw = &adapter->hw; 436 437 /* SYSCTL stuff */ 438 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 439 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 440 OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 441 adapter, 0, igc_sysctl_nvm_info, "I", "NVM Information"); 442 443 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 444 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 445 OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 446 adapter, 0, igc_sysctl_debug_info, "I", "Debug Information"); 447 448 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 449 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 450 OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 451 adapter, 0, igc_set_flowcntl, "I", "Flow Control"); 452 453 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 454 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 455 OID_AUTO, "reg_dump", 456 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 0, 457 igc_get_regs, "A", "Dump Registers"); 458 459 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 460 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 461 OID_AUTO, "rs_dump", 462 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, adapter, 0, 463 igc_get_rs, "I", "Dump RS indexes"); 464 465 /* Determine hardware and mac info */ 466 igc_identify_hardware(ctx); 467 468 scctx->isc_tx_nsegments = IGC_MAX_SCATTER; 469 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = igc_set_num_queues(ctx); 470 if (bootverbose) 471 device_printf(dev, "attach_pre capping queues at %d\n", 472 scctx->isc_ntxqsets_max); 473 474 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union igc_adv_tx_desc), IGC_DBA_ALIGN); 475 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union igc_adv_rx_desc), IGC_DBA_ALIGN); 476 scctx->isc_txd_size[0] = sizeof(union igc_adv_tx_desc); 477 scctx->isc_rxd_size[0] = sizeof(union igc_adv_rx_desc); 478 scctx->isc_txrx = &igc_txrx; 479 scctx->isc_tx_tso_segments_max = IGC_MAX_SCATTER; 480 scctx->isc_tx_tso_size_max = IGC_TSO_SIZE; 481 scctx->isc_tx_tso_segsize_max = IGC_TSO_SEG_SIZE; 482 scctx->isc_capabilities = scctx->isc_capenable = IGC_CAPS; 483 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 484 CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_SCTP | CSUM_IP6_SCTP; 485 486 /* 487 ** Some new devices, as with ixgbe, now may 488 ** use a different BAR, so we need to keep 489 ** track of which is used. 490 */ 491 scctx->isc_msix_bar = PCIR_BAR(IGC_MSIX_BAR); 492 if (pci_read_config(dev, scctx->isc_msix_bar, 4) == 0) 493 scctx->isc_msix_bar += 4; 494 495 /* Setup PCI resources */ 496 if (igc_allocate_pci_resources(ctx)) { 497 device_printf(dev, "Allocation of PCI resources failed\n"); 498 error = ENXIO; 499 goto err_pci; 500 } 501 502 /* Do Shared Code initialization */ 503 error = igc_setup_init_funcs(hw, true); 504 if (error) { 505 device_printf(dev, "Setup of Shared code failed, error %d\n", 506 error); 507 error = ENXIO; 508 goto err_pci; 509 } 510 511 igc_setup_msix(ctx); 512 igc_get_bus_info(hw); 513 514 hw->mac.autoneg = DO_AUTO_NEG; 515 hw->phy.autoneg_wait_to_complete = false; 516 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 517 518 /* Copper options */ 519 if (hw->phy.media_type == igc_media_type_copper) { 520 hw->phy.mdix = AUTO_ALL_MODES; 521 } 522 523 /* 524 * Set the frame limits assuming 525 * standard ethernet sized frames. 526 */ 527 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 528 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 529 530 /* Allocate multicast array memory. */ 531 adapter->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 532 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 533 if (adapter->mta == NULL) { 534 device_printf(dev, "Can not allocate multicast setup array\n"); 535 error = ENOMEM; 536 goto err_late; 537 } 538 539 /* Check SOL/IDER usage */ 540 if (igc_check_reset_block(hw)) 541 device_printf(dev, "PHY reset is blocked" 542 " due to SOL/IDER session.\n"); 543 544 /* Sysctl for setting Energy Efficient Ethernet */ 545 adapter->hw.dev_spec._i225.eee_disable = igc_eee_setting; 546 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 547 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 548 OID_AUTO, "eee_control", 549 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 550 adapter, 0, igc_sysctl_eee, "I", 551 "Disable Energy Efficient Ethernet"); 552 553 /* 554 ** Start from a known state, this is 555 ** important in reading the nvm and 556 ** mac from that. 557 */ 558 igc_reset_hw(hw); 559 560 /* Make sure we have a good EEPROM before we read from it */ 561 if (igc_validate_nvm_checksum(hw) < 0) { 562 /* 563 ** Some PCI-E parts fail the first check due to 564 ** the link being in sleep state, call it again, 565 ** if it fails a second time its a real issue. 566 */ 567 if (igc_validate_nvm_checksum(hw) < 0) { 568 device_printf(dev, 569 "The EEPROM Checksum Is Not Valid\n"); 570 error = EIO; 571 goto err_late; 572 } 573 } 574 575 /* Copy the permanent MAC address out of the EEPROM */ 576 if (igc_read_mac_addr(hw) < 0) { 577 device_printf(dev, "EEPROM read error while reading MAC" 578 " address\n"); 579 error = EIO; 580 goto err_late; 581 } 582 583 if (!igc_is_valid_ether_addr(hw->mac.addr)) { 584 device_printf(dev, "Invalid MAC address\n"); 585 error = EIO; 586 goto err_late; 587 } 588 589 /* 590 * Get Wake-on-Lan and Management info for later use 591 */ 592 igc_get_wakeup(ctx); 593 594 /* Enable only WOL MAGIC by default */ 595 scctx->isc_capenable &= ~IFCAP_WOL; 596 if (adapter->wol != 0) 597 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 598 599 iflib_set_mac(ctx, hw->mac.addr); 600 601 return (0); 602 603 err_late: 604 igc_release_hw_control(adapter); 605 err_pci: 606 igc_free_pci_resources(ctx); 607 free(adapter->mta, M_DEVBUF); 608 609 return (error); 610 } 611 612 static int 613 igc_if_attach_post(if_ctx_t ctx) 614 { 615 struct igc_adapter *adapter = iflib_get_softc(ctx); 616 struct igc_hw *hw = &adapter->hw; 617 int error = 0; 618 619 /* Setup OS specific network interface */ 620 error = igc_setup_interface(ctx); 621 if (error != 0) { 622 goto err_late; 623 } 624 625 igc_reset(ctx); 626 627 /* Initialize statistics */ 628 igc_update_stats_counters(adapter); 629 hw->mac.get_link_status = true; 630 igc_if_update_admin_status(ctx); 631 igc_add_hw_stats(adapter); 632 633 /* the driver can now take control from firmware */ 634 igc_get_hw_control(adapter); 635 636 INIT_DEBUGOUT("igc_if_attach_post: end"); 637 638 return (error); 639 640 err_late: 641 igc_release_hw_control(adapter); 642 igc_free_pci_resources(ctx); 643 igc_if_queues_free(ctx); 644 free(adapter->mta, M_DEVBUF); 645 646 return (error); 647 } 648 649 /********************************************************************* 650 * Device removal routine 651 * 652 * The detach entry point is called when the driver is being removed. 653 * This routine stops the adapter and deallocates all the resources 654 * that were allocated for driver operation. 655 * 656 * return 0 on success, positive on failure 657 *********************************************************************/ 658 static int 659 igc_if_detach(if_ctx_t ctx) 660 { 661 struct igc_adapter *adapter = iflib_get_softc(ctx); 662 663 INIT_DEBUGOUT("igc_if_detach: begin"); 664 665 igc_phy_hw_reset(&adapter->hw); 666 667 igc_release_hw_control(adapter); 668 igc_free_pci_resources(ctx); 669 670 return (0); 671 } 672 673 /********************************************************************* 674 * 675 * Shutdown entry point 676 * 677 **********************************************************************/ 678 679 static int 680 igc_if_shutdown(if_ctx_t ctx) 681 { 682 return igc_if_suspend(ctx); 683 } 684 685 /* 686 * Suspend/resume device methods. 687 */ 688 static int 689 igc_if_suspend(if_ctx_t ctx) 690 { 691 struct igc_adapter *adapter = iflib_get_softc(ctx); 692 693 igc_release_hw_control(adapter); 694 igc_enable_wakeup(ctx); 695 return (0); 696 } 697 698 static int 699 igc_if_resume(if_ctx_t ctx) 700 { 701 igc_if_init(ctx); 702 703 return(0); 704 } 705 706 static int 707 igc_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 708 { 709 int max_frame_size; 710 struct igc_adapter *adapter = iflib_get_softc(ctx); 711 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 712 713 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 714 715 /* 9K Jumbo Frame size */ 716 max_frame_size = 9234; 717 718 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 719 return (EINVAL); 720 } 721 722 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 723 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 724 return (0); 725 } 726 727 /********************************************************************* 728 * Init entry point 729 * 730 * This routine is used in two ways. It is used by the stack as 731 * init entry point in network interface structure. It is also used 732 * by the driver as a hw/sw initialization routine to get to a 733 * consistent state. 734 * 735 **********************************************************************/ 736 static void 737 igc_if_init(if_ctx_t ctx) 738 { 739 struct igc_adapter *adapter = iflib_get_softc(ctx); 740 if_softc_ctx_t scctx = adapter->shared; 741 if_t ifp = iflib_get_ifp(ctx); 742 struct igc_tx_queue *tx_que; 743 int i; 744 745 INIT_DEBUGOUT("igc_if_init: begin"); 746 747 /* Get the latest mac address, User can use a LAA */ 748 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 749 ETHER_ADDR_LEN); 750 751 /* Put the address into the Receive Address Array */ 752 igc_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 753 754 /* Initialize the hardware */ 755 igc_reset(ctx); 756 igc_if_update_admin_status(ctx); 757 758 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 759 struct tx_ring *txr = &tx_que->txr; 760 761 txr->tx_rs_cidx = txr->tx_rs_pidx; 762 763 /* Initialize the last processed descriptor to be the end of 764 * the ring, rather than the start, so that we avoid an 765 * off-by-one error when calculating how many descriptors are 766 * done in the credits_update function. 767 */ 768 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 769 } 770 771 /* Setup VLAN support, basic and offload if available */ 772 IGC_WRITE_REG(&adapter->hw, IGC_VET, ETHERTYPE_VLAN); 773 774 /* Prepare transmit descriptors and buffers */ 775 igc_initialize_transmit_unit(ctx); 776 777 /* Setup Multicast table */ 778 igc_if_multi_set(ctx); 779 780 adapter->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 781 igc_initialize_receive_unit(ctx); 782 783 /* Set up VLAN support */ 784 igc_setup_vlan_hw_support(ctx); 785 786 /* Don't lose promiscuous settings */ 787 igc_if_set_promisc(ctx, if_getflags(ifp)); 788 igc_clear_hw_cntrs_base_generic(&adapter->hw); 789 790 if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 791 igc_configure_queues(adapter); 792 793 /* this clears any pending interrupts */ 794 IGC_READ_REG(&adapter->hw, IGC_ICR); 795 IGC_WRITE_REG(&adapter->hw, IGC_ICS, IGC_ICS_LSC); 796 797 /* the driver can now take control from firmware */ 798 igc_get_hw_control(adapter); 799 800 /* Set Energy Efficient Ethernet */ 801 igc_set_eee_i225(&adapter->hw, true, true, true); 802 } 803 804 /********************************************************************* 805 * 806 * Fast Legacy/MSI Combined Interrupt Service routine 807 * 808 *********************************************************************/ 809 int 810 igc_intr(void *arg) 811 { 812 struct igc_adapter *adapter = arg; 813 if_ctx_t ctx = adapter->ctx; 814 u32 reg_icr; 815 816 reg_icr = IGC_READ_REG(&adapter->hw, IGC_ICR); 817 818 /* Hot eject? */ 819 if (reg_icr == 0xffffffff) 820 return FILTER_STRAY; 821 822 /* Definitely not our interrupt. */ 823 if (reg_icr == 0x0) 824 return FILTER_STRAY; 825 826 if ((reg_icr & IGC_ICR_INT_ASSERTED) == 0) 827 return FILTER_STRAY; 828 829 /* 830 * Only MSI-X interrupts have one-shot behavior by taking advantage 831 * of the EIAC register. Thus, explicitly disable interrupts. This 832 * also works around the MSI message reordering errata on certain 833 * systems. 834 */ 835 IFDI_INTR_DISABLE(ctx); 836 837 /* Link status change */ 838 if (reg_icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) 839 igc_handle_link(ctx); 840 841 if (reg_icr & IGC_ICR_RXO) 842 adapter->rx_overruns++; 843 844 return (FILTER_SCHEDULE_THREAD); 845 } 846 847 static int 848 igc_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 849 { 850 struct igc_adapter *adapter = iflib_get_softc(ctx); 851 struct igc_rx_queue *rxq = &adapter->rx_queues[rxqid]; 852 853 IGC_WRITE_REG(&adapter->hw, IGC_EIMS, rxq->eims); 854 return (0); 855 } 856 857 static int 858 igc_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 859 { 860 struct igc_adapter *adapter = iflib_get_softc(ctx); 861 struct igc_tx_queue *txq = &adapter->tx_queues[txqid]; 862 863 IGC_WRITE_REG(&adapter->hw, IGC_EIMS, txq->eims); 864 return (0); 865 } 866 867 /********************************************************************* 868 * 869 * MSI-X RX Interrupt Service routine 870 * 871 **********************************************************************/ 872 static int 873 igc_msix_que(void *arg) 874 { 875 struct igc_rx_queue *que = arg; 876 877 ++que->irqs; 878 879 return (FILTER_SCHEDULE_THREAD); 880 } 881 882 /********************************************************************* 883 * 884 * MSI-X Link Fast Interrupt Service routine 885 * 886 **********************************************************************/ 887 static int 888 igc_msix_link(void *arg) 889 { 890 struct igc_adapter *adapter = arg; 891 u32 reg_icr; 892 893 ++adapter->link_irq; 894 MPASS(adapter->hw.back != NULL); 895 reg_icr = IGC_READ_REG(&adapter->hw, IGC_ICR); 896 897 if (reg_icr & IGC_ICR_RXO) 898 adapter->rx_overruns++; 899 900 if (reg_icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) { 901 igc_handle_link(adapter->ctx); 902 } 903 904 IGC_WRITE_REG(&adapter->hw, IGC_IMS, IGC_IMS_LSC); 905 IGC_WRITE_REG(&adapter->hw, IGC_EIMS, adapter->link_mask); 906 907 return (FILTER_HANDLED); 908 } 909 910 static void 911 igc_handle_link(void *context) 912 { 913 if_ctx_t ctx = context; 914 struct igc_adapter *adapter = iflib_get_softc(ctx); 915 916 adapter->hw.mac.get_link_status = true; 917 iflib_admin_intr_deferred(ctx); 918 } 919 920 /********************************************************************* 921 * 922 * Media Ioctl callback 923 * 924 * This routine is called whenever the user queries the status of 925 * the interface using ifconfig. 926 * 927 **********************************************************************/ 928 static void 929 igc_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 930 { 931 struct igc_adapter *adapter = iflib_get_softc(ctx); 932 933 INIT_DEBUGOUT("igc_if_media_status: begin"); 934 935 iflib_admin_intr_deferred(ctx); 936 937 ifmr->ifm_status = IFM_AVALID; 938 ifmr->ifm_active = IFM_ETHER; 939 940 if (!adapter->link_active) { 941 return; 942 } 943 944 ifmr->ifm_status |= IFM_ACTIVE; 945 946 switch (adapter->link_speed) { 947 case 10: 948 ifmr->ifm_active |= IFM_10_T; 949 break; 950 case 100: 951 ifmr->ifm_active |= IFM_100_TX; 952 break; 953 case 1000: 954 ifmr->ifm_active |= IFM_1000_T; 955 break; 956 case 2500: 957 ifmr->ifm_active |= IFM_2500_T; 958 break; 959 } 960 961 if (adapter->link_duplex == FULL_DUPLEX) 962 ifmr->ifm_active |= IFM_FDX; 963 else 964 ifmr->ifm_active |= IFM_HDX; 965 } 966 967 /********************************************************************* 968 * 969 * Media Ioctl callback 970 * 971 * This routine is called when the user changes speed/duplex using 972 * media/mediopt option with ifconfig. 973 * 974 **********************************************************************/ 975 static int 976 igc_if_media_change(if_ctx_t ctx) 977 { 978 struct igc_adapter *adapter = iflib_get_softc(ctx); 979 struct ifmedia *ifm = iflib_get_media(ctx); 980 981 INIT_DEBUGOUT("igc_if_media_change: begin"); 982 983 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 984 return (EINVAL); 985 986 adapter->hw.mac.autoneg = DO_AUTO_NEG; 987 988 switch (IFM_SUBTYPE(ifm->ifm_media)) { 989 case IFM_AUTO: 990 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 991 break; 992 case IFM_2500_T: 993 adapter->hw.phy.autoneg_advertised = ADVERTISE_2500_FULL; 994 break; 995 case IFM_1000_T: 996 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 997 break; 998 case IFM_100_TX: 999 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1000 adapter->hw.phy.autoneg_advertised = ADVERTISE_100_FULL; 1001 else 1002 adapter->hw.phy.autoneg_advertised = ADVERTISE_100_HALF; 1003 break; 1004 case IFM_10_T: 1005 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1006 adapter->hw.phy.autoneg_advertised = ADVERTISE_10_FULL; 1007 else 1008 adapter->hw.phy.autoneg_advertised = ADVERTISE_10_HALF; 1009 break; 1010 default: 1011 device_printf(adapter->dev, "Unsupported media type\n"); 1012 } 1013 1014 igc_if_init(ctx); 1015 1016 return (0); 1017 } 1018 1019 static int 1020 igc_if_set_promisc(if_ctx_t ctx, int flags) 1021 { 1022 struct igc_adapter *adapter = iflib_get_softc(ctx); 1023 if_t ifp = iflib_get_ifp(ctx); 1024 u32 reg_rctl; 1025 int mcnt = 0; 1026 1027 reg_rctl = IGC_READ_REG(&adapter->hw, IGC_RCTL); 1028 reg_rctl &= ~(IGC_RCTL_SBP | IGC_RCTL_UPE); 1029 if (flags & IFF_ALLMULTI) 1030 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1031 else 1032 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1033 1034 /* Don't disable if in MAX groups */ 1035 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1036 reg_rctl &= (~IGC_RCTL_MPE); 1037 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, reg_rctl); 1038 1039 if (flags & IFF_PROMISC) { 1040 reg_rctl |= (IGC_RCTL_UPE | IGC_RCTL_MPE); 1041 /* Turn this on if you want to see bad packets */ 1042 if (igc_debug_sbp) 1043 reg_rctl |= IGC_RCTL_SBP; 1044 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, reg_rctl); 1045 } else if (flags & IFF_ALLMULTI) { 1046 reg_rctl |= IGC_RCTL_MPE; 1047 reg_rctl &= ~IGC_RCTL_UPE; 1048 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, reg_rctl); 1049 } 1050 return (0); 1051 } 1052 1053 static u_int 1054 igc_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1055 { 1056 u8 *mta = arg; 1057 1058 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1059 return (0); 1060 1061 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1062 1063 return (1); 1064 } 1065 1066 /********************************************************************* 1067 * Multicast Update 1068 * 1069 * This routine is called whenever multicast address list is updated. 1070 * 1071 **********************************************************************/ 1072 1073 static void 1074 igc_if_multi_set(if_ctx_t ctx) 1075 { 1076 struct igc_adapter *adapter = iflib_get_softc(ctx); 1077 if_t ifp = iflib_get_ifp(ctx); 1078 u8 *mta; /* Multicast array memory */ 1079 u32 reg_rctl = 0; 1080 int mcnt = 0; 1081 1082 IOCTL_DEBUGOUT("igc_set_multi: begin"); 1083 1084 mta = adapter->mta; 1085 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1086 1087 mcnt = if_foreach_llmaddr(ifp, igc_copy_maddr, mta); 1088 1089 reg_rctl = IGC_READ_REG(&adapter->hw, IGC_RCTL); 1090 1091 if (if_getflags(ifp) & IFF_PROMISC) { 1092 reg_rctl |= (IGC_RCTL_UPE | IGC_RCTL_MPE); 1093 /* Turn this on if you want to see bad packets */ 1094 if (igc_debug_sbp) 1095 reg_rctl |= IGC_RCTL_SBP; 1096 } else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1097 if_getflags(ifp) & IFF_ALLMULTI) { 1098 reg_rctl |= IGC_RCTL_MPE; 1099 reg_rctl &= ~IGC_RCTL_UPE; 1100 } else 1101 reg_rctl &= ~(IGC_RCTL_UPE | IGC_RCTL_MPE); 1102 1103 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1104 igc_update_mc_addr_list(&adapter->hw, mta, mcnt); 1105 1106 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, reg_rctl); 1107 } 1108 1109 /********************************************************************* 1110 * Timer routine 1111 * 1112 * This routine schedules igc_if_update_admin_status() to check for 1113 * link status and to gather statistics as well as to perform some 1114 * controller-specific hardware patting. 1115 * 1116 **********************************************************************/ 1117 static void 1118 igc_if_timer(if_ctx_t ctx, uint16_t qid) 1119 { 1120 1121 if (qid != 0) 1122 return; 1123 1124 iflib_admin_intr_deferred(ctx); 1125 } 1126 1127 static void 1128 igc_if_update_admin_status(if_ctx_t ctx) 1129 { 1130 struct igc_adapter *adapter = iflib_get_softc(ctx); 1131 struct igc_hw *hw = &adapter->hw; 1132 device_t dev = iflib_get_dev(ctx); 1133 u32 link_check, thstat, ctrl; 1134 1135 link_check = thstat = ctrl = 0; 1136 /* Get the cached link value or read phy for real */ 1137 switch (hw->phy.media_type) { 1138 case igc_media_type_copper: 1139 if (hw->mac.get_link_status == true) { 1140 /* Do the work to read phy */ 1141 igc_check_for_link(hw); 1142 link_check = !hw->mac.get_link_status; 1143 } else 1144 link_check = true; 1145 break; 1146 case igc_media_type_unknown: 1147 igc_check_for_link(hw); 1148 link_check = !hw->mac.get_link_status; 1149 /* FALLTHROUGH */ 1150 default: 1151 break; 1152 } 1153 1154 /* Now check for a transition */ 1155 if (link_check && (adapter->link_active == 0)) { 1156 igc_get_speed_and_duplex(hw, &adapter->link_speed, 1157 &adapter->link_duplex); 1158 if (bootverbose) 1159 device_printf(dev, "Link is up %d Mbps %s\n", 1160 adapter->link_speed, 1161 ((adapter->link_duplex == FULL_DUPLEX) ? 1162 "Full Duplex" : "Half Duplex")); 1163 adapter->link_active = 1; 1164 iflib_link_state_change(ctx, LINK_STATE_UP, 1165 IF_Mbps(adapter->link_speed)); 1166 } else if (!link_check && (adapter->link_active == 1)) { 1167 adapter->link_speed = 0; 1168 adapter->link_duplex = 0; 1169 adapter->link_active = 0; 1170 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1171 } 1172 igc_update_stats_counters(adapter); 1173 } 1174 1175 static void 1176 igc_if_watchdog_reset(if_ctx_t ctx) 1177 { 1178 struct igc_adapter *adapter = iflib_get_softc(ctx); 1179 1180 /* 1181 * Just count the event; iflib(4) will already trigger a 1182 * sufficient reset of the controller. 1183 */ 1184 adapter->watchdog_events++; 1185 } 1186 1187 /********************************************************************* 1188 * 1189 * This routine disables all traffic on the adapter by issuing a 1190 * global reset on the MAC. 1191 * 1192 **********************************************************************/ 1193 static void 1194 igc_if_stop(if_ctx_t ctx) 1195 { 1196 struct igc_adapter *adapter = iflib_get_softc(ctx); 1197 1198 INIT_DEBUGOUT("igc_if_stop: begin"); 1199 1200 igc_reset_hw(&adapter->hw); 1201 IGC_WRITE_REG(&adapter->hw, IGC_WUC, 0); 1202 } 1203 1204 /********************************************************************* 1205 * 1206 * Determine hardware revision. 1207 * 1208 **********************************************************************/ 1209 static void 1210 igc_identify_hardware(if_ctx_t ctx) 1211 { 1212 device_t dev = iflib_get_dev(ctx); 1213 struct igc_adapter *adapter = iflib_get_softc(ctx); 1214 1215 /* Make sure our PCI config space has the necessary stuff set */ 1216 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1217 1218 /* Save off the information about this board */ 1219 adapter->hw.vendor_id = pci_get_vendor(dev); 1220 adapter->hw.device_id = pci_get_device(dev); 1221 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1222 adapter->hw.subsystem_vendor_id = 1223 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1224 adapter->hw.subsystem_device_id = 1225 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1226 1227 /* Do Shared Code Init and Setup */ 1228 if (igc_set_mac_type(&adapter->hw)) { 1229 device_printf(dev, "Setup init failure\n"); 1230 return; 1231 } 1232 } 1233 1234 static int 1235 igc_allocate_pci_resources(if_ctx_t ctx) 1236 { 1237 struct igc_adapter *adapter = iflib_get_softc(ctx); 1238 device_t dev = iflib_get_dev(ctx); 1239 int rid; 1240 1241 rid = PCIR_BAR(0); 1242 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1243 &rid, RF_ACTIVE); 1244 if (adapter->memory == NULL) { 1245 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1246 return (ENXIO); 1247 } 1248 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1249 adapter->osdep.mem_bus_space_handle = 1250 rman_get_bushandle(adapter->memory); 1251 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1252 1253 adapter->hw.back = &adapter->osdep; 1254 1255 return (0); 1256 } 1257 1258 /********************************************************************* 1259 * 1260 * Set up the MSI-X Interrupt handlers 1261 * 1262 **********************************************************************/ 1263 static int 1264 igc_if_msix_intr_assign(if_ctx_t ctx, int msix) 1265 { 1266 struct igc_adapter *adapter = iflib_get_softc(ctx); 1267 struct igc_rx_queue *rx_que = adapter->rx_queues; 1268 struct igc_tx_queue *tx_que = adapter->tx_queues; 1269 int error, rid, i, vector = 0, rx_vectors; 1270 char buf[16]; 1271 1272 /* First set up ring resources */ 1273 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 1274 rid = vector + 1; 1275 snprintf(buf, sizeof(buf), "rxq%d", i); 1276 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, igc_msix_que, rx_que, rx_que->me, buf); 1277 if (error) { 1278 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 1279 adapter->rx_num_queues = i + 1; 1280 goto fail; 1281 } 1282 1283 rx_que->msix = vector; 1284 1285 /* 1286 * Set the bit to enable interrupt 1287 * in IGC_IMS -- bits 20 and 21 1288 * are for RX0 and RX1, note this has 1289 * NOTHING to do with the MSI-X vector 1290 */ 1291 rx_que->eims = 1 << vector; 1292 } 1293 rx_vectors = vector; 1294 1295 vector = 0; 1296 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 1297 snprintf(buf, sizeof(buf), "txq%d", i); 1298 tx_que = &adapter->tx_queues[i]; 1299 iflib_softirq_alloc_generic(ctx, 1300 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq, 1301 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 1302 1303 tx_que->msix = (vector % adapter->rx_num_queues); 1304 1305 /* 1306 * Set the bit to enable interrupt 1307 * in IGC_IMS -- bits 22 and 23 1308 * are for TX0 and TX1, note this has 1309 * NOTHING to do with the MSI-X vector 1310 */ 1311 tx_que->eims = 1 << i; 1312 } 1313 1314 /* Link interrupt */ 1315 rid = rx_vectors + 1; 1316 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, igc_msix_link, adapter, 0, "aq"); 1317 1318 if (error) { 1319 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 1320 goto fail; 1321 } 1322 adapter->linkvec = rx_vectors; 1323 return (0); 1324 fail: 1325 iflib_irq_free(ctx, &adapter->irq); 1326 rx_que = adapter->rx_queues; 1327 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 1328 iflib_irq_free(ctx, &rx_que->que_irq); 1329 return (error); 1330 } 1331 1332 static void 1333 igc_configure_queues(struct igc_adapter *adapter) 1334 { 1335 struct igc_hw *hw = &adapter->hw; 1336 struct igc_rx_queue *rx_que; 1337 struct igc_tx_queue *tx_que; 1338 u32 ivar = 0, newitr = 0; 1339 1340 /* First turn on RSS capability */ 1341 IGC_WRITE_REG(hw, IGC_GPIE, 1342 IGC_GPIE_MSIX_MODE | IGC_GPIE_EIAME | IGC_GPIE_PBA | 1343 IGC_GPIE_NSICR); 1344 1345 /* Turn on MSI-X */ 1346 /* RX entries */ 1347 for (int i = 0; i < adapter->rx_num_queues; i++) { 1348 u32 index = i >> 1; 1349 ivar = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, index); 1350 rx_que = &adapter->rx_queues[i]; 1351 if (i & 1) { 1352 ivar &= 0xFF00FFFF; 1353 ivar |= (rx_que->msix | IGC_IVAR_VALID) << 16; 1354 } else { 1355 ivar &= 0xFFFFFF00; 1356 ivar |= rx_que->msix | IGC_IVAR_VALID; 1357 } 1358 IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, index, ivar); 1359 } 1360 /* TX entries */ 1361 for (int i = 0; i < adapter->tx_num_queues; i++) { 1362 u32 index = i >> 1; 1363 ivar = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, index); 1364 tx_que = &adapter->tx_queues[i]; 1365 if (i & 1) { 1366 ivar &= 0x00FFFFFF; 1367 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 24; 1368 } else { 1369 ivar &= 0xFFFF00FF; 1370 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 8; 1371 } 1372 IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, index, ivar); 1373 adapter->que_mask |= tx_que->eims; 1374 } 1375 1376 /* And for the link interrupt */ 1377 ivar = (adapter->linkvec | IGC_IVAR_VALID) << 8; 1378 adapter->link_mask = 1 << adapter->linkvec; 1379 IGC_WRITE_REG(hw, IGC_IVAR_MISC, ivar); 1380 1381 /* Set the starting interrupt rate */ 1382 if (igc_max_interrupt_rate > 0) 1383 newitr = (4000000 / igc_max_interrupt_rate) & 0x7FFC; 1384 1385 newitr |= IGC_EITR_CNT_IGNR; 1386 1387 for (int i = 0; i < adapter->rx_num_queues; i++) { 1388 rx_que = &adapter->rx_queues[i]; 1389 IGC_WRITE_REG(hw, IGC_EITR(rx_que->msix), newitr); 1390 } 1391 1392 return; 1393 } 1394 1395 static void 1396 igc_free_pci_resources(if_ctx_t ctx) 1397 { 1398 struct igc_adapter *adapter = iflib_get_softc(ctx); 1399 struct igc_rx_queue *que = adapter->rx_queues; 1400 device_t dev = iflib_get_dev(ctx); 1401 1402 /* Release all MSI-X queue resources */ 1403 if (adapter->intr_type == IFLIB_INTR_MSIX) 1404 iflib_irq_free(ctx, &adapter->irq); 1405 1406 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 1407 iflib_irq_free(ctx, &que->que_irq); 1408 } 1409 1410 if (adapter->memory != NULL) { 1411 bus_release_resource(dev, SYS_RES_MEMORY, 1412 rman_get_rid(adapter->memory), adapter->memory); 1413 adapter->memory = NULL; 1414 } 1415 1416 if (adapter->flash != NULL) { 1417 bus_release_resource(dev, SYS_RES_MEMORY, 1418 rman_get_rid(adapter->flash), adapter->flash); 1419 adapter->flash = NULL; 1420 } 1421 1422 if (adapter->ioport != NULL) { 1423 bus_release_resource(dev, SYS_RES_IOPORT, 1424 rman_get_rid(adapter->ioport), adapter->ioport); 1425 adapter->ioport = NULL; 1426 } 1427 } 1428 1429 /* Set up MSI or MSI-X */ 1430 static int 1431 igc_setup_msix(if_ctx_t ctx) 1432 { 1433 return (0); 1434 } 1435 1436 /********************************************************************* 1437 * 1438 * Initialize the DMA Coalescing feature 1439 * 1440 **********************************************************************/ 1441 static void 1442 igc_init_dmac(struct igc_adapter *adapter, u32 pba) 1443 { 1444 device_t dev = adapter->dev; 1445 struct igc_hw *hw = &adapter->hw; 1446 u32 dmac, reg = ~IGC_DMACR_DMAC_EN; 1447 u16 hwm; 1448 u16 max_frame_size; 1449 int status; 1450 1451 max_frame_size = adapter->shared->isc_max_frame_size; 1452 1453 if (adapter->dmac == 0) { /* Disabling it */ 1454 IGC_WRITE_REG(hw, IGC_DMACR, reg); 1455 return; 1456 } else 1457 device_printf(dev, "DMA Coalescing enabled\n"); 1458 1459 /* Set starting threshold */ 1460 IGC_WRITE_REG(hw, IGC_DMCTXTH, 0); 1461 1462 hwm = 64 * pba - max_frame_size / 16; 1463 if (hwm < 64 * (pba - 6)) 1464 hwm = 64 * (pba - 6); 1465 reg = IGC_READ_REG(hw, IGC_FCRTC); 1466 reg &= ~IGC_FCRTC_RTH_COAL_MASK; 1467 reg |= ((hwm << IGC_FCRTC_RTH_COAL_SHIFT) 1468 & IGC_FCRTC_RTH_COAL_MASK); 1469 IGC_WRITE_REG(hw, IGC_FCRTC, reg); 1470 1471 dmac = pba - max_frame_size / 512; 1472 if (dmac < pba - 10) 1473 dmac = pba - 10; 1474 reg = IGC_READ_REG(hw, IGC_DMACR); 1475 reg &= ~IGC_DMACR_DMACTHR_MASK; 1476 reg |= ((dmac << IGC_DMACR_DMACTHR_SHIFT) 1477 & IGC_DMACR_DMACTHR_MASK); 1478 1479 /* transition to L0x or L1 if available..*/ 1480 reg |= (IGC_DMACR_DMAC_EN | IGC_DMACR_DMAC_LX_MASK); 1481 1482 /* Check if status is 2.5Gb backplane connection 1483 * before configuration of watchdog timer, which is 1484 * in msec values in 12.8usec intervals 1485 * watchdog timer= msec values in 32usec intervals 1486 * for non 2.5Gb connection 1487 */ 1488 status = IGC_READ_REG(hw, IGC_STATUS); 1489 if ((status & IGC_STATUS_2P5_SKU) && 1490 (!(status & IGC_STATUS_2P5_SKU_OVER))) 1491 reg |= ((adapter->dmac * 5) >> 6); 1492 else 1493 reg |= (adapter->dmac >> 5); 1494 1495 IGC_WRITE_REG(hw, IGC_DMACR, reg); 1496 1497 IGC_WRITE_REG(hw, IGC_DMCRTRH, 0); 1498 1499 /* Set the interval before transition */ 1500 reg = IGC_READ_REG(hw, IGC_DMCTLX); 1501 reg |= IGC_DMCTLX_DCFLUSH_DIS; 1502 1503 /* 1504 ** in 2.5Gb connection, TTLX unit is 0.4 usec 1505 ** which is 0x4*2 = 0xA. But delay is still 4 usec 1506 */ 1507 status = IGC_READ_REG(hw, IGC_STATUS); 1508 if ((status & IGC_STATUS_2P5_SKU) && 1509 (!(status & IGC_STATUS_2P5_SKU_OVER))) 1510 reg |= 0xA; 1511 else 1512 reg |= 0x4; 1513 1514 IGC_WRITE_REG(hw, IGC_DMCTLX, reg); 1515 1516 /* free space in tx packet buffer to wake from DMA coal */ 1517 IGC_WRITE_REG(hw, IGC_DMCTXTH, (IGC_TXPBSIZE - 1518 (2 * max_frame_size)) >> 6); 1519 1520 /* make low power state decision controlled by DMA coal */ 1521 reg = IGC_READ_REG(hw, IGC_PCIEMISC); 1522 reg &= ~IGC_PCIEMISC_LX_DECISION; 1523 IGC_WRITE_REG(hw, IGC_PCIEMISC, reg); 1524 } 1525 1526 /********************************************************************* 1527 * 1528 * Initialize the hardware to a configuration as specified by the 1529 * adapter structure. 1530 * 1531 **********************************************************************/ 1532 static void 1533 igc_reset(if_ctx_t ctx) 1534 { 1535 device_t dev = iflib_get_dev(ctx); 1536 struct igc_adapter *adapter = iflib_get_softc(ctx); 1537 struct igc_hw *hw = &adapter->hw; 1538 u32 rx_buffer_size; 1539 u32 pba; 1540 1541 INIT_DEBUGOUT("igc_reset: begin"); 1542 /* Let the firmware know the OS is in control */ 1543 igc_get_hw_control(adapter); 1544 1545 /* 1546 * Packet Buffer Allocation (PBA) 1547 * Writing PBA sets the receive portion of the buffer 1548 * the remainder is used for the transmit buffer. 1549 */ 1550 pba = IGC_PBA_34K; 1551 1552 INIT_DEBUGOUT1("igc_reset: pba=%dK",pba); 1553 1554 /* 1555 * These parameters control the automatic generation (Tx) and 1556 * response (Rx) to Ethernet PAUSE frames. 1557 * - High water mark should allow for at least two frames to be 1558 * received after sending an XOFF. 1559 * - Low water mark works best when it is very near the high water mark. 1560 * This allows the receiver to restart by sending XON when it has 1561 * drained a bit. Here we use an arbitrary value of 1500 which will 1562 * restart after one full frame is pulled from the buffer. There 1563 * could be several smaller frames in the buffer and if so they will 1564 * not trigger the XON until their total number reduces the buffer 1565 * by 1500. 1566 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 1567 */ 1568 rx_buffer_size = (pba & 0xffff) << 10; 1569 hw->fc.high_water = rx_buffer_size - 1570 roundup2(adapter->hw.mac.max_frame_size, 1024); 1571 /* 16-byte granularity */ 1572 hw->fc.low_water = hw->fc.high_water - 16; 1573 1574 if (adapter->fc) /* locally set flow control value? */ 1575 hw->fc.requested_mode = adapter->fc; 1576 else 1577 hw->fc.requested_mode = igc_fc_full; 1578 1579 hw->fc.pause_time = IGC_FC_PAUSE_TIME; 1580 1581 hw->fc.send_xon = true; 1582 1583 /* Issue a global reset */ 1584 igc_reset_hw(hw); 1585 IGC_WRITE_REG(hw, IGC_WUC, 0); 1586 1587 /* and a re-init */ 1588 if (igc_init_hw(hw) < 0) { 1589 device_printf(dev, "Hardware Initialization Failed\n"); 1590 return; 1591 } 1592 1593 /* Setup DMA Coalescing */ 1594 igc_init_dmac(adapter, pba); 1595 1596 IGC_WRITE_REG(hw, IGC_VET, ETHERTYPE_VLAN); 1597 igc_get_phy_info(hw); 1598 igc_check_for_link(hw); 1599 } 1600 1601 /* 1602 * Initialise the RSS mapping for NICs that support multiple transmit/ 1603 * receive rings. 1604 */ 1605 1606 #define RSSKEYLEN 10 1607 static void 1608 igc_initialize_rss_mapping(struct igc_adapter *adapter) 1609 { 1610 struct igc_hw *hw = &adapter->hw; 1611 int i; 1612 int queue_id; 1613 u32 reta; 1614 u32 rss_key[RSSKEYLEN], mrqc, shift = 0; 1615 1616 /* 1617 * The redirection table controls which destination 1618 * queue each bucket redirects traffic to. 1619 * Each DWORD represents four queues, with the LSB 1620 * being the first queue in the DWORD. 1621 * 1622 * This just allocates buckets to queues using round-robin 1623 * allocation. 1624 * 1625 * NOTE: It Just Happens to line up with the default 1626 * RSS allocation method. 1627 */ 1628 1629 /* Warning FM follows */ 1630 reta = 0; 1631 for (i = 0; i < 128; i++) { 1632 #ifdef RSS 1633 queue_id = rss_get_indirection_to_bucket(i); 1634 /* 1635 * If we have more queues than buckets, we'll 1636 * end up mapping buckets to a subset of the 1637 * queues. 1638 * 1639 * If we have more buckets than queues, we'll 1640 * end up instead assigning multiple buckets 1641 * to queues. 1642 * 1643 * Both are suboptimal, but we need to handle 1644 * the case so we don't go out of bounds 1645 * indexing arrays and such. 1646 */ 1647 queue_id = queue_id % adapter->rx_num_queues; 1648 #else 1649 queue_id = (i % adapter->rx_num_queues); 1650 #endif 1651 /* Adjust if required */ 1652 queue_id = queue_id << shift; 1653 1654 /* 1655 * The low 8 bits are for hash value (n+0); 1656 * The next 8 bits are for hash value (n+1), etc. 1657 */ 1658 reta = reta >> 8; 1659 reta = reta | ( ((uint32_t) queue_id) << 24); 1660 if ((i & 3) == 3) { 1661 IGC_WRITE_REG(hw, IGC_RETA(i >> 2), reta); 1662 reta = 0; 1663 } 1664 } 1665 1666 /* Now fill in hash table */ 1667 1668 /* 1669 * MRQC: Multiple Receive Queues Command 1670 * Set queuing to RSS control, number depends on the device. 1671 */ 1672 mrqc = IGC_MRQC_ENABLE_RSS_4Q; 1673 1674 #ifdef RSS 1675 /* XXX ew typecasting */ 1676 rss_getkey((uint8_t *) &rss_key); 1677 #else 1678 arc4rand(&rss_key, sizeof(rss_key), 0); 1679 #endif 1680 for (i = 0; i < RSSKEYLEN; i++) 1681 IGC_WRITE_REG_ARRAY(hw, IGC_RSSRK(0), i, rss_key[i]); 1682 1683 /* 1684 * Configure the RSS fields to hash upon. 1685 */ 1686 mrqc |= (IGC_MRQC_RSS_FIELD_IPV4 | 1687 IGC_MRQC_RSS_FIELD_IPV4_TCP); 1688 mrqc |= (IGC_MRQC_RSS_FIELD_IPV6 | 1689 IGC_MRQC_RSS_FIELD_IPV6_TCP); 1690 mrqc |=( IGC_MRQC_RSS_FIELD_IPV4_UDP | 1691 IGC_MRQC_RSS_FIELD_IPV6_UDP); 1692 mrqc |=( IGC_MRQC_RSS_FIELD_IPV6_UDP_EX | 1693 IGC_MRQC_RSS_FIELD_IPV6_TCP_EX); 1694 1695 IGC_WRITE_REG(hw, IGC_MRQC, mrqc); 1696 } 1697 1698 /********************************************************************* 1699 * 1700 * Setup networking device structure and register interface media. 1701 * 1702 **********************************************************************/ 1703 static int 1704 igc_setup_interface(if_ctx_t ctx) 1705 { 1706 if_t ifp = iflib_get_ifp(ctx); 1707 struct igc_adapter *adapter = iflib_get_softc(ctx); 1708 if_softc_ctx_t scctx = adapter->shared; 1709 1710 INIT_DEBUGOUT("igc_setup_interface: begin"); 1711 1712 /* Single Queue */ 1713 if (adapter->tx_num_queues == 1) { 1714 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 1715 if_setsendqready(ifp); 1716 } 1717 1718 /* 1719 * Specify the media types supported by this adapter and register 1720 * callbacks to update media and link information 1721 */ 1722 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 1723 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1724 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 1725 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1726 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1727 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 1728 ifmedia_add(adapter->media, IFM_ETHER | IFM_2500_T, 0, NULL); 1729 1730 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1731 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 1732 return (0); 1733 } 1734 1735 static int 1736 igc_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 1737 { 1738 struct igc_adapter *adapter = iflib_get_softc(ctx); 1739 if_softc_ctx_t scctx = adapter->shared; 1740 int error = IGC_SUCCESS; 1741 struct igc_tx_queue *que; 1742 int i, j; 1743 1744 MPASS(adapter->tx_num_queues > 0); 1745 MPASS(adapter->tx_num_queues == ntxqsets); 1746 1747 /* First allocate the top level queue structs */ 1748 if (!(adapter->tx_queues = 1749 (struct igc_tx_queue *) malloc(sizeof(struct igc_tx_queue) * 1750 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 1751 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 1752 return(ENOMEM); 1753 } 1754 1755 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 1756 /* Set up some basics */ 1757 1758 struct tx_ring *txr = &que->txr; 1759 txr->adapter = que->adapter = adapter; 1760 que->me = txr->me = i; 1761 1762 /* Allocate report status array */ 1763 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 1764 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 1765 error = ENOMEM; 1766 goto fail; 1767 } 1768 for (j = 0; j < scctx->isc_ntxd[0]; j++) 1769 txr->tx_rsq[j] = QIDX_INVALID; 1770 /* get the virtual and physical address of the hardware queues */ 1771 txr->tx_base = (struct igc_tx_desc *)vaddrs[i*ntxqs]; 1772 txr->tx_paddr = paddrs[i*ntxqs]; 1773 } 1774 1775 if (bootverbose) 1776 device_printf(iflib_get_dev(ctx), 1777 "allocated for %d tx_queues\n", adapter->tx_num_queues); 1778 return (0); 1779 fail: 1780 igc_if_queues_free(ctx); 1781 return (error); 1782 } 1783 1784 static int 1785 igc_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 1786 { 1787 struct igc_adapter *adapter = iflib_get_softc(ctx); 1788 int error = IGC_SUCCESS; 1789 struct igc_rx_queue *que; 1790 int i; 1791 1792 MPASS(adapter->rx_num_queues > 0); 1793 MPASS(adapter->rx_num_queues == nrxqsets); 1794 1795 /* First allocate the top level queue structs */ 1796 if (!(adapter->rx_queues = 1797 (struct igc_rx_queue *) malloc(sizeof(struct igc_rx_queue) * 1798 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 1799 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 1800 error = ENOMEM; 1801 goto fail; 1802 } 1803 1804 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 1805 /* Set up some basics */ 1806 struct rx_ring *rxr = &que->rxr; 1807 rxr->adapter = que->adapter = adapter; 1808 rxr->que = que; 1809 que->me = rxr->me = i; 1810 1811 /* get the virtual and physical address of the hardware queues */ 1812 rxr->rx_base = (union igc_rx_desc_extended *)vaddrs[i*nrxqs]; 1813 rxr->rx_paddr = paddrs[i*nrxqs]; 1814 } 1815 1816 if (bootverbose) 1817 device_printf(iflib_get_dev(ctx), 1818 "allocated for %d rx_queues\n", adapter->rx_num_queues); 1819 1820 return (0); 1821 fail: 1822 igc_if_queues_free(ctx); 1823 return (error); 1824 } 1825 1826 static void 1827 igc_if_queues_free(if_ctx_t ctx) 1828 { 1829 struct igc_adapter *adapter = iflib_get_softc(ctx); 1830 struct igc_tx_queue *tx_que = adapter->tx_queues; 1831 struct igc_rx_queue *rx_que = adapter->rx_queues; 1832 1833 if (tx_que != NULL) { 1834 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 1835 struct tx_ring *txr = &tx_que->txr; 1836 if (txr->tx_rsq == NULL) 1837 break; 1838 1839 free(txr->tx_rsq, M_DEVBUF); 1840 txr->tx_rsq = NULL; 1841 } 1842 free(adapter->tx_queues, M_DEVBUF); 1843 adapter->tx_queues = NULL; 1844 } 1845 1846 if (rx_que != NULL) { 1847 free(adapter->rx_queues, M_DEVBUF); 1848 adapter->rx_queues = NULL; 1849 } 1850 1851 igc_release_hw_control(adapter); 1852 1853 if (adapter->mta != NULL) { 1854 free(adapter->mta, M_DEVBUF); 1855 } 1856 } 1857 1858 /********************************************************************* 1859 * 1860 * Enable transmit unit. 1861 * 1862 **********************************************************************/ 1863 static void 1864 igc_initialize_transmit_unit(if_ctx_t ctx) 1865 { 1866 struct igc_adapter *adapter = iflib_get_softc(ctx); 1867 if_softc_ctx_t scctx = adapter->shared; 1868 struct igc_tx_queue *que; 1869 struct tx_ring *txr; 1870 struct igc_hw *hw = &adapter->hw; 1871 u32 tctl, txdctl = 0; 1872 1873 INIT_DEBUGOUT("igc_initialize_transmit_unit: begin"); 1874 1875 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 1876 u64 bus_addr; 1877 caddr_t offp, endp; 1878 1879 que = &adapter->tx_queues[i]; 1880 txr = &que->txr; 1881 bus_addr = txr->tx_paddr; 1882 1883 /* Clear checksum offload context. */ 1884 offp = (caddr_t)&txr->csum_flags; 1885 endp = (caddr_t)(txr + 1); 1886 bzero(offp, endp - offp); 1887 1888 /* Base and Len of TX Ring */ 1889 IGC_WRITE_REG(hw, IGC_TDLEN(i), 1890 scctx->isc_ntxd[0] * sizeof(struct igc_tx_desc)); 1891 IGC_WRITE_REG(hw, IGC_TDBAH(i), 1892 (u32)(bus_addr >> 32)); 1893 IGC_WRITE_REG(hw, IGC_TDBAL(i), 1894 (u32)bus_addr); 1895 /* Init the HEAD/TAIL indices */ 1896 IGC_WRITE_REG(hw, IGC_TDT(i), 0); 1897 IGC_WRITE_REG(hw, IGC_TDH(i), 0); 1898 1899 HW_DEBUGOUT2("Base = %x, Length = %x\n", 1900 IGC_READ_REG(&adapter->hw, IGC_TDBAL(i)), 1901 IGC_READ_REG(&adapter->hw, IGC_TDLEN(i))); 1902 1903 txdctl = 0; /* clear txdctl */ 1904 txdctl |= 0x1f; /* PTHRESH */ 1905 txdctl |= 1 << 8; /* HTHRESH */ 1906 txdctl |= 1 << 16;/* WTHRESH */ 1907 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 1908 txdctl |= IGC_TXDCTL_GRAN; 1909 txdctl |= 1 << 25; /* LWTHRESH */ 1910 1911 IGC_WRITE_REG(hw, IGC_TXDCTL(i), txdctl); 1912 } 1913 1914 /* Program the Transmit Control Register */ 1915 tctl = IGC_READ_REG(&adapter->hw, IGC_TCTL); 1916 tctl &= ~IGC_TCTL_CT; 1917 tctl |= (IGC_TCTL_PSP | IGC_TCTL_RTLC | IGC_TCTL_EN | 1918 (IGC_COLLISION_THRESHOLD << IGC_CT_SHIFT)); 1919 1920 /* This write will effectively turn on the transmit unit. */ 1921 IGC_WRITE_REG(&adapter->hw, IGC_TCTL, tctl); 1922 } 1923 1924 /********************************************************************* 1925 * 1926 * Enable receive unit. 1927 * 1928 **********************************************************************/ 1929 #define BSIZEPKT_ROUNDUP ((1<<IGC_SRRCTL_BSIZEPKT_SHIFT)-1) 1930 1931 static void 1932 igc_initialize_receive_unit(if_ctx_t ctx) 1933 { 1934 struct igc_adapter *adapter = iflib_get_softc(ctx); 1935 if_softc_ctx_t scctx = adapter->shared; 1936 if_t ifp = iflib_get_ifp(ctx); 1937 struct igc_hw *hw = &adapter->hw; 1938 struct igc_rx_queue *que; 1939 int i; 1940 u32 psize, rctl, rxcsum, srrctl = 0; 1941 1942 INIT_DEBUGOUT("igc_initialize_receive_units: begin"); 1943 1944 /* 1945 * Make sure receives are disabled while setting 1946 * up the descriptor ring 1947 */ 1948 rctl = IGC_READ_REG(hw, IGC_RCTL); 1949 IGC_WRITE_REG(hw, IGC_RCTL, rctl & ~IGC_RCTL_EN); 1950 1951 /* Setup the Receive Control Register */ 1952 rctl &= ~(3 << IGC_RCTL_MO_SHIFT); 1953 rctl |= IGC_RCTL_EN | IGC_RCTL_BAM | 1954 IGC_RCTL_LBM_NO | IGC_RCTL_RDMTS_HALF | 1955 (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT); 1956 1957 /* Do not store bad packets */ 1958 rctl &= ~IGC_RCTL_SBP; 1959 1960 /* Enable Long Packet receive */ 1961 if (if_getmtu(ifp) > ETHERMTU) 1962 rctl |= IGC_RCTL_LPE; 1963 else 1964 rctl &= ~IGC_RCTL_LPE; 1965 1966 /* Strip the CRC */ 1967 if (!igc_disable_crc_stripping) 1968 rctl |= IGC_RCTL_SECRC; 1969 1970 rxcsum = IGC_READ_REG(hw, IGC_RXCSUM); 1971 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 1972 rxcsum |= IGC_RXCSUM_CRCOFL; 1973 if (adapter->tx_num_queues > 1) 1974 rxcsum |= IGC_RXCSUM_PCSD; 1975 else 1976 rxcsum |= IGC_RXCSUM_IPPCSE; 1977 } else { 1978 if (adapter->tx_num_queues > 1) 1979 rxcsum |= IGC_RXCSUM_PCSD; 1980 else 1981 rxcsum &= ~IGC_RXCSUM_TUOFL; 1982 } 1983 IGC_WRITE_REG(hw, IGC_RXCSUM, rxcsum); 1984 1985 if (adapter->rx_num_queues > 1) 1986 igc_initialize_rss_mapping(adapter); 1987 1988 if (if_getmtu(ifp) > ETHERMTU) { 1989 psize = scctx->isc_max_frame_size; 1990 /* are we on a vlan? */ 1991 if (if_vlantrunkinuse(ifp)) 1992 psize += VLAN_TAG_SIZE; 1993 IGC_WRITE_REG(&adapter->hw, IGC_RLPML, psize); 1994 } 1995 1996 /* Set maximum packet buffer len */ 1997 srrctl |= (adapter->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 1998 IGC_SRRCTL_BSIZEPKT_SHIFT; 1999 /* srrctl above overrides this but set the register to a sane value */ 2000 rctl |= IGC_RCTL_SZ_2048; 2001 2002 /* 2003 * If TX flow control is disabled and there's >1 queue defined, 2004 * enable DROP. 2005 * 2006 * This drops frames rather than hanging the RX MAC for all queues. 2007 */ 2008 if ((adapter->rx_num_queues > 1) && 2009 (adapter->fc == igc_fc_none || 2010 adapter->fc == igc_fc_rx_pause)) { 2011 srrctl |= IGC_SRRCTL_DROP_EN; 2012 } 2013 2014 /* Setup the Base and Length of the Rx Descriptor Rings */ 2015 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 2016 struct rx_ring *rxr = &que->rxr; 2017 u64 bus_addr = rxr->rx_paddr; 2018 u32 rxdctl; 2019 2020 #ifdef notyet 2021 /* Configure for header split? -- ignore for now */ 2022 rxr->hdr_split = igc_header_split; 2023 #else 2024 srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF; 2025 #endif 2026 2027 IGC_WRITE_REG(hw, IGC_RDLEN(i), 2028 scctx->isc_nrxd[0] * sizeof(struct igc_rx_desc)); 2029 IGC_WRITE_REG(hw, IGC_RDBAH(i), 2030 (uint32_t)(bus_addr >> 32)); 2031 IGC_WRITE_REG(hw, IGC_RDBAL(i), 2032 (uint32_t)bus_addr); 2033 IGC_WRITE_REG(hw, IGC_SRRCTL(i), srrctl); 2034 /* Setup the Head and Tail Descriptor Pointers */ 2035 IGC_WRITE_REG(hw, IGC_RDH(i), 0); 2036 IGC_WRITE_REG(hw, IGC_RDT(i), 0); 2037 /* Enable this Queue */ 2038 rxdctl = IGC_READ_REG(hw, IGC_RXDCTL(i)); 2039 rxdctl |= IGC_RXDCTL_QUEUE_ENABLE; 2040 rxdctl &= 0xFFF00000; 2041 rxdctl |= IGC_RX_PTHRESH; 2042 rxdctl |= IGC_RX_HTHRESH << 8; 2043 rxdctl |= IGC_RX_WTHRESH << 16; 2044 IGC_WRITE_REG(hw, IGC_RXDCTL(i), rxdctl); 2045 } 2046 2047 /* Make sure VLAN Filters are off */ 2048 rctl &= ~IGC_RCTL_VFE; 2049 2050 /* Write out the settings */ 2051 IGC_WRITE_REG(hw, IGC_RCTL, rctl); 2052 2053 return; 2054 } 2055 2056 static void 2057 igc_setup_vlan_hw_support(if_ctx_t ctx) 2058 { 2059 struct igc_adapter *adapter = iflib_get_softc(ctx); 2060 struct igc_hw *hw = &adapter->hw; 2061 struct ifnet *ifp = iflib_get_ifp(ctx); 2062 u32 reg; 2063 2064 /* igc hardware doesn't seem to implement VFTA for HWFILTER */ 2065 2066 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 2067 !igc_disable_crc_stripping) { 2068 reg = IGC_READ_REG(hw, IGC_CTRL); 2069 reg |= IGC_CTRL_VME; 2070 IGC_WRITE_REG(hw, IGC_CTRL, reg); 2071 } else { 2072 reg = IGC_READ_REG(hw, IGC_CTRL); 2073 reg &= ~IGC_CTRL_VME; 2074 IGC_WRITE_REG(hw, IGC_CTRL, reg); 2075 } 2076 } 2077 2078 static void 2079 igc_if_intr_enable(if_ctx_t ctx) 2080 { 2081 struct igc_adapter *adapter = iflib_get_softc(ctx); 2082 struct igc_hw *hw = &adapter->hw; 2083 u32 mask; 2084 2085 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 2086 mask = (adapter->que_mask | adapter->link_mask); 2087 IGC_WRITE_REG(hw, IGC_EIAC, mask); 2088 IGC_WRITE_REG(hw, IGC_EIAM, mask); 2089 IGC_WRITE_REG(hw, IGC_EIMS, mask); 2090 IGC_WRITE_REG(hw, IGC_IMS, IGC_IMS_LSC); 2091 } else 2092 IGC_WRITE_REG(hw, IGC_IMS, IMS_ENABLE_MASK); 2093 IGC_WRITE_FLUSH(hw); 2094 } 2095 2096 static void 2097 igc_if_intr_disable(if_ctx_t ctx) 2098 { 2099 struct igc_adapter *adapter = iflib_get_softc(ctx); 2100 struct igc_hw *hw = &adapter->hw; 2101 2102 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 2103 IGC_WRITE_REG(hw, IGC_EIMC, 0xffffffff); 2104 IGC_WRITE_REG(hw, IGC_EIAC, 0); 2105 } 2106 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff); 2107 IGC_WRITE_FLUSH(hw); 2108 } 2109 2110 /* 2111 * igc_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 2112 * For ASF and Pass Through versions of f/w this means 2113 * that the driver is loaded. For AMT version type f/w 2114 * this means that the network i/f is open. 2115 */ 2116 static void 2117 igc_get_hw_control(struct igc_adapter *adapter) 2118 { 2119 u32 ctrl_ext; 2120 2121 if (adapter->vf_ifp) 2122 return; 2123 2124 ctrl_ext = IGC_READ_REG(&adapter->hw, IGC_CTRL_EXT); 2125 IGC_WRITE_REG(&adapter->hw, IGC_CTRL_EXT, 2126 ctrl_ext | IGC_CTRL_EXT_DRV_LOAD); 2127 } 2128 2129 /* 2130 * igc_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 2131 * For ASF and Pass Through versions of f/w this means that 2132 * the driver is no longer loaded. For AMT versions of the 2133 * f/w this means that the network i/f is closed. 2134 */ 2135 static void 2136 igc_release_hw_control(struct igc_adapter *adapter) 2137 { 2138 u32 ctrl_ext; 2139 2140 ctrl_ext = IGC_READ_REG(&adapter->hw, IGC_CTRL_EXT); 2141 IGC_WRITE_REG(&adapter->hw, IGC_CTRL_EXT, 2142 ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD); 2143 return; 2144 } 2145 2146 static int 2147 igc_is_valid_ether_addr(u8 *addr) 2148 { 2149 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 2150 2151 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 2152 return (false); 2153 } 2154 2155 return (true); 2156 } 2157 2158 /* 2159 ** Parse the interface capabilities with regard 2160 ** to both system management and wake-on-lan for 2161 ** later use. 2162 */ 2163 static void 2164 igc_get_wakeup(if_ctx_t ctx) 2165 { 2166 struct igc_adapter *adapter = iflib_get_softc(ctx); 2167 u16 eeprom_data = 0, apme_mask; 2168 2169 apme_mask = IGC_WUC_APME; 2170 eeprom_data = IGC_READ_REG(&adapter->hw, IGC_WUC); 2171 2172 if (eeprom_data & apme_mask) 2173 adapter->wol = IGC_WUFC_LNKC; 2174 } 2175 2176 2177 /* 2178 * Enable PCI Wake On Lan capability 2179 */ 2180 static void 2181 igc_enable_wakeup(if_ctx_t ctx) 2182 { 2183 struct igc_adapter *adapter = iflib_get_softc(ctx); 2184 device_t dev = iflib_get_dev(ctx); 2185 if_t ifp = iflib_get_ifp(ctx); 2186 int error = 0; 2187 u32 pmc, ctrl, rctl; 2188 u16 status; 2189 2190 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 2191 return; 2192 2193 /* 2194 * Determine type of Wakeup: note that wol 2195 * is set with all bits on by default. 2196 */ 2197 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 2198 adapter->wol &= ~IGC_WUFC_MAG; 2199 2200 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 2201 adapter->wol &= ~IGC_WUFC_EX; 2202 2203 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 2204 adapter->wol &= ~IGC_WUFC_MC; 2205 else { 2206 rctl = IGC_READ_REG(&adapter->hw, IGC_RCTL); 2207 rctl |= IGC_RCTL_MPE; 2208 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, rctl); 2209 } 2210 2211 if (!(adapter->wol & (IGC_WUFC_EX | IGC_WUFC_MAG | IGC_WUFC_MC))) 2212 goto pme; 2213 2214 /* Advertise the wakeup capability */ 2215 ctrl = IGC_READ_REG(&adapter->hw, IGC_CTRL); 2216 ctrl |= IGC_CTRL_ADVD3WUC; 2217 IGC_WRITE_REG(&adapter->hw, IGC_CTRL, ctrl); 2218 2219 /* Enable wakeup by the MAC */ 2220 IGC_WRITE_REG(&adapter->hw, IGC_WUC, IGC_WUC_PME_EN); 2221 IGC_WRITE_REG(&adapter->hw, IGC_WUFC, adapter->wol); 2222 2223 pme: 2224 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 2225 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2226 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 2227 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2228 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 2229 2230 return; 2231 } 2232 2233 /********************************************************************** 2234 * 2235 * Update the board statistics counters. 2236 * 2237 **********************************************************************/ 2238 static void 2239 igc_update_stats_counters(struct igc_adapter *adapter) 2240 { 2241 u64 prev_xoffrxc = adapter->stats.xoffrxc; 2242 2243 adapter->stats.crcerrs += IGC_READ_REG(&adapter->hw, IGC_CRCERRS); 2244 adapter->stats.mpc += IGC_READ_REG(&adapter->hw, IGC_MPC); 2245 adapter->stats.scc += IGC_READ_REG(&adapter->hw, IGC_SCC); 2246 adapter->stats.ecol += IGC_READ_REG(&adapter->hw, IGC_ECOL); 2247 2248 adapter->stats.mcc += IGC_READ_REG(&adapter->hw, IGC_MCC); 2249 adapter->stats.latecol += IGC_READ_REG(&adapter->hw, IGC_LATECOL); 2250 adapter->stats.colc += IGC_READ_REG(&adapter->hw, IGC_COLC); 2251 adapter->stats.colc += IGC_READ_REG(&adapter->hw, IGC_RERC); 2252 adapter->stats.dc += IGC_READ_REG(&adapter->hw, IGC_DC); 2253 adapter->stats.rlec += IGC_READ_REG(&adapter->hw, IGC_RLEC); 2254 adapter->stats.xonrxc += IGC_READ_REG(&adapter->hw, IGC_XONRXC); 2255 adapter->stats.xontxc += IGC_READ_REG(&adapter->hw, IGC_XONTXC); 2256 adapter->stats.xoffrxc += IGC_READ_REG(&adapter->hw, IGC_XOFFRXC); 2257 /* 2258 * For watchdog management we need to know if we have been 2259 * paused during the last interval, so capture that here. 2260 */ 2261 if (adapter->stats.xoffrxc != prev_xoffrxc) 2262 adapter->shared->isc_pause_frames = 1; 2263 adapter->stats.xofftxc += IGC_READ_REG(&adapter->hw, IGC_XOFFTXC); 2264 adapter->stats.fcruc += IGC_READ_REG(&adapter->hw, IGC_FCRUC); 2265 adapter->stats.prc64 += IGC_READ_REG(&adapter->hw, IGC_PRC64); 2266 adapter->stats.prc127 += IGC_READ_REG(&adapter->hw, IGC_PRC127); 2267 adapter->stats.prc255 += IGC_READ_REG(&adapter->hw, IGC_PRC255); 2268 adapter->stats.prc511 += IGC_READ_REG(&adapter->hw, IGC_PRC511); 2269 adapter->stats.prc1023 += IGC_READ_REG(&adapter->hw, IGC_PRC1023); 2270 adapter->stats.prc1522 += IGC_READ_REG(&adapter->hw, IGC_PRC1522); 2271 adapter->stats.tlpic += IGC_READ_REG(&adapter->hw, IGC_TLPIC); 2272 adapter->stats.rlpic += IGC_READ_REG(&adapter->hw, IGC_RLPIC); 2273 adapter->stats.gprc += IGC_READ_REG(&adapter->hw, IGC_GPRC); 2274 adapter->stats.bprc += IGC_READ_REG(&adapter->hw, IGC_BPRC); 2275 adapter->stats.mprc += IGC_READ_REG(&adapter->hw, IGC_MPRC); 2276 adapter->stats.gptc += IGC_READ_REG(&adapter->hw, IGC_GPTC); 2277 2278 /* For the 64-bit byte counters the low dword must be read first. */ 2279 /* Both registers clear on the read of the high dword */ 2280 2281 adapter->stats.gorc += IGC_READ_REG(&adapter->hw, IGC_GORCL) + 2282 ((u64)IGC_READ_REG(&adapter->hw, IGC_GORCH) << 32); 2283 adapter->stats.gotc += IGC_READ_REG(&adapter->hw, IGC_GOTCL) + 2284 ((u64)IGC_READ_REG(&adapter->hw, IGC_GOTCH) << 32); 2285 2286 adapter->stats.rnbc += IGC_READ_REG(&adapter->hw, IGC_RNBC); 2287 adapter->stats.ruc += IGC_READ_REG(&adapter->hw, IGC_RUC); 2288 adapter->stats.rfc += IGC_READ_REG(&adapter->hw, IGC_RFC); 2289 adapter->stats.roc += IGC_READ_REG(&adapter->hw, IGC_ROC); 2290 adapter->stats.rjc += IGC_READ_REG(&adapter->hw, IGC_RJC); 2291 2292 adapter->stats.tor += IGC_READ_REG(&adapter->hw, IGC_TORH); 2293 adapter->stats.tot += IGC_READ_REG(&adapter->hw, IGC_TOTH); 2294 2295 adapter->stats.tpr += IGC_READ_REG(&adapter->hw, IGC_TPR); 2296 adapter->stats.tpt += IGC_READ_REG(&adapter->hw, IGC_TPT); 2297 adapter->stats.ptc64 += IGC_READ_REG(&adapter->hw, IGC_PTC64); 2298 adapter->stats.ptc127 += IGC_READ_REG(&adapter->hw, IGC_PTC127); 2299 adapter->stats.ptc255 += IGC_READ_REG(&adapter->hw, IGC_PTC255); 2300 adapter->stats.ptc511 += IGC_READ_REG(&adapter->hw, IGC_PTC511); 2301 adapter->stats.ptc1023 += IGC_READ_REG(&adapter->hw, IGC_PTC1023); 2302 adapter->stats.ptc1522 += IGC_READ_REG(&adapter->hw, IGC_PTC1522); 2303 adapter->stats.mptc += IGC_READ_REG(&adapter->hw, IGC_MPTC); 2304 adapter->stats.bptc += IGC_READ_REG(&adapter->hw, IGC_BPTC); 2305 2306 /* Interrupt Counts */ 2307 adapter->stats.iac += IGC_READ_REG(&adapter->hw, IGC_IAC); 2308 adapter->stats.rxdmtc += IGC_READ_REG(&adapter->hw, IGC_RXDMTC); 2309 2310 adapter->stats.algnerrc += IGC_READ_REG(&adapter->hw, IGC_ALGNERRC); 2311 adapter->stats.tncrs += IGC_READ_REG(&adapter->hw, IGC_TNCRS); 2312 adapter->stats.htdpmc += IGC_READ_REG(&adapter->hw, IGC_HTDPMC); 2313 adapter->stats.tsctc += IGC_READ_REG(&adapter->hw, IGC_TSCTC); 2314 } 2315 2316 static uint64_t 2317 igc_if_get_counter(if_ctx_t ctx, ift_counter cnt) 2318 { 2319 struct igc_adapter *adapter = iflib_get_softc(ctx); 2320 if_t ifp = iflib_get_ifp(ctx); 2321 2322 switch (cnt) { 2323 case IFCOUNTER_COLLISIONS: 2324 return (adapter->stats.colc); 2325 case IFCOUNTER_IERRORS: 2326 return (adapter->dropped_pkts + adapter->stats.rxerrc + 2327 adapter->stats.crcerrs + adapter->stats.algnerrc + 2328 adapter->stats.ruc + adapter->stats.roc + 2329 adapter->stats.mpc + adapter->stats.htdpmc); 2330 case IFCOUNTER_OERRORS: 2331 return (adapter->stats.ecol + adapter->stats.latecol + 2332 adapter->watchdog_events); 2333 default: 2334 return (if_get_counter_default(ifp, cnt)); 2335 } 2336 } 2337 2338 /* igc_if_needs_restart - Tell iflib when the driver needs to be reinitialized 2339 * @ctx: iflib context 2340 * @event: event code to check 2341 * 2342 * Defaults to returning false for unknown events. 2343 * 2344 * @returns true if iflib needs to reinit the interface 2345 */ 2346 static bool 2347 igc_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 2348 { 2349 switch (event) { 2350 case IFLIB_RESTART_VLAN_CONFIG: 2351 default: 2352 return (false); 2353 } 2354 } 2355 2356 /* Export a single 32-bit register via a read-only sysctl. */ 2357 static int 2358 igc_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 2359 { 2360 struct igc_adapter *adapter; 2361 u_int val; 2362 2363 adapter = oidp->oid_arg1; 2364 val = IGC_READ_REG(&adapter->hw, oidp->oid_arg2); 2365 return (sysctl_handle_int(oidp, &val, 0, req)); 2366 } 2367 2368 /* 2369 * Add sysctl variables, one per statistic, to the system. 2370 */ 2371 static void 2372 igc_add_hw_stats(struct igc_adapter *adapter) 2373 { 2374 device_t dev = iflib_get_dev(adapter->ctx); 2375 struct igc_tx_queue *tx_que = adapter->tx_queues; 2376 struct igc_rx_queue *rx_que = adapter->rx_queues; 2377 2378 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 2379 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 2380 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 2381 struct igc_hw_stats *stats = &adapter->stats; 2382 2383 struct sysctl_oid *stat_node, *queue_node, *int_node; 2384 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 2385 2386 #define QUEUE_NAME_LEN 32 2387 char namebuf[QUEUE_NAME_LEN]; 2388 2389 /* Driver Statistics */ 2390 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 2391 CTLFLAG_RD, &adapter->dropped_pkts, 2392 "Driver dropped packets"); 2393 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 2394 CTLFLAG_RD, &adapter->link_irq, 2395 "Link MSI-X IRQ Handled"); 2396 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 2397 CTLFLAG_RD, &adapter->rx_overruns, 2398 "RX overruns"); 2399 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 2400 CTLFLAG_RD, &adapter->watchdog_events, 2401 "Watchdog timeouts"); 2402 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 2403 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 2404 adapter, IGC_CTRL, igc_sysctl_reg_handler, "IU", 2405 "Device Control Register"); 2406 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 2407 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 2408 adapter, IGC_RCTL, igc_sysctl_reg_handler, "IU", 2409 "Receiver Control Register"); 2410 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 2411 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 2412 "Flow Control High Watermark"); 2413 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 2414 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 2415 "Flow Control Low Watermark"); 2416 2417 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 2418 struct tx_ring *txr = &tx_que->txr; 2419 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 2420 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 2421 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 2422 queue_list = SYSCTL_CHILDREN(queue_node); 2423 2424 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 2425 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 2426 IGC_TDH(txr->me), igc_sysctl_reg_handler, "IU", 2427 "Transmit Descriptor Head"); 2428 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 2429 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 2430 IGC_TDT(txr->me), igc_sysctl_reg_handler, "IU", 2431 "Transmit Descriptor Tail"); 2432 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 2433 CTLFLAG_RD, &txr->tx_irq, 2434 "Queue MSI-X Transmit Interrupts"); 2435 } 2436 2437 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 2438 struct rx_ring *rxr = &rx_que->rxr; 2439 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 2440 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 2441 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 2442 queue_list = SYSCTL_CHILDREN(queue_node); 2443 2444 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 2445 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 2446 IGC_RDH(rxr->me), igc_sysctl_reg_handler, "IU", 2447 "Receive Descriptor Head"); 2448 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 2449 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 2450 IGC_RDT(rxr->me), igc_sysctl_reg_handler, "IU", 2451 "Receive Descriptor Tail"); 2452 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 2453 CTLFLAG_RD, &rxr->rx_irq, 2454 "Queue MSI-X Receive Interrupts"); 2455 } 2456 2457 /* MAC stats get their own sub node */ 2458 2459 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 2460 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 2461 stat_list = SYSCTL_CHILDREN(stat_node); 2462 2463 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 2464 CTLFLAG_RD, &stats->ecol, 2465 "Excessive collisions"); 2466 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 2467 CTLFLAG_RD, &stats->scc, 2468 "Single collisions"); 2469 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 2470 CTLFLAG_RD, &stats->mcc, 2471 "Multiple collisions"); 2472 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 2473 CTLFLAG_RD, &stats->latecol, 2474 "Late collisions"); 2475 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 2476 CTLFLAG_RD, &stats->colc, 2477 "Collision Count"); 2478 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 2479 CTLFLAG_RD, &adapter->stats.symerrs, 2480 "Symbol Errors"); 2481 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 2482 CTLFLAG_RD, &adapter->stats.sec, 2483 "Sequence Errors"); 2484 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 2485 CTLFLAG_RD, &adapter->stats.dc, 2486 "Defer Count"); 2487 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 2488 CTLFLAG_RD, &adapter->stats.mpc, 2489 "Missed Packets"); 2490 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 2491 CTLFLAG_RD, &adapter->stats.rnbc, 2492 "Receive No Buffers"); 2493 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 2494 CTLFLAG_RD, &adapter->stats.ruc, 2495 "Receive Undersize"); 2496 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 2497 CTLFLAG_RD, &adapter->stats.rfc, 2498 "Fragmented Packets Received "); 2499 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 2500 CTLFLAG_RD, &adapter->stats.roc, 2501 "Oversized Packets Received"); 2502 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 2503 CTLFLAG_RD, &adapter->stats.rjc, 2504 "Recevied Jabber"); 2505 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 2506 CTLFLAG_RD, &adapter->stats.rxerrc, 2507 "Receive Errors"); 2508 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 2509 CTLFLAG_RD, &adapter->stats.crcerrs, 2510 "CRC errors"); 2511 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 2512 CTLFLAG_RD, &adapter->stats.algnerrc, 2513 "Alignment Errors"); 2514 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 2515 CTLFLAG_RD, &adapter->stats.xonrxc, 2516 "XON Received"); 2517 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 2518 CTLFLAG_RD, &adapter->stats.xontxc, 2519 "XON Transmitted"); 2520 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 2521 CTLFLAG_RD, &adapter->stats.xoffrxc, 2522 "XOFF Received"); 2523 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 2524 CTLFLAG_RD, &adapter->stats.xofftxc, 2525 "XOFF Transmitted"); 2526 2527 /* Packet Reception Stats */ 2528 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 2529 CTLFLAG_RD, &adapter->stats.tpr, 2530 "Total Packets Received "); 2531 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 2532 CTLFLAG_RD, &adapter->stats.gprc, 2533 "Good Packets Received"); 2534 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 2535 CTLFLAG_RD, &adapter->stats.bprc, 2536 "Broadcast Packets Received"); 2537 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 2538 CTLFLAG_RD, &adapter->stats.mprc, 2539 "Multicast Packets Received"); 2540 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 2541 CTLFLAG_RD, &adapter->stats.prc64, 2542 "64 byte frames received "); 2543 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 2544 CTLFLAG_RD, &adapter->stats.prc127, 2545 "65-127 byte frames received"); 2546 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 2547 CTLFLAG_RD, &adapter->stats.prc255, 2548 "128-255 byte frames received"); 2549 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 2550 CTLFLAG_RD, &adapter->stats.prc511, 2551 "256-511 byte frames received"); 2552 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 2553 CTLFLAG_RD, &adapter->stats.prc1023, 2554 "512-1023 byte frames received"); 2555 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 2556 CTLFLAG_RD, &adapter->stats.prc1522, 2557 "1023-1522 byte frames received"); 2558 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 2559 CTLFLAG_RD, &adapter->stats.gorc, 2560 "Good Octets Received"); 2561 2562 /* Packet Transmission Stats */ 2563 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 2564 CTLFLAG_RD, &adapter->stats.gotc, 2565 "Good Octets Transmitted"); 2566 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 2567 CTLFLAG_RD, &adapter->stats.tpt, 2568 "Total Packets Transmitted"); 2569 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 2570 CTLFLAG_RD, &adapter->stats.gptc, 2571 "Good Packets Transmitted"); 2572 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 2573 CTLFLAG_RD, &adapter->stats.bptc, 2574 "Broadcast Packets Transmitted"); 2575 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 2576 CTLFLAG_RD, &adapter->stats.mptc, 2577 "Multicast Packets Transmitted"); 2578 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 2579 CTLFLAG_RD, &adapter->stats.ptc64, 2580 "64 byte frames transmitted "); 2581 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 2582 CTLFLAG_RD, &adapter->stats.ptc127, 2583 "65-127 byte frames transmitted"); 2584 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 2585 CTLFLAG_RD, &adapter->stats.ptc255, 2586 "128-255 byte frames transmitted"); 2587 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 2588 CTLFLAG_RD, &adapter->stats.ptc511, 2589 "256-511 byte frames transmitted"); 2590 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 2591 CTLFLAG_RD, &adapter->stats.ptc1023, 2592 "512-1023 byte frames transmitted"); 2593 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 2594 CTLFLAG_RD, &adapter->stats.ptc1522, 2595 "1024-1522 byte frames transmitted"); 2596 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 2597 CTLFLAG_RD, &adapter->stats.tsctc, 2598 "TSO Contexts Transmitted"); 2599 2600 /* Interrupt Stats */ 2601 2602 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 2603 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 2604 int_list = SYSCTL_CHILDREN(int_node); 2605 2606 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 2607 CTLFLAG_RD, &adapter->stats.iac, 2608 "Interrupt Assertion Count"); 2609 2610 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 2611 CTLFLAG_RD, &adapter->stats.rxdmtc, 2612 "Rx Desc Min Thresh Count"); 2613 } 2614 2615 /********************************************************************** 2616 * 2617 * This routine provides a way to dump out the adapter eeprom, 2618 * often a useful debug/service tool. This only dumps the first 2619 * 32 words, stuff that matters is in that extent. 2620 * 2621 **********************************************************************/ 2622 static int 2623 igc_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 2624 { 2625 struct igc_adapter *adapter = (struct igc_adapter *)arg1; 2626 int error; 2627 int result; 2628 2629 result = -1; 2630 error = sysctl_handle_int(oidp, &result, 0, req); 2631 2632 if (error || !req->newptr) 2633 return (error); 2634 2635 /* 2636 * This value will cause a hex dump of the 2637 * first 32 16-bit words of the EEPROM to 2638 * the screen. 2639 */ 2640 if (result == 1) 2641 igc_print_nvm_info(adapter); 2642 2643 return (error); 2644 } 2645 2646 static void 2647 igc_print_nvm_info(struct igc_adapter *adapter) 2648 { 2649 u16 eeprom_data; 2650 int i, j, row = 0; 2651 2652 /* Its a bit crude, but it gets the job done */ 2653 printf("\nInterface EEPROM Dump:\n"); 2654 printf("Offset\n0x0000 "); 2655 for (i = 0, j = 0; i < 32; i++, j++) { 2656 if (j == 8) { /* Make the offset block */ 2657 j = 0; ++row; 2658 printf("\n0x00%x0 ",row); 2659 } 2660 igc_read_nvm(&adapter->hw, i, 1, &eeprom_data); 2661 printf("%04x ", eeprom_data); 2662 } 2663 printf("\n"); 2664 } 2665 2666 /* 2667 * Set flow control using sysctl: 2668 * Flow control values: 2669 * 0 - off 2670 * 1 - rx pause 2671 * 2 - tx pause 2672 * 3 - full 2673 */ 2674 static int 2675 igc_set_flowcntl(SYSCTL_HANDLER_ARGS) 2676 { 2677 int error; 2678 static int input = 3; /* default is full */ 2679 struct igc_adapter *adapter = (struct igc_adapter *) arg1; 2680 2681 error = sysctl_handle_int(oidp, &input, 0, req); 2682 2683 if ((error) || (req->newptr == NULL)) 2684 return (error); 2685 2686 if (input == adapter->fc) /* no change? */ 2687 return (error); 2688 2689 switch (input) { 2690 case igc_fc_rx_pause: 2691 case igc_fc_tx_pause: 2692 case igc_fc_full: 2693 case igc_fc_none: 2694 adapter->hw.fc.requested_mode = input; 2695 adapter->fc = input; 2696 break; 2697 default: 2698 /* Do nothing */ 2699 return (error); 2700 } 2701 2702 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 2703 igc_force_mac_fc(&adapter->hw); 2704 return (error); 2705 } 2706 2707 /* 2708 * Manage Energy Efficient Ethernet: 2709 * Control values: 2710 * 0/1 - enabled/disabled 2711 */ 2712 static int 2713 igc_sysctl_eee(SYSCTL_HANDLER_ARGS) 2714 { 2715 struct igc_adapter *adapter = (struct igc_adapter *) arg1; 2716 int error, value; 2717 2718 value = adapter->hw.dev_spec._i225.eee_disable; 2719 error = sysctl_handle_int(oidp, &value, 0, req); 2720 if (error || req->newptr == NULL) 2721 return (error); 2722 2723 adapter->hw.dev_spec._i225.eee_disable = (value != 0); 2724 igc_if_init(adapter->ctx); 2725 2726 return (0); 2727 } 2728 2729 static int 2730 igc_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 2731 { 2732 struct igc_adapter *adapter; 2733 int error; 2734 int result; 2735 2736 result = -1; 2737 error = sysctl_handle_int(oidp, &result, 0, req); 2738 2739 if (error || !req->newptr) 2740 return (error); 2741 2742 if (result == 1) { 2743 adapter = (struct igc_adapter *) arg1; 2744 igc_print_debug_info(adapter); 2745 } 2746 2747 return (error); 2748 } 2749 2750 static int 2751 igc_get_rs(SYSCTL_HANDLER_ARGS) 2752 { 2753 struct igc_adapter *adapter = (struct igc_adapter *) arg1; 2754 int error; 2755 int result; 2756 2757 result = 0; 2758 error = sysctl_handle_int(oidp, &result, 0, req); 2759 2760 if (error || !req->newptr || result != 1) 2761 return (error); 2762 igc_dump_rs(adapter); 2763 2764 return (error); 2765 } 2766 2767 static void 2768 igc_if_debug(if_ctx_t ctx) 2769 { 2770 igc_dump_rs(iflib_get_softc(ctx)); 2771 } 2772 2773 /* 2774 * This routine is meant to be fluid, add whatever is 2775 * needed for debugging a problem. -jfv 2776 */ 2777 static void 2778 igc_print_debug_info(struct igc_adapter *adapter) 2779 { 2780 device_t dev = iflib_get_dev(adapter->ctx); 2781 if_t ifp = iflib_get_ifp(adapter->ctx); 2782 struct tx_ring *txr = &adapter->tx_queues->txr; 2783 struct rx_ring *rxr = &adapter->rx_queues->rxr; 2784 2785 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2786 printf("Interface is RUNNING "); 2787 else 2788 printf("Interface is NOT RUNNING\n"); 2789 2790 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 2791 printf("and INACTIVE\n"); 2792 else 2793 printf("and ACTIVE\n"); 2794 2795 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 2796 device_printf(dev, "TX Queue %d ------\n", i); 2797 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 2798 IGC_READ_REG(&adapter->hw, IGC_TDH(i)), 2799 IGC_READ_REG(&adapter->hw, IGC_TDT(i))); 2800 2801 } 2802 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 2803 device_printf(dev, "RX Queue %d ------\n", j); 2804 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 2805 IGC_READ_REG(&adapter->hw, IGC_RDH(j)), 2806 IGC_READ_REG(&adapter->hw, IGC_RDT(j))); 2807 } 2808 } 2809