1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * Copyright (c) 2021 Rubicon Communications, LLC (Netgate) 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 #include "if_igc.h" 32 #include <sys/sbuf.h> 33 #include <machine/_inttypes.h> 34 35 #ifdef RSS 36 #include <net/rss_config.h> 37 #include <netinet/in_rss.h> 38 #endif 39 40 /********************************************************************* 41 * PCI Device ID Table 42 * 43 * Used by probe to select devices to load on 44 * Last entry must be all 0s 45 * 46 * { Vendor ID, Device ID, String } 47 *********************************************************************/ 48 49 static const pci_vendor_info_t igc_vendor_info_array[] = 50 { 51 /* Intel(R) PRO/1000 Network Connection - igc */ 52 PVID(0x8086, IGC_DEV_ID_I225_LM, "Intel(R) Ethernet Controller I225-LM"), 53 PVID(0x8086, IGC_DEV_ID_I225_V, "Intel(R) Ethernet Controller I225-V"), 54 PVID(0x8086, IGC_DEV_ID_I225_K, "Intel(R) Ethernet Controller I225-K"), 55 PVID(0x8086, IGC_DEV_ID_I225_I, "Intel(R) Ethernet Controller I225-I"), 56 PVID(0x8086, IGC_DEV_ID_I220_V, "Intel(R) Ethernet Controller I220-V"), 57 PVID(0x8086, IGC_DEV_ID_I225_K2, "Intel(R) Ethernet Controller I225-K(2)"), 58 PVID(0x8086, IGC_DEV_ID_I225_LMVP, "Intel(R) Ethernet Controller I225-LMvP(2)"), 59 PVID(0x8086, IGC_DEV_ID_I226_K, "Intel(R) Ethernet Controller I226-K"), 60 PVID(0x8086, IGC_DEV_ID_I226_LMVP, "Intel(R) Ethernet Controller I226-LMvP"), 61 PVID(0x8086, IGC_DEV_ID_I225_IT, "Intel(R) Ethernet Controller I225-IT(2)"), 62 PVID(0x8086, IGC_DEV_ID_I226_LM, "Intel(R) Ethernet Controller I226-LM"), 63 PVID(0x8086, IGC_DEV_ID_I226_V, "Intel(R) Ethernet Controller I226-V"), 64 PVID(0x8086, IGC_DEV_ID_I226_IT, "Intel(R) Ethernet Controller I226-IT"), 65 PVID(0x8086, IGC_DEV_ID_I221_V, "Intel(R) Ethernet Controller I221-V"), 66 PVID(0x8086, IGC_DEV_ID_I226_BLANK_NVM, "Intel(R) Ethernet Controller I226(blankNVM)"), 67 PVID(0x8086, IGC_DEV_ID_I225_BLANK_NVM, "Intel(R) Ethernet Controller I225(blankNVM)"), 68 /* required last entry */ 69 PVID_END 70 }; 71 72 /********************************************************************* 73 * Function prototypes 74 *********************************************************************/ 75 static void *igc_register(device_t dev); 76 static int igc_if_attach_pre(if_ctx_t ctx); 77 static int igc_if_attach_post(if_ctx_t ctx); 78 static int igc_if_detach(if_ctx_t ctx); 79 static int igc_if_shutdown(if_ctx_t ctx); 80 static int igc_if_suspend(if_ctx_t ctx); 81 static int igc_if_resume(if_ctx_t ctx); 82 83 static int igc_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 84 static int igc_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 85 static void igc_if_queues_free(if_ctx_t ctx); 86 87 static uint64_t igc_if_get_counter(if_ctx_t, ift_counter); 88 static void igc_if_init(if_ctx_t ctx); 89 static void igc_if_stop(if_ctx_t ctx); 90 static void igc_if_media_status(if_ctx_t, struct ifmediareq *); 91 static int igc_if_media_change(if_ctx_t ctx); 92 static int igc_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 93 static void igc_if_timer(if_ctx_t ctx, uint16_t qid); 94 static void igc_if_watchdog_reset(if_ctx_t ctx); 95 static bool igc_if_needs_restart(if_ctx_t ctx, enum iflib_restart_event event); 96 97 static void igc_identify_hardware(if_ctx_t ctx); 98 static int igc_allocate_pci_resources(if_ctx_t ctx); 99 static void igc_free_pci_resources(if_ctx_t ctx); 100 static void igc_reset(if_ctx_t ctx); 101 static int igc_setup_interface(if_ctx_t ctx); 102 static int igc_setup_msix(if_ctx_t ctx); 103 104 static void igc_initialize_transmit_unit(if_ctx_t ctx); 105 static void igc_initialize_receive_unit(if_ctx_t ctx); 106 107 static void igc_if_intr_enable(if_ctx_t ctx); 108 static void igc_if_intr_disable(if_ctx_t ctx); 109 static int igc_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 110 static int igc_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 111 static void igc_if_multi_set(if_ctx_t ctx); 112 static void igc_if_update_admin_status(if_ctx_t ctx); 113 static void igc_if_debug(if_ctx_t ctx); 114 static void igc_update_stats_counters(struct igc_adapter *); 115 static void igc_add_hw_stats(struct igc_adapter *adapter); 116 static int igc_if_set_promisc(if_ctx_t ctx, int flags); 117 static void igc_setup_vlan_hw_support(if_ctx_t ctx); 118 static void igc_fw_version(struct igc_adapter *); 119 static void igc_sbuf_fw_version(struct igc_fw_version *, struct sbuf *); 120 static void igc_print_fw_version(struct igc_adapter *); 121 static int igc_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 122 static int igc_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 123 static void igc_print_nvm_info(struct igc_adapter *); 124 static int igc_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 125 static int igc_get_rs(SYSCTL_HANDLER_ARGS); 126 static void igc_print_debug_info(struct igc_adapter *); 127 static int igc_is_valid_ether_addr(u8 *); 128 /* Management and WOL Support */ 129 static void igc_get_hw_control(struct igc_adapter *); 130 static void igc_release_hw_control(struct igc_adapter *); 131 static void igc_get_wakeup(if_ctx_t ctx); 132 static void igc_enable_wakeup(if_ctx_t ctx); 133 134 int igc_intr(void *arg); 135 136 /* MSI-X handlers */ 137 static int igc_if_msix_intr_assign(if_ctx_t, int); 138 static int igc_msix_link(void *); 139 static void igc_handle_link(void *context); 140 141 static int igc_set_flowcntl(SYSCTL_HANDLER_ARGS); 142 static int igc_sysctl_eee(SYSCTL_HANDLER_ARGS); 143 144 static int igc_get_regs(SYSCTL_HANDLER_ARGS); 145 146 static void igc_configure_queues(struct igc_adapter *adapter); 147 148 149 /********************************************************************* 150 * FreeBSD Device Interface Entry Points 151 *********************************************************************/ 152 static device_method_t igc_methods[] = { 153 /* Device interface */ 154 DEVMETHOD(device_register, igc_register), 155 DEVMETHOD(device_probe, iflib_device_probe), 156 DEVMETHOD(device_attach, iflib_device_attach), 157 DEVMETHOD(device_detach, iflib_device_detach), 158 DEVMETHOD(device_shutdown, iflib_device_shutdown), 159 DEVMETHOD(device_suspend, iflib_device_suspend), 160 DEVMETHOD(device_resume, iflib_device_resume), 161 DEVMETHOD_END 162 }; 163 164 static driver_t igc_driver = { 165 "igc", igc_methods, sizeof(struct igc_adapter), 166 }; 167 168 DRIVER_MODULE(igc, pci, igc_driver, 0, 0); 169 170 MODULE_DEPEND(igc, pci, 1, 1, 1); 171 MODULE_DEPEND(igc, ether, 1, 1, 1); 172 MODULE_DEPEND(igc, iflib, 1, 1, 1); 173 174 IFLIB_PNP_INFO(pci, igc, igc_vendor_info_array); 175 176 static device_method_t igc_if_methods[] = { 177 DEVMETHOD(ifdi_attach_pre, igc_if_attach_pre), 178 DEVMETHOD(ifdi_attach_post, igc_if_attach_post), 179 DEVMETHOD(ifdi_detach, igc_if_detach), 180 DEVMETHOD(ifdi_shutdown, igc_if_shutdown), 181 DEVMETHOD(ifdi_suspend, igc_if_suspend), 182 DEVMETHOD(ifdi_resume, igc_if_resume), 183 DEVMETHOD(ifdi_init, igc_if_init), 184 DEVMETHOD(ifdi_stop, igc_if_stop), 185 DEVMETHOD(ifdi_msix_intr_assign, igc_if_msix_intr_assign), 186 DEVMETHOD(ifdi_intr_enable, igc_if_intr_enable), 187 DEVMETHOD(ifdi_intr_disable, igc_if_intr_disable), 188 DEVMETHOD(ifdi_tx_queues_alloc, igc_if_tx_queues_alloc), 189 DEVMETHOD(ifdi_rx_queues_alloc, igc_if_rx_queues_alloc), 190 DEVMETHOD(ifdi_queues_free, igc_if_queues_free), 191 DEVMETHOD(ifdi_update_admin_status, igc_if_update_admin_status), 192 DEVMETHOD(ifdi_multi_set, igc_if_multi_set), 193 DEVMETHOD(ifdi_media_status, igc_if_media_status), 194 DEVMETHOD(ifdi_media_change, igc_if_media_change), 195 DEVMETHOD(ifdi_mtu_set, igc_if_mtu_set), 196 DEVMETHOD(ifdi_promisc_set, igc_if_set_promisc), 197 DEVMETHOD(ifdi_timer, igc_if_timer), 198 DEVMETHOD(ifdi_watchdog_reset, igc_if_watchdog_reset), 199 DEVMETHOD(ifdi_get_counter, igc_if_get_counter), 200 DEVMETHOD(ifdi_rx_queue_intr_enable, igc_if_rx_queue_intr_enable), 201 DEVMETHOD(ifdi_tx_queue_intr_enable, igc_if_tx_queue_intr_enable), 202 DEVMETHOD(ifdi_debug, igc_if_debug), 203 DEVMETHOD(ifdi_needs_restart, igc_if_needs_restart), 204 DEVMETHOD_END 205 }; 206 207 static driver_t igc_if_driver = { 208 "igc_if", igc_if_methods, sizeof(struct igc_adapter) 209 }; 210 211 /********************************************************************* 212 * Tunable default values. 213 *********************************************************************/ 214 215 /* Allow common code without TSO */ 216 #ifndef CSUM_TSO 217 #define CSUM_TSO 0 218 #endif 219 220 static SYSCTL_NODE(_hw, OID_AUTO, igc, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 221 "igc driver parameters"); 222 223 static int igc_disable_crc_stripping = 0; 224 SYSCTL_INT(_hw_igc, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 225 &igc_disable_crc_stripping, 0, "Disable CRC Stripping"); 226 227 static int igc_smart_pwr_down = false; 228 SYSCTL_INT(_hw_igc, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &igc_smart_pwr_down, 229 0, "Set to true to leave smart power down enabled on newer adapters"); 230 231 /* Controls whether promiscuous also shows bad packets */ 232 static int igc_debug_sbp = true; 233 SYSCTL_INT(_hw_igc, OID_AUTO, sbp, CTLFLAG_RDTUN, &igc_debug_sbp, 0, 234 "Show bad packets in promiscuous mode"); 235 236 /* Energy efficient ethernet - default to OFF */ 237 static int igc_eee_setting = 1; 238 SYSCTL_INT(_hw_igc, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &igc_eee_setting, 0, 239 "Enable Energy Efficient Ethernet"); 240 241 /* 242 ** Tuneable Interrupt rate 243 */ 244 static int igc_max_interrupt_rate = 20000; 245 SYSCTL_INT(_hw_igc, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 246 &igc_max_interrupt_rate, 0, "Maximum interrupts per second"); 247 248 extern struct if_txrx igc_txrx; 249 250 static struct if_shared_ctx igc_sctx_init = { 251 .isc_magic = IFLIB_MAGIC, 252 .isc_q_align = PAGE_SIZE, 253 .isc_tx_maxsize = IGC_TSO_SIZE + sizeof(struct ether_vlan_header), 254 .isc_tx_maxsegsize = PAGE_SIZE, 255 .isc_tso_maxsize = IGC_TSO_SIZE + sizeof(struct ether_vlan_header), 256 .isc_tso_maxsegsize = IGC_TSO_SEG_SIZE, 257 .isc_rx_maxsize = MAX_JUMBO_FRAME_SIZE, 258 .isc_rx_nsegments = 1, 259 .isc_rx_maxsegsize = MJUM9BYTES, 260 .isc_nfl = 1, 261 .isc_nrxqs = 1, 262 .isc_ntxqs = 1, 263 .isc_admin_intrcnt = 1, 264 .isc_vendor_info = igc_vendor_info_array, 265 .isc_driver_version = "1", 266 .isc_driver = &igc_if_driver, 267 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 268 269 .isc_nrxd_min = {IGC_MIN_RXD}, 270 .isc_ntxd_min = {IGC_MIN_TXD}, 271 .isc_nrxd_max = {IGC_MAX_RXD}, 272 .isc_ntxd_max = {IGC_MAX_TXD}, 273 .isc_nrxd_default = {IGC_DEFAULT_RXD}, 274 .isc_ntxd_default = {IGC_DEFAULT_TXD}, 275 }; 276 277 /***************************************************************** 278 * 279 * Dump Registers 280 * 281 ****************************************************************/ 282 #define IGC_REGS_LEN 739 283 284 static int igc_get_regs(SYSCTL_HANDLER_ARGS) 285 { 286 struct igc_adapter *adapter = (struct igc_adapter *)arg1; 287 struct igc_hw *hw = &adapter->hw; 288 struct sbuf *sb; 289 u32 *regs_buff; 290 int rc; 291 292 regs_buff = malloc(sizeof(u32) * IGC_REGS_LEN, M_DEVBUF, M_WAITOK); 293 memset(regs_buff, 0, IGC_REGS_LEN * sizeof(u32)); 294 295 rc = sysctl_wire_old_buffer(req, 0); 296 MPASS(rc == 0); 297 if (rc != 0) { 298 free(regs_buff, M_DEVBUF); 299 return (rc); 300 } 301 302 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 303 MPASS(sb != NULL); 304 if (sb == NULL) { 305 free(regs_buff, M_DEVBUF); 306 return (ENOMEM); 307 } 308 309 /* General Registers */ 310 regs_buff[0] = IGC_READ_REG(hw, IGC_CTRL); 311 regs_buff[1] = IGC_READ_REG(hw, IGC_STATUS); 312 regs_buff[2] = IGC_READ_REG(hw, IGC_CTRL_EXT); 313 regs_buff[3] = IGC_READ_REG(hw, IGC_ICR); 314 regs_buff[4] = IGC_READ_REG(hw, IGC_RCTL); 315 regs_buff[5] = IGC_READ_REG(hw, IGC_RDLEN(0)); 316 regs_buff[6] = IGC_READ_REG(hw, IGC_RDH(0)); 317 regs_buff[7] = IGC_READ_REG(hw, IGC_RDT(0)); 318 regs_buff[8] = IGC_READ_REG(hw, IGC_RXDCTL(0)); 319 regs_buff[9] = IGC_READ_REG(hw, IGC_RDBAL(0)); 320 regs_buff[10] = IGC_READ_REG(hw, IGC_RDBAH(0)); 321 regs_buff[11] = IGC_READ_REG(hw, IGC_TCTL); 322 regs_buff[12] = IGC_READ_REG(hw, IGC_TDBAL(0)); 323 regs_buff[13] = IGC_READ_REG(hw, IGC_TDBAH(0)); 324 regs_buff[14] = IGC_READ_REG(hw, IGC_TDLEN(0)); 325 regs_buff[15] = IGC_READ_REG(hw, IGC_TDH(0)); 326 regs_buff[16] = IGC_READ_REG(hw, IGC_TDT(0)); 327 regs_buff[17] = IGC_READ_REG(hw, IGC_TXDCTL(0)); 328 329 sbuf_printf(sb, "General Registers\n"); 330 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 331 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 332 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 333 334 sbuf_printf(sb, "Interrupt Registers\n"); 335 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 336 337 sbuf_printf(sb, "RX Registers\n"); 338 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 339 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 340 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 341 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 342 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 343 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 344 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 345 346 sbuf_printf(sb, "TX Registers\n"); 347 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 348 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 349 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 350 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 351 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 352 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 353 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 354 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 355 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 356 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 357 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 358 359 free(regs_buff, M_DEVBUF); 360 361 #ifdef DUMP_DESCS 362 { 363 if_softc_ctx_t scctx = adapter->shared; 364 struct rx_ring *rxr = &rx_que->rxr; 365 struct tx_ring *txr = &tx_que->txr; 366 int ntxd = scctx->isc_ntxd[0]; 367 int nrxd = scctx->isc_nrxd[0]; 368 int j; 369 370 for (j = 0; j < nrxd; j++) { 371 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 372 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 373 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 374 } 375 376 for (j = 0; j < min(ntxd, 256); j++) { 377 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 378 379 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 380 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 381 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & IGC_TXD_STAT_DD : 0); 382 383 } 384 } 385 #endif 386 387 rc = sbuf_finish(sb); 388 sbuf_delete(sb); 389 return(rc); 390 } 391 392 static void * 393 igc_register(device_t dev) 394 { 395 return (&igc_sctx_init); 396 } 397 398 static int 399 igc_set_num_queues(if_ctx_t ctx) 400 { 401 int maxqueues; 402 403 maxqueues = 4; 404 405 return (maxqueues); 406 } 407 408 #define IGC_CAPS \ 409 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 410 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_TSO4 | IFCAP_LRO | \ 411 IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | IFCAP_TSO6 412 413 /********************************************************************* 414 * Device initialization routine 415 * 416 * The attach entry point is called when the driver is being loaded. 417 * This routine identifies the type of hardware, allocates all resources 418 * and initializes the hardware. 419 * 420 * return 0 on success, positive on failure 421 *********************************************************************/ 422 static int 423 igc_if_attach_pre(if_ctx_t ctx) 424 { 425 struct igc_adapter *adapter; 426 if_softc_ctx_t scctx; 427 device_t dev; 428 struct igc_hw *hw; 429 int error = 0; 430 431 INIT_DEBUGOUT("igc_if_attach_pre: begin"); 432 dev = iflib_get_dev(ctx); 433 adapter = iflib_get_softc(ctx); 434 435 adapter->ctx = adapter->osdep.ctx = ctx; 436 adapter->dev = adapter->osdep.dev = dev; 437 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 438 adapter->media = iflib_get_media(ctx); 439 hw = &adapter->hw; 440 441 /* SYSCTL stuff */ 442 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 443 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 444 OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 445 adapter, 0, igc_sysctl_nvm_info, "I", "NVM Information"); 446 447 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 448 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 449 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, 450 adapter, 0, igc_sysctl_print_fw_version, "A", 451 "Prints FW/NVM Versions"); 452 453 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 454 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 455 OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 456 adapter, 0, igc_sysctl_debug_info, "I", "Debug Information"); 457 458 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 459 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 460 OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 461 adapter, 0, igc_set_flowcntl, "I", "Flow Control"); 462 463 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 464 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 465 OID_AUTO, "reg_dump", 466 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 0, 467 igc_get_regs, "A", "Dump Registers"); 468 469 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 470 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 471 OID_AUTO, "rs_dump", 472 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, adapter, 0, 473 igc_get_rs, "I", "Dump RS indexes"); 474 475 /* Determine hardware and mac info */ 476 igc_identify_hardware(ctx); 477 478 scctx->isc_tx_nsegments = IGC_MAX_SCATTER; 479 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = igc_set_num_queues(ctx); 480 if (bootverbose) 481 device_printf(dev, "attach_pre capping queues at %d\n", 482 scctx->isc_ntxqsets_max); 483 484 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union igc_adv_tx_desc), IGC_DBA_ALIGN); 485 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union igc_adv_rx_desc), IGC_DBA_ALIGN); 486 scctx->isc_txd_size[0] = sizeof(union igc_adv_tx_desc); 487 scctx->isc_rxd_size[0] = sizeof(union igc_adv_rx_desc); 488 scctx->isc_txrx = &igc_txrx; 489 scctx->isc_tx_tso_segments_max = IGC_MAX_SCATTER; 490 scctx->isc_tx_tso_size_max = IGC_TSO_SIZE; 491 scctx->isc_tx_tso_segsize_max = IGC_TSO_SEG_SIZE; 492 scctx->isc_capabilities = scctx->isc_capenable = IGC_CAPS; 493 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 494 CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_SCTP | CSUM_IP6_SCTP; 495 496 /* 497 ** Some new devices, as with ixgbe, now may 498 ** use a different BAR, so we need to keep 499 ** track of which is used. 500 */ 501 scctx->isc_msix_bar = PCIR_BAR(IGC_MSIX_BAR); 502 if (pci_read_config(dev, scctx->isc_msix_bar, 4) == 0) 503 scctx->isc_msix_bar += 4; 504 505 /* Setup PCI resources */ 506 if (igc_allocate_pci_resources(ctx)) { 507 device_printf(dev, "Allocation of PCI resources failed\n"); 508 error = ENXIO; 509 goto err_pci; 510 } 511 512 /* Do Shared Code initialization */ 513 error = igc_setup_init_funcs(hw, true); 514 if (error) { 515 device_printf(dev, "Setup of Shared code failed, error %d\n", 516 error); 517 error = ENXIO; 518 goto err_pci; 519 } 520 521 igc_setup_msix(ctx); 522 igc_get_bus_info(hw); 523 524 hw->mac.autoneg = DO_AUTO_NEG; 525 hw->phy.autoneg_wait_to_complete = false; 526 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 527 528 /* Copper options */ 529 if (hw->phy.media_type == igc_media_type_copper) { 530 hw->phy.mdix = AUTO_ALL_MODES; 531 } 532 533 /* 534 * Set the frame limits assuming 535 * standard ethernet sized frames. 536 */ 537 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 538 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 539 540 /* Allocate multicast array memory. */ 541 adapter->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 542 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 543 if (adapter->mta == NULL) { 544 device_printf(dev, "Can not allocate multicast setup array\n"); 545 error = ENOMEM; 546 goto err_late; 547 } 548 549 /* Check SOL/IDER usage */ 550 if (igc_check_reset_block(hw)) 551 device_printf(dev, "PHY reset is blocked" 552 " due to SOL/IDER session.\n"); 553 554 /* Sysctl for setting Energy Efficient Ethernet */ 555 adapter->hw.dev_spec._i225.eee_disable = igc_eee_setting; 556 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 557 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 558 OID_AUTO, "eee_control", 559 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 560 adapter, 0, igc_sysctl_eee, "I", 561 "Disable Energy Efficient Ethernet"); 562 563 /* 564 ** Start from a known state, this is 565 ** important in reading the nvm and 566 ** mac from that. 567 */ 568 igc_reset_hw(hw); 569 570 /* Make sure we have a good EEPROM before we read from it */ 571 if (igc_validate_nvm_checksum(hw) < 0) { 572 /* 573 ** Some PCI-E parts fail the first check due to 574 ** the link being in sleep state, call it again, 575 ** if it fails a second time its a real issue. 576 */ 577 if (igc_validate_nvm_checksum(hw) < 0) { 578 device_printf(dev, 579 "The EEPROM Checksum Is Not Valid\n"); 580 error = EIO; 581 goto err_late; 582 } 583 } 584 585 /* Copy the permanent MAC address out of the EEPROM */ 586 if (igc_read_mac_addr(hw) < 0) { 587 device_printf(dev, "EEPROM read error while reading MAC" 588 " address\n"); 589 error = EIO; 590 goto err_late; 591 } 592 593 if (!igc_is_valid_ether_addr(hw->mac.addr)) { 594 device_printf(dev, "Invalid MAC address\n"); 595 error = EIO; 596 goto err_late; 597 } 598 599 /* Save the EEPROM/NVM versions */ 600 igc_fw_version(adapter); 601 602 igc_print_fw_version(adapter); 603 604 /* 605 * Get Wake-on-Lan and Management info for later use 606 */ 607 igc_get_wakeup(ctx); 608 609 /* Enable only WOL MAGIC by default */ 610 scctx->isc_capenable &= ~IFCAP_WOL; 611 if (adapter->wol != 0) 612 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 613 614 iflib_set_mac(ctx, hw->mac.addr); 615 616 return (0); 617 618 err_late: 619 igc_release_hw_control(adapter); 620 err_pci: 621 igc_free_pci_resources(ctx); 622 free(adapter->mta, M_DEVBUF); 623 624 return (error); 625 } 626 627 static int 628 igc_if_attach_post(if_ctx_t ctx) 629 { 630 struct igc_adapter *adapter = iflib_get_softc(ctx); 631 struct igc_hw *hw = &adapter->hw; 632 int error = 0; 633 634 /* Setup OS specific network interface */ 635 error = igc_setup_interface(ctx); 636 if (error != 0) { 637 goto err_late; 638 } 639 640 igc_reset(ctx); 641 642 /* Initialize statistics */ 643 igc_update_stats_counters(adapter); 644 hw->mac.get_link_status = true; 645 igc_if_update_admin_status(ctx); 646 igc_add_hw_stats(adapter); 647 648 /* the driver can now take control from firmware */ 649 igc_get_hw_control(adapter); 650 651 INIT_DEBUGOUT("igc_if_attach_post: end"); 652 653 return (error); 654 655 err_late: 656 igc_release_hw_control(adapter); 657 igc_free_pci_resources(ctx); 658 igc_if_queues_free(ctx); 659 free(adapter->mta, M_DEVBUF); 660 661 return (error); 662 } 663 664 /********************************************************************* 665 * Device removal routine 666 * 667 * The detach entry point is called when the driver is being removed. 668 * This routine stops the adapter and deallocates all the resources 669 * that were allocated for driver operation. 670 * 671 * return 0 on success, positive on failure 672 *********************************************************************/ 673 static int 674 igc_if_detach(if_ctx_t ctx) 675 { 676 struct igc_adapter *adapter = iflib_get_softc(ctx); 677 678 INIT_DEBUGOUT("igc_if_detach: begin"); 679 680 igc_phy_hw_reset(&adapter->hw); 681 682 igc_release_hw_control(adapter); 683 igc_free_pci_resources(ctx); 684 685 return (0); 686 } 687 688 /********************************************************************* 689 * 690 * Shutdown entry point 691 * 692 **********************************************************************/ 693 694 static int 695 igc_if_shutdown(if_ctx_t ctx) 696 { 697 return igc_if_suspend(ctx); 698 } 699 700 /* 701 * Suspend/resume device methods. 702 */ 703 static int 704 igc_if_suspend(if_ctx_t ctx) 705 { 706 struct igc_adapter *adapter = iflib_get_softc(ctx); 707 708 igc_release_hw_control(adapter); 709 igc_enable_wakeup(ctx); 710 return (0); 711 } 712 713 static int 714 igc_if_resume(if_ctx_t ctx) 715 { 716 igc_if_init(ctx); 717 718 return(0); 719 } 720 721 static int 722 igc_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 723 { 724 int max_frame_size; 725 struct igc_adapter *adapter = iflib_get_softc(ctx); 726 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 727 728 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 729 730 /* 9K Jumbo Frame size */ 731 max_frame_size = 9234; 732 733 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 734 return (EINVAL); 735 } 736 737 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 738 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 739 return (0); 740 } 741 742 /********************************************************************* 743 * Init entry point 744 * 745 * This routine is used in two ways. It is used by the stack as 746 * init entry point in network interface structure. It is also used 747 * by the driver as a hw/sw initialization routine to get to a 748 * consistent state. 749 * 750 **********************************************************************/ 751 static void 752 igc_if_init(if_ctx_t ctx) 753 { 754 struct igc_adapter *adapter = iflib_get_softc(ctx); 755 if_softc_ctx_t scctx = adapter->shared; 756 if_t ifp = iflib_get_ifp(ctx); 757 struct igc_tx_queue *tx_que; 758 int i; 759 760 INIT_DEBUGOUT("igc_if_init: begin"); 761 762 /* Get the latest mac address, User can use a LAA */ 763 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 764 ETHER_ADDR_LEN); 765 766 /* Put the address into the Receive Address Array */ 767 igc_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 768 769 /* Initialize the hardware */ 770 igc_reset(ctx); 771 igc_if_update_admin_status(ctx); 772 773 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 774 struct tx_ring *txr = &tx_que->txr; 775 776 txr->tx_rs_cidx = txr->tx_rs_pidx; 777 778 /* Initialize the last processed descriptor to be the end of 779 * the ring, rather than the start, so that we avoid an 780 * off-by-one error when calculating how many descriptors are 781 * done in the credits_update function. 782 */ 783 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 784 } 785 786 /* Setup VLAN support, basic and offload if available */ 787 IGC_WRITE_REG(&adapter->hw, IGC_VET, ETHERTYPE_VLAN); 788 789 /* Prepare transmit descriptors and buffers */ 790 igc_initialize_transmit_unit(ctx); 791 792 /* Setup Multicast table */ 793 igc_if_multi_set(ctx); 794 795 adapter->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 796 igc_initialize_receive_unit(ctx); 797 798 /* Set up VLAN support */ 799 igc_setup_vlan_hw_support(ctx); 800 801 /* Don't lose promiscuous settings */ 802 igc_if_set_promisc(ctx, if_getflags(ifp)); 803 igc_clear_hw_cntrs_base_generic(&adapter->hw); 804 805 if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 806 igc_configure_queues(adapter); 807 808 /* this clears any pending interrupts */ 809 IGC_READ_REG(&adapter->hw, IGC_ICR); 810 IGC_WRITE_REG(&adapter->hw, IGC_ICS, IGC_ICS_LSC); 811 812 /* the driver can now take control from firmware */ 813 igc_get_hw_control(adapter); 814 815 /* Set Energy Efficient Ethernet */ 816 igc_set_eee_i225(&adapter->hw, true, true, true); 817 } 818 819 /********************************************************************* 820 * 821 * Fast Legacy/MSI Combined Interrupt Service routine 822 * 823 *********************************************************************/ 824 int 825 igc_intr(void *arg) 826 { 827 struct igc_adapter *adapter = arg; 828 if_ctx_t ctx = adapter->ctx; 829 u32 reg_icr; 830 831 reg_icr = IGC_READ_REG(&adapter->hw, IGC_ICR); 832 833 /* Hot eject? */ 834 if (reg_icr == 0xffffffff) 835 return FILTER_STRAY; 836 837 /* Definitely not our interrupt. */ 838 if (reg_icr == 0x0) 839 return FILTER_STRAY; 840 841 if ((reg_icr & IGC_ICR_INT_ASSERTED) == 0) 842 return FILTER_STRAY; 843 844 /* 845 * Only MSI-X interrupts have one-shot behavior by taking advantage 846 * of the EIAC register. Thus, explicitly disable interrupts. This 847 * also works around the MSI message reordering errata on certain 848 * systems. 849 */ 850 IFDI_INTR_DISABLE(ctx); 851 852 /* Link status change */ 853 if (reg_icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) 854 igc_handle_link(ctx); 855 856 if (reg_icr & IGC_ICR_RXO) 857 adapter->rx_overruns++; 858 859 return (FILTER_SCHEDULE_THREAD); 860 } 861 862 static int 863 igc_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 864 { 865 struct igc_adapter *adapter = iflib_get_softc(ctx); 866 struct igc_rx_queue *rxq = &adapter->rx_queues[rxqid]; 867 868 IGC_WRITE_REG(&adapter->hw, IGC_EIMS, rxq->eims); 869 return (0); 870 } 871 872 static int 873 igc_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 874 { 875 struct igc_adapter *adapter = iflib_get_softc(ctx); 876 struct igc_tx_queue *txq = &adapter->tx_queues[txqid]; 877 878 IGC_WRITE_REG(&adapter->hw, IGC_EIMS, txq->eims); 879 return (0); 880 } 881 882 /********************************************************************* 883 * 884 * MSI-X RX Interrupt Service routine 885 * 886 **********************************************************************/ 887 static int 888 igc_msix_que(void *arg) 889 { 890 struct igc_rx_queue *que = arg; 891 892 ++que->irqs; 893 894 return (FILTER_SCHEDULE_THREAD); 895 } 896 897 /********************************************************************* 898 * 899 * MSI-X Link Fast Interrupt Service routine 900 * 901 **********************************************************************/ 902 static int 903 igc_msix_link(void *arg) 904 { 905 struct igc_adapter *adapter = arg; 906 u32 reg_icr; 907 908 ++adapter->link_irq; 909 MPASS(adapter->hw.back != NULL); 910 reg_icr = IGC_READ_REG(&adapter->hw, IGC_ICR); 911 912 if (reg_icr & IGC_ICR_RXO) 913 adapter->rx_overruns++; 914 915 if (reg_icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) { 916 igc_handle_link(adapter->ctx); 917 } 918 919 IGC_WRITE_REG(&adapter->hw, IGC_IMS, IGC_IMS_LSC); 920 IGC_WRITE_REG(&adapter->hw, IGC_EIMS, adapter->link_mask); 921 922 return (FILTER_HANDLED); 923 } 924 925 static void 926 igc_handle_link(void *context) 927 { 928 if_ctx_t ctx = context; 929 struct igc_adapter *adapter = iflib_get_softc(ctx); 930 931 adapter->hw.mac.get_link_status = true; 932 iflib_admin_intr_deferred(ctx); 933 } 934 935 /********************************************************************* 936 * 937 * Media Ioctl callback 938 * 939 * This routine is called whenever the user queries the status of 940 * the interface using ifconfig. 941 * 942 **********************************************************************/ 943 static void 944 igc_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 945 { 946 struct igc_adapter *adapter = iflib_get_softc(ctx); 947 948 INIT_DEBUGOUT("igc_if_media_status: begin"); 949 950 iflib_admin_intr_deferred(ctx); 951 952 ifmr->ifm_status = IFM_AVALID; 953 ifmr->ifm_active = IFM_ETHER; 954 955 if (!adapter->link_active) { 956 return; 957 } 958 959 ifmr->ifm_status |= IFM_ACTIVE; 960 961 switch (adapter->link_speed) { 962 case 10: 963 ifmr->ifm_active |= IFM_10_T; 964 break; 965 case 100: 966 ifmr->ifm_active |= IFM_100_TX; 967 break; 968 case 1000: 969 ifmr->ifm_active |= IFM_1000_T; 970 break; 971 case 2500: 972 ifmr->ifm_active |= IFM_2500_T; 973 break; 974 } 975 976 if (adapter->link_duplex == FULL_DUPLEX) 977 ifmr->ifm_active |= IFM_FDX; 978 else 979 ifmr->ifm_active |= IFM_HDX; 980 } 981 982 /********************************************************************* 983 * 984 * Media Ioctl callback 985 * 986 * This routine is called when the user changes speed/duplex using 987 * media/mediopt option with ifconfig. 988 * 989 **********************************************************************/ 990 static int 991 igc_if_media_change(if_ctx_t ctx) 992 { 993 struct igc_adapter *adapter = iflib_get_softc(ctx); 994 struct ifmedia *ifm = iflib_get_media(ctx); 995 996 INIT_DEBUGOUT("igc_if_media_change: begin"); 997 998 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 999 return (EINVAL); 1000 1001 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1002 1003 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1004 case IFM_AUTO: 1005 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1006 break; 1007 case IFM_2500_T: 1008 adapter->hw.phy.autoneg_advertised = ADVERTISE_2500_FULL; 1009 break; 1010 case IFM_1000_T: 1011 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1012 break; 1013 case IFM_100_TX: 1014 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1015 adapter->hw.phy.autoneg_advertised = ADVERTISE_100_FULL; 1016 else 1017 adapter->hw.phy.autoneg_advertised = ADVERTISE_100_HALF; 1018 break; 1019 case IFM_10_T: 1020 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1021 adapter->hw.phy.autoneg_advertised = ADVERTISE_10_FULL; 1022 else 1023 adapter->hw.phy.autoneg_advertised = ADVERTISE_10_HALF; 1024 break; 1025 default: 1026 device_printf(adapter->dev, "Unsupported media type\n"); 1027 } 1028 1029 igc_if_init(ctx); 1030 1031 return (0); 1032 } 1033 1034 static int 1035 igc_if_set_promisc(if_ctx_t ctx, int flags) 1036 { 1037 struct igc_adapter *adapter = iflib_get_softc(ctx); 1038 if_t ifp = iflib_get_ifp(ctx); 1039 u32 reg_rctl; 1040 int mcnt = 0; 1041 1042 reg_rctl = IGC_READ_REG(&adapter->hw, IGC_RCTL); 1043 reg_rctl &= ~(IGC_RCTL_SBP | IGC_RCTL_UPE); 1044 if (flags & IFF_ALLMULTI) 1045 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1046 else 1047 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1048 1049 /* Don't disable if in MAX groups */ 1050 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1051 reg_rctl &= (~IGC_RCTL_MPE); 1052 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, reg_rctl); 1053 1054 if (flags & IFF_PROMISC) { 1055 reg_rctl |= (IGC_RCTL_UPE | IGC_RCTL_MPE); 1056 /* Turn this on if you want to see bad packets */ 1057 if (igc_debug_sbp) 1058 reg_rctl |= IGC_RCTL_SBP; 1059 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, reg_rctl); 1060 } else if (flags & IFF_ALLMULTI) { 1061 reg_rctl |= IGC_RCTL_MPE; 1062 reg_rctl &= ~IGC_RCTL_UPE; 1063 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, reg_rctl); 1064 } 1065 return (0); 1066 } 1067 1068 static u_int 1069 igc_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1070 { 1071 u8 *mta = arg; 1072 1073 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1074 return (0); 1075 1076 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1077 1078 return (1); 1079 } 1080 1081 /********************************************************************* 1082 * Multicast Update 1083 * 1084 * This routine is called whenever multicast address list is updated. 1085 * 1086 **********************************************************************/ 1087 1088 static void 1089 igc_if_multi_set(if_ctx_t ctx) 1090 { 1091 struct igc_adapter *adapter = iflib_get_softc(ctx); 1092 if_t ifp = iflib_get_ifp(ctx); 1093 u8 *mta; /* Multicast array memory */ 1094 u32 reg_rctl = 0; 1095 int mcnt = 0; 1096 1097 IOCTL_DEBUGOUT("igc_set_multi: begin"); 1098 1099 mta = adapter->mta; 1100 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1101 1102 mcnt = if_foreach_llmaddr(ifp, igc_copy_maddr, mta); 1103 1104 reg_rctl = IGC_READ_REG(&adapter->hw, IGC_RCTL); 1105 1106 if (if_getflags(ifp) & IFF_PROMISC) { 1107 reg_rctl |= (IGC_RCTL_UPE | IGC_RCTL_MPE); 1108 /* Turn this on if you want to see bad packets */ 1109 if (igc_debug_sbp) 1110 reg_rctl |= IGC_RCTL_SBP; 1111 } else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1112 if_getflags(ifp) & IFF_ALLMULTI) { 1113 reg_rctl |= IGC_RCTL_MPE; 1114 reg_rctl &= ~IGC_RCTL_UPE; 1115 } else 1116 reg_rctl &= ~(IGC_RCTL_UPE | IGC_RCTL_MPE); 1117 1118 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1119 igc_update_mc_addr_list(&adapter->hw, mta, mcnt); 1120 1121 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, reg_rctl); 1122 } 1123 1124 /********************************************************************* 1125 * Timer routine 1126 * 1127 * This routine schedules igc_if_update_admin_status() to check for 1128 * link status and to gather statistics as well as to perform some 1129 * controller-specific hardware patting. 1130 * 1131 **********************************************************************/ 1132 static void 1133 igc_if_timer(if_ctx_t ctx, uint16_t qid) 1134 { 1135 1136 if (qid != 0) 1137 return; 1138 1139 iflib_admin_intr_deferred(ctx); 1140 } 1141 1142 static void 1143 igc_if_update_admin_status(if_ctx_t ctx) 1144 { 1145 struct igc_adapter *adapter = iflib_get_softc(ctx); 1146 struct igc_hw *hw = &adapter->hw; 1147 device_t dev = iflib_get_dev(ctx); 1148 u32 link_check, thstat, ctrl; 1149 1150 link_check = thstat = ctrl = 0; 1151 /* Get the cached link value or read phy for real */ 1152 switch (hw->phy.media_type) { 1153 case igc_media_type_copper: 1154 if (hw->mac.get_link_status == true) { 1155 /* Do the work to read phy */ 1156 igc_check_for_link(hw); 1157 link_check = !hw->mac.get_link_status; 1158 } else 1159 link_check = true; 1160 break; 1161 case igc_media_type_unknown: 1162 igc_check_for_link(hw); 1163 link_check = !hw->mac.get_link_status; 1164 /* FALLTHROUGH */ 1165 default: 1166 break; 1167 } 1168 1169 /* Now check for a transition */ 1170 if (link_check && (adapter->link_active == 0)) { 1171 igc_get_speed_and_duplex(hw, &adapter->link_speed, 1172 &adapter->link_duplex); 1173 if (bootverbose) 1174 device_printf(dev, "Link is up %d Mbps %s\n", 1175 adapter->link_speed, 1176 ((adapter->link_duplex == FULL_DUPLEX) ? 1177 "Full Duplex" : "Half Duplex")); 1178 adapter->link_active = 1; 1179 iflib_link_state_change(ctx, LINK_STATE_UP, 1180 IF_Mbps(adapter->link_speed)); 1181 } else if (!link_check && (adapter->link_active == 1)) { 1182 adapter->link_speed = 0; 1183 adapter->link_duplex = 0; 1184 adapter->link_active = 0; 1185 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1186 } 1187 igc_update_stats_counters(adapter); 1188 } 1189 1190 static void 1191 igc_if_watchdog_reset(if_ctx_t ctx) 1192 { 1193 struct igc_adapter *adapter = iflib_get_softc(ctx); 1194 1195 /* 1196 * Just count the event; iflib(4) will already trigger a 1197 * sufficient reset of the controller. 1198 */ 1199 adapter->watchdog_events++; 1200 } 1201 1202 /********************************************************************* 1203 * 1204 * This routine disables all traffic on the adapter by issuing a 1205 * global reset on the MAC. 1206 * 1207 **********************************************************************/ 1208 static void 1209 igc_if_stop(if_ctx_t ctx) 1210 { 1211 struct igc_adapter *adapter = iflib_get_softc(ctx); 1212 1213 INIT_DEBUGOUT("igc_if_stop: begin"); 1214 1215 igc_reset_hw(&adapter->hw); 1216 IGC_WRITE_REG(&adapter->hw, IGC_WUC, 0); 1217 } 1218 1219 /********************************************************************* 1220 * 1221 * Determine hardware revision. 1222 * 1223 **********************************************************************/ 1224 static void 1225 igc_identify_hardware(if_ctx_t ctx) 1226 { 1227 device_t dev = iflib_get_dev(ctx); 1228 struct igc_adapter *adapter = iflib_get_softc(ctx); 1229 1230 /* Make sure our PCI config space has the necessary stuff set */ 1231 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1232 1233 /* Save off the information about this board */ 1234 adapter->hw.vendor_id = pci_get_vendor(dev); 1235 adapter->hw.device_id = pci_get_device(dev); 1236 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1237 adapter->hw.subsystem_vendor_id = 1238 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1239 adapter->hw.subsystem_device_id = 1240 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1241 1242 /* Do Shared Code Init and Setup */ 1243 if (igc_set_mac_type(&adapter->hw)) { 1244 device_printf(dev, "Setup init failure\n"); 1245 return; 1246 } 1247 } 1248 1249 static int 1250 igc_allocate_pci_resources(if_ctx_t ctx) 1251 { 1252 struct igc_adapter *adapter = iflib_get_softc(ctx); 1253 device_t dev = iflib_get_dev(ctx); 1254 int rid; 1255 1256 rid = PCIR_BAR(0); 1257 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1258 &rid, RF_ACTIVE); 1259 if (adapter->memory == NULL) { 1260 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1261 return (ENXIO); 1262 } 1263 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1264 adapter->osdep.mem_bus_space_handle = 1265 rman_get_bushandle(adapter->memory); 1266 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1267 1268 adapter->hw.back = &adapter->osdep; 1269 1270 return (0); 1271 } 1272 1273 /********************************************************************* 1274 * 1275 * Set up the MSI-X Interrupt handlers 1276 * 1277 **********************************************************************/ 1278 static int 1279 igc_if_msix_intr_assign(if_ctx_t ctx, int msix) 1280 { 1281 struct igc_adapter *adapter = iflib_get_softc(ctx); 1282 struct igc_rx_queue *rx_que = adapter->rx_queues; 1283 struct igc_tx_queue *tx_que = adapter->tx_queues; 1284 int error, rid, i, vector = 0, rx_vectors; 1285 char buf[16]; 1286 1287 /* First set up ring resources */ 1288 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 1289 rid = vector + 1; 1290 snprintf(buf, sizeof(buf), "rxq%d", i); 1291 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, igc_msix_que, rx_que, rx_que->me, buf); 1292 if (error) { 1293 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 1294 adapter->rx_num_queues = i + 1; 1295 goto fail; 1296 } 1297 1298 rx_que->msix = vector; 1299 1300 /* 1301 * Set the bit to enable interrupt 1302 * in IGC_IMS -- bits 20 and 21 1303 * are for RX0 and RX1, note this has 1304 * NOTHING to do with the MSI-X vector 1305 */ 1306 rx_que->eims = 1 << vector; 1307 } 1308 rx_vectors = vector; 1309 1310 vector = 0; 1311 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 1312 snprintf(buf, sizeof(buf), "txq%d", i); 1313 tx_que = &adapter->tx_queues[i]; 1314 iflib_softirq_alloc_generic(ctx, 1315 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq, 1316 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 1317 1318 tx_que->msix = (vector % adapter->rx_num_queues); 1319 1320 /* 1321 * Set the bit to enable interrupt 1322 * in IGC_IMS -- bits 22 and 23 1323 * are for TX0 and TX1, note this has 1324 * NOTHING to do with the MSI-X vector 1325 */ 1326 tx_que->eims = 1 << i; 1327 } 1328 1329 /* Link interrupt */ 1330 rid = rx_vectors + 1; 1331 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, igc_msix_link, adapter, 0, "aq"); 1332 1333 if (error) { 1334 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 1335 goto fail; 1336 } 1337 adapter->linkvec = rx_vectors; 1338 return (0); 1339 fail: 1340 iflib_irq_free(ctx, &adapter->irq); 1341 rx_que = adapter->rx_queues; 1342 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 1343 iflib_irq_free(ctx, &rx_que->que_irq); 1344 return (error); 1345 } 1346 1347 static void 1348 igc_configure_queues(struct igc_adapter *adapter) 1349 { 1350 struct igc_hw *hw = &adapter->hw; 1351 struct igc_rx_queue *rx_que; 1352 struct igc_tx_queue *tx_que; 1353 u32 ivar = 0, newitr = 0; 1354 1355 /* First turn on RSS capability */ 1356 IGC_WRITE_REG(hw, IGC_GPIE, 1357 IGC_GPIE_MSIX_MODE | IGC_GPIE_EIAME | IGC_GPIE_PBA | 1358 IGC_GPIE_NSICR); 1359 1360 /* Turn on MSI-X */ 1361 /* RX entries */ 1362 for (int i = 0; i < adapter->rx_num_queues; i++) { 1363 u32 index = i >> 1; 1364 ivar = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, index); 1365 rx_que = &adapter->rx_queues[i]; 1366 if (i & 1) { 1367 ivar &= 0xFF00FFFF; 1368 ivar |= (rx_que->msix | IGC_IVAR_VALID) << 16; 1369 } else { 1370 ivar &= 0xFFFFFF00; 1371 ivar |= rx_que->msix | IGC_IVAR_VALID; 1372 } 1373 IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, index, ivar); 1374 } 1375 /* TX entries */ 1376 for (int i = 0; i < adapter->tx_num_queues; i++) { 1377 u32 index = i >> 1; 1378 ivar = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, index); 1379 tx_que = &adapter->tx_queues[i]; 1380 if (i & 1) { 1381 ivar &= 0x00FFFFFF; 1382 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 24; 1383 } else { 1384 ivar &= 0xFFFF00FF; 1385 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 8; 1386 } 1387 IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, index, ivar); 1388 adapter->que_mask |= tx_que->eims; 1389 } 1390 1391 /* And for the link interrupt */ 1392 ivar = (adapter->linkvec | IGC_IVAR_VALID) << 8; 1393 adapter->link_mask = 1 << adapter->linkvec; 1394 IGC_WRITE_REG(hw, IGC_IVAR_MISC, ivar); 1395 1396 /* Set the starting interrupt rate */ 1397 if (igc_max_interrupt_rate > 0) 1398 newitr = (4000000 / igc_max_interrupt_rate) & 0x7FFC; 1399 1400 newitr |= IGC_EITR_CNT_IGNR; 1401 1402 for (int i = 0; i < adapter->rx_num_queues; i++) { 1403 rx_que = &adapter->rx_queues[i]; 1404 IGC_WRITE_REG(hw, IGC_EITR(rx_que->msix), newitr); 1405 } 1406 1407 return; 1408 } 1409 1410 static void 1411 igc_free_pci_resources(if_ctx_t ctx) 1412 { 1413 struct igc_adapter *adapter = iflib_get_softc(ctx); 1414 struct igc_rx_queue *que = adapter->rx_queues; 1415 device_t dev = iflib_get_dev(ctx); 1416 1417 /* Release all MSI-X queue resources */ 1418 if (adapter->intr_type == IFLIB_INTR_MSIX) 1419 iflib_irq_free(ctx, &adapter->irq); 1420 1421 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 1422 iflib_irq_free(ctx, &que->que_irq); 1423 } 1424 1425 if (adapter->memory != NULL) { 1426 bus_release_resource(dev, SYS_RES_MEMORY, 1427 rman_get_rid(adapter->memory), adapter->memory); 1428 adapter->memory = NULL; 1429 } 1430 1431 if (adapter->flash != NULL) { 1432 bus_release_resource(dev, SYS_RES_MEMORY, 1433 rman_get_rid(adapter->flash), adapter->flash); 1434 adapter->flash = NULL; 1435 } 1436 1437 if (adapter->ioport != NULL) { 1438 bus_release_resource(dev, SYS_RES_IOPORT, 1439 rman_get_rid(adapter->ioport), adapter->ioport); 1440 adapter->ioport = NULL; 1441 } 1442 } 1443 1444 /* Set up MSI or MSI-X */ 1445 static int 1446 igc_setup_msix(if_ctx_t ctx) 1447 { 1448 return (0); 1449 } 1450 1451 /********************************************************************* 1452 * 1453 * Initialize the DMA Coalescing feature 1454 * 1455 **********************************************************************/ 1456 static void 1457 igc_init_dmac(struct igc_adapter *adapter, u32 pba) 1458 { 1459 device_t dev = adapter->dev; 1460 struct igc_hw *hw = &adapter->hw; 1461 u32 dmac, reg = ~IGC_DMACR_DMAC_EN; 1462 u16 hwm; 1463 u16 max_frame_size; 1464 int status; 1465 1466 max_frame_size = adapter->shared->isc_max_frame_size; 1467 1468 if (adapter->dmac == 0) { /* Disabling it */ 1469 IGC_WRITE_REG(hw, IGC_DMACR, reg); 1470 return; 1471 } else 1472 device_printf(dev, "DMA Coalescing enabled\n"); 1473 1474 /* Set starting threshold */ 1475 IGC_WRITE_REG(hw, IGC_DMCTXTH, 0); 1476 1477 hwm = 64 * pba - max_frame_size / 16; 1478 if (hwm < 64 * (pba - 6)) 1479 hwm = 64 * (pba - 6); 1480 reg = IGC_READ_REG(hw, IGC_FCRTC); 1481 reg &= ~IGC_FCRTC_RTH_COAL_MASK; 1482 reg |= ((hwm << IGC_FCRTC_RTH_COAL_SHIFT) 1483 & IGC_FCRTC_RTH_COAL_MASK); 1484 IGC_WRITE_REG(hw, IGC_FCRTC, reg); 1485 1486 dmac = pba - max_frame_size / 512; 1487 if (dmac < pba - 10) 1488 dmac = pba - 10; 1489 reg = IGC_READ_REG(hw, IGC_DMACR); 1490 reg &= ~IGC_DMACR_DMACTHR_MASK; 1491 reg |= ((dmac << IGC_DMACR_DMACTHR_SHIFT) 1492 & IGC_DMACR_DMACTHR_MASK); 1493 1494 /* transition to L0x or L1 if available..*/ 1495 reg |= (IGC_DMACR_DMAC_EN | IGC_DMACR_DMAC_LX_MASK); 1496 1497 /* Check if status is 2.5Gb backplane connection 1498 * before configuration of watchdog timer, which is 1499 * in msec values in 12.8usec intervals 1500 * watchdog timer= msec values in 32usec intervals 1501 * for non 2.5Gb connection 1502 */ 1503 status = IGC_READ_REG(hw, IGC_STATUS); 1504 if ((status & IGC_STATUS_2P5_SKU) && 1505 (!(status & IGC_STATUS_2P5_SKU_OVER))) 1506 reg |= ((adapter->dmac * 5) >> 6); 1507 else 1508 reg |= (adapter->dmac >> 5); 1509 1510 IGC_WRITE_REG(hw, IGC_DMACR, reg); 1511 1512 IGC_WRITE_REG(hw, IGC_DMCRTRH, 0); 1513 1514 /* Set the interval before transition */ 1515 reg = IGC_READ_REG(hw, IGC_DMCTLX); 1516 reg |= IGC_DMCTLX_DCFLUSH_DIS; 1517 1518 /* 1519 ** in 2.5Gb connection, TTLX unit is 0.4 usec 1520 ** which is 0x4*2 = 0xA. But delay is still 4 usec 1521 */ 1522 status = IGC_READ_REG(hw, IGC_STATUS); 1523 if ((status & IGC_STATUS_2P5_SKU) && 1524 (!(status & IGC_STATUS_2P5_SKU_OVER))) 1525 reg |= 0xA; 1526 else 1527 reg |= 0x4; 1528 1529 IGC_WRITE_REG(hw, IGC_DMCTLX, reg); 1530 1531 /* free space in tx packet buffer to wake from DMA coal */ 1532 IGC_WRITE_REG(hw, IGC_DMCTXTH, (IGC_TXPBSIZE - 1533 (2 * max_frame_size)) >> 6); 1534 1535 /* make low power state decision controlled by DMA coal */ 1536 reg = IGC_READ_REG(hw, IGC_PCIEMISC); 1537 reg &= ~IGC_PCIEMISC_LX_DECISION; 1538 IGC_WRITE_REG(hw, IGC_PCIEMISC, reg); 1539 } 1540 1541 /********************************************************************* 1542 * 1543 * Initialize the hardware to a configuration as specified by the 1544 * adapter structure. 1545 * 1546 **********************************************************************/ 1547 static void 1548 igc_reset(if_ctx_t ctx) 1549 { 1550 device_t dev = iflib_get_dev(ctx); 1551 struct igc_adapter *adapter = iflib_get_softc(ctx); 1552 struct igc_hw *hw = &adapter->hw; 1553 u32 rx_buffer_size; 1554 u32 pba; 1555 1556 INIT_DEBUGOUT("igc_reset: begin"); 1557 /* Let the firmware know the OS is in control */ 1558 igc_get_hw_control(adapter); 1559 1560 /* 1561 * Packet Buffer Allocation (PBA) 1562 * Writing PBA sets the receive portion of the buffer 1563 * the remainder is used for the transmit buffer. 1564 */ 1565 pba = IGC_PBA_34K; 1566 1567 INIT_DEBUGOUT1("igc_reset: pba=%dK",pba); 1568 1569 /* 1570 * These parameters control the automatic generation (Tx) and 1571 * response (Rx) to Ethernet PAUSE frames. 1572 * - High water mark should allow for at least two frames to be 1573 * received after sending an XOFF. 1574 * - Low water mark works best when it is very near the high water mark. 1575 * This allows the receiver to restart by sending XON when it has 1576 * drained a bit. Here we use an arbitrary value of 1500 which will 1577 * restart after one full frame is pulled from the buffer. There 1578 * could be several smaller frames in the buffer and if so they will 1579 * not trigger the XON until their total number reduces the buffer 1580 * by 1500. 1581 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 1582 */ 1583 rx_buffer_size = (pba & 0xffff) << 10; 1584 hw->fc.high_water = rx_buffer_size - 1585 roundup2(adapter->hw.mac.max_frame_size, 1024); 1586 /* 16-byte granularity */ 1587 hw->fc.low_water = hw->fc.high_water - 16; 1588 1589 if (adapter->fc) /* locally set flow control value? */ 1590 hw->fc.requested_mode = adapter->fc; 1591 else 1592 hw->fc.requested_mode = igc_fc_full; 1593 1594 hw->fc.pause_time = IGC_FC_PAUSE_TIME; 1595 1596 hw->fc.send_xon = true; 1597 1598 /* Issue a global reset */ 1599 igc_reset_hw(hw); 1600 IGC_WRITE_REG(hw, IGC_WUC, 0); 1601 1602 /* and a re-init */ 1603 if (igc_init_hw(hw) < 0) { 1604 device_printf(dev, "Hardware Initialization Failed\n"); 1605 return; 1606 } 1607 1608 /* Setup DMA Coalescing */ 1609 igc_init_dmac(adapter, pba); 1610 1611 IGC_WRITE_REG(hw, IGC_VET, ETHERTYPE_VLAN); 1612 igc_get_phy_info(hw); 1613 igc_check_for_link(hw); 1614 } 1615 1616 /* 1617 * Initialise the RSS mapping for NICs that support multiple transmit/ 1618 * receive rings. 1619 */ 1620 1621 #define RSSKEYLEN 10 1622 static void 1623 igc_initialize_rss_mapping(struct igc_adapter *adapter) 1624 { 1625 struct igc_hw *hw = &adapter->hw; 1626 int i; 1627 int queue_id; 1628 u32 reta; 1629 u32 rss_key[RSSKEYLEN], mrqc, shift = 0; 1630 1631 /* 1632 * The redirection table controls which destination 1633 * queue each bucket redirects traffic to. 1634 * Each DWORD represents four queues, with the LSB 1635 * being the first queue in the DWORD. 1636 * 1637 * This just allocates buckets to queues using round-robin 1638 * allocation. 1639 * 1640 * NOTE: It Just Happens to line up with the default 1641 * RSS allocation method. 1642 */ 1643 1644 /* Warning FM follows */ 1645 reta = 0; 1646 for (i = 0; i < 128; i++) { 1647 #ifdef RSS 1648 queue_id = rss_get_indirection_to_bucket(i); 1649 /* 1650 * If we have more queues than buckets, we'll 1651 * end up mapping buckets to a subset of the 1652 * queues. 1653 * 1654 * If we have more buckets than queues, we'll 1655 * end up instead assigning multiple buckets 1656 * to queues. 1657 * 1658 * Both are suboptimal, but we need to handle 1659 * the case so we don't go out of bounds 1660 * indexing arrays and such. 1661 */ 1662 queue_id = queue_id % adapter->rx_num_queues; 1663 #else 1664 queue_id = (i % adapter->rx_num_queues); 1665 #endif 1666 /* Adjust if required */ 1667 queue_id = queue_id << shift; 1668 1669 /* 1670 * The low 8 bits are for hash value (n+0); 1671 * The next 8 bits are for hash value (n+1), etc. 1672 */ 1673 reta = reta >> 8; 1674 reta = reta | ( ((uint32_t) queue_id) << 24); 1675 if ((i & 3) == 3) { 1676 IGC_WRITE_REG(hw, IGC_RETA(i >> 2), reta); 1677 reta = 0; 1678 } 1679 } 1680 1681 /* Now fill in hash table */ 1682 1683 /* 1684 * MRQC: Multiple Receive Queues Command 1685 * Set queuing to RSS control, number depends on the device. 1686 */ 1687 mrqc = IGC_MRQC_ENABLE_RSS_4Q; 1688 1689 #ifdef RSS 1690 /* XXX ew typecasting */ 1691 rss_getkey((uint8_t *) &rss_key); 1692 #else 1693 arc4rand(&rss_key, sizeof(rss_key), 0); 1694 #endif 1695 for (i = 0; i < RSSKEYLEN; i++) 1696 IGC_WRITE_REG_ARRAY(hw, IGC_RSSRK(0), i, rss_key[i]); 1697 1698 /* 1699 * Configure the RSS fields to hash upon. 1700 */ 1701 mrqc |= (IGC_MRQC_RSS_FIELD_IPV4 | 1702 IGC_MRQC_RSS_FIELD_IPV4_TCP); 1703 mrqc |= (IGC_MRQC_RSS_FIELD_IPV6 | 1704 IGC_MRQC_RSS_FIELD_IPV6_TCP); 1705 mrqc |=( IGC_MRQC_RSS_FIELD_IPV4_UDP | 1706 IGC_MRQC_RSS_FIELD_IPV6_UDP); 1707 mrqc |=( IGC_MRQC_RSS_FIELD_IPV6_UDP_EX | 1708 IGC_MRQC_RSS_FIELD_IPV6_TCP_EX); 1709 1710 IGC_WRITE_REG(hw, IGC_MRQC, mrqc); 1711 } 1712 1713 /********************************************************************* 1714 * 1715 * Setup networking device structure and register interface media. 1716 * 1717 **********************************************************************/ 1718 static int 1719 igc_setup_interface(if_ctx_t ctx) 1720 { 1721 if_t ifp = iflib_get_ifp(ctx); 1722 struct igc_adapter *adapter = iflib_get_softc(ctx); 1723 if_softc_ctx_t scctx = adapter->shared; 1724 1725 INIT_DEBUGOUT("igc_setup_interface: begin"); 1726 1727 /* Single Queue */ 1728 if (adapter->tx_num_queues == 1) { 1729 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 1730 if_setsendqready(ifp); 1731 } 1732 1733 /* 1734 * Specify the media types supported by this adapter and register 1735 * callbacks to update media and link information 1736 */ 1737 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 1738 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1739 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 1740 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1741 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1742 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 1743 ifmedia_add(adapter->media, IFM_ETHER | IFM_2500_T, 0, NULL); 1744 1745 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1746 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 1747 return (0); 1748 } 1749 1750 static int 1751 igc_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 1752 { 1753 struct igc_adapter *adapter = iflib_get_softc(ctx); 1754 if_softc_ctx_t scctx = adapter->shared; 1755 int error = IGC_SUCCESS; 1756 struct igc_tx_queue *que; 1757 int i, j; 1758 1759 MPASS(adapter->tx_num_queues > 0); 1760 MPASS(adapter->tx_num_queues == ntxqsets); 1761 1762 /* First allocate the top level queue structs */ 1763 if (!(adapter->tx_queues = 1764 (struct igc_tx_queue *) malloc(sizeof(struct igc_tx_queue) * 1765 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 1766 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 1767 return(ENOMEM); 1768 } 1769 1770 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 1771 /* Set up some basics */ 1772 1773 struct tx_ring *txr = &que->txr; 1774 txr->adapter = que->adapter = adapter; 1775 que->me = txr->me = i; 1776 1777 /* Allocate report status array */ 1778 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 1779 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 1780 error = ENOMEM; 1781 goto fail; 1782 } 1783 for (j = 0; j < scctx->isc_ntxd[0]; j++) 1784 txr->tx_rsq[j] = QIDX_INVALID; 1785 /* get the virtual and physical address of the hardware queues */ 1786 txr->tx_base = (struct igc_tx_desc *)vaddrs[i*ntxqs]; 1787 txr->tx_paddr = paddrs[i*ntxqs]; 1788 } 1789 1790 if (bootverbose) 1791 device_printf(iflib_get_dev(ctx), 1792 "allocated for %d tx_queues\n", adapter->tx_num_queues); 1793 return (0); 1794 fail: 1795 igc_if_queues_free(ctx); 1796 return (error); 1797 } 1798 1799 static int 1800 igc_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 1801 { 1802 struct igc_adapter *adapter = iflib_get_softc(ctx); 1803 int error = IGC_SUCCESS; 1804 struct igc_rx_queue *que; 1805 int i; 1806 1807 MPASS(adapter->rx_num_queues > 0); 1808 MPASS(adapter->rx_num_queues == nrxqsets); 1809 1810 /* First allocate the top level queue structs */ 1811 if (!(adapter->rx_queues = 1812 (struct igc_rx_queue *) malloc(sizeof(struct igc_rx_queue) * 1813 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 1814 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 1815 error = ENOMEM; 1816 goto fail; 1817 } 1818 1819 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 1820 /* Set up some basics */ 1821 struct rx_ring *rxr = &que->rxr; 1822 rxr->adapter = que->adapter = adapter; 1823 rxr->que = que; 1824 que->me = rxr->me = i; 1825 1826 /* get the virtual and physical address of the hardware queues */ 1827 rxr->rx_base = (union igc_rx_desc_extended *)vaddrs[i*nrxqs]; 1828 rxr->rx_paddr = paddrs[i*nrxqs]; 1829 } 1830 1831 if (bootverbose) 1832 device_printf(iflib_get_dev(ctx), 1833 "allocated for %d rx_queues\n", adapter->rx_num_queues); 1834 1835 return (0); 1836 fail: 1837 igc_if_queues_free(ctx); 1838 return (error); 1839 } 1840 1841 static void 1842 igc_if_queues_free(if_ctx_t ctx) 1843 { 1844 struct igc_adapter *adapter = iflib_get_softc(ctx); 1845 struct igc_tx_queue *tx_que = adapter->tx_queues; 1846 struct igc_rx_queue *rx_que = adapter->rx_queues; 1847 1848 if (tx_que != NULL) { 1849 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 1850 struct tx_ring *txr = &tx_que->txr; 1851 if (txr->tx_rsq == NULL) 1852 break; 1853 1854 free(txr->tx_rsq, M_DEVBUF); 1855 txr->tx_rsq = NULL; 1856 } 1857 free(adapter->tx_queues, M_DEVBUF); 1858 adapter->tx_queues = NULL; 1859 } 1860 1861 if (rx_que != NULL) { 1862 free(adapter->rx_queues, M_DEVBUF); 1863 adapter->rx_queues = NULL; 1864 } 1865 1866 igc_release_hw_control(adapter); 1867 1868 if (adapter->mta != NULL) { 1869 free(adapter->mta, M_DEVBUF); 1870 } 1871 } 1872 1873 /********************************************************************* 1874 * 1875 * Enable transmit unit. 1876 * 1877 **********************************************************************/ 1878 static void 1879 igc_initialize_transmit_unit(if_ctx_t ctx) 1880 { 1881 struct igc_adapter *adapter = iflib_get_softc(ctx); 1882 if_softc_ctx_t scctx = adapter->shared; 1883 struct igc_tx_queue *que; 1884 struct tx_ring *txr; 1885 struct igc_hw *hw = &adapter->hw; 1886 u32 tctl, txdctl = 0; 1887 1888 INIT_DEBUGOUT("igc_initialize_transmit_unit: begin"); 1889 1890 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 1891 u64 bus_addr; 1892 caddr_t offp, endp; 1893 1894 que = &adapter->tx_queues[i]; 1895 txr = &que->txr; 1896 bus_addr = txr->tx_paddr; 1897 1898 /* Clear checksum offload context. */ 1899 offp = (caddr_t)&txr->csum_flags; 1900 endp = (caddr_t)(txr + 1); 1901 bzero(offp, endp - offp); 1902 1903 /* Base and Len of TX Ring */ 1904 IGC_WRITE_REG(hw, IGC_TDLEN(i), 1905 scctx->isc_ntxd[0] * sizeof(struct igc_tx_desc)); 1906 IGC_WRITE_REG(hw, IGC_TDBAH(i), 1907 (u32)(bus_addr >> 32)); 1908 IGC_WRITE_REG(hw, IGC_TDBAL(i), 1909 (u32)bus_addr); 1910 /* Init the HEAD/TAIL indices */ 1911 IGC_WRITE_REG(hw, IGC_TDT(i), 0); 1912 IGC_WRITE_REG(hw, IGC_TDH(i), 0); 1913 1914 HW_DEBUGOUT2("Base = %x, Length = %x\n", 1915 IGC_READ_REG(&adapter->hw, IGC_TDBAL(i)), 1916 IGC_READ_REG(&adapter->hw, IGC_TDLEN(i))); 1917 1918 txdctl = 0; /* clear txdctl */ 1919 txdctl |= 0x1f; /* PTHRESH */ 1920 txdctl |= 1 << 8; /* HTHRESH */ 1921 txdctl |= 1 << 16;/* WTHRESH */ 1922 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 1923 txdctl |= IGC_TXDCTL_GRAN; 1924 txdctl |= 1 << 25; /* LWTHRESH */ 1925 1926 IGC_WRITE_REG(hw, IGC_TXDCTL(i), txdctl); 1927 } 1928 1929 /* Program the Transmit Control Register */ 1930 tctl = IGC_READ_REG(&adapter->hw, IGC_TCTL); 1931 tctl &= ~IGC_TCTL_CT; 1932 tctl |= (IGC_TCTL_PSP | IGC_TCTL_RTLC | IGC_TCTL_EN | 1933 (IGC_COLLISION_THRESHOLD << IGC_CT_SHIFT)); 1934 1935 /* This write will effectively turn on the transmit unit. */ 1936 IGC_WRITE_REG(&adapter->hw, IGC_TCTL, tctl); 1937 } 1938 1939 /********************************************************************* 1940 * 1941 * Enable receive unit. 1942 * 1943 **********************************************************************/ 1944 #define BSIZEPKT_ROUNDUP ((1<<IGC_SRRCTL_BSIZEPKT_SHIFT)-1) 1945 1946 static void 1947 igc_initialize_receive_unit(if_ctx_t ctx) 1948 { 1949 struct igc_adapter *adapter = iflib_get_softc(ctx); 1950 if_softc_ctx_t scctx = adapter->shared; 1951 if_t ifp = iflib_get_ifp(ctx); 1952 struct igc_hw *hw = &adapter->hw; 1953 struct igc_rx_queue *que; 1954 int i; 1955 u32 psize, rctl, rxcsum, srrctl = 0; 1956 1957 INIT_DEBUGOUT("igc_initialize_receive_units: begin"); 1958 1959 /* 1960 * Make sure receives are disabled while setting 1961 * up the descriptor ring 1962 */ 1963 rctl = IGC_READ_REG(hw, IGC_RCTL); 1964 IGC_WRITE_REG(hw, IGC_RCTL, rctl & ~IGC_RCTL_EN); 1965 1966 /* Setup the Receive Control Register */ 1967 rctl &= ~(3 << IGC_RCTL_MO_SHIFT); 1968 rctl |= IGC_RCTL_EN | IGC_RCTL_BAM | 1969 IGC_RCTL_LBM_NO | IGC_RCTL_RDMTS_HALF | 1970 (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT); 1971 1972 /* Do not store bad packets */ 1973 rctl &= ~IGC_RCTL_SBP; 1974 1975 /* Enable Long Packet receive */ 1976 if (if_getmtu(ifp) > ETHERMTU) 1977 rctl |= IGC_RCTL_LPE; 1978 else 1979 rctl &= ~IGC_RCTL_LPE; 1980 1981 /* Strip the CRC */ 1982 if (!igc_disable_crc_stripping) 1983 rctl |= IGC_RCTL_SECRC; 1984 1985 rxcsum = IGC_READ_REG(hw, IGC_RXCSUM); 1986 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 1987 rxcsum |= IGC_RXCSUM_CRCOFL; 1988 if (adapter->tx_num_queues > 1) 1989 rxcsum |= IGC_RXCSUM_PCSD; 1990 else 1991 rxcsum |= IGC_RXCSUM_IPPCSE; 1992 } else { 1993 if (adapter->tx_num_queues > 1) 1994 rxcsum |= IGC_RXCSUM_PCSD; 1995 else 1996 rxcsum &= ~IGC_RXCSUM_TUOFL; 1997 } 1998 IGC_WRITE_REG(hw, IGC_RXCSUM, rxcsum); 1999 2000 if (adapter->rx_num_queues > 1) 2001 igc_initialize_rss_mapping(adapter); 2002 2003 if (if_getmtu(ifp) > ETHERMTU) { 2004 psize = scctx->isc_max_frame_size; 2005 /* are we on a vlan? */ 2006 if (if_vlantrunkinuse(ifp)) 2007 psize += VLAN_TAG_SIZE; 2008 IGC_WRITE_REG(&adapter->hw, IGC_RLPML, psize); 2009 } 2010 2011 /* Set maximum packet buffer len */ 2012 srrctl |= (adapter->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 2013 IGC_SRRCTL_BSIZEPKT_SHIFT; 2014 /* srrctl above overrides this but set the register to a sane value */ 2015 rctl |= IGC_RCTL_SZ_2048; 2016 2017 /* 2018 * If TX flow control is disabled and there's >1 queue defined, 2019 * enable DROP. 2020 * 2021 * This drops frames rather than hanging the RX MAC for all queues. 2022 */ 2023 if ((adapter->rx_num_queues > 1) && 2024 (adapter->fc == igc_fc_none || 2025 adapter->fc == igc_fc_rx_pause)) { 2026 srrctl |= IGC_SRRCTL_DROP_EN; 2027 } 2028 2029 /* Setup the Base and Length of the Rx Descriptor Rings */ 2030 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 2031 struct rx_ring *rxr = &que->rxr; 2032 u64 bus_addr = rxr->rx_paddr; 2033 u32 rxdctl; 2034 2035 #ifdef notyet 2036 /* Configure for header split? -- ignore for now */ 2037 rxr->hdr_split = igc_header_split; 2038 #else 2039 srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF; 2040 #endif 2041 2042 IGC_WRITE_REG(hw, IGC_RDLEN(i), 2043 scctx->isc_nrxd[0] * sizeof(struct igc_rx_desc)); 2044 IGC_WRITE_REG(hw, IGC_RDBAH(i), 2045 (uint32_t)(bus_addr >> 32)); 2046 IGC_WRITE_REG(hw, IGC_RDBAL(i), 2047 (uint32_t)bus_addr); 2048 IGC_WRITE_REG(hw, IGC_SRRCTL(i), srrctl); 2049 /* Setup the Head and Tail Descriptor Pointers */ 2050 IGC_WRITE_REG(hw, IGC_RDH(i), 0); 2051 IGC_WRITE_REG(hw, IGC_RDT(i), 0); 2052 /* Enable this Queue */ 2053 rxdctl = IGC_READ_REG(hw, IGC_RXDCTL(i)); 2054 rxdctl |= IGC_RXDCTL_QUEUE_ENABLE; 2055 rxdctl &= 0xFFF00000; 2056 rxdctl |= IGC_RX_PTHRESH; 2057 rxdctl |= IGC_RX_HTHRESH << 8; 2058 rxdctl |= IGC_RX_WTHRESH << 16; 2059 IGC_WRITE_REG(hw, IGC_RXDCTL(i), rxdctl); 2060 } 2061 2062 /* Make sure VLAN Filters are off */ 2063 rctl &= ~IGC_RCTL_VFE; 2064 2065 /* Write out the settings */ 2066 IGC_WRITE_REG(hw, IGC_RCTL, rctl); 2067 2068 return; 2069 } 2070 2071 static void 2072 igc_setup_vlan_hw_support(if_ctx_t ctx) 2073 { 2074 struct igc_adapter *adapter = iflib_get_softc(ctx); 2075 struct igc_hw *hw = &adapter->hw; 2076 struct ifnet *ifp = iflib_get_ifp(ctx); 2077 u32 reg; 2078 2079 /* igc hardware doesn't seem to implement VFTA for HWFILTER */ 2080 2081 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 2082 !igc_disable_crc_stripping) { 2083 reg = IGC_READ_REG(hw, IGC_CTRL); 2084 reg |= IGC_CTRL_VME; 2085 IGC_WRITE_REG(hw, IGC_CTRL, reg); 2086 } else { 2087 reg = IGC_READ_REG(hw, IGC_CTRL); 2088 reg &= ~IGC_CTRL_VME; 2089 IGC_WRITE_REG(hw, IGC_CTRL, reg); 2090 } 2091 } 2092 2093 static void 2094 igc_if_intr_enable(if_ctx_t ctx) 2095 { 2096 struct igc_adapter *adapter = iflib_get_softc(ctx); 2097 struct igc_hw *hw = &adapter->hw; 2098 u32 mask; 2099 2100 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 2101 mask = (adapter->que_mask | adapter->link_mask); 2102 IGC_WRITE_REG(hw, IGC_EIAC, mask); 2103 IGC_WRITE_REG(hw, IGC_EIAM, mask); 2104 IGC_WRITE_REG(hw, IGC_EIMS, mask); 2105 IGC_WRITE_REG(hw, IGC_IMS, IGC_IMS_LSC); 2106 } else 2107 IGC_WRITE_REG(hw, IGC_IMS, IMS_ENABLE_MASK); 2108 IGC_WRITE_FLUSH(hw); 2109 } 2110 2111 static void 2112 igc_if_intr_disable(if_ctx_t ctx) 2113 { 2114 struct igc_adapter *adapter = iflib_get_softc(ctx); 2115 struct igc_hw *hw = &adapter->hw; 2116 2117 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 2118 IGC_WRITE_REG(hw, IGC_EIMC, 0xffffffff); 2119 IGC_WRITE_REG(hw, IGC_EIAC, 0); 2120 } 2121 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff); 2122 IGC_WRITE_FLUSH(hw); 2123 } 2124 2125 /* 2126 * igc_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 2127 * For ASF and Pass Through versions of f/w this means 2128 * that the driver is loaded. For AMT version type f/w 2129 * this means that the network i/f is open. 2130 */ 2131 static void 2132 igc_get_hw_control(struct igc_adapter *adapter) 2133 { 2134 u32 ctrl_ext; 2135 2136 if (adapter->vf_ifp) 2137 return; 2138 2139 ctrl_ext = IGC_READ_REG(&adapter->hw, IGC_CTRL_EXT); 2140 IGC_WRITE_REG(&adapter->hw, IGC_CTRL_EXT, 2141 ctrl_ext | IGC_CTRL_EXT_DRV_LOAD); 2142 } 2143 2144 /* 2145 * igc_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 2146 * For ASF and Pass Through versions of f/w this means that 2147 * the driver is no longer loaded. For AMT versions of the 2148 * f/w this means that the network i/f is closed. 2149 */ 2150 static void 2151 igc_release_hw_control(struct igc_adapter *adapter) 2152 { 2153 u32 ctrl_ext; 2154 2155 ctrl_ext = IGC_READ_REG(&adapter->hw, IGC_CTRL_EXT); 2156 IGC_WRITE_REG(&adapter->hw, IGC_CTRL_EXT, 2157 ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD); 2158 return; 2159 } 2160 2161 static int 2162 igc_is_valid_ether_addr(u8 *addr) 2163 { 2164 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 2165 2166 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 2167 return (false); 2168 } 2169 2170 return (true); 2171 } 2172 2173 /* 2174 ** Parse the interface capabilities with regard 2175 ** to both system management and wake-on-lan for 2176 ** later use. 2177 */ 2178 static void 2179 igc_get_wakeup(if_ctx_t ctx) 2180 { 2181 struct igc_adapter *adapter = iflib_get_softc(ctx); 2182 u16 eeprom_data = 0, apme_mask; 2183 2184 apme_mask = IGC_WUC_APME; 2185 eeprom_data = IGC_READ_REG(&adapter->hw, IGC_WUC); 2186 2187 if (eeprom_data & apme_mask) 2188 adapter->wol = IGC_WUFC_LNKC; 2189 } 2190 2191 2192 /* 2193 * Enable PCI Wake On Lan capability 2194 */ 2195 static void 2196 igc_enable_wakeup(if_ctx_t ctx) 2197 { 2198 struct igc_adapter *adapter = iflib_get_softc(ctx); 2199 device_t dev = iflib_get_dev(ctx); 2200 if_t ifp = iflib_get_ifp(ctx); 2201 int error = 0; 2202 u32 pmc, ctrl, rctl; 2203 u16 status; 2204 2205 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 2206 return; 2207 2208 /* 2209 * Determine type of Wakeup: note that wol 2210 * is set with all bits on by default. 2211 */ 2212 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 2213 adapter->wol &= ~IGC_WUFC_MAG; 2214 2215 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 2216 adapter->wol &= ~IGC_WUFC_EX; 2217 2218 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 2219 adapter->wol &= ~IGC_WUFC_MC; 2220 else { 2221 rctl = IGC_READ_REG(&adapter->hw, IGC_RCTL); 2222 rctl |= IGC_RCTL_MPE; 2223 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, rctl); 2224 } 2225 2226 if (!(adapter->wol & (IGC_WUFC_EX | IGC_WUFC_MAG | IGC_WUFC_MC))) 2227 goto pme; 2228 2229 /* Advertise the wakeup capability */ 2230 ctrl = IGC_READ_REG(&adapter->hw, IGC_CTRL); 2231 ctrl |= IGC_CTRL_ADVD3WUC; 2232 IGC_WRITE_REG(&adapter->hw, IGC_CTRL, ctrl); 2233 2234 /* Enable wakeup by the MAC */ 2235 IGC_WRITE_REG(&adapter->hw, IGC_WUC, IGC_WUC_PME_EN); 2236 IGC_WRITE_REG(&adapter->hw, IGC_WUFC, adapter->wol); 2237 2238 pme: 2239 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 2240 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2241 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 2242 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2243 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 2244 2245 return; 2246 } 2247 2248 /********************************************************************** 2249 * 2250 * Update the board statistics counters. 2251 * 2252 **********************************************************************/ 2253 static void 2254 igc_update_stats_counters(struct igc_adapter *adapter) 2255 { 2256 u64 prev_xoffrxc = adapter->stats.xoffrxc; 2257 2258 adapter->stats.crcerrs += IGC_READ_REG(&adapter->hw, IGC_CRCERRS); 2259 adapter->stats.mpc += IGC_READ_REG(&adapter->hw, IGC_MPC); 2260 adapter->stats.scc += IGC_READ_REG(&adapter->hw, IGC_SCC); 2261 adapter->stats.ecol += IGC_READ_REG(&adapter->hw, IGC_ECOL); 2262 2263 adapter->stats.mcc += IGC_READ_REG(&adapter->hw, IGC_MCC); 2264 adapter->stats.latecol += IGC_READ_REG(&adapter->hw, IGC_LATECOL); 2265 adapter->stats.colc += IGC_READ_REG(&adapter->hw, IGC_COLC); 2266 adapter->stats.colc += IGC_READ_REG(&adapter->hw, IGC_RERC); 2267 adapter->stats.dc += IGC_READ_REG(&adapter->hw, IGC_DC); 2268 adapter->stats.rlec += IGC_READ_REG(&adapter->hw, IGC_RLEC); 2269 adapter->stats.xonrxc += IGC_READ_REG(&adapter->hw, IGC_XONRXC); 2270 adapter->stats.xontxc += IGC_READ_REG(&adapter->hw, IGC_XONTXC); 2271 adapter->stats.xoffrxc += IGC_READ_REG(&adapter->hw, IGC_XOFFRXC); 2272 /* 2273 * For watchdog management we need to know if we have been 2274 * paused during the last interval, so capture that here. 2275 */ 2276 if (adapter->stats.xoffrxc != prev_xoffrxc) 2277 adapter->shared->isc_pause_frames = 1; 2278 adapter->stats.xofftxc += IGC_READ_REG(&adapter->hw, IGC_XOFFTXC); 2279 adapter->stats.fcruc += IGC_READ_REG(&adapter->hw, IGC_FCRUC); 2280 adapter->stats.prc64 += IGC_READ_REG(&adapter->hw, IGC_PRC64); 2281 adapter->stats.prc127 += IGC_READ_REG(&adapter->hw, IGC_PRC127); 2282 adapter->stats.prc255 += IGC_READ_REG(&adapter->hw, IGC_PRC255); 2283 adapter->stats.prc511 += IGC_READ_REG(&adapter->hw, IGC_PRC511); 2284 adapter->stats.prc1023 += IGC_READ_REG(&adapter->hw, IGC_PRC1023); 2285 adapter->stats.prc1522 += IGC_READ_REG(&adapter->hw, IGC_PRC1522); 2286 adapter->stats.tlpic += IGC_READ_REG(&adapter->hw, IGC_TLPIC); 2287 adapter->stats.rlpic += IGC_READ_REG(&adapter->hw, IGC_RLPIC); 2288 adapter->stats.gprc += IGC_READ_REG(&adapter->hw, IGC_GPRC); 2289 adapter->stats.bprc += IGC_READ_REG(&adapter->hw, IGC_BPRC); 2290 adapter->stats.mprc += IGC_READ_REG(&adapter->hw, IGC_MPRC); 2291 adapter->stats.gptc += IGC_READ_REG(&adapter->hw, IGC_GPTC); 2292 2293 /* For the 64-bit byte counters the low dword must be read first. */ 2294 /* Both registers clear on the read of the high dword */ 2295 2296 adapter->stats.gorc += IGC_READ_REG(&adapter->hw, IGC_GORCL) + 2297 ((u64)IGC_READ_REG(&adapter->hw, IGC_GORCH) << 32); 2298 adapter->stats.gotc += IGC_READ_REG(&adapter->hw, IGC_GOTCL) + 2299 ((u64)IGC_READ_REG(&adapter->hw, IGC_GOTCH) << 32); 2300 2301 adapter->stats.rnbc += IGC_READ_REG(&adapter->hw, IGC_RNBC); 2302 adapter->stats.ruc += IGC_READ_REG(&adapter->hw, IGC_RUC); 2303 adapter->stats.rfc += IGC_READ_REG(&adapter->hw, IGC_RFC); 2304 adapter->stats.roc += IGC_READ_REG(&adapter->hw, IGC_ROC); 2305 adapter->stats.rjc += IGC_READ_REG(&adapter->hw, IGC_RJC); 2306 2307 adapter->stats.tor += IGC_READ_REG(&adapter->hw, IGC_TORH); 2308 adapter->stats.tot += IGC_READ_REG(&adapter->hw, IGC_TOTH); 2309 2310 adapter->stats.tpr += IGC_READ_REG(&adapter->hw, IGC_TPR); 2311 adapter->stats.tpt += IGC_READ_REG(&adapter->hw, IGC_TPT); 2312 adapter->stats.ptc64 += IGC_READ_REG(&adapter->hw, IGC_PTC64); 2313 adapter->stats.ptc127 += IGC_READ_REG(&adapter->hw, IGC_PTC127); 2314 adapter->stats.ptc255 += IGC_READ_REG(&adapter->hw, IGC_PTC255); 2315 adapter->stats.ptc511 += IGC_READ_REG(&adapter->hw, IGC_PTC511); 2316 adapter->stats.ptc1023 += IGC_READ_REG(&adapter->hw, IGC_PTC1023); 2317 adapter->stats.ptc1522 += IGC_READ_REG(&adapter->hw, IGC_PTC1522); 2318 adapter->stats.mptc += IGC_READ_REG(&adapter->hw, IGC_MPTC); 2319 adapter->stats.bptc += IGC_READ_REG(&adapter->hw, IGC_BPTC); 2320 2321 /* Interrupt Counts */ 2322 adapter->stats.iac += IGC_READ_REG(&adapter->hw, IGC_IAC); 2323 adapter->stats.rxdmtc += IGC_READ_REG(&adapter->hw, IGC_RXDMTC); 2324 2325 adapter->stats.algnerrc += IGC_READ_REG(&adapter->hw, IGC_ALGNERRC); 2326 adapter->stats.tncrs += IGC_READ_REG(&adapter->hw, IGC_TNCRS); 2327 adapter->stats.htdpmc += IGC_READ_REG(&adapter->hw, IGC_HTDPMC); 2328 adapter->stats.tsctc += IGC_READ_REG(&adapter->hw, IGC_TSCTC); 2329 } 2330 2331 static uint64_t 2332 igc_if_get_counter(if_ctx_t ctx, ift_counter cnt) 2333 { 2334 struct igc_adapter *adapter = iflib_get_softc(ctx); 2335 if_t ifp = iflib_get_ifp(ctx); 2336 2337 switch (cnt) { 2338 case IFCOUNTER_COLLISIONS: 2339 return (adapter->stats.colc); 2340 case IFCOUNTER_IERRORS: 2341 return (adapter->dropped_pkts + adapter->stats.rxerrc + 2342 adapter->stats.crcerrs + adapter->stats.algnerrc + 2343 adapter->stats.ruc + adapter->stats.roc + 2344 adapter->stats.mpc + adapter->stats.htdpmc); 2345 case IFCOUNTER_OERRORS: 2346 return (adapter->stats.ecol + adapter->stats.latecol + 2347 adapter->watchdog_events); 2348 default: 2349 return (if_get_counter_default(ifp, cnt)); 2350 } 2351 } 2352 2353 /* igc_if_needs_restart - Tell iflib when the driver needs to be reinitialized 2354 * @ctx: iflib context 2355 * @event: event code to check 2356 * 2357 * Defaults to returning false for unknown events. 2358 * 2359 * @returns true if iflib needs to reinit the interface 2360 */ 2361 static bool 2362 igc_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 2363 { 2364 switch (event) { 2365 case IFLIB_RESTART_VLAN_CONFIG: 2366 default: 2367 return (false); 2368 } 2369 } 2370 2371 /* Export a single 32-bit register via a read-only sysctl. */ 2372 static int 2373 igc_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 2374 { 2375 struct igc_adapter *adapter; 2376 u_int val; 2377 2378 adapter = oidp->oid_arg1; 2379 val = IGC_READ_REG(&adapter->hw, oidp->oid_arg2); 2380 return (sysctl_handle_int(oidp, &val, 0, req)); 2381 } 2382 2383 /* 2384 * Add sysctl variables, one per statistic, to the system. 2385 */ 2386 static void 2387 igc_add_hw_stats(struct igc_adapter *adapter) 2388 { 2389 device_t dev = iflib_get_dev(adapter->ctx); 2390 struct igc_tx_queue *tx_que = adapter->tx_queues; 2391 struct igc_rx_queue *rx_que = adapter->rx_queues; 2392 2393 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 2394 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 2395 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 2396 struct igc_hw_stats *stats = &adapter->stats; 2397 2398 struct sysctl_oid *stat_node, *queue_node, *int_node; 2399 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 2400 2401 #define QUEUE_NAME_LEN 32 2402 char namebuf[QUEUE_NAME_LEN]; 2403 2404 /* Driver Statistics */ 2405 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 2406 CTLFLAG_RD, &adapter->dropped_pkts, 2407 "Driver dropped packets"); 2408 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 2409 CTLFLAG_RD, &adapter->link_irq, 2410 "Link MSI-X IRQ Handled"); 2411 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 2412 CTLFLAG_RD, &adapter->rx_overruns, 2413 "RX overruns"); 2414 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 2415 CTLFLAG_RD, &adapter->watchdog_events, 2416 "Watchdog timeouts"); 2417 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 2418 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 2419 adapter, IGC_CTRL, igc_sysctl_reg_handler, "IU", 2420 "Device Control Register"); 2421 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 2422 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 2423 adapter, IGC_RCTL, igc_sysctl_reg_handler, "IU", 2424 "Receiver Control Register"); 2425 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 2426 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 2427 "Flow Control High Watermark"); 2428 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 2429 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 2430 "Flow Control Low Watermark"); 2431 2432 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 2433 struct tx_ring *txr = &tx_que->txr; 2434 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 2435 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 2436 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 2437 queue_list = SYSCTL_CHILDREN(queue_node); 2438 2439 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 2440 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 2441 IGC_TDH(txr->me), igc_sysctl_reg_handler, "IU", 2442 "Transmit Descriptor Head"); 2443 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 2444 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 2445 IGC_TDT(txr->me), igc_sysctl_reg_handler, "IU", 2446 "Transmit Descriptor Tail"); 2447 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 2448 CTLFLAG_RD, &txr->tx_irq, 2449 "Queue MSI-X Transmit Interrupts"); 2450 } 2451 2452 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 2453 struct rx_ring *rxr = &rx_que->rxr; 2454 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 2455 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 2456 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 2457 queue_list = SYSCTL_CHILDREN(queue_node); 2458 2459 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 2460 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 2461 IGC_RDH(rxr->me), igc_sysctl_reg_handler, "IU", 2462 "Receive Descriptor Head"); 2463 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 2464 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 2465 IGC_RDT(rxr->me), igc_sysctl_reg_handler, "IU", 2466 "Receive Descriptor Tail"); 2467 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 2468 CTLFLAG_RD, &rxr->rx_irq, 2469 "Queue MSI-X Receive Interrupts"); 2470 } 2471 2472 /* MAC stats get their own sub node */ 2473 2474 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 2475 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 2476 stat_list = SYSCTL_CHILDREN(stat_node); 2477 2478 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 2479 CTLFLAG_RD, &stats->ecol, 2480 "Excessive collisions"); 2481 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 2482 CTLFLAG_RD, &stats->scc, 2483 "Single collisions"); 2484 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 2485 CTLFLAG_RD, &stats->mcc, 2486 "Multiple collisions"); 2487 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 2488 CTLFLAG_RD, &stats->latecol, 2489 "Late collisions"); 2490 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 2491 CTLFLAG_RD, &stats->colc, 2492 "Collision Count"); 2493 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 2494 CTLFLAG_RD, &adapter->stats.symerrs, 2495 "Symbol Errors"); 2496 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 2497 CTLFLAG_RD, &adapter->stats.sec, 2498 "Sequence Errors"); 2499 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 2500 CTLFLAG_RD, &adapter->stats.dc, 2501 "Defer Count"); 2502 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 2503 CTLFLAG_RD, &adapter->stats.mpc, 2504 "Missed Packets"); 2505 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 2506 CTLFLAG_RD, &adapter->stats.rnbc, 2507 "Receive No Buffers"); 2508 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 2509 CTLFLAG_RD, &adapter->stats.ruc, 2510 "Receive Undersize"); 2511 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 2512 CTLFLAG_RD, &adapter->stats.rfc, 2513 "Fragmented Packets Received "); 2514 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 2515 CTLFLAG_RD, &adapter->stats.roc, 2516 "Oversized Packets Received"); 2517 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 2518 CTLFLAG_RD, &adapter->stats.rjc, 2519 "Recevied Jabber"); 2520 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 2521 CTLFLAG_RD, &adapter->stats.rxerrc, 2522 "Receive Errors"); 2523 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 2524 CTLFLAG_RD, &adapter->stats.crcerrs, 2525 "CRC errors"); 2526 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 2527 CTLFLAG_RD, &adapter->stats.algnerrc, 2528 "Alignment Errors"); 2529 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 2530 CTLFLAG_RD, &adapter->stats.xonrxc, 2531 "XON Received"); 2532 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 2533 CTLFLAG_RD, &adapter->stats.xontxc, 2534 "XON Transmitted"); 2535 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 2536 CTLFLAG_RD, &adapter->stats.xoffrxc, 2537 "XOFF Received"); 2538 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 2539 CTLFLAG_RD, &adapter->stats.xofftxc, 2540 "XOFF Transmitted"); 2541 2542 /* Packet Reception Stats */ 2543 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 2544 CTLFLAG_RD, &adapter->stats.tpr, 2545 "Total Packets Received "); 2546 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 2547 CTLFLAG_RD, &adapter->stats.gprc, 2548 "Good Packets Received"); 2549 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 2550 CTLFLAG_RD, &adapter->stats.bprc, 2551 "Broadcast Packets Received"); 2552 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 2553 CTLFLAG_RD, &adapter->stats.mprc, 2554 "Multicast Packets Received"); 2555 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 2556 CTLFLAG_RD, &adapter->stats.prc64, 2557 "64 byte frames received "); 2558 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 2559 CTLFLAG_RD, &adapter->stats.prc127, 2560 "65-127 byte frames received"); 2561 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 2562 CTLFLAG_RD, &adapter->stats.prc255, 2563 "128-255 byte frames received"); 2564 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 2565 CTLFLAG_RD, &adapter->stats.prc511, 2566 "256-511 byte frames received"); 2567 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 2568 CTLFLAG_RD, &adapter->stats.prc1023, 2569 "512-1023 byte frames received"); 2570 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 2571 CTLFLAG_RD, &adapter->stats.prc1522, 2572 "1023-1522 byte frames received"); 2573 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 2574 CTLFLAG_RD, &adapter->stats.gorc, 2575 "Good Octets Received"); 2576 2577 /* Packet Transmission Stats */ 2578 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 2579 CTLFLAG_RD, &adapter->stats.gotc, 2580 "Good Octets Transmitted"); 2581 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 2582 CTLFLAG_RD, &adapter->stats.tpt, 2583 "Total Packets Transmitted"); 2584 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 2585 CTLFLAG_RD, &adapter->stats.gptc, 2586 "Good Packets Transmitted"); 2587 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 2588 CTLFLAG_RD, &adapter->stats.bptc, 2589 "Broadcast Packets Transmitted"); 2590 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 2591 CTLFLAG_RD, &adapter->stats.mptc, 2592 "Multicast Packets Transmitted"); 2593 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 2594 CTLFLAG_RD, &adapter->stats.ptc64, 2595 "64 byte frames transmitted "); 2596 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 2597 CTLFLAG_RD, &adapter->stats.ptc127, 2598 "65-127 byte frames transmitted"); 2599 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 2600 CTLFLAG_RD, &adapter->stats.ptc255, 2601 "128-255 byte frames transmitted"); 2602 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 2603 CTLFLAG_RD, &adapter->stats.ptc511, 2604 "256-511 byte frames transmitted"); 2605 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 2606 CTLFLAG_RD, &adapter->stats.ptc1023, 2607 "512-1023 byte frames transmitted"); 2608 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 2609 CTLFLAG_RD, &adapter->stats.ptc1522, 2610 "1024-1522 byte frames transmitted"); 2611 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 2612 CTLFLAG_RD, &adapter->stats.tsctc, 2613 "TSO Contexts Transmitted"); 2614 2615 /* Interrupt Stats */ 2616 2617 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 2618 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 2619 int_list = SYSCTL_CHILDREN(int_node); 2620 2621 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 2622 CTLFLAG_RD, &adapter->stats.iac, 2623 "Interrupt Assertion Count"); 2624 2625 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 2626 CTLFLAG_RD, &adapter->stats.rxdmtc, 2627 "Rx Desc Min Thresh Count"); 2628 } 2629 2630 static void 2631 igc_fw_version(struct igc_adapter *sc) 2632 { 2633 struct igc_hw *hw = &sc->hw; 2634 struct igc_fw_version *fw_ver = &sc->fw_ver; 2635 2636 *fw_ver = (struct igc_fw_version){0}; 2637 2638 igc_get_fw_version(hw, fw_ver); 2639 } 2640 2641 static void 2642 igc_sbuf_fw_version(struct igc_fw_version *fw_ver, struct sbuf *buf) 2643 { 2644 const char *space = ""; 2645 2646 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { 2647 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, 2648 fw_ver->eep_minor, fw_ver->eep_build); 2649 space = " "; 2650 } 2651 2652 if (fw_ver->invm_major || fw_ver->invm_minor || fw_ver->invm_img_type) { 2653 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d", 2654 space, fw_ver->invm_major, fw_ver->invm_minor, 2655 fw_ver->invm_img_type); 2656 space = " "; 2657 } 2658 2659 if (fw_ver->or_valid) { 2660 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 2661 space, fw_ver->or_major, fw_ver->or_build, 2662 fw_ver->or_patch); 2663 space = " "; 2664 } 2665 2666 if (fw_ver->etrack_id) 2667 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); 2668 } 2669 2670 static void 2671 igc_print_fw_version(struct igc_adapter *sc ) 2672 { 2673 device_t dev = sc->dev; 2674 struct sbuf *buf; 2675 int error = 0; 2676 2677 buf = sbuf_new_auto(); 2678 if (!buf) { 2679 device_printf(dev, "Could not allocate sbuf for output.\n"); 2680 return; 2681 } 2682 2683 igc_sbuf_fw_version(&sc->fw_ver, buf); 2684 2685 error = sbuf_finish(buf); 2686 if (error) 2687 device_printf(dev, "Error finishing sbuf: %d\n", error); 2688 else if (sbuf_len(buf)) 2689 device_printf(dev, "%s\n", sbuf_data(buf)); 2690 2691 sbuf_delete(buf); 2692 } 2693 2694 static int 2695 igc_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 2696 { 2697 struct igc_adapter *sc = (struct igc_adapter *)arg1; 2698 device_t dev = sc->dev; 2699 struct sbuf *buf; 2700 int error = 0; 2701 2702 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 2703 if (!buf) { 2704 device_printf(dev, "Could not allocate sbuf for output.\n"); 2705 return (ENOMEM); 2706 } 2707 2708 igc_sbuf_fw_version(&sc->fw_ver, buf); 2709 2710 error = sbuf_finish(buf); 2711 if (error) 2712 device_printf(dev, "Error finishing sbuf: %d\n", error); 2713 2714 sbuf_delete(buf); 2715 2716 return (0); 2717 } 2718 2719 /********************************************************************** 2720 * 2721 * This routine provides a way to dump out the adapter eeprom, 2722 * often a useful debug/service tool. This only dumps the first 2723 * 32 words, stuff that matters is in that extent. 2724 * 2725 **********************************************************************/ 2726 static int 2727 igc_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 2728 { 2729 struct igc_adapter *adapter = (struct igc_adapter *)arg1; 2730 int error; 2731 int result; 2732 2733 result = -1; 2734 error = sysctl_handle_int(oidp, &result, 0, req); 2735 2736 if (error || !req->newptr) 2737 return (error); 2738 2739 /* 2740 * This value will cause a hex dump of the 2741 * first 32 16-bit words of the EEPROM to 2742 * the screen. 2743 */ 2744 if (result == 1) 2745 igc_print_nvm_info(adapter); 2746 2747 return (error); 2748 } 2749 2750 static void 2751 igc_print_nvm_info(struct igc_adapter *adapter) 2752 { 2753 u16 eeprom_data; 2754 int i, j, row = 0; 2755 2756 /* Its a bit crude, but it gets the job done */ 2757 printf("\nInterface EEPROM Dump:\n"); 2758 printf("Offset\n0x0000 "); 2759 for (i = 0, j = 0; i < 32; i++, j++) { 2760 if (j == 8) { /* Make the offset block */ 2761 j = 0; ++row; 2762 printf("\n0x00%x0 ",row); 2763 } 2764 igc_read_nvm(&adapter->hw, i, 1, &eeprom_data); 2765 printf("%04x ", eeprom_data); 2766 } 2767 printf("\n"); 2768 } 2769 2770 /* 2771 * Set flow control using sysctl: 2772 * Flow control values: 2773 * 0 - off 2774 * 1 - rx pause 2775 * 2 - tx pause 2776 * 3 - full 2777 */ 2778 static int 2779 igc_set_flowcntl(SYSCTL_HANDLER_ARGS) 2780 { 2781 int error; 2782 static int input = 3; /* default is full */ 2783 struct igc_adapter *adapter = (struct igc_adapter *) arg1; 2784 2785 error = sysctl_handle_int(oidp, &input, 0, req); 2786 2787 if ((error) || (req->newptr == NULL)) 2788 return (error); 2789 2790 if (input == adapter->fc) /* no change? */ 2791 return (error); 2792 2793 switch (input) { 2794 case igc_fc_rx_pause: 2795 case igc_fc_tx_pause: 2796 case igc_fc_full: 2797 case igc_fc_none: 2798 adapter->hw.fc.requested_mode = input; 2799 adapter->fc = input; 2800 break; 2801 default: 2802 /* Do nothing */ 2803 return (error); 2804 } 2805 2806 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 2807 igc_force_mac_fc(&adapter->hw); 2808 return (error); 2809 } 2810 2811 /* 2812 * Manage Energy Efficient Ethernet: 2813 * Control values: 2814 * 0/1 - enabled/disabled 2815 */ 2816 static int 2817 igc_sysctl_eee(SYSCTL_HANDLER_ARGS) 2818 { 2819 struct igc_adapter *adapter = (struct igc_adapter *) arg1; 2820 int error, value; 2821 2822 value = adapter->hw.dev_spec._i225.eee_disable; 2823 error = sysctl_handle_int(oidp, &value, 0, req); 2824 if (error || req->newptr == NULL) 2825 return (error); 2826 2827 adapter->hw.dev_spec._i225.eee_disable = (value != 0); 2828 igc_if_init(adapter->ctx); 2829 2830 return (0); 2831 } 2832 2833 static int 2834 igc_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 2835 { 2836 struct igc_adapter *adapter; 2837 int error; 2838 int result; 2839 2840 result = -1; 2841 error = sysctl_handle_int(oidp, &result, 0, req); 2842 2843 if (error || !req->newptr) 2844 return (error); 2845 2846 if (result == 1) { 2847 adapter = (struct igc_adapter *) arg1; 2848 igc_print_debug_info(adapter); 2849 } 2850 2851 return (error); 2852 } 2853 2854 static int 2855 igc_get_rs(SYSCTL_HANDLER_ARGS) 2856 { 2857 struct igc_adapter *adapter = (struct igc_adapter *) arg1; 2858 int error; 2859 int result; 2860 2861 result = 0; 2862 error = sysctl_handle_int(oidp, &result, 0, req); 2863 2864 if (error || !req->newptr || result != 1) 2865 return (error); 2866 igc_dump_rs(adapter); 2867 2868 return (error); 2869 } 2870 2871 static void 2872 igc_if_debug(if_ctx_t ctx) 2873 { 2874 igc_dump_rs(iflib_get_softc(ctx)); 2875 } 2876 2877 /* 2878 * This routine is meant to be fluid, add whatever is 2879 * needed for debugging a problem. -jfv 2880 */ 2881 static void 2882 igc_print_debug_info(struct igc_adapter *adapter) 2883 { 2884 device_t dev = iflib_get_dev(adapter->ctx); 2885 if_t ifp = iflib_get_ifp(adapter->ctx); 2886 struct tx_ring *txr = &adapter->tx_queues->txr; 2887 struct rx_ring *rxr = &adapter->rx_queues->rxr; 2888 2889 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2890 printf("Interface is RUNNING "); 2891 else 2892 printf("Interface is NOT RUNNING\n"); 2893 2894 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 2895 printf("and INACTIVE\n"); 2896 else 2897 printf("and ACTIVE\n"); 2898 2899 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 2900 device_printf(dev, "TX Queue %d ------\n", i); 2901 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 2902 IGC_READ_REG(&adapter->hw, IGC_TDH(i)), 2903 IGC_READ_REG(&adapter->hw, IGC_TDT(i))); 2904 2905 } 2906 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 2907 device_printf(dev, "RX Queue %d ------\n", j); 2908 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 2909 IGC_READ_REG(&adapter->hw, IGC_RDH(j)), 2910 IGC_READ_REG(&adapter->hw, IGC_RDT(j))); 2911 } 2912 } 2913