1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2001-2024, Intel Corporation 5 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 6 * Copyright (c) 2021-2024 Rubicon Communications, LLC (Netgate) 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 #include "if_igc.h" 32 #include <sys/sbuf.h> 33 #include <machine/_inttypes.h> 34 35 #include <net/rss_config.h> 36 #include <netinet/in_rss.h> 37 38 39 /********************************************************************* 40 * PCI Device ID Table 41 * 42 * Used by probe to select devices to load on 43 * Last entry must be all 0s 44 * 45 * { Vendor ID, Device ID, String } 46 *********************************************************************/ 47 48 static const pci_vendor_info_t igc_vendor_info_array[] = 49 { 50 /* Intel(R) PRO/1000 Network Connection - igc */ 51 PVID(0x8086, IGC_DEV_ID_I225_LM, 52 "Intel(R) Ethernet Controller I225-LM"), 53 PVID(0x8086, IGC_DEV_ID_I225_V, 54 "Intel(R) Ethernet Controller I225-V"), 55 PVID(0x8086, IGC_DEV_ID_I225_K, 56 "Intel(R) Ethernet Controller I225-K"), 57 PVID(0x8086, IGC_DEV_ID_I225_I, 58 "Intel(R) Ethernet Controller I225-IT"), 59 PVID(0x8086, IGC_DEV_ID_I220_V, 60 "Intel(R) Ethernet Controller I220-V"), 61 PVID(0x8086, IGC_DEV_ID_I225_K2, 62 "Intel(R) Ethernet Controller I225-K(2)"), 63 PVID(0x8086, IGC_DEV_ID_I225_LMVP, 64 "Intel(R) Ethernet Controller I225-LMvP(2)"), 65 PVID(0x8086, IGC_DEV_ID_I226_K, 66 "Intel(R) Ethernet Controller I226-K"), 67 PVID(0x8086, IGC_DEV_ID_I226_LMVP, 68 "Intel(R) Ethernet Controller I226-LMvP"), 69 PVID(0x8086, IGC_DEV_ID_I225_IT, 70 "Intel(R) Ethernet Controller I225-IT(2)"), 71 PVID(0x8086, IGC_DEV_ID_I226_LM, 72 "Intel(R) Ethernet Controller I226-LM"), 73 PVID(0x8086, IGC_DEV_ID_I226_V, 74 "Intel(R) Ethernet Controller I226-V"), 75 PVID(0x8086, IGC_DEV_ID_I226_IT, 76 "Intel(R) Ethernet Controller I226-IT"), 77 PVID(0x8086, IGC_DEV_ID_I221_V, 78 "Intel(R) Ethernet Controller I221-V"), 79 PVID(0x8086, IGC_DEV_ID_I226_BLANK_NVM, 80 "Intel(R) Ethernet Controller I226(blankNVM)"), 81 PVID(0x8086, IGC_DEV_ID_I225_BLANK_NVM, 82 "Intel(R) Ethernet Controller I225(blankNVM)"), 83 /* required last entry */ 84 PVID_END 85 }; 86 87 /********************************************************************* 88 * Function prototypes 89 *********************************************************************/ 90 static void *igc_register(device_t); 91 static int igc_if_attach_pre(if_ctx_t); 92 static int igc_if_attach_post(if_ctx_t); 93 static int igc_if_detach(if_ctx_t); 94 static int igc_if_shutdown(if_ctx_t); 95 static int igc_if_suspend(if_ctx_t); 96 static int igc_if_resume(if_ctx_t); 97 98 static int igc_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, 99 int); 100 static int igc_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, 101 int); 102 static void igc_if_queues_free(if_ctx_t); 103 104 static uint64_t igc_if_get_counter(if_ctx_t, ift_counter); 105 static void igc_if_init(if_ctx_t); 106 static void igc_if_stop(if_ctx_t); 107 static void igc_if_media_status(if_ctx_t, struct ifmediareq *); 108 static int igc_if_media_change(if_ctx_t); 109 static int igc_if_mtu_set(if_ctx_t, uint32_t); 110 static void igc_if_timer(if_ctx_t, uint16_t); 111 static void igc_if_vlan_register(if_ctx_t, u16); 112 static void igc_if_vlan_unregister(if_ctx_t, u16); 113 static bool igc_if_needs_restart(if_ctx_t, enum iflib_restart_event); 114 115 static void igc_identify_hardware(if_ctx_t); 116 static int igc_allocate_pci_resources(if_ctx_t); 117 static void igc_free_pci_resources(if_ctx_t); 118 static void igc_disable_broken_l1_2(if_ctx_t); 119 static int igc_reset(if_ctx_t); 120 static int igc_setup_interface(if_ctx_t); 121 static int igc_setup_msix(if_ctx_t); 122 123 static void igc_initialize_transmit_unit(if_ctx_t); 124 static void igc_initialize_receive_unit(if_ctx_t); 125 126 static void igc_if_intr_enable(if_ctx_t); 127 static void igc_if_intr_disable(if_ctx_t); 128 static int igc_if_rx_queue_intr_enable(if_ctx_t, uint16_t); 129 static int igc_if_tx_queue_intr_enable(if_ctx_t, uint16_t); 130 static void igc_handle_fatal_error_intr(struct igc_softc *, u32); 131 static bool igc_handle_fatal_error_admin(struct igc_softc *); 132 static void igc_prepare_fatal_error_reset(struct igc_softc *); 133 static void igc_finish_fatal_error_reset(struct igc_softc *); 134 static void igc_if_multi_set(if_ctx_t); 135 static void igc_if_update_admin_status(if_ctx_t); 136 static void igc_apply_i225_ipg_workaround(struct igc_softc *); 137 static void igc_if_debug(if_ctx_t); 138 static void igc_update_ecc_stats(struct igc_softc *); 139 static void igc_update_stats_counters(struct igc_softc *); 140 static void igc_add_hw_stats(struct igc_softc *); 141 static int igc_if_set_promisc(if_ctx_t, int); 142 static bool igc_if_vlan_filter_capable(if_ctx_t); 143 static bool igc_if_vlan_filter_used(if_ctx_t); 144 static void igc_if_vlan_filter_enable(struct igc_softc *); 145 static void igc_if_vlan_filter_disable(struct igc_softc *); 146 static void igc_setup_vlan_hw_support(if_ctx_t); 147 static void igc_if_led_func(if_ctx_t, int); 148 static void igc_led_restore(struct igc_softc *); 149 static void igc_fw_version(struct igc_softc *); 150 static void igc_sbuf_fw_version(struct igc_fw_version *, struct sbuf *); 151 static void igc_print_fw_version(struct igc_softc *); 152 static int igc_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS); 153 static int igc_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 154 static void igc_print_nvm_info(struct igc_softc *); 155 static int igc_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 156 static int igc_get_rs(SYSCTL_HANDLER_ARGS); 157 static void igc_print_debug_info(struct igc_softc *); 158 static int igc_is_valid_ether_addr(u8 *); 159 static void igc_neweitr(struct igc_softc *, struct igc_rx_queue *, 160 struct rx_ring *); 161 static int igc_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS); 162 /* Management and WOL Support */ 163 static void igc_get_hw_control(struct igc_softc *); 164 static void igc_release_hw_control(struct igc_softc *); 165 static int igc_enable_pci_busmaster(struct igc_softc *); 166 static void igc_configure_wakeup(if_ctx_t); 167 static int igc_enable_wakeup(if_ctx_t); 168 static void igc_power_up_wakeup_link(struct igc_softc *); 169 170 int igc_intr(void *); 171 172 enum igc_fatal_error_state { 173 IGC_FATAL_ERROR_NONE, 174 IGC_FATAL_ERROR_CAPTURING, 175 IGC_FATAL_ERROR_DETECTED, 176 IGC_FATAL_ERROR_RESET_REQUESTED, 177 }; 178 179 /* MSI-X handlers */ 180 static int igc_if_msix_intr_assign(if_ctx_t, int); 181 static int igc_msix_link(void *); 182 static void igc_handle_link(void *context); 183 184 static int igc_set_flowcntl(SYSCTL_HANDLER_ARGS); 185 static int igc_sysctl_dmac(SYSCTL_HANDLER_ARGS); 186 static int igc_sysctl_eee(SYSCTL_HANDLER_ARGS); 187 188 static int igc_get_regs(SYSCTL_HANDLER_ARGS); 189 190 static void igc_configure_queues(struct igc_softc *); 191 static void igc_initialize_interrupt_rate(struct igc_softc *); 192 193 194 /********************************************************************* 195 * FreeBSD Device Interface Entry Points 196 *********************************************************************/ 197 static device_method_t igc_methods[] = { 198 /* Device interface */ 199 DEVMETHOD(device_register, igc_register), 200 DEVMETHOD(device_probe, iflib_device_probe), 201 DEVMETHOD(device_attach, iflib_device_attach), 202 DEVMETHOD(device_detach, iflib_device_detach), 203 DEVMETHOD(device_shutdown, iflib_device_shutdown), 204 DEVMETHOD(device_suspend, iflib_device_suspend), 205 DEVMETHOD(device_resume, iflib_device_resume), 206 DEVMETHOD_END 207 }; 208 209 static driver_t igc_driver = { 210 "igc", igc_methods, sizeof(struct igc_softc), 211 }; 212 213 DRIVER_MODULE(igc, pci, igc_driver, 0, 0); 214 215 MODULE_DEPEND(igc, pci, 1, 1, 1); 216 MODULE_DEPEND(igc, ether, 1, 1, 1); 217 MODULE_DEPEND(igc, iflib, 1, 1, 1); 218 219 IFLIB_PNP_INFO(pci, igc, igc_vendor_info_array); 220 221 static device_method_t igc_if_methods[] = { 222 DEVMETHOD(ifdi_attach_pre, igc_if_attach_pre), 223 DEVMETHOD(ifdi_attach_post, igc_if_attach_post), 224 DEVMETHOD(ifdi_detach, igc_if_detach), 225 DEVMETHOD(ifdi_shutdown, igc_if_shutdown), 226 DEVMETHOD(ifdi_suspend, igc_if_suspend), 227 DEVMETHOD(ifdi_resume, igc_if_resume), 228 DEVMETHOD(ifdi_init, igc_if_init), 229 DEVMETHOD(ifdi_stop, igc_if_stop), 230 DEVMETHOD(ifdi_msix_intr_assign, igc_if_msix_intr_assign), 231 DEVMETHOD(ifdi_intr_enable, igc_if_intr_enable), 232 DEVMETHOD(ifdi_intr_disable, igc_if_intr_disable), 233 DEVMETHOD(ifdi_tx_queues_alloc, igc_if_tx_queues_alloc), 234 DEVMETHOD(ifdi_rx_queues_alloc, igc_if_rx_queues_alloc), 235 DEVMETHOD(ifdi_queues_free, igc_if_queues_free), 236 DEVMETHOD(ifdi_update_admin_status, igc_if_update_admin_status), 237 DEVMETHOD(ifdi_multi_set, igc_if_multi_set), 238 DEVMETHOD(ifdi_media_status, igc_if_media_status), 239 DEVMETHOD(ifdi_media_change, igc_if_media_change), 240 DEVMETHOD(ifdi_mtu_set, igc_if_mtu_set), 241 DEVMETHOD(ifdi_promisc_set, igc_if_set_promisc), 242 DEVMETHOD(ifdi_timer, igc_if_timer), 243 DEVMETHOD(ifdi_vlan_register, igc_if_vlan_register), 244 DEVMETHOD(ifdi_vlan_unregister, igc_if_vlan_unregister), 245 DEVMETHOD(ifdi_get_counter, igc_if_get_counter), 246 DEVMETHOD(ifdi_rx_queue_intr_enable, igc_if_rx_queue_intr_enable), 247 DEVMETHOD(ifdi_tx_queue_intr_enable, igc_if_tx_queue_intr_enable), 248 DEVMETHOD(ifdi_debug, igc_if_debug), 249 DEVMETHOD(ifdi_needs_restart, igc_if_needs_restart), 250 DEVMETHOD(ifdi_led_func, igc_if_led_func), 251 DEVMETHOD_END 252 }; 253 254 static driver_t igc_if_driver = { 255 "igc_if", igc_if_methods, sizeof(struct igc_softc) 256 }; 257 258 /********************************************************************* 259 * Tunable default values. 260 *********************************************************************/ 261 262 /* Allow common code without TSO */ 263 #ifndef CSUM_TSO 264 #define CSUM_TSO 0 265 #endif 266 267 static SYSCTL_NODE(_hw, OID_AUTO, igc, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 268 "igc driver parameters"); 269 270 static int igc_disable_crc_stripping = 0; 271 SYSCTL_INT(_hw_igc, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 272 &igc_disable_crc_stripping, 0, "Disable CRC Stripping"); 273 274 static int igc_smart_pwr_down = false; 275 SYSCTL_INT(_hw_igc, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, 276 &igc_smart_pwr_down, 277 0, "Set to true to leave smart power down enabled on newer adapters"); 278 279 /* Controls whether promiscuous also shows bad packets */ 280 static int igc_debug_sbp = false; 281 SYSCTL_INT(_hw_igc, OID_AUTO, sbp, CTLFLAG_RDTUN, &igc_debug_sbp, 0, 282 "Show bad packets in promiscuous mode"); 283 284 /* Energy efficient ethernet - default to OFF */ 285 static int igc_eee_setting = 1; 286 SYSCTL_INT(_hw_igc, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &igc_eee_setting, 0, 287 "Enable Energy Efficient Ethernet"); 288 289 /* 290 * AIM: Adaptive Interrupt Moderation 291 * which means that the interrupt rate is varied over time based on the 292 * traffic for that interrupt vector 293 */ 294 static int igc_enable_aim = 1; 295 SYSCTL_INT(_hw_igc, OID_AUTO, enable_aim, CTLFLAG_RWTUN, &igc_enable_aim, 296 0, "Enable adaptive interrupt moderation (1=normal, 2=lowlatency)"); 297 298 /* 299 ** Tuneable Interrupt rate 300 */ 301 static int igc_max_interrupt_rate = IGC_INTS_DEFAULT; 302 SYSCTL_INT(_hw_igc, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 303 &igc_max_interrupt_rate, 0, "Maximum interrupts per second"); 304 305 extern struct if_txrx igc_txrx; 306 307 static struct if_shared_ctx igc_sctx_init = { 308 .isc_magic = IFLIB_MAGIC, 309 .isc_q_align = PAGE_SIZE, 310 .isc_tx_maxsize = IGC_TSO_SIZE + sizeof(struct ether_vlan_header), 311 .isc_tx_maxsegsize = PAGE_SIZE, 312 .isc_tso_maxsize = IGC_TSO_SIZE + sizeof(struct ether_vlan_header), 313 .isc_tso_maxsegsize = IGC_TSO_SEG_SIZE, 314 .isc_rx_maxsize = MAX_JUMBO_FRAME_SIZE, 315 .isc_rx_nsegments = 1, 316 .isc_rx_maxsegsize = MJUM9BYTES, 317 .isc_nfl = 1, 318 .isc_nrxqs = 1, 319 .isc_ntxqs = 1, 320 .isc_admin_intrcnt = 1, 321 .isc_vendor_info = igc_vendor_info_array, 322 .isc_driver_version = "1", 323 .isc_driver = &igc_if_driver, 324 .isc_flags = 325 IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 326 327 .isc_nrxd_min = {IGC_MIN_RXD}, 328 .isc_ntxd_min = {IGC_MIN_TXD}, 329 .isc_nrxd_max = {IGC_MAX_RXD}, 330 .isc_ntxd_max = {IGC_MAX_TXD}, 331 .isc_nrxd_default = {IGC_DEFAULT_RXD}, 332 .isc_ntxd_default = {IGC_DEFAULT_TXD}, 333 }; 334 335 /***************************************************************** 336 * 337 * Dump Registers 338 * 339 ****************************************************************/ 340 #define IGC_REGS_LEN 739 341 342 static int igc_get_regs(SYSCTL_HANDLER_ARGS) 343 { 344 struct igc_softc *sc = (struct igc_softc *)arg1; 345 struct igc_hw *hw = &sc->hw; 346 struct sbuf *sb; 347 u32 *regs_buff; 348 int rc; 349 350 regs_buff = malloc(sizeof(u32) * IGC_REGS_LEN, M_DEVBUF, M_WAITOK); 351 memset(regs_buff, 0, IGC_REGS_LEN * sizeof(u32)); 352 353 rc = sysctl_wire_old_buffer(req, 0); 354 MPASS(rc == 0); 355 if (rc != 0) { 356 free(regs_buff, M_DEVBUF); 357 return (rc); 358 } 359 360 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 361 MPASS(sb != NULL); 362 if (sb == NULL) { 363 free(regs_buff, M_DEVBUF); 364 return (ENOMEM); 365 } 366 367 /* General Registers */ 368 regs_buff[0] = IGC_READ_REG(hw, IGC_CTRL); 369 regs_buff[1] = IGC_READ_REG(hw, IGC_STATUS); 370 regs_buff[2] = IGC_READ_REG(hw, IGC_CTRL_EXT); 371 regs_buff[3] = IGC_READ_REG(hw, IGC_ICR); 372 regs_buff[4] = IGC_READ_REG(hw, IGC_RCTL); 373 regs_buff[5] = IGC_READ_REG(hw, IGC_RDLEN(0)); 374 regs_buff[6] = IGC_READ_REG(hw, IGC_RDH(0)); 375 regs_buff[7] = IGC_READ_REG(hw, IGC_RDT(0)); 376 regs_buff[8] = IGC_READ_REG(hw, IGC_RXDCTL(0)); 377 regs_buff[9] = IGC_READ_REG(hw, IGC_RDBAL(0)); 378 regs_buff[10] = IGC_READ_REG(hw, IGC_RDBAH(0)); 379 regs_buff[11] = IGC_READ_REG(hw, IGC_TCTL); 380 regs_buff[12] = IGC_READ_REG(hw, IGC_TDBAL(0)); 381 regs_buff[13] = IGC_READ_REG(hw, IGC_TDBAH(0)); 382 regs_buff[14] = IGC_READ_REG(hw, IGC_TDLEN(0)); 383 regs_buff[15] = IGC_READ_REG(hw, IGC_TDH(0)); 384 regs_buff[16] = IGC_READ_REG(hw, IGC_TDT(0)); 385 regs_buff[17] = IGC_READ_REG(hw, IGC_TXDCTL(0)); 386 387 sbuf_printf(sb, "General Registers\n"); 388 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 389 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 390 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 391 392 sbuf_printf(sb, "Interrupt Registers\n"); 393 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 394 395 sbuf_printf(sb, "RX Registers\n"); 396 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 397 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 398 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 399 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 400 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 401 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 402 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 403 404 sbuf_printf(sb, "TX Registers\n"); 405 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 406 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 407 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 408 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 409 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 410 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 411 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 412 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 413 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 414 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 415 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 416 417 free(regs_buff, M_DEVBUF); 418 419 #ifdef DUMP_DESCS 420 { 421 if_softc_ctx_t scctx = sc->shared; 422 struct rx_ring *rxr = &rx_que->rxr; 423 struct tx_ring *txr = &tx_que->txr; 424 int ntxd = scctx->isc_ntxd[0]; 425 int nrxd = scctx->isc_nrxd[0]; 426 int j; 427 428 for (j = 0; j < nrxd; j++) { 429 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 430 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 431 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" 432 PRIx64 " Error:%d Length:%d\n", 433 j, rxr->rx_base[j].read.buffer_addr, staterr, length); 434 } 435 436 for (j = 0; j < min(ntxd, 256); j++) { 437 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 438 439 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x" 440 "[3]: %08x eop: %d DD=%d\n", 441 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 442 buf->eop != -1 ? 443 txr->tx_base[buf->eop].upper.fields.status & 444 IGC_TXD_STAT_DD : 0); 445 446 } 447 } 448 #endif 449 450 rc = sbuf_finish(sb); 451 sbuf_delete(sb); 452 return(rc); 453 } 454 455 static void * 456 igc_register(device_t dev) 457 { 458 return (&igc_sctx_init); 459 } 460 461 static int 462 igc_set_num_queues(if_ctx_t ctx) 463 { 464 int maxqueues; 465 466 maxqueues = 4; 467 468 return (maxqueues); 469 } 470 471 #define IGC_CAPS \ 472 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 473 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER | IFCAP_WOL | IFCAP_TSO4 | \ 474 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | \ 475 IFCAP_HWCSUM_IPV6 | IFCAP_TSO6 476 477 /********************************************************************* 478 * Device initialization routine 479 * 480 * The attach entry point is called when the driver is being loaded. 481 * This routine identifies the type of hardware, allocates all resources 482 * and initializes the hardware. 483 * 484 * return 0 on success, positive on failure 485 *********************************************************************/ 486 static int 487 igc_if_attach_pre(if_ctx_t ctx) 488 { 489 struct igc_softc *sc; 490 if_softc_ctx_t scctx; 491 device_t dev; 492 struct igc_hw *hw; 493 int error = 0; 494 495 INIT_DEBUGOUT("igc_if_attach_pre: begin"); 496 dev = iflib_get_dev(ctx); 497 sc = iflib_get_softc(ctx); 498 499 if (igc_max_interrupt_rate <= 0) { 500 device_printf(dev, 501 "Invalid max_interrupt_rate %d; using default %d\n", 502 igc_max_interrupt_rate, IGC_INTS_DEFAULT); 503 igc_max_interrupt_rate = IGC_INTS_DEFAULT; 504 } 505 506 sc->ctx = sc->osdep.ctx = ctx; 507 sc->dev = sc->osdep.dev = dev; 508 scctx = sc->shared = iflib_get_softc_ctx(ctx); 509 sc->media = iflib_get_media(ctx); 510 hw = &sc->hw; 511 512 /* SYSCTL stuff */ 513 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 514 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 515 OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 516 sc, 0, igc_sysctl_nvm_info, "I", "NVM Information"); 517 518 sc->enable_aim = igc_enable_aim; 519 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 520 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 521 OID_AUTO, "enable_aim", CTLFLAG_RW, 522 &sc->enable_aim, 0, 523 "Interrupt Moderation (1=normal, 2=lowlatency)"); 524 525 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 526 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 527 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, 528 sc, 0, igc_sysctl_print_fw_version, "A", 529 "Prints FW/NVM Versions"); 530 531 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 532 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 533 OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 534 sc, 0, igc_sysctl_debug_info, "I", "Debug Information"); 535 536 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 537 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 538 OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 539 sc, 0, igc_set_flowcntl, "I", "Flow Control"); 540 541 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 542 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 543 OID_AUTO, "reg_dump", 544 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, 545 igc_get_regs, "A", "Dump Registers"); 546 547 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 548 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 549 OID_AUTO, "rs_dump", 550 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 551 igc_get_rs, "I", "Dump RS indexes"); 552 553 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 554 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 555 OID_AUTO, "dmac", 556 CTLTYPE_INT | CTLFLAG_RW, sc, 0, 557 igc_sysctl_dmac, "I", "DMA Coalesce"); 558 559 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 560 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 561 OID_AUTO, "tso_tcp_flags_mask_first_segment", 562 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 563 sc, 0, igc_sysctl_tso_tcp_flags_mask, "IU", 564 "TSO TCP flags mask for first segment"); 565 566 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 567 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 568 OID_AUTO, "tso_tcp_flags_mask_middle_segment", 569 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 570 sc, 1, igc_sysctl_tso_tcp_flags_mask, "IU", 571 "TSO TCP flags mask for middle segment"); 572 573 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 574 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 575 OID_AUTO, "tso_tcp_flags_mask_last_segment", 576 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 577 sc, 2, igc_sysctl_tso_tcp_flags_mask, "IU", 578 "TSO TCP flags mask for last segment"); 579 580 /* Determine hardware and mac info */ 581 igc_identify_hardware(ctx); 582 583 /* Apply device-specific PCIe L1.2 errata workarounds. */ 584 igc_disable_broken_l1_2(ctx); 585 586 scctx->isc_tx_nsegments = IGC_MAX_SCATTER; 587 scctx->isc_nrxqsets_max = 588 scctx->isc_ntxqsets_max = igc_set_num_queues(ctx); 589 if (bootverbose) 590 device_printf(dev, "attach_pre capping queues at %d\n", 591 scctx->isc_ntxqsets_max); 592 593 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * 594 sizeof(union igc_adv_tx_desc), IGC_DBA_ALIGN); 595 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * 596 sizeof(union igc_adv_rx_desc), IGC_DBA_ALIGN); 597 scctx->isc_txd_size[0] = sizeof(union igc_adv_tx_desc); 598 scctx->isc_rxd_size[0] = sizeof(union igc_adv_rx_desc); 599 scctx->isc_txrx = &igc_txrx; 600 scctx->isc_tx_tso_segments_max = IGC_MAX_SCATTER; 601 scctx->isc_tx_tso_size_max = IGC_TSO_SIZE; 602 scctx->isc_tx_tso_segsize_max = IGC_TSO_SEG_SIZE; 603 scctx->isc_capabilities = scctx->isc_capenable = IGC_CAPS; 604 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 605 CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_SCTP | CSUM_IP6_SCTP; 606 607 /* 608 ** Some new devices, as with ixgbe, now may 609 ** use a different BAR, so we need to keep 610 ** track of which is used. 611 */ 612 scctx->isc_msix_bar = PCIR_BAR(IGC_MSIX_BAR); 613 if (pci_read_config(dev, scctx->isc_msix_bar, 4) == 0) 614 scctx->isc_msix_bar += 4; 615 616 /* Setup PCI resources */ 617 if (igc_allocate_pci_resources(ctx)) { 618 device_printf(dev, "Allocation of PCI resources failed\n"); 619 error = ENXIO; 620 goto err_pci; 621 } 622 623 /* Do Shared Code initialization */ 624 error = igc_setup_init_funcs(hw, true); 625 if (error) { 626 device_printf(dev, "Setup of Shared code failed, error %d\n", 627 error); 628 error = ENXIO; 629 goto err_pci; 630 } 631 632 igc_setup_msix(ctx); 633 igc_get_bus_info(hw); 634 635 hw->mac.autoneg = DO_AUTO_NEG; 636 hw->phy.autoneg_wait_to_complete = false; 637 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 638 639 /* Copper options */ 640 if (hw->phy.media_type == igc_media_type_copper) { 641 hw->phy.mdix = AUTO_ALL_MODES; 642 } 643 644 /* 645 * Set the frame limits assuming 646 * standard ethernet sized frames. 647 */ 648 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 649 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 650 651 /* Allocate multicast array memory. */ 652 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 653 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 654 if (sc->mta == NULL) { 655 device_printf(dev, 656 "Can not allocate multicast setup array\n"); 657 error = ENOMEM; 658 goto err_late; 659 } 660 661 /* Check SOL/IDER usage */ 662 if (igc_check_reset_block(hw)) 663 device_printf(dev, "PHY reset is blocked" 664 " due to SOL/IDER session.\n"); 665 666 /* Sysctl for setting Energy Efficient Ethernet */ 667 sc->hw.dev_spec._i225.eee_disable = igc_eee_setting; 668 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 669 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 670 OID_AUTO, "eee_control", 671 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 672 sc, 0, igc_sysctl_eee, "I", 673 "Disable Energy Efficient Ethernet"); 674 675 /* 676 ** Start from a known state, this is 677 ** important in reading the nvm and 678 ** mac from that. 679 */ 680 error = igc_reset_hw(hw); 681 if (error != IGC_SUCCESS) { 682 device_printf(dev, "Hardware reset failed: %d\n", error); 683 error = EIO; 684 goto err_late; 685 } 686 687 /* Make sure we have a good EEPROM before we read from it */ 688 if (igc_validate_nvm_checksum(hw) < 0) { 689 /* 690 ** Some PCI-E parts fail the first check due to 691 ** the link being in sleep state, call it again, 692 ** if it fails a second time its a real issue. 693 */ 694 if (igc_validate_nvm_checksum(hw) < 0) { 695 device_printf(dev, 696 "The EEPROM Checksum Is Not Valid\n"); 697 error = EIO; 698 goto err_late; 699 } 700 } 701 702 /* Copy the permanent MAC address out of the EEPROM */ 703 if (igc_read_mac_addr(hw) < 0) { 704 device_printf(dev, "EEPROM read error while reading MAC" 705 " address\n"); 706 error = EIO; 707 goto err_late; 708 } 709 710 if (!igc_is_valid_ether_addr(hw->mac.addr)) { 711 device_printf(dev, "Invalid MAC address\n"); 712 error = EIO; 713 goto err_late; 714 } 715 716 /* Save the EEPROM/NVM versions */ 717 igc_fw_version(sc); 718 719 igc_print_fw_version(sc); 720 721 /* 722 * Get Wake-on-Lan and Management info for later use 723 */ 724 igc_configure_wakeup(ctx); 725 726 iflib_set_mac(ctx, hw->mac.addr); 727 728 return (0); 729 730 err_late: 731 igc_release_hw_control(sc); 732 err_pci: 733 igc_free_pci_resources(ctx); 734 free(sc->mta, M_DEVBUF); 735 736 return (error); 737 } 738 739 static int 740 igc_if_attach_post(if_ctx_t ctx) 741 { 742 struct igc_softc *sc = iflib_get_softc(ctx); 743 struct igc_hw *hw = &sc->hw; 744 int error = 0; 745 746 /* Setup OS specific network interface */ 747 error = igc_setup_interface(ctx); 748 if (error != 0) 749 return (error); 750 751 if (igc_reset(ctx) != IGC_SUCCESS) 752 return (EIO); 753 754 /* Initialize statistics */ 755 igc_update_stats_counters(sc); 756 hw->mac.get_link_status = true; 757 igc_if_update_admin_status(ctx); 758 igc_add_hw_stats(sc); 759 760 /* the driver can now take control from firmware */ 761 igc_get_hw_control(sc); 762 763 INIT_DEBUGOUT("igc_if_attach_post: end"); 764 765 return (error); 766 } 767 768 /********************************************************************* 769 * Device removal routine 770 * 771 * The detach entry point is called when the driver is being removed. 772 * This routine stops the adapter and deallocates all the resources 773 * that were allocated for driver operation. 774 * 775 * return 0 on success, positive on failure 776 *********************************************************************/ 777 static int 778 igc_if_detach(if_ctx_t ctx) 779 { 780 struct igc_softc *sc = iflib_get_softc(ctx); 781 782 INIT_DEBUGOUT("igc_if_detach: begin"); 783 784 igc_phy_hw_reset(&sc->hw); 785 786 igc_release_hw_control(sc); 787 igc_free_pci_resources(ctx); 788 789 return (0); 790 } 791 792 /********************************************************************* 793 * 794 * Shutdown entry point 795 * 796 **********************************************************************/ 797 798 static int 799 igc_if_shutdown(if_ctx_t ctx) 800 { 801 int error; 802 803 error = igc_if_suspend(ctx); 804 if (error != 0) 805 device_printf(iflib_get_dev(ctx), 806 "Wake configuration failed during shutdown: %d\n", error); 807 return (0); 808 } 809 810 /* 811 * Suspend/resume device methods. 812 */ 813 static int 814 igc_if_suspend(if_ctx_t ctx) 815 { 816 struct igc_softc *sc = iflib_get_softc(ctx); 817 int error; 818 819 error = igc_enable_wakeup(ctx); 820 igc_release_hw_control(sc); 821 return (error); 822 } 823 824 static int 825 igc_if_resume(if_ctx_t ctx) 826 { 827 struct igc_softc *sc = iflib_get_softc(ctx); 828 u32 wus, wus_ext; 829 830 /* 831 * PCIe config space, and with it L1.2, may have been reset 832 * across the suspend/resume cycle. 833 */ 834 igc_disable_broken_l1_2(ctx); 835 wus = IGC_READ_REG(&sc->hw, IGC_WUS); 836 wus_ext = IGC_READ_REG(&sc->hw, IGC_WUS_EXT); 837 if (wus != 0 || wus_ext != 0) 838 device_printf(sc->dev, 839 "Wakeup status: %#010x, extended %#010x\n", wus, wus_ext); 840 IGC_WRITE_REG(&sc->hw, IGC_WUFC, 0); 841 IGC_WRITE_REG(&sc->hw, IGC_WUFC_EXT, 0); 842 IGC_WRITE_REG(&sc->hw, IGC_WUC, 0); 843 IGC_WRITE_REG(&sc->hw, IGC_WUS, ~0U); 844 IGC_WRITE_REG(&sc->hw, IGC_WUS_EXT, ~0U); 845 /* Clear PME after its MAC wake source has been removed. */ 846 pci_clear_pme(sc->dev); 847 848 return (0); 849 } 850 851 static int 852 igc_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 853 { 854 int max_frame_size; 855 struct igc_softc *sc = iflib_get_softc(ctx); 856 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 857 858 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 859 860 /* 9K Jumbo Frame size */ 861 max_frame_size = 9234; 862 863 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 864 return (EINVAL); 865 } 866 867 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size = 868 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 869 return (0); 870 } 871 872 /********************************************************************* 873 * Init entry point 874 * 875 * This routine is used in two ways. It is used by the stack as 876 * init entry point in network interface structure. It is also used 877 * by the driver as a hw/sw initialization routine to get to a 878 * consistent state. 879 * 880 **********************************************************************/ 881 static void 882 igc_if_init(if_ctx_t ctx) 883 { 884 struct igc_softc *sc = iflib_get_softc(ctx); 885 if_softc_ctx_t scctx = sc->shared; 886 if_t ifp = iflib_get_ifp(ctx); 887 struct igc_tx_queue *tx_que; 888 int i; 889 890 INIT_DEBUGOUT("igc_if_init: begin"); 891 892 if (igc_enable_pci_busmaster(sc) != 0) { 893 device_printf(sc->dev, "Could not enable PCI bus mastering\n"); 894 iflib_init_failed(ctx); 895 return; 896 } 897 if (sc->suspend_link_powered_down) 898 igc_power_up_wakeup_link(sc); 899 900 /* Get the latest mac address, User can use a LAA */ 901 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, 902 ETHER_ADDR_LEN); 903 904 /* Initialize the hardware */ 905 if (igc_reset(ctx) != IGC_SUCCESS) { 906 iflib_init_failed(ctx); 907 return; 908 } 909 igc_if_update_admin_status(ctx); 910 911 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; 912 i++, tx_que++) { 913 struct tx_ring *txr = &tx_que->txr; 914 915 txr->tx_rs_cidx = txr->tx_rs_pidx; 916 917 /* Initialize the last processed descriptor to be the end of 918 * the ring, rather than the start, so that we avoid an 919 * off-by-one error when calculating how many descriptors are 920 * done in the credits_update function. 921 */ 922 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 923 } 924 925 /* Setup VLAN support, basic and offload if available */ 926 IGC_WRITE_REG(&sc->hw, IGC_VET, ETHERTYPE_VLAN); 927 928 /* Prepare transmit descriptors and buffers */ 929 igc_initialize_transmit_unit(ctx); 930 931 /* Setup Multicast table */ 932 igc_if_multi_set(ctx); 933 934 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 935 igc_initialize_receive_unit(ctx); 936 937 /* Set up VLAN support */ 938 igc_setup_vlan_hw_support(ctx); 939 940 /* Don't lose promiscuous settings */ 941 igc_if_set_promisc(ctx, if_getflags(ifp)); 942 igc_clear_hw_cntrs_base_generic(&sc->hw); 943 944 if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 945 igc_configure_queues(sc); 946 igc_initialize_interrupt_rate(sc); 947 948 /* this clears any pending interrupts */ 949 IGC_READ_REG(&sc->hw, IGC_ICR); 950 IGC_WRITE_REG(&sc->hw, IGC_ICS, IGC_ICS_LSC); 951 952 /* the driver can now take control from firmware */ 953 igc_get_hw_control(sc); 954 955 /* Set Energy Efficient Ethernet */ 956 igc_set_eee_i225(&sc->hw, true, true, true); 957 } 958 959 /* 960 * RX publishes its byte and packet counters as one snapshot when iflib 961 * returns descriptors to hardware. This also covers watchdog-driven RX 962 * processing, which can run while the interrupt vector is unmasked. 963 */ 964 static __inline void 965 igc_aim_rx_delta(struct rx_ring *rxr, u32 *bytes, u32 *packets) 966 { 967 uint64_t snapshot; 968 u32 now_bytes, now_packets; 969 970 snapshot = atomic_load_acq_64(&rxr->rx_aim_snapshot); 971 now_bytes = snapshot >> 32; 972 now_packets = (u32)snapshot; 973 *bytes = now_bytes - rxr->rx_bytes_last; 974 *packets = now_packets - rxr->rx_packets_last; 975 rxr->rx_bytes_last = now_bytes; 976 rxr->rx_packets_last = now_packets; 977 } 978 979 /* 980 * TX publishes its byte and packet counters as one snapshot at the doorbell, 981 * because encapsulation can overlap the interrupt filter. The two halves 982 * remain independent free running u32 counters, so their deltas are correct 983 * across wrap. 984 */ 985 static __inline void 986 igc_aim_tx_delta(struct tx_ring *txr, u32 *bytes, u32 *packets) 987 { 988 uint64_t snapshot; 989 u32 now_bytes, now_packets; 990 991 snapshot = atomic_load_acq_64(&txr->tx_aim_snapshot); 992 now_bytes = snapshot >> 32; 993 now_packets = (u32)snapshot; 994 *bytes = now_bytes - txr->tx_bytes_last; 995 *packets = now_packets - txr->tx_packets_last; 996 txr->tx_bytes_last = now_bytes; 997 txr->tx_packets_last = now_packets; 998 } 999 1000 /********************************************************************* 1001 * 1002 * Do Adaptive Interrupt Moderation: 1003 * - Calculate based on average size over the last interval 1004 * 1005 * Returns interrupts per second rather than a register value, so that the 1006 * caller's IGC_INTS_TO_EITR() conversion applies, or zero if the interval 1007 * carried no packet to measure. 1008 * 1009 *********************************************************************/ 1010 static u32 1011 igc_ring_itr(struct igc_softc *sc, u32 rxbytes, u32 rxpackets, u32 txbytes, 1012 u32 txpackets) 1013 { 1014 u32 newitr = 0; 1015 1016 if (txbytes && txpackets) 1017 newitr = txbytes / txpackets; 1018 if (rxbytes && rxpackets) 1019 newitr = max(newitr, rxbytes / rxpackets); 1020 1021 /* 1022 * No packet was observed, so there is no size to work from. Report no 1023 * observation and let the caller keep the rate it already has. 1024 */ 1025 if (newitr == 0) 1026 return (0); 1027 1028 newitr += 24; /* account for hardware frame, crc */ 1029 /* set an upper boundary */ 1030 newitr = min(newitr, 3000); 1031 /* Be nice to the mid range */ 1032 if ((newitr > 300) && (newitr < 1200)) 1033 newitr = (newitr / 3); 1034 else 1035 newitr = (newitr / 2); 1036 1037 /* The value above was written straight to EITR; make it a rate */ 1038 newitr = IGC_AIM_DIVIDEND / newitr; 1039 1040 /* 1041 * Cap the rate: enable_aim=1 is the normal setting, enable_aim=2 opts 1042 * into the low latency end. The original was unbounded and would ask 1043 * for ~95k ints/s on minimum sized frames. There is deliberately no 1044 * floor, so jumbo traffic settles near 2.7k ints/s. 1045 */ 1046 if (sc->enable_aim == 1) 1047 newitr = min(newitr, IGC_INTS_20K); 1048 else 1049 newitr = min(newitr, IGC_INTS_70K); 1050 1051 return (newitr); 1052 } 1053 1054 /********************************************************************* 1055 * 1056 * Helper to calculate next EITR value for AIM 1057 * 1058 *********************************************************************/ 1059 static void 1060 igc_neweitr(struct igc_softc *sc, struct igc_rx_queue *que, 1061 struct rx_ring *rxr) 1062 { 1063 struct igc_hw *hw = &sc->hw; 1064 struct igc_tx_queue *tx_que; 1065 u32 ringbytes, ringpackets, rxbytes, rxpackets, txbytes, txpackets; 1066 u32 neweitr; 1067 int i; 1068 1069 igc_aim_rx_delta(rxr, &rxbytes, &rxpackets); 1070 1071 /* 1072 * A vector can service more than one TX ring when iflib is configured 1073 * with unequal RX and TX queue counts. Sample every ring routed to 1074 * this vector rather than treating the vector as a TX queue index. 1075 */ 1076 txbytes = txpackets = 0; 1077 for (i = 0; i < sc->tx_num_queues; i++) { 1078 tx_que = &sc->tx_queues[i]; 1079 if (tx_que->msix != que->msix) 1080 continue; 1081 igc_aim_tx_delta(&tx_que->txr, &ringbytes, &ringpackets); 1082 txbytes += ringbytes; 1083 txpackets += ringpackets; 1084 } 1085 1086 /* Idle, do nothing */ 1087 if (txbytes == 0 && rxbytes == 0) 1088 return; 1089 1090 if (sc->enable_aim == 0) { 1091 neweitr = igc_max_interrupt_rate; 1092 } else if (sc->link_speed < SPEED_1000) { 1093 /* Use half default (4K) ITR if sub-gig */ 1094 neweitr = IGC_INTS_4K; 1095 } else if (sc->shared->isc_max_frame_size * 2 > (sc->pba << 10)) { 1096 /* Want at least enough packet buffer for two frames to AIM */ 1097 neweitr = igc_max_interrupt_rate; 1098 } else { 1099 neweitr = igc_ring_itr(sc, rxbytes, rxpackets, txbytes, 1100 txpackets); 1101 /* No usable observation; leave the rate where it is */ 1102 if (neweitr == 0) 1103 return; 1104 } 1105 1106 neweitr = IGC_INTS_TO_EITR(neweitr); 1107 1108 neweitr |= IGC_EITR_CNT_IGNR; 1109 1110 if (neweitr != que->eitr_setting) { 1111 que->eitr_setting = neweitr; 1112 IGC_WRITE_REG(hw, IGC_EITR(que->msix), que->eitr_setting); 1113 } 1114 } 1115 1116 /********************************************************************* 1117 * 1118 * Fast Legacy/MSI Combined Interrupt Service routine 1119 * 1120 *********************************************************************/ 1121 int 1122 igc_intr(void *arg) 1123 { 1124 struct igc_softc *sc = arg; 1125 struct igc_hw *hw = &sc->hw; 1126 struct igc_rx_queue *que = &sc->rx_queues[0]; 1127 struct rx_ring *rxr = &que->rxr; 1128 if_ctx_t ctx = sc->ctx; 1129 u32 reg_icr; 1130 1131 reg_icr = IGC_READ_REG(hw, IGC_ICR); 1132 1133 /* Hot eject? */ 1134 if (reg_icr == 0xffffffff) 1135 return FILTER_STRAY; 1136 1137 /* Definitely not our interrupt. */ 1138 if (reg_icr == 0x0) 1139 return FILTER_STRAY; 1140 1141 if ((reg_icr & IGC_ICR_INT_ASSERTED) == 0) 1142 return FILTER_STRAY; 1143 1144 /* 1145 * Only MSI-X interrupts have one-shot behavior by taking advantage 1146 * of the EIAC register. Thus, explicitly disable interrupts. This 1147 * also works around the MSI message reordering errata on certain 1148 * systems. 1149 */ 1150 IFDI_INTR_DISABLE(ctx); 1151 1152 /* Link status change */ 1153 if (reg_icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) 1154 igc_handle_link(ctx); 1155 1156 if (reg_icr & IGC_ICR_RXO) 1157 sc->rx_overruns++; 1158 1159 igc_handle_fatal_error_intr(sc, reg_icr); 1160 1161 igc_neweitr(sc, que, rxr); 1162 1163 return (FILTER_SCHEDULE_THREAD); 1164 } 1165 1166 static int 1167 igc_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 1168 { 1169 struct igc_softc *sc = iflib_get_softc(ctx); 1170 struct igc_rx_queue *rxq = &sc->rx_queues[rxqid]; 1171 1172 IGC_WRITE_REG(&sc->hw, IGC_EIMS, rxq->eims); 1173 return (0); 1174 } 1175 1176 static int 1177 igc_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 1178 { 1179 struct igc_softc *sc = iflib_get_softc(ctx); 1180 struct igc_tx_queue *txq = &sc->tx_queues[txqid]; 1181 1182 IGC_WRITE_REG(&sc->hw, IGC_EIMS, txq->eims); 1183 return (0); 1184 } 1185 1186 /********************************************************************* 1187 * 1188 * MSI-X RX Interrupt Service routine 1189 * 1190 **********************************************************************/ 1191 static int 1192 igc_msix_que(void *arg) 1193 { 1194 struct igc_rx_queue *que = arg; 1195 struct igc_softc *sc = que->sc; 1196 struct rx_ring *rxr = &que->rxr; 1197 1198 ++que->irqs; 1199 1200 igc_neweitr(sc, que, rxr); 1201 1202 return (FILTER_SCHEDULE_THREAD); 1203 } 1204 1205 /********************************************************************* 1206 * 1207 * MSI-X Link Fast Interrupt Service routine 1208 * 1209 **********************************************************************/ 1210 static int 1211 igc_msix_link(void *arg) 1212 { 1213 struct igc_softc *sc = arg; 1214 u32 reg_icr; 1215 1216 ++sc->link_irq; 1217 MPASS(sc->hw.back != NULL); 1218 reg_icr = IGC_READ_REG(&sc->hw, IGC_ICR); 1219 1220 if (reg_icr & IGC_ICR_RXO) 1221 sc->rx_overruns++; 1222 1223 if (reg_icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) { 1224 igc_handle_link(sc->ctx); 1225 } 1226 igc_handle_fatal_error_intr(sc, reg_icr); 1227 1228 reg_icr = IGC_IMS_LSC; 1229 if (atomic_load_acq_32(&sc->fatal_error_state) == 1230 IGC_FATAL_ERROR_NONE) 1231 reg_icr |= IGC_IMS_FER; 1232 IGC_WRITE_REG(&sc->hw, IGC_IMS, reg_icr); 1233 IGC_WRITE_REG(&sc->hw, IGC_EIMS, sc->link_mask); 1234 1235 return (FILTER_HANDLED); 1236 } 1237 1238 static void 1239 igc_handle_link(void *context) 1240 { 1241 if_ctx_t ctx = context; 1242 struct igc_softc *sc = iflib_get_softc(ctx); 1243 1244 sc->hw.mac.get_link_status = true; 1245 iflib_admin_intr_deferred(ctx); 1246 } 1247 1248 /* 1249 * Fatal internal memory errors stop some or all device traffic. Capture the 1250 * read-clear indication before handing recovery to the iflib admin task. 1251 */ 1252 static void 1253 igc_handle_fatal_error_intr(struct igc_softc *sc, u32 icr) 1254 { 1255 struct igc_hw *hw; 1256 u32 lanerr, mngerr, pcieerr, peind; 1257 1258 if ((icr & IGC_ICR_FER) == 0) 1259 return; 1260 1261 hw = &sc->hw; 1262 IGC_WRITE_REG(hw, IGC_IMC, IGC_IMS_FER); 1263 if (!atomic_cmpset_32(&sc->fatal_error_state, 1264 IGC_FATAL_ERROR_NONE, IGC_FATAL_ERROR_CAPTURING)) 1265 return; 1266 1267 peind = IGC_READ_REG(hw, IGC_PEIND) & IGC_PEIND_FATAL_MASK; 1268 pcieerr = IGC_READ_REG(hw, IGC_PCIEERRSTS) & 1269 IGC_PCIEERRSTS_FATAL_MASK; 1270 lanerr = IGC_READ_REG(hw, IGC_LANPERRSTS) & 1271 IGC_LANPERRSTS_RETX_BUF; 1272 mngerr = IGC_READ_REG(hw, IGC_MNGPARSTS) & 1273 IGC_MNGPARSTS_FATAL_MASK; 1274 if (pcieerr != 0) 1275 peind |= IGC_PEIND_PCIE_PARITY_FATAL; 1276 if (lanerr != 0) 1277 peind |= IGC_PEIND_LANPORT_PARITY_FATAL; 1278 1279 sc->fatal_error_peind = peind; 1280 sc->fatal_error_pcie = pcieerr; 1281 sc->fatal_error_lan = lanerr; 1282 sc->fatal_error_mng = mngerr; 1283 atomic_store_rel_32(&sc->fatal_error_state, 1284 IGC_FATAL_ERROR_DETECTED); 1285 iflib_admin_intr_deferred(sc->ctx); 1286 } 1287 1288 static bool 1289 igc_handle_fatal_error_admin(struct igc_softc *sc) 1290 { 1291 u32 peind; 1292 1293 if (!atomic_cmpset_acq_32(&sc->fatal_error_state, 1294 IGC_FATAL_ERROR_DETECTED, IGC_FATAL_ERROR_RESET_REQUESTED)) 1295 return (atomic_load_acq_32(&sc->fatal_error_state) != 1296 IGC_FATAL_ERROR_NONE); 1297 1298 peind = sc->fatal_error_peind; 1299 if (peind & IGC_PEIND_LANPORT_PARITY_FATAL) 1300 sc->fatal_error_lan_count++; 1301 if (peind & IGC_PEIND_MNG_PARITY_FATAL) 1302 sc->fatal_error_mng_count++; 1303 if (peind & IGC_PEIND_PCIE_PARITY_FATAL) 1304 sc->fatal_error_pcie_count++; 1305 if (peind & IGC_PEIND_DMA_PARITY_FATAL) 1306 sc->fatal_error_dma_count++; 1307 if (peind == 0) 1308 sc->fatal_error_unknown_count++; 1309 1310 device_printf(sc->dev, 1311 "fatal internal memory error: PEIND %#x, PCIEERRSTS %#x, " 1312 "LANPERRSTS %#x, MNGPARSTS %#x\n", 1313 peind, sc->fatal_error_pcie, sc->fatal_error_lan, 1314 sc->fatal_error_mng); 1315 /* Management-memory recovery is owned by management firmware. */ 1316 if (peind != 0 && (peind & IGC_PEIND_HOST_FATAL_MASK) == 0) { 1317 sc->fatal_error_peind = 0; 1318 sc->fatal_error_pcie = 0; 1319 sc->fatal_error_lan = 0; 1320 sc->fatal_error_mng = 0; 1321 atomic_store_rel_32(&sc->fatal_error_state, 1322 IGC_FATAL_ERROR_NONE); 1323 IGC_WRITE_REG(&sc->hw, IGC_IMS, IGC_IMS_FER); 1324 IGC_WRITE_FLUSH(&sc->hw); 1325 return (true); 1326 } 1327 1328 device_printf(sc->dev, "requesting reset after memory error\n"); 1329 iflib_request_reset(sc->ctx); 1330 /* Re-enter the admin task so it observes the reset request. */ 1331 iflib_admin_intr_deferred(sc->ctx); 1332 return (true); 1333 } 1334 1335 /********************************************************************* 1336 * 1337 * Media Ioctl callback 1338 * 1339 * This routine is called whenever the user queries the status of 1340 * the interface using ifconfig. 1341 * 1342 **********************************************************************/ 1343 static void 1344 igc_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1345 { 1346 struct igc_softc *sc = iflib_get_softc(ctx); 1347 1348 INIT_DEBUGOUT("igc_if_media_status: begin"); 1349 1350 iflib_admin_intr_deferred(ctx); 1351 1352 ifmr->ifm_status = IFM_AVALID; 1353 ifmr->ifm_active = IFM_ETHER; 1354 1355 if (!sc->link_active) { 1356 return; 1357 } 1358 1359 ifmr->ifm_status |= IFM_ACTIVE; 1360 1361 switch (sc->link_speed) { 1362 case 10: 1363 ifmr->ifm_active |= IFM_10_T; 1364 break; 1365 case 100: 1366 ifmr->ifm_active |= IFM_100_TX; 1367 break; 1368 case 1000: 1369 ifmr->ifm_active |= IFM_1000_T; 1370 break; 1371 case 2500: 1372 ifmr->ifm_active |= IFM_2500_T; 1373 break; 1374 } 1375 1376 if (sc->link_duplex == FULL_DUPLEX) 1377 ifmr->ifm_active |= IFM_FDX; 1378 else 1379 ifmr->ifm_active |= IFM_HDX; 1380 } 1381 1382 /********************************************************************* 1383 * 1384 * Media Ioctl callback 1385 * 1386 * This routine is called when the user changes speed/duplex using 1387 * media/mediopt option with ifconfig. 1388 * 1389 **********************************************************************/ 1390 static int 1391 igc_if_media_change(if_ctx_t ctx) 1392 { 1393 struct igc_softc *sc = iflib_get_softc(ctx); 1394 struct ifmedia *ifm = iflib_get_media(ctx); 1395 1396 INIT_DEBUGOUT("igc_if_media_change: begin"); 1397 1398 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1399 return (EINVAL); 1400 1401 sc->hw.mac.autoneg = DO_AUTO_NEG; 1402 1403 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1404 case IFM_AUTO: 1405 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1406 break; 1407 case IFM_2500_T: 1408 sc->hw.phy.autoneg_advertised = ADVERTISE_2500_FULL; 1409 break; 1410 case IFM_1000_T: 1411 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1412 break; 1413 case IFM_100_TX: 1414 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1415 sc->hw.phy.autoneg_advertised = ADVERTISE_100_FULL; 1416 else 1417 sc->hw.phy.autoneg_advertised = ADVERTISE_100_HALF; 1418 break; 1419 case IFM_10_T: 1420 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1421 sc->hw.phy.autoneg_advertised = ADVERTISE_10_FULL; 1422 else 1423 sc->hw.phy.autoneg_advertised = ADVERTISE_10_HALF; 1424 break; 1425 default: 1426 device_printf(sc->dev, "Unsupported media type\n"); 1427 } 1428 1429 return (0); 1430 } 1431 1432 static int 1433 igc_if_set_promisc(if_ctx_t ctx, int flags) 1434 { 1435 struct igc_softc *sc = iflib_get_softc(ctx); 1436 if_t ifp = iflib_get_ifp(ctx); 1437 u32 reg_rctl; 1438 int mcnt = 0; 1439 1440 reg_rctl = IGC_READ_REG(&sc->hw, IGC_RCTL); 1441 reg_rctl &= ~(IGC_RCTL_SBP | IGC_RCTL_UPE); 1442 if (flags & IFF_ALLMULTI) 1443 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1444 else 1445 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1446 1447 /* Don't disable if in MAX groups */ 1448 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1449 reg_rctl &= ~IGC_RCTL_MPE; 1450 1451 if (flags & IFF_PROMISC) { 1452 reg_rctl |= (IGC_RCTL_UPE | IGC_RCTL_MPE); 1453 /* Turn this on if you want to see bad packets */ 1454 if (igc_debug_sbp) 1455 reg_rctl |= IGC_RCTL_SBP; 1456 } else if (flags & IFF_ALLMULTI) { 1457 reg_rctl |= IGC_RCTL_MPE; 1458 reg_rctl &= ~IGC_RCTL_UPE; 1459 } 1460 1461 if ((flags & IFF_PROMISC) || !igc_if_vlan_filter_used(ctx)) 1462 reg_rctl &= ~IGC_RCTL_VFE; 1463 else 1464 reg_rctl |= IGC_RCTL_VFE; 1465 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg_rctl); 1466 1467 return (0); 1468 } 1469 1470 static u_int 1471 igc_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1472 { 1473 u8 *mta = arg; 1474 1475 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1476 return (0); 1477 1478 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1479 1480 return (1); 1481 } 1482 1483 /********************************************************************* 1484 * Multicast Update 1485 * 1486 * This routine is called whenever multicast address list is updated. 1487 * 1488 **********************************************************************/ 1489 1490 static void 1491 igc_if_multi_set(if_ctx_t ctx) 1492 { 1493 struct igc_softc *sc = iflib_get_softc(ctx); 1494 if_t ifp = iflib_get_ifp(ctx); 1495 u8 *mta; /* Multicast array memory */ 1496 u32 reg_rctl = 0; 1497 int mcnt = 0; 1498 1499 IOCTL_DEBUGOUT("igc_set_multi: begin"); 1500 1501 mta = sc->mta; 1502 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1503 1504 mcnt = if_foreach_llmaddr(ifp, igc_copy_maddr, mta); 1505 1506 reg_rctl = IGC_READ_REG(&sc->hw, IGC_RCTL); 1507 1508 if (if_getflags(ifp) & IFF_PROMISC) { 1509 reg_rctl |= (IGC_RCTL_UPE | IGC_RCTL_MPE); 1510 /* Turn this on if you want to see bad packets */ 1511 if (igc_debug_sbp) 1512 reg_rctl |= IGC_RCTL_SBP; 1513 } else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1514 if_getflags(ifp) & IFF_ALLMULTI) { 1515 reg_rctl |= IGC_RCTL_MPE; 1516 reg_rctl &= ~IGC_RCTL_UPE; 1517 } else 1518 reg_rctl &= ~(IGC_RCTL_UPE | IGC_RCTL_MPE); 1519 1520 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1521 igc_update_mc_addr_list(&sc->hw, mta, mcnt); 1522 1523 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg_rctl); 1524 } 1525 1526 /********************************************************************* 1527 * Timer routine 1528 * 1529 * This routine schedules igc_if_update_admin_status() to check for 1530 * link status and to gather statistics as well as to perform some 1531 * controller-specific hardware patting. 1532 * 1533 **********************************************************************/ 1534 static void 1535 igc_if_timer(if_ctx_t ctx, uint16_t qid) 1536 { 1537 1538 if (qid != 0) 1539 return; 1540 1541 iflib_admin_intr_deferred(ctx); 1542 } 1543 1544 static void 1545 igc_apply_i225_ipg_workaround(struct igc_softc *sc) 1546 { 1547 struct igc_hw *hw = &sc->hw; 1548 u32 ipgt, tipg; 1549 1550 /* 1551 * I225 v1 cannot receive the minimum IPG required at 2.5 Gb/s. 1552 * Intel's documented back-to-back workaround is for the transmitter 1553 * to use a 15-byte IPG instead of 12 bytes. I225 v2 and later have 1554 * the receive-side fix and should retain the standard IPG. 1555 */ 1556 if (!igc_is_device_id_i225(hw) || 1557 hw->revision_id >= IGC_REVISION_2) 1558 return; 1559 1560 ipgt = sc->link_speed == SPEED_2500 ? IGC_I225_TIPG_IPGT_2P5 : 1561 DEFAULT_82543_TIPG_IPGT_COPPER; 1562 tipg = IGC_READ_REG(hw, IGC_TIPG); 1563 if ((tipg & IGC_TIPG_IPGT_MASK) == ipgt) 1564 return; 1565 1566 tipg &= ~IGC_TIPG_IPGT_MASK; 1567 tipg |= ipgt; 1568 IGC_WRITE_REG(hw, IGC_TIPG, tipg); 1569 } 1570 1571 static void 1572 igc_if_update_admin_status(if_ctx_t ctx) 1573 { 1574 struct igc_softc *sc = iflib_get_softc(ctx); 1575 struct igc_hw *hw = &sc->hw; 1576 device_t dev = iflib_get_dev(ctx); 1577 u32 link_check, thstat, ctrl; 1578 1579 if (igc_handle_fatal_error_admin(sc)) 1580 return; 1581 1582 link_check = thstat = ctrl = 0; 1583 /* Get the cached link value or read phy for real */ 1584 switch (hw->phy.media_type) { 1585 case igc_media_type_copper: 1586 if (hw->mac.get_link_status == true) { 1587 /* Do the work to read phy */ 1588 igc_check_for_link(hw); 1589 link_check = !hw->mac.get_link_status; 1590 } else 1591 link_check = true; 1592 break; 1593 case igc_media_type_unknown: 1594 igc_check_for_link(hw); 1595 link_check = !hw->mac.get_link_status; 1596 /* FALLTHROUGH */ 1597 default: 1598 break; 1599 } 1600 1601 /* Now check for a transition */ 1602 if (link_check && (sc->link_active == 0)) { 1603 igc_get_speed_and_duplex(hw, &sc->link_speed, 1604 &sc->link_duplex); 1605 if (bootverbose) 1606 device_printf(dev, "Link is up %d Mbps %s\n", 1607 sc->link_speed, 1608 ((sc->link_duplex == FULL_DUPLEX) ? 1609 "Full Duplex" : "Half Duplex")); 1610 sc->link_active = 1; 1611 iflib_link_state_change(ctx, LINK_STATE_UP, 1612 IF_Mbps(sc->link_speed)); 1613 } else if (!link_check && (sc->link_active == 1)) { 1614 sc->link_speed = 0; 1615 sc->link_duplex = 0; 1616 sc->link_active = 0; 1617 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1618 } 1619 igc_apply_i225_ipg_workaround(sc); 1620 igc_update_stats_counters(sc); 1621 } 1622 1623 /********************************************************************* 1624 * 1625 * This routine disables all traffic on the adapter by issuing a 1626 * global reset on the MAC. 1627 * 1628 **********************************************************************/ 1629 static void 1630 igc_if_stop(if_ctx_t ctx) 1631 { 1632 struct igc_softc *sc = iflib_get_softc(ctx); 1633 s32 error; 1634 1635 INIT_DEBUGOUT("igc_if_stop: begin"); 1636 1637 igc_led_restore(sc); 1638 igc_prepare_fatal_error_reset(sc); 1639 error = igc_reset_hw(&sc->hw); 1640 if (error != IGC_SUCCESS) { 1641 device_printf(sc->dev, "Hardware reset failed while stopping: " 1642 "%d\n", error); 1643 return; 1644 } 1645 igc_finish_fatal_error_reset(sc); 1646 IGC_WRITE_REG(&sc->hw, IGC_WUC, 0); 1647 } 1648 1649 /* 1650 * A PCIe-region parity failure stops PCIe and DMA traffic. Intel requires a 1651 * device reset before master disable in this case, unlike the normal reset 1652 * path, which disables the bus master first. 1653 */ 1654 static void 1655 igc_prepare_fatal_error_reset(struct igc_softc *sc) 1656 { 1657 struct igc_hw *hw; 1658 s32 error; 1659 u32 ctrl, pcieerr; 1660 int i; 1661 1662 if (atomic_load_acq_32(&sc->fatal_error_state) == 1663 IGC_FATAL_ERROR_NONE) 1664 return; 1665 1666 hw = &sc->hw; 1667 pcieerr = sc->fatal_error_pcie | 1668 (IGC_READ_REG(hw, IGC_PCIEERRSTS) & IGC_PCIEERRSTS_FATAL_MASK); 1669 if ((sc->fatal_error_peind & IGC_PEIND_PCIE_PARITY_FATAL) == 0 && 1670 pcieerr == 0) 1671 return; 1672 1673 ctrl = IGC_READ_REG(hw, IGC_CTRL); 1674 IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_DEV_RST); 1675 /* Do not access device registers for at least 3 ms after DEV_RST. */ 1676 msec_delay(3); 1677 for (i = 0; i < AUTO_READ_DONE_TIMEOUT; i++) { 1678 if ((IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_AUTO_RD) != 0 && 1679 (IGC_READ_REG(hw, IGC_STATUS) & IGC_STATUS_RST_DONE) != 0) 1680 break; 1681 msec_delay(1); 1682 } 1683 if (i == AUTO_READ_DONE_TIMEOUT) 1684 device_printf(sc->dev, 1685 "device reset did not complete during parity recovery\n"); 1686 error = igc_disable_pcie_master_generic(hw); 1687 if (error != IGC_SUCCESS) 1688 device_printf(sc->dev, 1689 "PCIe master disable failed during parity recovery: %d\n", 1690 error); 1691 pcieerr |= IGC_READ_REG(hw, IGC_PCIEERRSTS) & 1692 IGC_PCIEERRSTS_FATAL_MASK; 1693 if (pcieerr != 0) 1694 IGC_WRITE_REG(hw, IGC_PCIEERRSTS, pcieerr); 1695 } 1696 1697 static void 1698 igc_finish_fatal_error_reset(struct igc_softc *sc) 1699 { 1700 struct igc_hw *hw; 1701 u32 lanerr, pcieerr; 1702 1703 if (atomic_load_acq_32(&sc->fatal_error_state) == 1704 IGC_FATAL_ERROR_NONE) 1705 return; 1706 1707 hw = &sc->hw; 1708 pcieerr = sc->fatal_error_pcie | 1709 (IGC_READ_REG(hw, IGC_PCIEERRSTS) & IGC_PCIEERRSTS_FATAL_MASK); 1710 if (pcieerr != 0) 1711 IGC_WRITE_REG(hw, IGC_PCIEERRSTS, pcieerr); 1712 lanerr = sc->fatal_error_lan | 1713 (IGC_READ_REG(hw, IGC_LANPERRSTS) & IGC_LANPERRSTS_RETX_BUF); 1714 if (lanerr != 0) 1715 IGC_WRITE_REG(hw, IGC_LANPERRSTS, lanerr); 1716 /* 1717 * DEV_RST can relatch PEIND from a subordinate status register 1718 * before that register is cleared. Drain the recovered indication 1719 * before unmasking FER so a later error is not misattributed. 1720 */ 1721 (void)IGC_READ_REG(hw, IGC_PEIND); 1722 1723 sc->fatal_error_peind = 0; 1724 sc->fatal_error_pcie = 0; 1725 sc->fatal_error_lan = 0; 1726 sc->fatal_error_mng = 0; 1727 atomic_store_rel_32(&sc->fatal_error_state, IGC_FATAL_ERROR_NONE); 1728 } 1729 1730 /* 1731 * I225/I226 have three configurable LED outputs. DPDK uses LED1 for 1732 * adapter identification; retain that convention and preserve the OEM's 1733 * configuration for normal link and activity indication. 1734 */ 1735 static void 1736 igc_if_led_func(if_ctx_t ctx, int onoff) 1737 { 1738 struct igc_softc *sc; 1739 struct igc_hw *hw; 1740 u32 ledctl; 1741 1742 sc = iflib_get_softc(ctx); 1743 hw = &sc->hw; 1744 if (onoff) { 1745 if (!sc->led_active) { 1746 sc->ledctl_default = IGC_READ_REG(hw, IGC_LEDCTL); 1747 sc->led_active = true; 1748 } 1749 ledctl = sc->ledctl_default; 1750 ledctl &= ~(IGC_LEDCTL_LED1_MODE_MASK | 1751 IGC_LEDCTL_LED1_BLINK); 1752 ledctl |= IGC_LEDCTL_MODE_LED_ON << 1753 IGC_LEDCTL_LED1_MODE_SHIFT; 1754 IGC_WRITE_REG(hw, IGC_LEDCTL, ledctl); 1755 } else { 1756 igc_led_restore(sc); 1757 } 1758 } 1759 1760 static void 1761 igc_led_restore(struct igc_softc *sc) 1762 { 1763 1764 if (!sc->led_active) 1765 return; 1766 IGC_WRITE_REG(&sc->hw, IGC_LEDCTL, sc->ledctl_default); 1767 sc->led_active = false; 1768 } 1769 1770 /********************************************************************* 1771 * 1772 * Determine hardware revision. 1773 * 1774 **********************************************************************/ 1775 static void 1776 igc_identify_hardware(if_ctx_t ctx) 1777 { 1778 device_t dev = iflib_get_dev(ctx); 1779 struct igc_softc *sc = iflib_get_softc(ctx); 1780 1781 /* Make sure our PCI config space has the necessary stuff set */ 1782 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1783 1784 /* Save off the information about this board */ 1785 sc->hw.vendor_id = pci_get_vendor(dev); 1786 sc->hw.device_id = pci_get_device(dev); 1787 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1788 sc->hw.subsystem_vendor_id = 1789 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1790 sc->hw.subsystem_device_id = 1791 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1792 1793 /* Do Shared Code Init and Setup */ 1794 if (igc_set_mac_type(&sc->hw)) { 1795 device_printf(dev, "Setup init failure\n"); 1796 return; 1797 } 1798 } 1799 1800 /********************************************************************* 1801 * 1802 * Intel's I225/I226 Specification Update, erratum 2, states that I225 1803 * devices can incorrectly enter L1 substates while CLKREQ# is asserted, 1804 * causing repeated L1-substate entry and exit. Disable both ASPM and 1805 * PCI-PM L1.2, as the erratum can occur while idle or in D3. 1806 * 1807 * I226 devices have a separate erratum where ASPM L1.2 exit latency can 1808 * exceed what the packet buffer can tolerate under load. Disabling ASPM 1809 * L1.2 on the device itself works around the issue. 1810 * 1811 **********************************************************************/ 1812 static void 1813 igc_disable_broken_l1_2(if_ctx_t ctx) 1814 { 1815 device_t dev = iflib_get_dev(ctx); 1816 struct igc_softc *sc = iflib_get_softc(ctx); 1817 int cap; 1818 uint32_t ctl1, mask; 1819 1820 if (igc_is_device_id_i225(&sc->hw)) 1821 mask = PCIM_L1PM_CTL1_ASPM_L1_2 | 1822 PCIM_L1PM_CTL1_PCIPM_L1_2; 1823 else if (igc_is_device_id_i226(&sc->hw)) 1824 mask = PCIM_L1PM_CTL1_ASPM_L1_2; 1825 else 1826 return; 1827 1828 if (pci_find_extcap(dev, PCIZ_L1PM, &cap) != 0) 1829 return; 1830 1831 ctl1 = pci_read_config(dev, cap + PCIR_L1PM_CTL1, 4); 1832 ctl1 &= ~mask; 1833 pci_write_config(dev, cap + PCIR_L1PM_CTL1, ctl1, 4); 1834 } 1835 1836 static int 1837 igc_allocate_pci_resources(if_ctx_t ctx) 1838 { 1839 struct igc_softc *sc = iflib_get_softc(ctx); 1840 device_t dev = iflib_get_dev(ctx); 1841 int rid; 1842 1843 rid = PCIR_BAR(0); 1844 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1845 &rid, RF_ACTIVE); 1846 if (sc->memory == NULL) { 1847 device_printf(dev, 1848 "Unable to allocate bus resource: memory\n"); 1849 return (ENXIO); 1850 } 1851 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory); 1852 sc->osdep.mem_bus_space_handle = 1853 rman_get_bushandle(sc->memory); 1854 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle; 1855 1856 sc->hw.back = &sc->osdep; 1857 1858 return (0); 1859 } 1860 1861 /********************************************************************* 1862 * 1863 * Set up the MSI-X Interrupt handlers 1864 * 1865 **********************************************************************/ 1866 static int 1867 igc_if_msix_intr_assign(if_ctx_t ctx, int msix) 1868 { 1869 struct igc_softc *sc = iflib_get_softc(ctx); 1870 struct igc_rx_queue *rx_que = sc->rx_queues; 1871 struct igc_tx_queue *tx_que = sc->tx_queues; 1872 int error, rid, i, vector = 0, rx_vectors; 1873 char buf[16]; 1874 1875 /* First set up ring resources */ 1876 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) { 1877 rid = vector + 1; 1878 snprintf(buf, sizeof(buf), "rxq%d", i); 1879 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, 1880 IFLIB_INTR_RXTX, igc_msix_que, rx_que, rx_que->me, buf); 1881 if (error) { 1882 device_printf(iflib_get_dev(ctx), 1883 "Failed to allocate que int %d err: %d", 1884 i, error); 1885 sc->rx_num_queues = i + 1; 1886 goto fail; 1887 } 1888 1889 rx_que->msix = vector; 1890 1891 /* 1892 * Set the bit to enable interrupt 1893 * in IGC_IMS -- bits 20 and 21 1894 * are for RX0 and RX1, note this has 1895 * NOTHING to do with the MSI-X vector 1896 */ 1897 rx_que->eims = 1 << vector; 1898 } 1899 rx_vectors = vector; 1900 1901 vector = 0; 1902 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) { 1903 snprintf(buf, sizeof(buf), "txq%d", i); 1904 tx_que = &sc->tx_queues[i]; 1905 iflib_softirq_alloc_generic(ctx, 1906 &sc->rx_queues[i % sc->rx_num_queues].que_irq, 1907 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 1908 1909 tx_que->msix = (vector % sc->rx_num_queues); 1910 1911 /* 1912 * Set the bit to enable interrupt 1913 * in IGC_IMS -- bits 22 and 23 1914 * are for TX0 and TX1, note this has 1915 * NOTHING to do with the MSI-X vector 1916 */ 1917 tx_que->eims = 1 << i; 1918 } 1919 1920 /* Link interrupt */ 1921 rid = rx_vectors + 1; 1922 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, 1923 igc_msix_link, sc, 0, "aq"); 1924 1925 if (error) { 1926 device_printf(iflib_get_dev(ctx), 1927 "Failed to register admin handler"); 1928 goto fail; 1929 } 1930 sc->linkvec = rx_vectors; 1931 return (0); 1932 fail: 1933 iflib_irq_free(ctx, &sc->irq); 1934 rx_que = sc->rx_queues; 1935 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++) 1936 iflib_irq_free(ctx, &rx_que->que_irq); 1937 return (error); 1938 } 1939 1940 static void 1941 igc_configure_queues(struct igc_softc *sc) 1942 { 1943 struct igc_hw *hw = &sc->hw; 1944 struct igc_rx_queue *rx_que; 1945 struct igc_tx_queue *tx_que; 1946 u32 ivar = 0; 1947 1948 /* First turn on RSS capability */ 1949 IGC_WRITE_REG(hw, IGC_GPIE, 1950 IGC_GPIE_MSIX_MODE | IGC_GPIE_EIAME | IGC_GPIE_PBA | 1951 IGC_GPIE_NSICR); 1952 1953 /* Turn on MSI-X */ 1954 /* RX entries */ 1955 for (int i = 0; i < sc->rx_num_queues; i++) { 1956 u32 index = i >> 1; 1957 ivar = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, index); 1958 rx_que = &sc->rx_queues[i]; 1959 if (i & 1) { 1960 ivar &= 0xFF00FFFF; 1961 ivar |= (rx_que->msix | IGC_IVAR_VALID) << 16; 1962 } else { 1963 ivar &= 0xFFFFFF00; 1964 ivar |= rx_que->msix | IGC_IVAR_VALID; 1965 } 1966 IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, index, ivar); 1967 } 1968 /* TX entries */ 1969 for (int i = 0; i < sc->tx_num_queues; i++) { 1970 u32 index = i >> 1; 1971 ivar = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, index); 1972 tx_que = &sc->tx_queues[i]; 1973 if (i & 1) { 1974 ivar &= 0x00FFFFFF; 1975 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 24; 1976 } else { 1977 ivar &= 0xFFFF00FF; 1978 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 8; 1979 } 1980 IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, index, ivar); 1981 sc->que_mask |= tx_que->eims; 1982 } 1983 1984 /* And for the link interrupt */ 1985 ivar = (sc->linkvec | IGC_IVAR_VALID) << 8; 1986 sc->link_mask = 1 << sc->linkvec; 1987 IGC_WRITE_REG(hw, IGC_IVAR_MISC, ivar); 1988 1989 return; 1990 } 1991 1992 static void 1993 igc_initialize_interrupt_rate(struct igc_softc *sc) 1994 { 1995 struct igc_hw *hw = &sc->hw; 1996 struct igc_rx_queue *rx_que; 1997 u32 newitr; 1998 1999 newitr = IGC_INTS_TO_EITR(igc_max_interrupt_rate); 2000 newitr |= IGC_EITR_CNT_IGNR; 2001 2002 for (int i = 0; i < sc->rx_num_queues; i++) { 2003 rx_que = &sc->rx_queues[i]; 2004 rx_que->eitr_setting = newitr; 2005 IGC_WRITE_REG(hw, IGC_EITR(rx_que->msix), 2006 rx_que->eitr_setting); 2007 } 2008 } 2009 2010 static void 2011 igc_free_pci_resources(if_ctx_t ctx) 2012 { 2013 struct igc_softc *sc = iflib_get_softc(ctx); 2014 struct igc_rx_queue *que = sc->rx_queues; 2015 device_t dev = iflib_get_dev(ctx); 2016 2017 /* Release all MSI-X queue resources */ 2018 if (sc->intr_type == IFLIB_INTR_MSIX) 2019 iflib_irq_free(ctx, &sc->irq); 2020 2021 if (que != NULL) { 2022 for (int i = 0; i < sc->rx_num_queues; i++, que++) 2023 iflib_irq_free(ctx, &que->que_irq); 2024 } 2025 2026 if (sc->memory != NULL) { 2027 bus_release_resource(dev, SYS_RES_MEMORY, 2028 rman_get_rid(sc->memory), sc->memory); 2029 sc->memory = NULL; 2030 } 2031 2032 if (sc->flash != NULL) { 2033 bus_release_resource(dev, SYS_RES_MEMORY, 2034 rman_get_rid(sc->flash), sc->flash); 2035 sc->flash = NULL; 2036 } 2037 2038 if (sc->ioport != NULL) { 2039 bus_release_resource(dev, SYS_RES_IOPORT, 2040 rman_get_rid(sc->ioport), sc->ioport); 2041 sc->ioport = NULL; 2042 } 2043 } 2044 2045 /* Set up MSI or MSI-X */ 2046 static int 2047 igc_setup_msix(if_ctx_t ctx) 2048 { 2049 return (0); 2050 } 2051 2052 /********************************************************************* 2053 * 2054 * Initialize the DMA Coalescing feature 2055 * 2056 **********************************************************************/ 2057 static void 2058 igc_init_dmac(struct igc_softc *sc, u32 pba) 2059 { 2060 device_t dev = sc->dev; 2061 struct igc_hw *hw = &sc->hw; 2062 u32 dmac, reg = ~IGC_DMACR_DMAC_EN; 2063 u16 hwm; 2064 u16 max_frame_size; 2065 int status; 2066 2067 max_frame_size = sc->shared->isc_max_frame_size; 2068 2069 if (sc->dmac == 0) { /* Disabling it */ 2070 IGC_WRITE_REG(hw, IGC_DMACR, reg); 2071 return; 2072 } else 2073 device_printf(dev, "DMA Coalescing enabled\n"); 2074 2075 /* Set starting threshold */ 2076 IGC_WRITE_REG(hw, IGC_DMCTXTH, 0); 2077 2078 hwm = 64 * pba - max_frame_size / 16; 2079 if (hwm < 64 * (pba - 6)) 2080 hwm = 64 * (pba - 6); 2081 reg = IGC_READ_REG(hw, IGC_FCRTC); 2082 reg &= ~IGC_FCRTC_RTH_COAL_MASK; 2083 reg |= ((hwm << IGC_FCRTC_RTH_COAL_SHIFT) 2084 & IGC_FCRTC_RTH_COAL_MASK); 2085 IGC_WRITE_REG(hw, IGC_FCRTC, reg); 2086 2087 dmac = pba - max_frame_size / 512; 2088 if (dmac < pba - 10) 2089 dmac = pba - 10; 2090 reg = IGC_READ_REG(hw, IGC_DMACR); 2091 reg &= ~IGC_DMACR_DMACTHR_MASK; 2092 reg |= ((dmac << IGC_DMACR_DMACTHR_SHIFT) 2093 & IGC_DMACR_DMACTHR_MASK); 2094 2095 /* transition to L0x or L1 if available..*/ 2096 reg |= (IGC_DMACR_DMAC_EN | IGC_DMACR_DMAC_LX_MASK); 2097 2098 /* Check if status is 2.5Gb backplane connection 2099 * before configuration of watchdog timer, which is 2100 * in msec values in 12.8usec intervals 2101 * watchdog timer= msec values in 32usec intervals 2102 * for non 2.5Gb connection 2103 */ 2104 status = IGC_READ_REG(hw, IGC_STATUS); 2105 if ((status & IGC_STATUS_2P5_SKU) && 2106 (!(status & IGC_STATUS_2P5_SKU_OVER))) 2107 reg |= ((sc->dmac * 5) >> 6); 2108 else 2109 reg |= (sc->dmac >> 5); 2110 2111 IGC_WRITE_REG(hw, IGC_DMACR, reg); 2112 2113 IGC_WRITE_REG(hw, IGC_DMCRTRH, 0); 2114 2115 /* Set the interval before transition */ 2116 reg = IGC_READ_REG(hw, IGC_DMCTLX); 2117 reg |= IGC_DMCTLX_DCFLUSH_DIS; 2118 2119 /* 2120 ** in 2.5Gb connection, TTLX unit is 0.4 usec 2121 ** which is 0x4*2 = 0xA. But delay is still 4 usec 2122 */ 2123 status = IGC_READ_REG(hw, IGC_STATUS); 2124 if ((status & IGC_STATUS_2P5_SKU) && 2125 (!(status & IGC_STATUS_2P5_SKU_OVER))) 2126 reg |= 0xA; 2127 else 2128 reg |= 0x4; 2129 2130 IGC_WRITE_REG(hw, IGC_DMCTLX, reg); 2131 2132 /* free space in tx packet buffer to wake from DMA coal */ 2133 IGC_WRITE_REG(hw, IGC_DMCTXTH, (IGC_TXPBSIZE - 2134 (2 * max_frame_size)) >> 6); 2135 2136 /* make low power state decision controlled by DMA coal */ 2137 reg = IGC_READ_REG(hw, IGC_PCIEMISC); 2138 reg &= ~IGC_PCIEMISC_LX_DECISION; 2139 IGC_WRITE_REG(hw, IGC_PCIEMISC, reg); 2140 } 2141 2142 /********************************************************************* 2143 * 2144 * Initialize the hardware to a configuration as specified by the 2145 * softc structure. 2146 * 2147 **********************************************************************/ 2148 static int 2149 igc_reset(if_ctx_t ctx) 2150 { 2151 device_t dev = iflib_get_dev(ctx); 2152 struct igc_softc *sc = iflib_get_softc(ctx); 2153 struct igc_hw *hw = &sc->hw; 2154 u32 rx_buffer_size; 2155 u32 pba; 2156 s32 error; 2157 2158 INIT_DEBUGOUT("igc_reset: begin"); 2159 igc_led_restore(sc); 2160 /* Let the firmware know the OS is in control */ 2161 igc_get_hw_control(sc); 2162 2163 /* 2164 * Packet Buffer Allocation (PBA) 2165 * Writing PBA sets the receive portion of the buffer 2166 * the remainder is used for the transmit buffer. 2167 */ 2168 pba = IGC_PBA_34K; 2169 2170 INIT_DEBUGOUT1("igc_reset: pba=%dK",pba); 2171 2172 /* 2173 * These parameters control the automatic generation (Tx) and 2174 * response (Rx) to Ethernet PAUSE frames. 2175 * - High water mark should allow for at least two frames to be 2176 * received after sending an XOFF. 2177 * - Low water mark works best when it is very near the high water 2178 * mark. 2179 * This allows the receiver to restart by sending XON when it has 2180 * drained a bit. Here we use an arbitrary value of 1500 which will 2181 * restart after one full frame is pulled from the buffer. There 2182 * could be several smaller frames in the buffer and if so they will 2183 * not trigger the XON until their total number reduces the buffer 2184 * by 1500. 2185 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2186 */ 2187 rx_buffer_size = (pba & 0xffff) << 10; 2188 hw->fc.high_water = rx_buffer_size - 2189 roundup2(sc->hw.mac.max_frame_size, 1024); 2190 /* 16-byte granularity */ 2191 hw->fc.low_water = hw->fc.high_water - 16; 2192 2193 if (sc->fc) /* locally set flow control value? */ 2194 hw->fc.requested_mode = sc->fc; 2195 else 2196 hw->fc.requested_mode = igc_fc_full; 2197 2198 hw->fc.pause_time = IGC_FC_PAUSE_TIME; 2199 2200 hw->fc.send_xon = true; 2201 2202 /* Issue a global reset */ 2203 error = igc_reset_hw(hw); 2204 if (error != IGC_SUCCESS) { 2205 device_printf(dev, "Hardware reset failed: %d\n", error); 2206 return (error); 2207 } 2208 IGC_WRITE_REG(hw, IGC_WUC, 0); 2209 2210 /* and a re-init */ 2211 error = igc_init_hw(hw); 2212 if (error != IGC_SUCCESS) { 2213 device_printf(dev, "Hardware initialization failed: %d\n", 2214 error); 2215 return (error); 2216 } 2217 igc_finish_fatal_error_reset(sc); 2218 2219 /* Setup DMA Coalescing */ 2220 igc_init_dmac(sc, pba); 2221 2222 /* Save the final PBA off if it needs to be used elsewhere i.e. AIM */ 2223 sc->pba = pba; 2224 2225 IGC_WRITE_REG(hw, IGC_VET, ETHERTYPE_VLAN); 2226 igc_get_phy_info(hw); 2227 igc_check_for_link(hw); 2228 2229 return (IGC_SUCCESS); 2230 } 2231 2232 /* 2233 * Initialise the RSS mapping for NICs that support multiple transmit/ 2234 * receive rings. 2235 */ 2236 2237 #define RSSKEYLEN 10 2238 static void 2239 igc_initialize_rss_mapping(struct igc_softc *sc) 2240 { 2241 struct igc_hw *hw = &sc->hw; 2242 int i; 2243 int queue_id; 2244 u32 reta; 2245 u32 rss_key[RSSKEYLEN], mrqc, shift = 0; 2246 2247 /* 2248 * The redirection table controls which destination 2249 * queue each bucket redirects traffic to. 2250 * Each DWORD represents four queues, with the LSB 2251 * being the first queue in the DWORD. 2252 * 2253 * This just allocates buckets to queues using round-robin 2254 * allocation. 2255 * 2256 * NOTE: It Just Happens to line up with the default 2257 * RSS allocation method. 2258 */ 2259 2260 /* Warning FM follows */ 2261 reta = 0; 2262 for (i = 0; i < 128; i++) { 2263 #ifdef RSS 2264 queue_id = rss_get_indirection_to_bucket(i); 2265 /* 2266 * If we have more queues than buckets, we'll 2267 * end up mapping buckets to a subset of the 2268 * queues. 2269 * 2270 * If we have more buckets than queues, we'll 2271 * end up instead assigning multiple buckets 2272 * to queues. 2273 * 2274 * Both are suboptimal, but we need to handle 2275 * the case so we don't go out of bounds 2276 * indexing arrays and such. 2277 */ 2278 queue_id = queue_id % sc->rx_num_queues; 2279 #else 2280 queue_id = (i % sc->rx_num_queues); 2281 #endif 2282 /* Adjust if required */ 2283 queue_id = queue_id << shift; 2284 2285 /* 2286 * The low 8 bits are for hash value (n+0); 2287 * The next 8 bits are for hash value (n+1), etc. 2288 */ 2289 reta = reta >> 8; 2290 reta = reta | ( ((uint32_t) queue_id) << 24); 2291 if ((i & 3) == 3) { 2292 IGC_WRITE_REG(hw, IGC_RETA(i >> 2), reta); 2293 reta = 0; 2294 } 2295 } 2296 2297 /* Now fill in hash table */ 2298 2299 /* 2300 * MRQC: Multiple Receive Queues Command 2301 * Set queuing to RSS control, number depends on the device. 2302 */ 2303 mrqc = IGC_MRQC_ENABLE_RSS_4Q; 2304 2305 /* XXX ew typecasting */ 2306 rss_getkey((uint8_t *) &rss_key); 2307 for (i = 0; i < RSSKEYLEN; i++) 2308 IGC_WRITE_REG_ARRAY(hw, IGC_RSSRK(0), i, rss_key[i]); 2309 2310 /* 2311 * Configure the RSS fields to hash upon. 2312 */ 2313 mrqc |= (IGC_MRQC_RSS_FIELD_IPV4 | 2314 IGC_MRQC_RSS_FIELD_IPV4_TCP); 2315 mrqc |= (IGC_MRQC_RSS_FIELD_IPV6 | 2316 IGC_MRQC_RSS_FIELD_IPV6_TCP); 2317 mrqc |=( IGC_MRQC_RSS_FIELD_IPV4_UDP | 2318 IGC_MRQC_RSS_FIELD_IPV6_UDP); 2319 mrqc |=( IGC_MRQC_RSS_FIELD_IPV6_UDP_EX | 2320 IGC_MRQC_RSS_FIELD_IPV6_TCP_EX); 2321 2322 IGC_WRITE_REG(hw, IGC_MRQC, mrqc); 2323 } 2324 2325 /********************************************************************* 2326 * 2327 * Setup networking device structure and register interface media. 2328 * 2329 **********************************************************************/ 2330 static int 2331 igc_setup_interface(if_ctx_t ctx) 2332 { 2333 if_t ifp = iflib_get_ifp(ctx); 2334 struct igc_softc *sc = iflib_get_softc(ctx); 2335 if_softc_ctx_t scctx = sc->shared; 2336 2337 INIT_DEBUGOUT("igc_setup_interface: begin"); 2338 2339 /* Single Queue */ 2340 if (sc->tx_num_queues == 1) { 2341 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 2342 if_setsendqready(ifp); 2343 } 2344 2345 /* 2346 * Specify the media types supported by this adapter and register 2347 * callbacks to update media and link information 2348 */ 2349 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL); 2350 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 2351 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); 2352 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 2353 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2354 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); 2355 ifmedia_add(sc->media, IFM_ETHER | IFM_2500_T, 0, NULL); 2356 2357 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2358 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO); 2359 return (0); 2360 } 2361 2362 static int 2363 igc_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 2364 int ntxqs, int ntxqsets) 2365 { 2366 struct igc_softc *sc = iflib_get_softc(ctx); 2367 if_softc_ctx_t scctx = sc->shared; 2368 int error = IGC_SUCCESS; 2369 struct igc_tx_queue *que; 2370 int i, j; 2371 2372 MPASS(sc->tx_num_queues > 0); 2373 MPASS(sc->tx_num_queues == ntxqsets); 2374 2375 /* First allocate the top level queue structs */ 2376 if (!(sc->tx_queues = 2377 (struct igc_tx_queue *) malloc(sizeof(struct igc_tx_queue) * 2378 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2379 device_printf(iflib_get_dev(ctx), 2380 "Unable to allocate queue memory\n"); 2381 return(ENOMEM); 2382 } 2383 2384 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) { 2385 /* Set up some basics */ 2386 2387 struct tx_ring *txr = &que->txr; 2388 KASSERT(__is_aligned(&txr->tx_aim_snapshot, sizeof(uint64_t)), 2389 ("%s: misaligned TX AIM snapshot %p", __func__, 2390 &txr->tx_aim_snapshot)); 2391 txr->sc = que->sc = sc; 2392 que->me = txr->me = i; 2393 2394 /* Allocate report status array */ 2395 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * 2396 scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 2397 device_printf(iflib_get_dev(ctx), 2398 "failed to allocate rs_idxs memory\n"); 2399 error = ENOMEM; 2400 goto fail; 2401 } 2402 for (j = 0; j < scctx->isc_ntxd[0]; j++) 2403 txr->tx_rsq[j] = QIDX_INVALID; 2404 /* get virtual and physical address of the hardware queues */ 2405 txr->tx_base = (struct igc_tx_desc *)vaddrs[i*ntxqs]; 2406 txr->tx_paddr = paddrs[i*ntxqs]; 2407 } 2408 2409 if (bootverbose) 2410 device_printf(iflib_get_dev(ctx), 2411 "allocated for %d tx_queues\n", sc->tx_num_queues); 2412 return (0); 2413 fail: 2414 igc_if_queues_free(ctx); 2415 return (error); 2416 } 2417 2418 static int 2419 igc_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, 2420 int nrxqs, int nrxqsets) 2421 { 2422 struct igc_softc *sc = iflib_get_softc(ctx); 2423 int error = IGC_SUCCESS; 2424 struct igc_rx_queue *que; 2425 int i; 2426 2427 MPASS(sc->rx_num_queues > 0); 2428 MPASS(sc->rx_num_queues == nrxqsets); 2429 2430 /* First allocate the top level queue structs */ 2431 if (!(sc->rx_queues = 2432 (struct igc_rx_queue *) malloc(sizeof(struct igc_rx_queue) * 2433 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 2434 device_printf(iflib_get_dev(ctx), 2435 "Unable to allocate queue memory\n"); 2436 error = ENOMEM; 2437 goto fail; 2438 } 2439 2440 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) { 2441 /* Set up some basics */ 2442 struct rx_ring *rxr = &que->rxr; 2443 KASSERT(__is_aligned(&rxr->rx_aim_snapshot, sizeof(uint64_t)), 2444 ("%s: misaligned RX AIM snapshot %p", __func__, 2445 &rxr->rx_aim_snapshot)); 2446 rxr->sc = que->sc = sc; 2447 rxr->que = que; 2448 que->me = rxr->me = i; 2449 2450 /* get virtual and physical address of the hardware queues */ 2451 rxr->rx_base = (union igc_rx_desc_extended *)vaddrs[i*nrxqs]; 2452 rxr->rx_paddr = paddrs[i*nrxqs]; 2453 } 2454 2455 if (bootverbose) 2456 device_printf(iflib_get_dev(ctx), 2457 "allocated for %d rx_queues\n", sc->rx_num_queues); 2458 2459 return (0); 2460 fail: 2461 igc_if_queues_free(ctx); 2462 return (error); 2463 } 2464 2465 static void 2466 igc_if_queues_free(if_ctx_t ctx) 2467 { 2468 struct igc_softc *sc = iflib_get_softc(ctx); 2469 struct igc_tx_queue *tx_que = sc->tx_queues; 2470 struct igc_rx_queue *rx_que = sc->rx_queues; 2471 2472 if (tx_que != NULL) { 2473 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 2474 struct tx_ring *txr = &tx_que->txr; 2475 if (txr->tx_rsq == NULL) 2476 break; 2477 2478 free(txr->tx_rsq, M_DEVBUF); 2479 txr->tx_rsq = NULL; 2480 } 2481 free(sc->tx_queues, M_DEVBUF); 2482 sc->tx_queues = NULL; 2483 } 2484 2485 if (rx_que != NULL) { 2486 free(sc->rx_queues, M_DEVBUF); 2487 sc->rx_queues = NULL; 2488 } 2489 2490 if (sc->mta != NULL) { 2491 free(sc->mta, M_DEVBUF); 2492 sc->mta = NULL; 2493 } 2494 } 2495 2496 /********************************************************************* 2497 * 2498 * Enable transmit unit. 2499 * 2500 **********************************************************************/ 2501 static void 2502 igc_initialize_transmit_unit(if_ctx_t ctx) 2503 { 2504 struct igc_softc *sc = iflib_get_softc(ctx); 2505 if_softc_ctx_t scctx = sc->shared; 2506 struct igc_tx_queue *que; 2507 struct tx_ring *txr; 2508 struct igc_hw *hw = &sc->hw; 2509 u32 tctl, txdctl = 0; 2510 2511 INIT_DEBUGOUT("igc_initialize_transmit_unit: begin"); 2512 2513 for (int i = 0; i < sc->tx_num_queues; i++, txr++) { 2514 u64 bus_addr; 2515 caddr_t offp, endp; 2516 2517 que = &sc->tx_queues[i]; 2518 txr = &que->txr; 2519 bus_addr = txr->tx_paddr; 2520 2521 /* Clear checksum offload context. */ 2522 offp = (caddr_t)&txr->csum_flags; 2523 endp = (caddr_t)(txr + 1); 2524 bzero(offp, endp - offp); 2525 2526 /* Base and Len of TX Ring */ 2527 IGC_WRITE_REG(hw, IGC_TDLEN(i), 2528 scctx->isc_ntxd[0] * sizeof(struct igc_tx_desc)); 2529 IGC_WRITE_REG(hw, IGC_TDBAH(i), 2530 (u32)(bus_addr >> 32)); 2531 IGC_WRITE_REG(hw, IGC_TDBAL(i), 2532 (u32)bus_addr); 2533 /* Init the HEAD/TAIL indices */ 2534 IGC_WRITE_REG(hw, IGC_TDT(i), 0); 2535 IGC_WRITE_REG(hw, IGC_TDH(i), 0); 2536 2537 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2538 IGC_READ_REG(&sc->hw, IGC_TDBAL(i)), 2539 IGC_READ_REG(&sc->hw, IGC_TDLEN(i))); 2540 2541 /* WTHRESH must be zero when iflib uses sparse RS. */ 2542 txdctl = IGC_TX_PTHRESH | (IGC_TX_HTHRESH << 8) | 2543 IGC_TXDCTL_QUEUE_ENABLE; 2544 2545 IGC_WRITE_REG(hw, IGC_TXDCTL(i), txdctl); 2546 } 2547 2548 /* Program the Transmit Control Register */ 2549 tctl = IGC_READ_REG(&sc->hw, IGC_TCTL); 2550 tctl &= ~IGC_TCTL_CT; 2551 tctl |= (IGC_TCTL_PSP | IGC_TCTL_RTLC | IGC_TCTL_EN | 2552 (IGC_COLLISION_THRESHOLD << IGC_CT_SHIFT)); 2553 2554 /* This write will effectively turn on the transmit unit. */ 2555 IGC_WRITE_REG(&sc->hw, IGC_TCTL, tctl); 2556 } 2557 2558 /********************************************************************* 2559 * 2560 * Enable receive unit. 2561 * 2562 **********************************************************************/ 2563 #define BSIZEPKT_ROUNDUP ((1<<IGC_SRRCTL_BSIZEPKT_SHIFT)-1) 2564 2565 static void 2566 igc_initialize_receive_unit(if_ctx_t ctx) 2567 { 2568 struct igc_softc *sc = iflib_get_softc(ctx); 2569 if_softc_ctx_t scctx = sc->shared; 2570 if_t ifp = iflib_get_ifp(ctx); 2571 struct igc_hw *hw = &sc->hw; 2572 struct igc_rx_queue *que; 2573 int i; 2574 u32 psize, rctl, rxcsum, srrctl = 0; 2575 2576 INIT_DEBUGOUT("igc_initialize_receive_units: begin"); 2577 2578 /* 2579 * Make sure receives are disabled while setting 2580 * up the descriptor ring 2581 */ 2582 rctl = IGC_READ_REG(hw, IGC_RCTL); 2583 IGC_WRITE_REG(hw, IGC_RCTL, rctl & ~IGC_RCTL_EN); 2584 2585 /* Setup the Receive Control Register */ 2586 rctl &= ~(3 << IGC_RCTL_MO_SHIFT); 2587 rctl |= IGC_RCTL_EN | IGC_RCTL_BAM | 2588 IGC_RCTL_LBM_NO | IGC_RCTL_RDMTS_HALF | 2589 (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT); 2590 2591 /* Do not store bad packets */ 2592 rctl &= ~IGC_RCTL_SBP; 2593 2594 /* Enable Long Packet receive */ 2595 if (if_getmtu(ifp) > ETHERMTU) 2596 rctl |= IGC_RCTL_LPE; 2597 else 2598 rctl &= ~IGC_RCTL_LPE; 2599 2600 /* Strip the CRC */ 2601 if (!igc_disable_crc_stripping) 2602 rctl |= IGC_RCTL_SECRC; 2603 2604 rxcsum = IGC_READ_REG(hw, IGC_RXCSUM); 2605 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 2606 rxcsum |= IGC_RXCSUM_CRCOFL; 2607 if (sc->tx_num_queues > 1) 2608 rxcsum |= IGC_RXCSUM_PCSD; 2609 else 2610 rxcsum |= IGC_RXCSUM_IPPCSE; 2611 } else { 2612 if (sc->tx_num_queues > 1) 2613 rxcsum |= IGC_RXCSUM_PCSD; 2614 else 2615 rxcsum &= ~IGC_RXCSUM_TUOFL; 2616 } 2617 IGC_WRITE_REG(hw, IGC_RXCSUM, rxcsum); 2618 2619 if (sc->rx_num_queues > 1) 2620 igc_initialize_rss_mapping(sc); 2621 2622 if (if_getmtu(ifp) > ETHERMTU) { 2623 psize = scctx->isc_max_frame_size; 2624 /* are we on a vlan? */ 2625 if (if_vlantrunkinuse(ifp)) 2626 psize += VLAN_TAG_SIZE; 2627 IGC_WRITE_REG(&sc->hw, IGC_RLPML, psize); 2628 } 2629 2630 /* Set maximum packet buffer len */ 2631 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 2632 IGC_SRRCTL_BSIZEPKT_SHIFT; 2633 /* srrctl above overrides this but set the register to a sane value */ 2634 rctl |= IGC_RCTL_SZ_2048; 2635 2636 /* 2637 * If TX flow control is disabled and there's >1 queue defined, 2638 * enable DROP. 2639 * 2640 * This drops frames rather than hanging the RX MAC for all queues. 2641 */ 2642 if ((sc->rx_num_queues > 1) && 2643 (sc->fc == igc_fc_none || 2644 sc->fc == igc_fc_rx_pause)) { 2645 srrctl |= IGC_SRRCTL_DROP_EN; 2646 } 2647 2648 /* Setup the Base and Length of the Rx Descriptor Rings */ 2649 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) { 2650 struct rx_ring *rxr = &que->rxr; 2651 u64 bus_addr = rxr->rx_paddr; 2652 u32 rxdctl; 2653 2654 #ifdef notyet 2655 /* Configure for header split? -- ignore for now */ 2656 rxr->hdr_split = igc_header_split; 2657 #else 2658 srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF; 2659 #endif 2660 2661 IGC_WRITE_REG(hw, IGC_RDLEN(i), 2662 scctx->isc_nrxd[0] * sizeof(struct igc_rx_desc)); 2663 IGC_WRITE_REG(hw, IGC_RDBAH(i), (uint32_t)(bus_addr >> 32)); 2664 IGC_WRITE_REG(hw, IGC_RDBAL(i), (uint32_t)bus_addr); 2665 IGC_WRITE_REG(hw, IGC_SRRCTL(i), srrctl); 2666 /* Setup the Head and Tail Descriptor Pointers */ 2667 IGC_WRITE_REG(hw, IGC_RDH(i), 0); 2668 IGC_WRITE_REG(hw, IGC_RDT(i), 0); 2669 /* Enable this Queue */ 2670 rxdctl = IGC_READ_REG(hw, IGC_RXDCTL(i)); 2671 rxdctl &= ~(IGC_RXDCTL_PTHRESH | IGC_RXDCTL_HTHRESH | 2672 IGC_RXDCTL_WTHRESH); 2673 rxdctl |= IGC_RX_PTHRESH | (IGC_RX_HTHRESH << 8) | 2674 (IGC_RX_WTHRESH << 16) | IGC_RXDCTL_QUEUE_ENABLE; 2675 IGC_WRITE_REG(hw, IGC_RXDCTL(i), rxdctl); 2676 } 2677 2678 /* Make sure VLAN Filters are off */ 2679 rctl &= ~IGC_RCTL_VFE; 2680 2681 /* Write out the settings */ 2682 IGC_WRITE_REG(hw, IGC_RCTL, rctl); 2683 2684 return; 2685 } 2686 2687 static void 2688 igc_if_vlan_register(if_ctx_t ctx, u16 vtag) 2689 { 2690 struct igc_softc *sc = iflib_get_softc(ctx); 2691 u32 index, mask; 2692 2693 index = (vtag >> 5) & 0x7f; 2694 mask = 1U << (vtag & 0x1f); 2695 if ((sc->shadow_vfta[index] & mask) != 0) 2696 return; 2697 sc->shadow_vfta[index] |= mask; 2698 igc_write_vfta(&sc->hw, index, sc->shadow_vfta[index]); 2699 } 2700 2701 static void 2702 igc_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 2703 { 2704 struct igc_softc *sc = iflib_get_softc(ctx); 2705 u32 index, mask; 2706 2707 index = (vtag >> 5) & 0x7f; 2708 mask = 1U << (vtag & 0x1f); 2709 if ((sc->shadow_vfta[index] & mask) == 0) 2710 return; 2711 sc->shadow_vfta[index] &= ~mask; 2712 igc_write_vfta(&sc->hw, index, sc->shadow_vfta[index]); 2713 } 2714 2715 static bool 2716 igc_if_vlan_filter_capable(if_ctx_t ctx) 2717 { 2718 if_t ifp = iflib_get_ifp(ctx); 2719 2720 return ((if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) != 0 && 2721 !igc_disable_crc_stripping); 2722 } 2723 2724 static bool 2725 igc_if_vlan_filter_used(if_ctx_t ctx) 2726 { 2727 struct igc_softc *sc = iflib_get_softc(ctx); 2728 2729 if (!igc_if_vlan_filter_capable(ctx)) 2730 return (false); 2731 2732 for (int i = 0; i < IGC_VFTA_SIZE; i++) 2733 if (sc->shadow_vfta[i] != 0) 2734 return (true); 2735 2736 return (false); 2737 } 2738 2739 static void 2740 igc_if_vlan_filter_enable(struct igc_softc *sc) 2741 { 2742 u32 reg; 2743 2744 reg = IGC_READ_REG(&sc->hw, IGC_RCTL); 2745 reg &= ~IGC_RCTL_CFIEN; 2746 reg |= IGC_RCTL_VFE; 2747 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg); 2748 } 2749 2750 static void 2751 igc_if_vlan_filter_disable(struct igc_softc *sc) 2752 { 2753 u32 reg; 2754 2755 reg = IGC_READ_REG(&sc->hw, IGC_RCTL); 2756 reg &= ~(IGC_RCTL_VFE | IGC_RCTL_CFIEN); 2757 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg); 2758 } 2759 2760 static void 2761 igc_setup_vlan_hw_support(if_ctx_t ctx) 2762 { 2763 struct igc_softc *sc = iflib_get_softc(ctx); 2764 struct igc_hw *hw = &sc->hw; 2765 if_t ifp = iflib_get_ifp(ctx); 2766 u32 reg; 2767 2768 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 2769 !igc_disable_crc_stripping) { 2770 reg = IGC_READ_REG(hw, IGC_CTRL); 2771 reg |= IGC_CTRL_VME; 2772 IGC_WRITE_REG(hw, IGC_CTRL, reg); 2773 } else { 2774 reg = IGC_READ_REG(hw, IGC_CTRL); 2775 reg &= ~IGC_CTRL_VME; 2776 IGC_WRITE_REG(hw, IGC_CTRL, reg); 2777 } 2778 2779 if (!igc_if_vlan_filter_capable(ctx)) { 2780 igc_if_vlan_filter_disable(sc); 2781 return; 2782 } 2783 2784 /* Always admit priority-tagged frames. */ 2785 sc->shadow_vfta[0] |= 1U; 2786 2787 /* A reset may clear the VFTA, so restore the complete desired table. */ 2788 for (int i = 0; i < IGC_VFTA_SIZE; i++) 2789 igc_write_vfta(hw, i, sc->shadow_vfta[i]); 2790 2791 igc_if_vlan_filter_enable(sc); 2792 } 2793 2794 static void 2795 igc_if_intr_enable(if_ctx_t ctx) 2796 { 2797 struct igc_softc *sc = iflib_get_softc(ctx); 2798 struct igc_hw *hw = &sc->hw; 2799 u32 mask; 2800 2801 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 2802 mask = (sc->que_mask | sc->link_mask); 2803 IGC_WRITE_REG(hw, IGC_EIAC, mask); 2804 IGC_WRITE_REG(hw, IGC_EIAM, mask); 2805 IGC_WRITE_REG(hw, IGC_EIMS, mask); 2806 mask = IGC_IMS_LSC; 2807 } else 2808 mask = IMS_ENABLE_MASK; 2809 if (atomic_load_acq_32(&sc->fatal_error_state) == 2810 IGC_FATAL_ERROR_NONE) 2811 mask |= IGC_IMS_FER; 2812 IGC_WRITE_REG(hw, IGC_IMS, mask); 2813 IGC_WRITE_FLUSH(hw); 2814 } 2815 2816 static void 2817 igc_if_intr_disable(if_ctx_t ctx) 2818 { 2819 struct igc_softc *sc = iflib_get_softc(ctx); 2820 struct igc_hw *hw = &sc->hw; 2821 2822 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) { 2823 IGC_WRITE_REG(hw, IGC_EIMC, 0xffffffff); 2824 IGC_WRITE_REG(hw, IGC_EIAC, 0); 2825 } 2826 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff); 2827 IGC_WRITE_FLUSH(hw); 2828 } 2829 2830 /* 2831 * igc_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 2832 * For ASF and Pass Through versions of f/w this means 2833 * that the driver is loaded. For AMT version type f/w 2834 * this means that the network i/f is open. 2835 */ 2836 static void 2837 igc_get_hw_control(struct igc_softc *sc) 2838 { 2839 u32 ctrl_ext; 2840 2841 if (sc->vf_ifp) 2842 return; 2843 2844 ctrl_ext = IGC_READ_REG(&sc->hw, IGC_CTRL_EXT); 2845 IGC_WRITE_REG(&sc->hw, IGC_CTRL_EXT, 2846 ctrl_ext | IGC_CTRL_EXT_DRV_LOAD); 2847 } 2848 2849 /* 2850 * igc_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 2851 * For ASF and Pass Through versions of f/w this means that 2852 * the driver is no longer loaded. For AMT versions of the 2853 * f/w this means that the network i/f is closed. 2854 */ 2855 static void 2856 igc_release_hw_control(struct igc_softc *sc) 2857 { 2858 u32 ctrl_ext; 2859 2860 ctrl_ext = IGC_READ_REG(&sc->hw, IGC_CTRL_EXT); 2861 IGC_WRITE_REG(&sc->hw, IGC_CTRL_EXT, 2862 ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD); 2863 return; 2864 } 2865 2866 static int 2867 igc_enable_pci_busmaster(struct igc_softc *sc) 2868 { 2869 device_t dev; 2870 u16 command; 2871 int error; 2872 2873 dev = sc->dev; 2874 command = pci_read_config(dev, PCIR_COMMAND, 2); 2875 if (command == 0xffff) 2876 return (ENXIO); 2877 if ((command & PCIM_CMD_BUSMASTEREN) != 0) 2878 return (0); 2879 2880 error = pci_enable_busmaster(dev); 2881 command = pci_read_config(dev, PCIR_COMMAND, 2); 2882 if (command == 0xffff) 2883 return (ENXIO); 2884 if ((command & PCIM_CMD_BUSMASTEREN) == 0) 2885 return (error != 0 ? error : EIO); 2886 return (0); 2887 } 2888 2889 static int 2890 igc_is_valid_ether_addr(u8 *addr) 2891 { 2892 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 2893 2894 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 2895 return (false); 2896 } 2897 2898 return (true); 2899 } 2900 2901 /* Advertise the wake modes supported by I225/I226 physical functions. */ 2902 static void 2903 igc_configure_wakeup(if_ctx_t ctx) 2904 { 2905 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 2906 device_t dev = iflib_get_dev(ctx); 2907 int capabilities; 2908 2909 capabilities = pci_has_pme(dev, PCI_POWERSTATE_D3_HOT) ? 2910 IFCAP_WOL : 0; 2911 scctx->isc_capabilities &= ~IFCAP_WOL; 2912 scctx->isc_capabilities |= capabilities; 2913 scctx->isc_capenable &= ~IFCAP_WOL; 2914 if (capabilities != 0) 2915 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 2916 } 2917 2918 /* Configure the requested PCI Wake-on-LAN filters for suspend. */ 2919 static int 2920 igc_enable_wakeup(if_ctx_t ctx) 2921 { 2922 struct igc_softc *sc = iflib_get_softc(ctx); 2923 device_t dev = iflib_get_dev(ctx); 2924 if_t ifp = iflib_get_ifp(ctx); 2925 int enabled, error = 0, master_error, mcnt; 2926 u32 ctrl, rctl, wufc; 2927 bool manage; 2928 2929 if (!pci_has_pme(dev, PCI_POWERSTATE_D3_HOT)) 2930 return (0); 2931 2932 enabled = if_getcapenable(ifp) & if_getcapabilities(ifp) & IFCAP_WOL; 2933 manage = igc_enable_mng_pass_thru(&sc->hw); 2934 wufc = 0; 2935 if ((enabled & IFCAP_WOL_MAGIC) != 0) 2936 wufc |= IGC_WUFC_MAG; 2937 if ((enabled & IFCAP_WOL_UCAST) != 0) 2938 wufc |= IGC_WUFC_EX; 2939 if ((enabled & IFCAP_WOL_MCAST) != 0) { 2940 wufc |= IGC_WUFC_MC; 2941 bzero(sc->mta, ETHER_ADDR_LEN * 2942 MAX_NUM_MULTICAST_ADDRESSES); 2943 mcnt = if_foreach_llmaddr(ifp, igc_copy_maddr, sc->mta); 2944 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 2945 igc_update_mc_addr_list(&sc->hw, sc->mta, mcnt); 2946 } 2947 2948 IGC_WRITE_REG(&sc->hw, IGC_WUFC, 0); 2949 IGC_WRITE_REG(&sc->hw, IGC_WUFC_EXT, 0); 2950 IGC_WRITE_REG(&sc->hw, IGC_WUC, 0); 2951 IGC_WRITE_REG(&sc->hw, IGC_WUS, ~0U); 2952 IGC_WRITE_REG(&sc->hw, IGC_WUS_EXT, ~0U); 2953 2954 if (wufc == 0) { 2955 if (manage) { 2956 if (sc->suspend_link_powered_down) 2957 igc_power_up_wakeup_link(sc); 2958 pci_enable_pme(dev); 2959 } else { 2960 igc_power_down_phy(&sc->hw); 2961 sc->suspend_link_powered_down = true; 2962 pci_clear_pme(dev); 2963 } 2964 goto master_disable; 2965 } 2966 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN); 2967 error = igc_rar_set(&sc->hw, sc->hw.mac.addr, 0); 2968 if (error != IGC_SUCCESS) { 2969 device_printf(dev, 2970 "Could not restore unicast wake address: %d\n", error); 2971 goto pme; 2972 } 2973 rctl = IGC_READ_REG(&sc->hw, IGC_RCTL); 2974 rctl &= ~(IGC_RCTL_UPE | IGC_RCTL_MPE | IGC_RCTL_MO_3); 2975 rctl |= IGC_RCTL_EN | IGC_RCTL_BAM | 2976 (sc->hw.mac.mc_filter_type << IGC_RCTL_MO_SHIFT); 2977 if ((wufc & IGC_WUFC_MC) != 0) 2978 rctl |= IGC_RCTL_MPE; 2979 IGC_WRITE_REG(&sc->hw, IGC_RCTL, rctl); 2980 2981 /* Advertise the wakeup capability */ 2982 ctrl = IGC_READ_REG(&sc->hw, IGC_CTRL); 2983 ctrl |= IGC_CTRL_ADVD3WUC; 2984 IGC_WRITE_REG(&sc->hw, IGC_CTRL, ctrl); 2985 igc_power_up_wakeup_link(sc); 2986 2987 /* Enable wakeup by the MAC */ 2988 IGC_WRITE_REG(&sc->hw, IGC_WUC, IGC_WUC_PME_EN); 2989 IGC_WRITE_REG(&sc->hw, IGC_WUFC, wufc); 2990 2991 pme: 2992 if (error == IGC_SUCCESS) 2993 pci_enable_pme(dev); 2994 else { 2995 IGC_WRITE_REG(&sc->hw, IGC_WUFC, 0); 2996 IGC_WRITE_REG(&sc->hw, IGC_WUFC_EXT, 0); 2997 IGC_WRITE_REG(&sc->hw, IGC_WUC, 0); 2998 pci_clear_pme(dev); 2999 } 3000 3001 master_disable: 3002 master_error = igc_disable_pcie_master(&sc->hw); 3003 if (master_error != IGC_SUCCESS) 3004 device_printf(dev, "PCIe master disable timed out: %d\n", 3005 master_error); 3006 master_error = pci_disable_busmaster(dev); 3007 if (master_error != 0) 3008 device_printf(dev, "PCI bus-master disable failed: %d\n", 3009 master_error); 3010 3011 return (error == IGC_SUCCESS ? 0 : EIO); 3012 } 3013 3014 static void 3015 igc_power_up_wakeup_link(struct igc_softc *sc) 3016 { 3017 igc_power_up_phy(&sc->hw); 3018 sc->suspend_link_powered_down = false; 3019 } 3020 3021 /********************************************************************** 3022 * 3023 * Update the board statistics counters. 3024 * 3025 **********************************************************************/ 3026 static void 3027 igc_update_ecc_stats(struct igc_softc *sc) 3028 { 3029 struct igc_hw *hw; 3030 u32 pbeccsts, pcieeccsts; 3031 3032 hw = &sc->hw; 3033 pbeccsts = IGC_READ_REG(hw, IGC_PBECCSTS); 3034 if (pbeccsts & IGC_PBECCSTS_CORR_ERR) { 3035 sc->corrected_error_dma_count++; 3036 /* Preserve the enable bit while clearing the RW1C status. */ 3037 IGC_WRITE_REG(hw, IGC_PBECCSTS, 3038 pbeccsts & (IGC_PBECCSTS_ECC_ENABLE | 3039 IGC_PBECCSTS_CORR_ERR)); 3040 } 3041 3042 pcieeccsts = IGC_READ_REG(hw, IGC_PCIEECCSTS) & 3043 IGC_PCIEECCSTS_CORR_MASK; 3044 if (pcieeccsts & IGC_PCIEECCSTS_TX_WR_DATA) 3045 sc->corrected_error_pcie_tx_data_count++; 3046 if (pcieeccsts & IGC_PCIEECCSTS_RETRY_BUF) 3047 sc->corrected_error_pcie_retry_count++; 3048 if (pcieeccsts != 0) 3049 IGC_WRITE_REG(hw, IGC_PCIEECCSTS, pcieeccsts); 3050 } 3051 3052 static void 3053 igc_update_stats_counters(struct igc_softc *sc) 3054 { 3055 u64 prev_xoffrxc = sc->stats.xoffrxc; 3056 3057 sc->stats.crcerrs += IGC_READ_REG(&sc->hw, IGC_CRCERRS); 3058 sc->stats.rxerrc += IGC_READ_REG(&sc->hw, IGC_RXERRC); 3059 sc->stats.mpc += IGC_READ_REG(&sc->hw, IGC_MPC); 3060 sc->stats.scc += IGC_READ_REG(&sc->hw, IGC_SCC); 3061 sc->stats.ecol += IGC_READ_REG(&sc->hw, IGC_ECOL); 3062 3063 sc->stats.mcc += IGC_READ_REG(&sc->hw, IGC_MCC); 3064 sc->stats.latecol += IGC_READ_REG(&sc->hw, IGC_LATECOL); 3065 sc->stats.colc += IGC_READ_REG(&sc->hw, IGC_COLC); 3066 sc->stats.rerc += IGC_READ_REG(&sc->hw, IGC_RERC); 3067 sc->stats.dc += IGC_READ_REG(&sc->hw, IGC_DC); 3068 sc->stats.rlec += IGC_READ_REG(&sc->hw, IGC_RLEC); 3069 sc->stats.xonrxc += IGC_READ_REG(&sc->hw, IGC_XONRXC); 3070 sc->stats.xontxc += IGC_READ_REG(&sc->hw, IGC_XONTXC); 3071 sc->stats.xoffrxc += IGC_READ_REG(&sc->hw, IGC_XOFFRXC); 3072 /* 3073 * For watchdog management we need to know if we have been 3074 * paused during the last interval, so capture that here. 3075 */ 3076 if (sc->stats.xoffrxc != prev_xoffrxc) 3077 sc->shared->isc_pause_frames = 1; 3078 sc->stats.xofftxc += IGC_READ_REG(&sc->hw, IGC_XOFFTXC); 3079 sc->stats.fcruc += IGC_READ_REG(&sc->hw, IGC_FCRUC); 3080 sc->stats.prc64 += IGC_READ_REG(&sc->hw, IGC_PRC64); 3081 sc->stats.prc127 += IGC_READ_REG(&sc->hw, IGC_PRC127); 3082 sc->stats.prc255 += IGC_READ_REG(&sc->hw, IGC_PRC255); 3083 sc->stats.prc511 += IGC_READ_REG(&sc->hw, IGC_PRC511); 3084 sc->stats.prc1023 += IGC_READ_REG(&sc->hw, IGC_PRC1023); 3085 sc->stats.prc1522 += IGC_READ_REG(&sc->hw, IGC_PRC1522); 3086 sc->stats.tlpic += IGC_READ_REG(&sc->hw, IGC_TLPIC); 3087 sc->stats.rlpic += IGC_READ_REG(&sc->hw, IGC_RLPIC); 3088 sc->stats.gprc += IGC_READ_REG(&sc->hw, IGC_GPRC); 3089 sc->stats.bprc += IGC_READ_REG(&sc->hw, IGC_BPRC); 3090 sc->stats.mprc += IGC_READ_REG(&sc->hw, IGC_MPRC); 3091 sc->stats.gptc += IGC_READ_REG(&sc->hw, IGC_GPTC); 3092 3093 /* For the 64-bit byte counters the low dword must be read first. */ 3094 /* Both registers clear on the read of the high dword */ 3095 3096 sc->stats.gorc += IGC_READ_REG(&sc->hw, IGC_GORCL) + 3097 ((u64)IGC_READ_REG(&sc->hw, IGC_GORCH) << 32); 3098 sc->stats.gotc += IGC_READ_REG(&sc->hw, IGC_GOTCL) + 3099 ((u64)IGC_READ_REG(&sc->hw, IGC_GOTCH) << 32); 3100 3101 sc->stats.rnbc += IGC_READ_REG(&sc->hw, IGC_RNBC); 3102 sc->stats.ruc += IGC_READ_REG(&sc->hw, IGC_RUC); 3103 sc->stats.rfc += IGC_READ_REG(&sc->hw, IGC_RFC); 3104 sc->stats.roc += IGC_READ_REG(&sc->hw, IGC_ROC); 3105 sc->stats.rjc += IGC_READ_REG(&sc->hw, IGC_RJC); 3106 3107 sc->stats.mgprc += IGC_READ_REG(&sc->hw, IGC_MGTPRC); 3108 sc->stats.mgpdc += IGC_READ_REG(&sc->hw, IGC_MGTPDC); 3109 sc->stats.mgptc += IGC_READ_REG(&sc->hw, IGC_MGTPTC); 3110 3111 sc->stats.tor += IGC_READ_REG(&sc->hw, IGC_TORH); 3112 sc->stats.tot += IGC_READ_REG(&sc->hw, IGC_TOTH); 3113 3114 sc->stats.tpr += IGC_READ_REG(&sc->hw, IGC_TPR); 3115 sc->stats.tpt += IGC_READ_REG(&sc->hw, IGC_TPT); 3116 sc->stats.ptc64 += IGC_READ_REG(&sc->hw, IGC_PTC64); 3117 sc->stats.ptc127 += IGC_READ_REG(&sc->hw, IGC_PTC127); 3118 sc->stats.ptc255 += IGC_READ_REG(&sc->hw, IGC_PTC255); 3119 sc->stats.ptc511 += IGC_READ_REG(&sc->hw, IGC_PTC511); 3120 sc->stats.ptc1023 += IGC_READ_REG(&sc->hw, IGC_PTC1023); 3121 sc->stats.ptc1522 += IGC_READ_REG(&sc->hw, IGC_PTC1522); 3122 sc->stats.mptc += IGC_READ_REG(&sc->hw, IGC_MPTC); 3123 sc->stats.bptc += IGC_READ_REG(&sc->hw, IGC_BPTC); 3124 3125 /* Interrupt Counts */ 3126 sc->stats.iac += IGC_READ_REG(&sc->hw, IGC_IAC); 3127 sc->stats.rxdmtc += IGC_READ_REG(&sc->hw, IGC_RXDMTC); 3128 3129 sc->stats.algnerrc += IGC_READ_REG(&sc->hw, IGC_ALGNERRC); 3130 sc->stats.tncrs += IGC_READ_REG(&sc->hw, IGC_TNCRS); 3131 sc->stats.htdpmc += IGC_READ_REG(&sc->hw, IGC_HTDPMC); 3132 sc->stats.tsctc += IGC_READ_REG(&sc->hw, IGC_TSCTC); 3133 3134 igc_update_ecc_stats(sc); 3135 } 3136 3137 static uint64_t 3138 igc_if_get_counter(if_ctx_t ctx, ift_counter cnt) 3139 { 3140 struct igc_softc *sc = iflib_get_softc(ctx); 3141 if_t ifp = iflib_get_ifp(ctx); 3142 3143 switch (cnt) { 3144 case IFCOUNTER_COLLISIONS: 3145 return (sc->stats.colc); 3146 case IFCOUNTER_IERRORS: 3147 /* 3148 * RERC overlaps the counters below and, on I225, omits length 3149 * errors. RFC covers bad-CRC runts that CRCERRS does not count. 3150 */ 3151 return (sc->dropped_pkts + sc->stats.rxerrc + 3152 sc->stats.crcerrs + sc->stats.algnerrc + 3153 sc->stats.ruc + sc->stats.rfc + sc->stats.roc + 3154 sc->stats.mpc); 3155 case IFCOUNTER_OERRORS: 3156 return (if_get_counter_default(ifp, cnt) + 3157 sc->stats.ecol + sc->stats.latecol); 3158 default: 3159 return (if_get_counter_default(ifp, cnt)); 3160 } 3161 } 3162 3163 /* igc_if_needs_restart - Tell iflib when the driver needs to be reinitialized 3164 * @ctx: iflib context 3165 * @event: event code to check 3166 * 3167 * Defaults to returning false for unknown events. 3168 * 3169 * @returns true if iflib needs to reinit the interface 3170 */ 3171 static bool 3172 igc_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 3173 { 3174 switch (event) { 3175 case IFLIB_RESTART_VLAN_CONFIG: 3176 default: 3177 return (false); 3178 } 3179 } 3180 3181 /* Export a single 32-bit register via a read-only sysctl. */ 3182 static int 3183 igc_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 3184 { 3185 struct igc_softc *sc; 3186 u_int val; 3187 3188 sc = oidp->oid_arg1; 3189 val = IGC_READ_REG(&sc->hw, oidp->oid_arg2); 3190 return (sysctl_handle_int(oidp, &val, 0, req)); 3191 } 3192 3193 /* Per queue holdoff interrupt rate handler */ 3194 static int 3195 igc_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS) 3196 { 3197 struct igc_rx_queue *rque; 3198 struct igc_tx_queue *tque; 3199 struct igc_hw *hw; 3200 int error; 3201 u32 reg, usec, rate; 3202 3203 bool tx = oidp->oid_arg2; 3204 3205 if (tx) { 3206 tque = oidp->oid_arg1; 3207 hw = &tque->sc->hw; 3208 reg = IGC_READ_REG(hw, IGC_EITR(tque->msix)); 3209 } else { 3210 rque = oidp->oid_arg1; 3211 hw = &rque->sc->hw; 3212 reg = IGC_READ_REG(hw, IGC_EITR(rque->msix)); 3213 } 3214 3215 usec = (reg & IGC_QVECTOR_MASK); 3216 if (usec > 0) 3217 rate = IGC_EITR_TO_INTS(usec); 3218 else 3219 rate = 0; 3220 3221 error = sysctl_handle_int(oidp, &rate, 0, req); 3222 if (error || !req->newptr) 3223 return error; 3224 return 0; 3225 } 3226 3227 /* 3228 * Add sysctl variables, one per statistic, to the system. 3229 */ 3230 static void 3231 igc_add_hw_stats(struct igc_softc *sc) 3232 { 3233 device_t dev = iflib_get_dev(sc->ctx); 3234 struct igc_tx_queue *tx_que = sc->tx_queues; 3235 struct igc_rx_queue *rx_que = sc->rx_queues; 3236 3237 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 3238 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 3239 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 3240 struct igc_hw_stats *stats = &sc->stats; 3241 3242 struct sysctl_oid *eee_node, *memerr_node, *stat_node, *queue_node, 3243 *int_node; 3244 struct sysctl_oid_list *eee_list, *memerr_list, *stat_list, *queue_list, 3245 *int_list; 3246 3247 #define QUEUE_NAME_LEN 32 3248 char namebuf[QUEUE_NAME_LEN]; 3249 3250 /* Driver Statistics */ 3251 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 3252 CTLFLAG_RD, &sc->dropped_pkts, 3253 "Driver dropped packets"); 3254 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 3255 CTLFLAG_RD, &sc->link_irq, 3256 "Link MSI-X IRQ Handled"); 3257 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 3258 CTLFLAG_RD, &sc->rx_overruns, 3259 "RX overruns"); 3260 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 3261 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 3262 sc, IGC_CTRL, igc_sysctl_reg_handler, "IU", 3263 "Device Control Register"); 3264 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 3265 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 3266 sc, IGC_RCTL, igc_sysctl_reg_handler, "IU", 3267 "Receiver Control Register"); 3268 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 3269 CTLFLAG_RD, &sc->hw.fc.high_water, 0, 3270 "Flow Control High Watermark"); 3271 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 3272 CTLFLAG_RD, &sc->hw.fc.low_water, 0, 3273 "Flow Control Low Watermark"); 3274 memerr_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "memory_errors", 3275 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 3276 "Internal memory error indications"); 3277 memerr_list = SYSCTL_CHILDREN(memerr_node); 3278 SYSCTL_ADD_UQUAD(ctx, memerr_list, OID_AUTO, "fatal_lan", 3279 CTLFLAG_RD, &sc->fatal_error_lan_count, 3280 "Fatal LAN-port memory error indications"); 3281 SYSCTL_ADD_UQUAD(ctx, memerr_list, OID_AUTO, "fatal_management", 3282 CTLFLAG_RD, &sc->fatal_error_mng_count, 3283 "Fatal management-memory error indications"); 3284 SYSCTL_ADD_UQUAD(ctx, memerr_list, OID_AUTO, "fatal_pcie", 3285 CTLFLAG_RD, &sc->fatal_error_pcie_count, 3286 "Fatal PCIe memory error indications"); 3287 SYSCTL_ADD_UQUAD(ctx, memerr_list, OID_AUTO, "fatal_dma", 3288 CTLFLAG_RD, &sc->fatal_error_dma_count, 3289 "Fatal DMA memory error indications"); 3290 SYSCTL_ADD_UQUAD(ctx, memerr_list, OID_AUTO, "fatal_unknown", 3291 CTLFLAG_RD, &sc->fatal_error_unknown_count, 3292 "Fatal memory errors without a reported region"); 3293 SYSCTL_ADD_UQUAD(ctx, memerr_list, OID_AUTO, "corrected_dma", 3294 CTLFLAG_RD, &sc->corrected_error_dma_count, 3295 "Corrected DMA memory error indications"); 3296 SYSCTL_ADD_UQUAD(ctx, memerr_list, OID_AUTO, 3297 "corrected_pcie_tx_data", CTLFLAG_RD, 3298 &sc->corrected_error_pcie_tx_data_count, 3299 "Corrected PCIe transmit-data memory error indications"); 3300 SYSCTL_ADD_UQUAD(ctx, memerr_list, OID_AUTO, 3301 "corrected_pcie_retry", CTLFLAG_RD, 3302 &sc->corrected_error_pcie_retry_count, 3303 "Corrected PCIe retry-buffer memory error indications"); 3304 eee_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "eee", 3305 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 3306 "Energy Efficient Ethernet statistics"); 3307 eee_list = SYSCTL_CHILDREN(eee_node); 3308 SYSCTL_ADD_UQUAD(ctx, eee_list, OID_AUTO, "tx_lpi_count", 3309 CTLFLAG_RD, &stats->tlpic, "TX LPI event count"); 3310 SYSCTL_ADD_UQUAD(ctx, eee_list, OID_AUTO, "rx_lpi_count", 3311 CTLFLAG_RD, &stats->rlpic, "RX LPI event count"); 3312 3313 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) { 3314 struct tx_ring *txr = &tx_que->txr; 3315 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 3316 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 3317 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 3318 queue_list = SYSCTL_CHILDREN(queue_node); 3319 3320 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 3321 CTLTYPE_UINT | CTLFLAG_RD, tx_que, 3322 true, igc_sysctl_interrupt_rate_handler, "IU", 3323 "Interrupt Rate"); 3324 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 3325 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 3326 IGC_TDH(txr->me), igc_sysctl_reg_handler, "IU", 3327 "Transmit Descriptor Head"); 3328 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 3329 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 3330 IGC_TDT(txr->me), igc_sysctl_reg_handler, "IU", 3331 "Transmit Descriptor Tail"); 3332 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 3333 CTLFLAG_RD, &txr->tx_irq, 3334 "Queue MSI-X Transmit Interrupts"); 3335 } 3336 3337 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) { 3338 struct rx_ring *rxr = &rx_que->rxr; 3339 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 3340 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 3341 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 3342 queue_list = SYSCTL_CHILDREN(queue_node); 3343 3344 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate", 3345 CTLTYPE_UINT | CTLFLAG_RD, rx_que, 3346 false, igc_sysctl_interrupt_rate_handler, "IU", 3347 "Interrupt Rate"); 3348 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 3349 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 3350 IGC_RDH(rxr->me), igc_sysctl_reg_handler, "IU", 3351 "Receive Descriptor Head"); 3352 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 3353 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 3354 IGC_RDT(rxr->me), igc_sysctl_reg_handler, "IU", 3355 "Receive Descriptor Tail"); 3356 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 3357 CTLFLAG_RD, &rxr->rx_irq, 3358 "Queue MSI-X Receive Interrupts"); 3359 } 3360 3361 /* MAC stats get their own sub node */ 3362 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 3363 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 3364 stat_list = SYSCTL_CHILDREN(stat_node); 3365 3366 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 3367 CTLFLAG_RD, &stats->ecol, 3368 "Excessive collisions"); 3369 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 3370 CTLFLAG_RD, &stats->scc, 3371 "Single collisions"); 3372 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 3373 CTLFLAG_RD, &stats->mcc, 3374 "Multiple collisions"); 3375 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 3376 CTLFLAG_RD, &stats->latecol, 3377 "Late collisions"); 3378 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 3379 CTLFLAG_RD, &stats->colc, 3380 "Collision Count"); 3381 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 3382 CTLFLAG_RD, &sc->stats.symerrs, 3383 "Symbol Errors"); 3384 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 3385 CTLFLAG_RD, &sc->stats.sec, 3386 "Sequence Errors"); 3387 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 3388 CTLFLAG_RD, &sc->stats.dc, 3389 "Defer Count"); 3390 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 3391 CTLFLAG_RD, &sc->stats.mpc, 3392 "Missed Packets"); 3393 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_length_errors", 3394 CTLFLAG_RD, &sc->stats.rlec, 3395 "Receive Length Errors"); 3396 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 3397 CTLFLAG_RD, &sc->stats.rnbc, 3398 "Receive No Buffers"); 3399 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 3400 CTLFLAG_RD, &sc->stats.ruc, 3401 "Receive Undersize"); 3402 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 3403 CTLFLAG_RD, &sc->stats.rfc, 3404 "Fragmented Packets Received "); 3405 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 3406 CTLFLAG_RD, &sc->stats.roc, 3407 "Oversized Packets Received"); 3408 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 3409 CTLFLAG_RD, &sc->stats.rjc, 3410 "Received Jabber"); 3411 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 3412 CTLFLAG_RD, &sc->stats.rxerrc, 3413 "Receive Errors"); 3414 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_error_count", 3415 CTLFLAG_RD, &sc->stats.rerc, 3416 "Receive Error Count (RERC)"); 3417 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 3418 CTLFLAG_RD, &sc->stats.crcerrs, 3419 "CRC errors"); 3420 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 3421 CTLFLAG_RD, &sc->stats.algnerrc, 3422 "Alignment Errors"); 3423 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 3424 CTLFLAG_RD, &sc->stats.xonrxc, 3425 "XON Received"); 3426 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 3427 CTLFLAG_RD, &sc->stats.xontxc, 3428 "XON Transmitted"); 3429 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 3430 CTLFLAG_RD, &sc->stats.xoffrxc, 3431 "XOFF Received"); 3432 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 3433 CTLFLAG_RD, &sc->stats.xofftxc, 3434 "XOFF Transmitted"); 3435 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "unsupported_fc_recvd", 3436 CTLFLAG_RD, &sc->stats.fcruc, 3437 "Unsupported Flow Control Received"); 3438 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_recvd", 3439 CTLFLAG_RD, &sc->stats.mgprc, 3440 "Management Packets Received"); 3441 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_drop", 3442 CTLFLAG_RD, &sc->stats.mgpdc, 3443 "Management Packets Dropped"); 3444 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_txd", 3445 CTLFLAG_RD, &sc->stats.mgptc, 3446 "Management Packets Transmitted"); 3447 3448 /* Packet Reception Stats */ 3449 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 3450 CTLFLAG_RD, &sc->stats.tpr, 3451 "Total Packets Received "); 3452 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 3453 CTLFLAG_RD, &sc->stats.gprc, 3454 "Good Packets Received"); 3455 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 3456 CTLFLAG_RD, &sc->stats.bprc, 3457 "Broadcast Packets Received"); 3458 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 3459 CTLFLAG_RD, &sc->stats.mprc, 3460 "Multicast Packets Received"); 3461 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 3462 CTLFLAG_RD, &sc->stats.prc64, 3463 "64 byte frames received "); 3464 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 3465 CTLFLAG_RD, &sc->stats.prc127, 3466 "65-127 byte frames received"); 3467 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 3468 CTLFLAG_RD, &sc->stats.prc255, 3469 "128-255 byte frames received"); 3470 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 3471 CTLFLAG_RD, &sc->stats.prc511, 3472 "256-511 byte frames received"); 3473 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 3474 CTLFLAG_RD, &sc->stats.prc1023, 3475 "512-1023 byte frames received"); 3476 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 3477 CTLFLAG_RD, &sc->stats.prc1522, 3478 "1023-1522 byte frames received"); 3479 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 3480 CTLFLAG_RD, &sc->stats.gorc, 3481 "Good Octets Received"); 3482 3483 /* Packet Transmission Stats */ 3484 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 3485 CTLFLAG_RD, &sc->stats.gotc, 3486 "Good Octets Transmitted"); 3487 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 3488 CTLFLAG_RD, &sc->stats.tpt, 3489 "Total Packets Transmitted"); 3490 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 3491 CTLFLAG_RD, &sc->stats.gptc, 3492 "Good Packets Transmitted"); 3493 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "host_tx_discarded", 3494 CTLFLAG_RD, &sc->stats.htdpmc, 3495 "Host Packets Discarded by Transmit MAC"); 3496 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 3497 CTLFLAG_RD, &sc->stats.bptc, 3498 "Broadcast Packets Transmitted"); 3499 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 3500 CTLFLAG_RD, &sc->stats.mptc, 3501 "Multicast Packets Transmitted"); 3502 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 3503 CTLFLAG_RD, &sc->stats.ptc64, 3504 "64 byte frames transmitted "); 3505 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 3506 CTLFLAG_RD, &sc->stats.ptc127, 3507 "65-127 byte frames transmitted"); 3508 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 3509 CTLFLAG_RD, &sc->stats.ptc255, 3510 "128-255 byte frames transmitted"); 3511 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 3512 CTLFLAG_RD, &sc->stats.ptc511, 3513 "256-511 byte frames transmitted"); 3514 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 3515 CTLFLAG_RD, &sc->stats.ptc1023, 3516 "512-1023 byte frames transmitted"); 3517 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 3518 CTLFLAG_RD, &sc->stats.ptc1522, 3519 "1024-1522 byte frames transmitted"); 3520 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 3521 CTLFLAG_RD, &sc->stats.tsctc, 3522 "TSO Contexts Transmitted"); 3523 3524 /* Interrupt Stats */ 3525 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 3526 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 3527 int_list = SYSCTL_CHILDREN(int_node); 3528 3529 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 3530 CTLFLAG_RD, &sc->stats.iac, 3531 "Interrupt Assertion Count"); 3532 3533 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 3534 CTLFLAG_RD, &sc->stats.rxdmtc, 3535 "Rx Desc Min Thresh Count"); 3536 } 3537 3538 static void 3539 igc_fw_version(struct igc_softc *sc) 3540 { 3541 struct igc_hw *hw = &sc->hw; 3542 struct igc_fw_version *fw_ver = &sc->fw_ver; 3543 3544 *fw_ver = (struct igc_fw_version){0}; 3545 3546 igc_get_fw_version(hw, fw_ver); 3547 } 3548 3549 static void 3550 igc_sbuf_fw_version(struct igc_fw_version *fw_ver, struct sbuf *buf) 3551 { 3552 const char *space = ""; 3553 3554 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) { 3555 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major, 3556 fw_ver->eep_minor, fw_ver->eep_build); 3557 space = " "; 3558 } 3559 3560 if (fw_ver->invm_major || fw_ver->invm_minor || 3561 fw_ver->invm_img_type) { 3562 sbuf_printf(buf, "%sNVM V%d.%d imgtype%d", 3563 space, fw_ver->invm_major, fw_ver->invm_minor, 3564 fw_ver->invm_img_type); 3565 space = " "; 3566 } 3567 3568 if (fw_ver->or_valid) { 3569 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d", 3570 space, fw_ver->or_major, fw_ver->or_build, 3571 fw_ver->or_patch); 3572 space = " "; 3573 } 3574 3575 if (fw_ver->etrack_id) 3576 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id); 3577 } 3578 3579 static void 3580 igc_print_fw_version(struct igc_softc *sc ) 3581 { 3582 device_t dev = sc->dev; 3583 struct sbuf *buf; 3584 int error = 0; 3585 3586 buf = sbuf_new_auto(); 3587 if (!buf) { 3588 device_printf(dev, "Could not allocate sbuf for output.\n"); 3589 return; 3590 } 3591 3592 igc_sbuf_fw_version(&sc->fw_ver, buf); 3593 3594 error = sbuf_finish(buf); 3595 if (error) 3596 device_printf(dev, "Error finishing sbuf: %d\n", error); 3597 else if (sbuf_len(buf)) 3598 device_printf(dev, "%s\n", sbuf_data(buf)); 3599 3600 sbuf_delete(buf); 3601 } 3602 3603 static int 3604 igc_sysctl_print_fw_version(SYSCTL_HANDLER_ARGS) 3605 { 3606 struct igc_softc *sc = (struct igc_softc *)arg1; 3607 device_t dev = sc->dev; 3608 struct sbuf *buf; 3609 int error = 0; 3610 3611 buf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 3612 if (!buf) { 3613 device_printf(dev, "Could not allocate sbuf for output.\n"); 3614 return (ENOMEM); 3615 } 3616 3617 igc_sbuf_fw_version(&sc->fw_ver, buf); 3618 3619 error = sbuf_finish(buf); 3620 if (error) 3621 device_printf(dev, "Error finishing sbuf: %d\n", error); 3622 3623 sbuf_delete(buf); 3624 3625 return (0); 3626 } 3627 3628 /********************************************************************** 3629 * 3630 * This routine provides a way to dump out the adapter eeprom, 3631 * often a useful debug/service tool. This only dumps the first 3632 * 32 words, stuff that matters is in that extent. 3633 * 3634 **********************************************************************/ 3635 static int 3636 igc_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 3637 { 3638 struct igc_softc *sc = (struct igc_softc *)arg1; 3639 int error; 3640 int result; 3641 3642 result = -1; 3643 error = sysctl_handle_int(oidp, &result, 0, req); 3644 3645 if (error || !req->newptr) 3646 return (error); 3647 3648 /* 3649 * This value will cause a hex dump of the 3650 * first 32 16-bit words of the EEPROM to 3651 * the screen. 3652 */ 3653 if (result == 1) 3654 igc_print_nvm_info(sc); 3655 3656 return (error); 3657 } 3658 3659 static void 3660 igc_print_nvm_info(struct igc_softc *sc) 3661 { 3662 u16 eeprom_data; 3663 int i, j, row = 0; 3664 3665 /* Its a bit crude, but it gets the job done */ 3666 printf("\nInterface EEPROM Dump:\n"); 3667 printf("Offset\n0x0000 "); 3668 for (i = 0, j = 0; i < 32; i++, j++) { 3669 if (j == 8) { /* Make the offset block */ 3670 j = 0; ++row; 3671 printf("\n0x00%x0 ",row); 3672 } 3673 igc_read_nvm(&sc->hw, i, 1, &eeprom_data); 3674 printf("%04x ", eeprom_data); 3675 } 3676 printf("\n"); 3677 } 3678 3679 static int 3680 igc_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS) 3681 { 3682 struct igc_softc *sc; 3683 u32 reg, val, shift; 3684 int error, mask; 3685 3686 sc = oidp->oid_arg1; 3687 switch (oidp->oid_arg2) { 3688 case 0: 3689 reg = IGC_DTXTCPFLGL; 3690 shift = 0; 3691 break; 3692 case 1: 3693 reg = IGC_DTXTCPFLGL; 3694 shift = 16; 3695 break; 3696 case 2: 3697 reg = IGC_DTXTCPFLGH; 3698 shift = 0; 3699 break; 3700 default: 3701 return (EINVAL); 3702 break; 3703 } 3704 val = IGC_READ_REG(&sc->hw, reg); 3705 mask = (val >> shift) & 0xfff; 3706 error = sysctl_handle_int(oidp, &mask, 0, req); 3707 if (error != 0 || req->newptr == NULL) 3708 return (error); 3709 if (mask < 0 || mask > 0xfff) 3710 return (EINVAL); 3711 val = (val & ~(0xfff << shift)) | (mask << shift); 3712 IGC_WRITE_REG(&sc->hw, reg, val); 3713 return (0); 3714 } 3715 3716 /* 3717 * Set flow control using sysctl: 3718 * Flow control values: 3719 * 0 - off 3720 * 1 - rx pause 3721 * 2 - tx pause 3722 * 3 - full 3723 */ 3724 static int 3725 igc_set_flowcntl(SYSCTL_HANDLER_ARGS) 3726 { 3727 int error; 3728 static int input = 3; /* default is full */ 3729 struct igc_softc *sc = (struct igc_softc *) arg1; 3730 3731 error = sysctl_handle_int(oidp, &input, 0, req); 3732 3733 if ((error) || (req->newptr == NULL)) 3734 return (error); 3735 3736 if (input == sc->fc) /* no change? */ 3737 return (error); 3738 3739 switch (input) { 3740 case igc_fc_rx_pause: 3741 case igc_fc_tx_pause: 3742 case igc_fc_full: 3743 case igc_fc_none: 3744 sc->hw.fc.requested_mode = input; 3745 sc->fc = input; 3746 break; 3747 default: 3748 /* Do nothing */ 3749 return (error); 3750 } 3751 3752 sc->hw.fc.current_mode = sc->hw.fc.requested_mode; 3753 igc_force_mac_fc(&sc->hw); 3754 return (error); 3755 } 3756 3757 static void 3758 igc_sysctl_request_reinit(struct igc_softc *sc) 3759 { 3760 if ((if_getflags(iflib_get_ifp(sc->ctx)) & IFF_UP) == 0) 3761 return; 3762 3763 iflib_request_reset(sc->ctx); 3764 iflib_admin_intr_deferred(sc->ctx); 3765 } 3766 3767 /* 3768 * Manage DMA Coalesce: 3769 * Control values: 3770 * 0/1 - off/on 3771 * Legal timer values are: 3772 * 250,500,1000-10000 in thousands 3773 */ 3774 static int 3775 igc_sysctl_dmac(SYSCTL_HANDLER_ARGS) 3776 { 3777 struct igc_softc *sc = (struct igc_softc *) arg1; 3778 int error; 3779 3780 error = sysctl_handle_int(oidp, &sc->dmac, 0, req); 3781 3782 if ((error) || (req->newptr == NULL)) 3783 return (error); 3784 3785 switch (sc->dmac) { 3786 case 0: 3787 /* Disabling */ 3788 break; 3789 case 1: /* Just enable and use default */ 3790 sc->dmac = 1000; 3791 break; 3792 case 250: 3793 case 500: 3794 case 1000: 3795 case 2000: 3796 case 3000: 3797 case 4000: 3798 case 5000: 3799 case 6000: 3800 case 7000: 3801 case 8000: 3802 case 9000: 3803 case 10000: 3804 /* Legal values - allow */ 3805 break; 3806 default: 3807 /* Do nothing, illegal value */ 3808 sc->dmac = 0; 3809 return (EINVAL); 3810 } 3811 /* Reinit the interface */ 3812 igc_sysctl_request_reinit(sc); 3813 return (error); 3814 } 3815 3816 /* 3817 * Manage Energy Efficient Ethernet: 3818 * Control values: 3819 * 0/1 - enabled/disabled 3820 */ 3821 static int 3822 igc_sysctl_eee(SYSCTL_HANDLER_ARGS) 3823 { 3824 struct igc_softc *sc = (struct igc_softc *) arg1; 3825 int error, value; 3826 3827 value = sc->hw.dev_spec._i225.eee_disable; 3828 error = sysctl_handle_int(oidp, &value, 0, req); 3829 if (error || req->newptr == NULL) 3830 return (error); 3831 3832 sc->hw.dev_spec._i225.eee_disable = (value != 0); 3833 igc_sysctl_request_reinit(sc); 3834 3835 return (0); 3836 } 3837 3838 static int 3839 igc_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 3840 { 3841 struct igc_softc *sc; 3842 int error; 3843 int result; 3844 3845 result = -1; 3846 error = sysctl_handle_int(oidp, &result, 0, req); 3847 3848 if (error || !req->newptr) 3849 return (error); 3850 3851 if (result == 1) { 3852 sc = (struct igc_softc *) arg1; 3853 igc_print_debug_info(sc); 3854 } 3855 3856 return (error); 3857 } 3858 3859 static int 3860 igc_get_rs(SYSCTL_HANDLER_ARGS) 3861 { 3862 struct igc_softc *sc = (struct igc_softc *) arg1; 3863 int error; 3864 int result; 3865 3866 result = 0; 3867 error = sysctl_handle_int(oidp, &result, 0, req); 3868 3869 if (error || !req->newptr || result != 1) 3870 return (error); 3871 igc_dump_rs(sc); 3872 3873 return (error); 3874 } 3875 3876 static void 3877 igc_if_debug(if_ctx_t ctx) 3878 { 3879 igc_dump_rs(iflib_get_softc(ctx)); 3880 } 3881 3882 /* 3883 * This routine is meant to be fluid, add whatever is 3884 * needed for debugging a problem. -jfv 3885 */ 3886 static void 3887 igc_print_debug_info(struct igc_softc *sc) 3888 { 3889 device_t dev = iflib_get_dev(sc->ctx); 3890 3891 device_printf(dev, "iflib software admission: %s\n", 3892 iflib_is_running(sc->ctx) ? "open" : "closed"); 3893 3894 for (int i = 0; i < sc->tx_num_queues; i++) { 3895 device_printf(dev, "TX Queue %d ------\n", i); 3896 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3897 IGC_READ_REG(&sc->hw, IGC_TDH(i)), 3898 IGC_READ_REG(&sc->hw, IGC_TDT(i))); 3899 3900 } 3901 for (int j = 0; j < sc->rx_num_queues; j++) { 3902 device_printf(dev, "RX Queue %d ------\n", j); 3903 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 3904 IGC_READ_REG(&sc->hw, IGC_RDH(j)), 3905 IGC_READ_REG(&sc->hw, IGC_RDT(j))); 3906 } 3907 } 3908