1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * Copyright (c) 2021 Rubicon Communications, LLC (Netgate) 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "if_igc.h" 34 #include <sys/sbuf.h> 35 #include <machine/_inttypes.h> 36 37 #ifdef RSS 38 #include <net/rss_config.h> 39 #include <netinet/in_rss.h> 40 #endif 41 42 /********************************************************************* 43 * PCI Device ID Table 44 * 45 * Used by probe to select devices to load on 46 * Last entry must be all 0s 47 * 48 * { Vendor ID, Device ID, String } 49 *********************************************************************/ 50 51 static pci_vendor_info_t igc_vendor_info_array[] = 52 { 53 /* Intel(R) PRO/1000 Network Connection - igc */ 54 PVID(0x8086, IGC_DEV_ID_I225_LM, "Intel(R) Ethernet Controller I225-LM"), 55 PVID(0x8086, IGC_DEV_ID_I225_V, "Intel(R) Ethernet Controller I225-V"), 56 PVID(0x8086, IGC_DEV_ID_I225_K, "Intel(R) Ethernet Controller I225-K"), 57 PVID(0x8086, IGC_DEV_ID_I225_I, "Intel(R) Ethernet Controller I225-I"), 58 PVID(0x8086, IGC_DEV_ID_I220_V, "Intel(R) Ethernet Controller I220-V"), 59 PVID(0x8086, IGC_DEV_ID_I225_K2, "Intel(R) Ethernet Controller I225-K(2)"), 60 PVID(0x8086, IGC_DEV_ID_I225_LMVP, "Intel(R) Ethernet Controller I225-LMvP(2)"), 61 PVID(0x8086, IGC_DEV_ID_I226_K, "Intel(R) Ethernet Controller I226-K"), 62 PVID(0x8086, IGC_DEV_ID_I225_IT, "Intel(R) Ethernet Controller I225-IT(2)"), 63 PVID(0x8086, IGC_DEV_ID_I226_LM, "Intel(R) Ethernet Controller I226-LM"), 64 PVID(0x8086, IGC_DEV_ID_I226_V, "Intel(R) Ethernet Controller I226-V"), 65 PVID(0x8086, IGC_DEV_ID_I226_IT, "Intel(R) Ethernet Controller I226-IT"), 66 PVID(0x8086, IGC_DEV_ID_I221_V, "Intel(R) Ethernet Controller I221-V"), 67 PVID(0x8086, IGC_DEV_ID_I226_BLANK_NVM, "Intel(R) Ethernet Controller I226(blankNVM)"), 68 PVID(0x8086, IGC_DEV_ID_I225_BLANK_NVM, "Intel(R) Ethernet Controller I225(blankNVM)"), 69 /* required last entry */ 70 PVID_END 71 }; 72 73 /********************************************************************* 74 * Function prototypes 75 *********************************************************************/ 76 static void *igc_register(device_t dev); 77 static int igc_if_attach_pre(if_ctx_t ctx); 78 static int igc_if_attach_post(if_ctx_t ctx); 79 static int igc_if_detach(if_ctx_t ctx); 80 static int igc_if_shutdown(if_ctx_t ctx); 81 static int igc_if_suspend(if_ctx_t ctx); 82 static int igc_if_resume(if_ctx_t ctx); 83 84 static int igc_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 85 static int igc_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 86 static void igc_if_queues_free(if_ctx_t ctx); 87 88 static uint64_t igc_if_get_counter(if_ctx_t, ift_counter); 89 static void igc_if_init(if_ctx_t ctx); 90 static void igc_if_stop(if_ctx_t ctx); 91 static void igc_if_media_status(if_ctx_t, struct ifmediareq *); 92 static int igc_if_media_change(if_ctx_t ctx); 93 static int igc_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 94 static void igc_if_timer(if_ctx_t ctx, uint16_t qid); 95 static void igc_if_vlan_register(if_ctx_t ctx, u16 vtag); 96 static void igc_if_vlan_unregister(if_ctx_t ctx, u16 vtag); 97 static void igc_if_watchdog_reset(if_ctx_t ctx); 98 static bool igc_if_needs_restart(if_ctx_t ctx, enum iflib_restart_event event); 99 100 static void igc_identify_hardware(if_ctx_t ctx); 101 static int igc_allocate_pci_resources(if_ctx_t ctx); 102 static void igc_free_pci_resources(if_ctx_t ctx); 103 static void igc_reset(if_ctx_t ctx); 104 static int igc_setup_interface(if_ctx_t ctx); 105 static int igc_setup_msix(if_ctx_t ctx); 106 107 static void igc_initialize_transmit_unit(if_ctx_t ctx); 108 static void igc_initialize_receive_unit(if_ctx_t ctx); 109 110 static void igc_if_intr_enable(if_ctx_t ctx); 111 static void igc_if_intr_disable(if_ctx_t ctx); 112 static int igc_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 113 static int igc_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 114 static void igc_if_multi_set(if_ctx_t ctx); 115 static void igc_if_update_admin_status(if_ctx_t ctx); 116 static void igc_if_debug(if_ctx_t ctx); 117 static void igc_update_stats_counters(struct igc_adapter *); 118 static void igc_add_hw_stats(struct igc_adapter *adapter); 119 static int igc_if_set_promisc(if_ctx_t ctx, int flags); 120 static void igc_setup_vlan_hw_support(struct igc_adapter *); 121 static int igc_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 122 static void igc_print_nvm_info(struct igc_adapter *); 123 static int igc_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 124 static int igc_get_rs(SYSCTL_HANDLER_ARGS); 125 static void igc_print_debug_info(struct igc_adapter *); 126 static int igc_is_valid_ether_addr(u8 *); 127 static int igc_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 128 static void igc_add_int_delay_sysctl(struct igc_adapter *, const char *, 129 const char *, struct igc_int_delay_info *, int, int); 130 /* Management and WOL Support */ 131 static void igc_get_hw_control(struct igc_adapter *); 132 static void igc_release_hw_control(struct igc_adapter *); 133 static void igc_get_wakeup(if_ctx_t ctx); 134 static void igc_enable_wakeup(if_ctx_t ctx); 135 136 int igc_intr(void *arg); 137 138 /* MSI-X handlers */ 139 static int igc_if_msix_intr_assign(if_ctx_t, int); 140 static int igc_msix_link(void *); 141 static void igc_handle_link(void *context); 142 143 static int igc_set_flowcntl(SYSCTL_HANDLER_ARGS); 144 static int igc_sysctl_eee(SYSCTL_HANDLER_ARGS); 145 146 static int igc_get_regs(SYSCTL_HANDLER_ARGS); 147 148 static void igc_configure_queues(struct igc_adapter *adapter); 149 150 151 /********************************************************************* 152 * FreeBSD Device Interface Entry Points 153 *********************************************************************/ 154 static device_method_t igc_methods[] = { 155 /* Device interface */ 156 DEVMETHOD(device_register, igc_register), 157 DEVMETHOD(device_probe, iflib_device_probe), 158 DEVMETHOD(device_attach, iflib_device_attach), 159 DEVMETHOD(device_detach, iflib_device_detach), 160 DEVMETHOD(device_shutdown, iflib_device_shutdown), 161 DEVMETHOD(device_suspend, iflib_device_suspend), 162 DEVMETHOD(device_resume, iflib_device_resume), 163 DEVMETHOD_END 164 }; 165 166 static driver_t igc_driver = { 167 "igc", igc_methods, sizeof(struct igc_adapter), 168 }; 169 170 DRIVER_MODULE(igc, pci, igc_driver, 0, 0); 171 172 MODULE_DEPEND(igc, pci, 1, 1, 1); 173 MODULE_DEPEND(igc, ether, 1, 1, 1); 174 MODULE_DEPEND(igc, iflib, 1, 1, 1); 175 176 IFLIB_PNP_INFO(pci, igc, igc_vendor_info_array); 177 178 static device_method_t igc_if_methods[] = { 179 DEVMETHOD(ifdi_attach_pre, igc_if_attach_pre), 180 DEVMETHOD(ifdi_attach_post, igc_if_attach_post), 181 DEVMETHOD(ifdi_detach, igc_if_detach), 182 DEVMETHOD(ifdi_shutdown, igc_if_shutdown), 183 DEVMETHOD(ifdi_suspend, igc_if_suspend), 184 DEVMETHOD(ifdi_resume, igc_if_resume), 185 DEVMETHOD(ifdi_init, igc_if_init), 186 DEVMETHOD(ifdi_stop, igc_if_stop), 187 DEVMETHOD(ifdi_msix_intr_assign, igc_if_msix_intr_assign), 188 DEVMETHOD(ifdi_intr_enable, igc_if_intr_enable), 189 DEVMETHOD(ifdi_intr_disable, igc_if_intr_disable), 190 DEVMETHOD(ifdi_tx_queues_alloc, igc_if_tx_queues_alloc), 191 DEVMETHOD(ifdi_rx_queues_alloc, igc_if_rx_queues_alloc), 192 DEVMETHOD(ifdi_queues_free, igc_if_queues_free), 193 DEVMETHOD(ifdi_update_admin_status, igc_if_update_admin_status), 194 DEVMETHOD(ifdi_multi_set, igc_if_multi_set), 195 DEVMETHOD(ifdi_media_status, igc_if_media_status), 196 DEVMETHOD(ifdi_media_change, igc_if_media_change), 197 DEVMETHOD(ifdi_mtu_set, igc_if_mtu_set), 198 DEVMETHOD(ifdi_promisc_set, igc_if_set_promisc), 199 DEVMETHOD(ifdi_timer, igc_if_timer), 200 DEVMETHOD(ifdi_watchdog_reset, igc_if_watchdog_reset), 201 DEVMETHOD(ifdi_vlan_register, igc_if_vlan_register), 202 DEVMETHOD(ifdi_vlan_unregister, igc_if_vlan_unregister), 203 DEVMETHOD(ifdi_get_counter, igc_if_get_counter), 204 DEVMETHOD(ifdi_rx_queue_intr_enable, igc_if_rx_queue_intr_enable), 205 DEVMETHOD(ifdi_tx_queue_intr_enable, igc_if_tx_queue_intr_enable), 206 DEVMETHOD(ifdi_debug, igc_if_debug), 207 DEVMETHOD(ifdi_needs_restart, igc_if_needs_restart), 208 DEVMETHOD_END 209 }; 210 211 static driver_t igc_if_driver = { 212 "igc_if", igc_if_methods, sizeof(struct igc_adapter) 213 }; 214 215 /********************************************************************* 216 * Tunable default values. 217 *********************************************************************/ 218 219 #define IGC_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 220 #define IGC_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 221 222 #define MAX_INTS_PER_SEC 8000 223 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 224 225 /* Allow common code without TSO */ 226 #ifndef CSUM_TSO 227 #define CSUM_TSO 0 228 #endif 229 230 static SYSCTL_NODE(_hw, OID_AUTO, igc, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 231 "igc driver parameters"); 232 233 static int igc_disable_crc_stripping = 0; 234 SYSCTL_INT(_hw_igc, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 235 &igc_disable_crc_stripping, 0, "Disable CRC Stripping"); 236 237 static int igc_tx_int_delay_dflt = IGC_TICKS_TO_USECS(IGC_TIDV_VAL); 238 static int igc_rx_int_delay_dflt = IGC_TICKS_TO_USECS(IGC_RDTR_VAL); 239 SYSCTL_INT(_hw_igc, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &igc_tx_int_delay_dflt, 240 0, "Default transmit interrupt delay in usecs"); 241 SYSCTL_INT(_hw_igc, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &igc_rx_int_delay_dflt, 242 0, "Default receive interrupt delay in usecs"); 243 244 static int igc_tx_abs_int_delay_dflt = IGC_TICKS_TO_USECS(IGC_TADV_VAL); 245 static int igc_rx_abs_int_delay_dflt = IGC_TICKS_TO_USECS(IGC_RADV_VAL); 246 SYSCTL_INT(_hw_igc, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 247 &igc_tx_abs_int_delay_dflt, 0, 248 "Default transmit interrupt delay limit in usecs"); 249 SYSCTL_INT(_hw_igc, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 250 &igc_rx_abs_int_delay_dflt, 0, 251 "Default receive interrupt delay limit in usecs"); 252 253 static int igc_smart_pwr_down = false; 254 SYSCTL_INT(_hw_igc, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &igc_smart_pwr_down, 255 0, "Set to true to leave smart power down enabled on newer adapters"); 256 257 /* Controls whether promiscuous also shows bad packets */ 258 static int igc_debug_sbp = true; 259 SYSCTL_INT(_hw_igc, OID_AUTO, sbp, CTLFLAG_RDTUN, &igc_debug_sbp, 0, 260 "Show bad packets in promiscuous mode"); 261 262 /* How many packets rxeof tries to clean at a time */ 263 static int igc_rx_process_limit = 100; 264 SYSCTL_INT(_hw_igc, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 265 &igc_rx_process_limit, 0, 266 "Maximum number of received packets to process " 267 "at a time, -1 means unlimited"); 268 269 /* Energy efficient ethernet - default to OFF */ 270 static int igc_eee_setting = 1; 271 SYSCTL_INT(_hw_igc, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &igc_eee_setting, 0, 272 "Enable Energy Efficient Ethernet"); 273 274 /* 275 ** Tuneable Interrupt rate 276 */ 277 static int igc_max_interrupt_rate = 8000; 278 SYSCTL_INT(_hw_igc, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 279 &igc_max_interrupt_rate, 0, "Maximum interrupts per second"); 280 281 extern struct if_txrx igc_txrx; 282 283 static struct if_shared_ctx igc_sctx_init = { 284 .isc_magic = IFLIB_MAGIC, 285 .isc_q_align = PAGE_SIZE, 286 .isc_tx_maxsize = IGC_TSO_SIZE + sizeof(struct ether_vlan_header), 287 .isc_tx_maxsegsize = PAGE_SIZE, 288 .isc_tso_maxsize = IGC_TSO_SIZE + sizeof(struct ether_vlan_header), 289 .isc_tso_maxsegsize = IGC_TSO_SEG_SIZE, 290 .isc_rx_maxsize = MAX_JUMBO_FRAME_SIZE, 291 .isc_rx_nsegments = 1, 292 .isc_rx_maxsegsize = MJUM9BYTES, 293 .isc_nfl = 1, 294 .isc_nrxqs = 1, 295 .isc_ntxqs = 1, 296 .isc_admin_intrcnt = 1, 297 .isc_vendor_info = igc_vendor_info_array, 298 .isc_driver_version = "1", 299 .isc_driver = &igc_if_driver, 300 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 301 302 .isc_nrxd_min = {IGC_MIN_RXD}, 303 .isc_ntxd_min = {IGC_MIN_TXD}, 304 .isc_nrxd_max = {IGC_MAX_RXD}, 305 .isc_ntxd_max = {IGC_MAX_TXD}, 306 .isc_nrxd_default = {IGC_DEFAULT_RXD}, 307 .isc_ntxd_default = {IGC_DEFAULT_TXD}, 308 }; 309 310 /***************************************************************** 311 * 312 * Dump Registers 313 * 314 ****************************************************************/ 315 #define IGC_REGS_LEN 739 316 317 static int igc_get_regs(SYSCTL_HANDLER_ARGS) 318 { 319 struct igc_adapter *adapter = (struct igc_adapter *)arg1; 320 struct igc_hw *hw = &adapter->hw; 321 struct sbuf *sb; 322 u32 *regs_buff; 323 int rc; 324 325 regs_buff = malloc(sizeof(u32) * IGC_REGS_LEN, M_DEVBUF, M_WAITOK); 326 memset(regs_buff, 0, IGC_REGS_LEN * sizeof(u32)); 327 328 rc = sysctl_wire_old_buffer(req, 0); 329 MPASS(rc == 0); 330 if (rc != 0) { 331 free(regs_buff, M_DEVBUF); 332 return (rc); 333 } 334 335 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 336 MPASS(sb != NULL); 337 if (sb == NULL) { 338 free(regs_buff, M_DEVBUF); 339 return (ENOMEM); 340 } 341 342 /* General Registers */ 343 regs_buff[0] = IGC_READ_REG(hw, IGC_CTRL); 344 regs_buff[1] = IGC_READ_REG(hw, IGC_STATUS); 345 regs_buff[2] = IGC_READ_REG(hw, IGC_CTRL_EXT); 346 regs_buff[3] = IGC_READ_REG(hw, IGC_ICR); 347 regs_buff[4] = IGC_READ_REG(hw, IGC_RCTL); 348 regs_buff[5] = IGC_READ_REG(hw, IGC_RDLEN(0)); 349 regs_buff[6] = IGC_READ_REG(hw, IGC_RDH(0)); 350 regs_buff[7] = IGC_READ_REG(hw, IGC_RDT(0)); 351 regs_buff[8] = IGC_READ_REG(hw, IGC_RXDCTL(0)); 352 regs_buff[9] = IGC_READ_REG(hw, IGC_RDBAL(0)); 353 regs_buff[10] = IGC_READ_REG(hw, IGC_RDBAH(0)); 354 regs_buff[11] = IGC_READ_REG(hw, IGC_TCTL); 355 regs_buff[12] = IGC_READ_REG(hw, IGC_TDBAL(0)); 356 regs_buff[13] = IGC_READ_REG(hw, IGC_TDBAH(0)); 357 regs_buff[14] = IGC_READ_REG(hw, IGC_TDLEN(0)); 358 regs_buff[15] = IGC_READ_REG(hw, IGC_TDH(0)); 359 regs_buff[16] = IGC_READ_REG(hw, IGC_TDT(0)); 360 regs_buff[17] = IGC_READ_REG(hw, IGC_TXDCTL(0)); 361 362 sbuf_printf(sb, "General Registers\n"); 363 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 364 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 365 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 366 367 sbuf_printf(sb, "Interrupt Registers\n"); 368 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 369 370 sbuf_printf(sb, "RX Registers\n"); 371 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 372 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 373 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 374 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 375 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 376 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 377 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 378 379 sbuf_printf(sb, "TX Registers\n"); 380 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 381 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 382 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 383 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 384 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 385 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 386 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 387 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 388 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 389 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 390 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 391 392 free(regs_buff, M_DEVBUF); 393 394 #ifdef DUMP_DESCS 395 { 396 if_softc_ctx_t scctx = adapter->shared; 397 struct rx_ring *rxr = &rx_que->rxr; 398 struct tx_ring *txr = &tx_que->txr; 399 int ntxd = scctx->isc_ntxd[0]; 400 int nrxd = scctx->isc_nrxd[0]; 401 int j; 402 403 for (j = 0; j < nrxd; j++) { 404 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 405 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 406 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 407 } 408 409 for (j = 0; j < min(ntxd, 256); j++) { 410 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 411 412 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 413 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 414 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & IGC_TXD_STAT_DD : 0); 415 416 } 417 } 418 #endif 419 420 rc = sbuf_finish(sb); 421 sbuf_delete(sb); 422 return(rc); 423 } 424 425 static void * 426 igc_register(device_t dev) 427 { 428 return (&igc_sctx_init); 429 } 430 431 static int 432 igc_set_num_queues(if_ctx_t ctx) 433 { 434 int maxqueues; 435 436 maxqueues = 4; 437 438 return (maxqueues); 439 } 440 441 #define IGC_CAPS \ 442 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 443 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_VLAN_HWFILTER | IFCAP_TSO4 | \ 444 IFCAP_LRO | IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 |\ 445 IFCAP_TSO6 446 447 /********************************************************************* 448 * Device initialization routine 449 * 450 * The attach entry point is called when the driver is being loaded. 451 * This routine identifies the type of hardware, allocates all resources 452 * and initializes the hardware. 453 * 454 * return 0 on success, positive on failure 455 *********************************************************************/ 456 static int 457 igc_if_attach_pre(if_ctx_t ctx) 458 { 459 struct igc_adapter *adapter; 460 if_softc_ctx_t scctx; 461 device_t dev; 462 struct igc_hw *hw; 463 int error = 0; 464 465 INIT_DEBUGOUT("igc_if_attach_pre: begin"); 466 dev = iflib_get_dev(ctx); 467 adapter = iflib_get_softc(ctx); 468 469 adapter->ctx = adapter->osdep.ctx = ctx; 470 adapter->dev = adapter->osdep.dev = dev; 471 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 472 adapter->media = iflib_get_media(ctx); 473 hw = &adapter->hw; 474 475 adapter->tx_process_limit = scctx->isc_ntxd[0]; 476 477 /* SYSCTL stuff */ 478 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 479 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 480 OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 481 adapter, 0, igc_sysctl_nvm_info, "I", "NVM Information"); 482 483 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 484 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 485 OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 486 adapter, 0, igc_sysctl_debug_info, "I", "Debug Information"); 487 488 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 489 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 490 OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 491 adapter, 0, igc_set_flowcntl, "I", "Flow Control"); 492 493 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 494 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 495 OID_AUTO, "reg_dump", 496 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 0, 497 igc_get_regs, "A", "Dump Registers"); 498 499 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 500 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 501 OID_AUTO, "rs_dump", 502 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, adapter, 0, 503 igc_get_rs, "I", "Dump RS indexes"); 504 505 /* Determine hardware and mac info */ 506 igc_identify_hardware(ctx); 507 508 scctx->isc_tx_nsegments = IGC_MAX_SCATTER; 509 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = igc_set_num_queues(ctx); 510 if (bootverbose) 511 device_printf(dev, "attach_pre capping queues at %d\n", 512 scctx->isc_ntxqsets_max); 513 514 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union igc_adv_tx_desc), IGC_DBA_ALIGN); 515 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union igc_adv_rx_desc), IGC_DBA_ALIGN); 516 scctx->isc_txd_size[0] = sizeof(union igc_adv_tx_desc); 517 scctx->isc_rxd_size[0] = sizeof(union igc_adv_rx_desc); 518 scctx->isc_txrx = &igc_txrx; 519 scctx->isc_tx_tso_segments_max = IGC_MAX_SCATTER; 520 scctx->isc_tx_tso_size_max = IGC_TSO_SIZE; 521 scctx->isc_tx_tso_segsize_max = IGC_TSO_SEG_SIZE; 522 scctx->isc_capabilities = scctx->isc_capenable = IGC_CAPS; 523 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 524 CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_SCTP | CSUM_IP6_SCTP; 525 526 /* 527 ** Some new devices, as with ixgbe, now may 528 ** use a different BAR, so we need to keep 529 ** track of which is used. 530 */ 531 scctx->isc_msix_bar = PCIR_BAR(IGC_MSIX_BAR); 532 if (pci_read_config(dev, scctx->isc_msix_bar, 4) == 0) 533 scctx->isc_msix_bar += 4; 534 535 /* Setup PCI resources */ 536 if (igc_allocate_pci_resources(ctx)) { 537 device_printf(dev, "Allocation of PCI resources failed\n"); 538 error = ENXIO; 539 goto err_pci; 540 } 541 542 /* Do Shared Code initialization */ 543 error = igc_setup_init_funcs(hw, true); 544 if (error) { 545 device_printf(dev, "Setup of Shared code failed, error %d\n", 546 error); 547 error = ENXIO; 548 goto err_pci; 549 } 550 551 igc_setup_msix(ctx); 552 igc_get_bus_info(hw); 553 554 /* Set up some sysctls for the tunable interrupt delays */ 555 igc_add_int_delay_sysctl(adapter, "rx_int_delay", 556 "receive interrupt delay in usecs", &adapter->rx_int_delay, 557 IGC_REGISTER(hw, IGC_RDTR), igc_rx_int_delay_dflt); 558 igc_add_int_delay_sysctl(adapter, "tx_int_delay", 559 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 560 IGC_REGISTER(hw, IGC_TIDV), igc_tx_int_delay_dflt); 561 igc_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 562 "receive interrupt delay limit in usecs", 563 &adapter->rx_abs_int_delay, 564 IGC_REGISTER(hw, IGC_RADV), 565 igc_rx_abs_int_delay_dflt); 566 igc_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 567 "transmit interrupt delay limit in usecs", 568 &adapter->tx_abs_int_delay, 569 IGC_REGISTER(hw, IGC_TADV), 570 igc_tx_abs_int_delay_dflt); 571 igc_add_int_delay_sysctl(adapter, "itr", 572 "interrupt delay limit in usecs/4", 573 &adapter->tx_itr, 574 IGC_REGISTER(hw, IGC_ITR), 575 DEFAULT_ITR); 576 577 hw->mac.autoneg = DO_AUTO_NEG; 578 hw->phy.autoneg_wait_to_complete = false; 579 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 580 581 /* Copper options */ 582 if (hw->phy.media_type == igc_media_type_copper) { 583 hw->phy.mdix = AUTO_ALL_MODES; 584 } 585 586 /* 587 * Set the frame limits assuming 588 * standard ethernet sized frames. 589 */ 590 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 591 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 592 593 /* Allocate multicast array memory. */ 594 adapter->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 595 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 596 if (adapter->mta == NULL) { 597 device_printf(dev, "Can not allocate multicast setup array\n"); 598 error = ENOMEM; 599 goto err_late; 600 } 601 602 /* Check SOL/IDER usage */ 603 if (igc_check_reset_block(hw)) 604 device_printf(dev, "PHY reset is blocked" 605 " due to SOL/IDER session.\n"); 606 607 /* Sysctl for setting Energy Efficient Ethernet */ 608 adapter->hw.dev_spec._i225.eee_disable = igc_eee_setting; 609 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 610 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 611 OID_AUTO, "eee_control", 612 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 613 adapter, 0, igc_sysctl_eee, "I", 614 "Disable Energy Efficient Ethernet"); 615 616 /* 617 ** Start from a known state, this is 618 ** important in reading the nvm and 619 ** mac from that. 620 */ 621 igc_reset_hw(hw); 622 623 /* Make sure we have a good EEPROM before we read from it */ 624 if (igc_validate_nvm_checksum(hw) < 0) { 625 /* 626 ** Some PCI-E parts fail the first check due to 627 ** the link being in sleep state, call it again, 628 ** if it fails a second time its a real issue. 629 */ 630 if (igc_validate_nvm_checksum(hw) < 0) { 631 device_printf(dev, 632 "The EEPROM Checksum Is Not Valid\n"); 633 error = EIO; 634 goto err_late; 635 } 636 } 637 638 /* Copy the permanent MAC address out of the EEPROM */ 639 if (igc_read_mac_addr(hw) < 0) { 640 device_printf(dev, "EEPROM read error while reading MAC" 641 " address\n"); 642 error = EIO; 643 goto err_late; 644 } 645 646 if (!igc_is_valid_ether_addr(hw->mac.addr)) { 647 device_printf(dev, "Invalid MAC address\n"); 648 error = EIO; 649 goto err_late; 650 } 651 652 /* 653 * Get Wake-on-Lan and Management info for later use 654 */ 655 igc_get_wakeup(ctx); 656 657 /* Enable only WOL MAGIC by default */ 658 scctx->isc_capenable &= ~IFCAP_WOL; 659 if (adapter->wol != 0) 660 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 661 662 iflib_set_mac(ctx, hw->mac.addr); 663 664 return (0); 665 666 err_late: 667 igc_release_hw_control(adapter); 668 err_pci: 669 igc_free_pci_resources(ctx); 670 free(adapter->mta, M_DEVBUF); 671 672 return (error); 673 } 674 675 static int 676 igc_if_attach_post(if_ctx_t ctx) 677 { 678 struct igc_adapter *adapter = iflib_get_softc(ctx); 679 struct igc_hw *hw = &adapter->hw; 680 int error = 0; 681 682 /* Setup OS specific network interface */ 683 error = igc_setup_interface(ctx); 684 if (error != 0) { 685 goto err_late; 686 } 687 688 igc_reset(ctx); 689 690 /* Initialize statistics */ 691 igc_update_stats_counters(adapter); 692 hw->mac.get_link_status = true; 693 igc_if_update_admin_status(ctx); 694 igc_add_hw_stats(adapter); 695 696 /* the driver can now take control from firmware */ 697 igc_get_hw_control(adapter); 698 699 INIT_DEBUGOUT("igc_if_attach_post: end"); 700 701 return (error); 702 703 err_late: 704 igc_release_hw_control(adapter); 705 igc_free_pci_resources(ctx); 706 igc_if_queues_free(ctx); 707 free(adapter->mta, M_DEVBUF); 708 709 return (error); 710 } 711 712 /********************************************************************* 713 * Device removal routine 714 * 715 * The detach entry point is called when the driver is being removed. 716 * This routine stops the adapter and deallocates all the resources 717 * that were allocated for driver operation. 718 * 719 * return 0 on success, positive on failure 720 *********************************************************************/ 721 static int 722 igc_if_detach(if_ctx_t ctx) 723 { 724 struct igc_adapter *adapter = iflib_get_softc(ctx); 725 726 INIT_DEBUGOUT("igc_if_detach: begin"); 727 728 igc_phy_hw_reset(&adapter->hw); 729 730 igc_release_hw_control(adapter); 731 igc_free_pci_resources(ctx); 732 733 return (0); 734 } 735 736 /********************************************************************* 737 * 738 * Shutdown entry point 739 * 740 **********************************************************************/ 741 742 static int 743 igc_if_shutdown(if_ctx_t ctx) 744 { 745 return igc_if_suspend(ctx); 746 } 747 748 /* 749 * Suspend/resume device methods. 750 */ 751 static int 752 igc_if_suspend(if_ctx_t ctx) 753 { 754 struct igc_adapter *adapter = iflib_get_softc(ctx); 755 756 igc_release_hw_control(adapter); 757 igc_enable_wakeup(ctx); 758 return (0); 759 } 760 761 static int 762 igc_if_resume(if_ctx_t ctx) 763 { 764 igc_if_init(ctx); 765 766 return(0); 767 } 768 769 static int 770 igc_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 771 { 772 int max_frame_size; 773 struct igc_adapter *adapter = iflib_get_softc(ctx); 774 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 775 776 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 777 778 /* 9K Jumbo Frame size */ 779 max_frame_size = 9234; 780 781 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 782 return (EINVAL); 783 } 784 785 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 786 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 787 return (0); 788 } 789 790 /********************************************************************* 791 * Init entry point 792 * 793 * This routine is used in two ways. It is used by the stack as 794 * init entry point in network interface structure. It is also used 795 * by the driver as a hw/sw initialization routine to get to a 796 * consistent state. 797 * 798 **********************************************************************/ 799 static void 800 igc_if_init(if_ctx_t ctx) 801 { 802 struct igc_adapter *adapter = iflib_get_softc(ctx); 803 if_softc_ctx_t scctx = adapter->shared; 804 struct ifnet *ifp = iflib_get_ifp(ctx); 805 struct igc_tx_queue *tx_que; 806 int i; 807 808 INIT_DEBUGOUT("igc_if_init: begin"); 809 810 /* Get the latest mac address, User can use a LAA */ 811 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 812 ETHER_ADDR_LEN); 813 814 /* Put the address into the Receive Address Array */ 815 igc_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 816 817 /* Initialize the hardware */ 818 igc_reset(ctx); 819 igc_if_update_admin_status(ctx); 820 821 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 822 struct tx_ring *txr = &tx_que->txr; 823 824 txr->tx_rs_cidx = txr->tx_rs_pidx; 825 826 /* Initialize the last processed descriptor to be the end of 827 * the ring, rather than the start, so that we avoid an 828 * off-by-one error when calculating how many descriptors are 829 * done in the credits_update function. 830 */ 831 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 832 } 833 834 /* Setup VLAN support, basic and offload if available */ 835 IGC_WRITE_REG(&adapter->hw, IGC_VET, ETHERTYPE_VLAN); 836 837 /* Prepare transmit descriptors and buffers */ 838 igc_initialize_transmit_unit(ctx); 839 840 /* Setup Multicast table */ 841 igc_if_multi_set(ctx); 842 843 adapter->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 844 igc_initialize_receive_unit(ctx); 845 846 /* Use real VLAN Filter support? */ 847 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 848 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER) 849 /* Use real VLAN Filter support */ 850 igc_setup_vlan_hw_support(adapter); 851 else { 852 u32 ctrl; 853 ctrl = IGC_READ_REG(&adapter->hw, IGC_CTRL); 854 ctrl |= IGC_CTRL_VME; 855 IGC_WRITE_REG(&adapter->hw, IGC_CTRL, ctrl); 856 } 857 } 858 859 /* Don't lose promiscuous settings */ 860 igc_if_set_promisc(ctx, IFF_PROMISC); 861 igc_clear_hw_cntrs_base_generic(&adapter->hw); 862 863 if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 864 igc_configure_queues(adapter); 865 866 /* this clears any pending interrupts */ 867 IGC_READ_REG(&adapter->hw, IGC_ICR); 868 IGC_WRITE_REG(&adapter->hw, IGC_ICS, IGC_ICS_LSC); 869 870 /* the driver can now take control from firmware */ 871 igc_get_hw_control(adapter); 872 873 /* Set Energy Efficient Ethernet */ 874 igc_set_eee_i225(&adapter->hw, true, true, true); 875 } 876 877 /********************************************************************* 878 * 879 * Fast Legacy/MSI Combined Interrupt Service routine 880 * 881 *********************************************************************/ 882 int 883 igc_intr(void *arg) 884 { 885 struct igc_adapter *adapter = arg; 886 if_ctx_t ctx = adapter->ctx; 887 u32 reg_icr; 888 889 reg_icr = IGC_READ_REG(&adapter->hw, IGC_ICR); 890 891 /* Hot eject? */ 892 if (reg_icr == 0xffffffff) 893 return FILTER_STRAY; 894 895 /* Definitely not our interrupt. */ 896 if (reg_icr == 0x0) 897 return FILTER_STRAY; 898 899 if ((reg_icr & IGC_ICR_INT_ASSERTED) == 0) 900 return FILTER_STRAY; 901 902 /* 903 * Only MSI-X interrupts have one-shot behavior by taking advantage 904 * of the EIAC register. Thus, explicitly disable interrupts. This 905 * also works around the MSI message reordering errata on certain 906 * systems. 907 */ 908 IFDI_INTR_DISABLE(ctx); 909 910 /* Link status change */ 911 if (reg_icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) 912 igc_handle_link(ctx); 913 914 if (reg_icr & IGC_ICR_RXO) 915 adapter->rx_overruns++; 916 917 return (FILTER_SCHEDULE_THREAD); 918 } 919 920 static int 921 igc_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 922 { 923 struct igc_adapter *adapter = iflib_get_softc(ctx); 924 struct igc_rx_queue *rxq = &adapter->rx_queues[rxqid]; 925 926 IGC_WRITE_REG(&adapter->hw, IGC_EIMS, rxq->eims); 927 return (0); 928 } 929 930 static int 931 igc_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 932 { 933 struct igc_adapter *adapter = iflib_get_softc(ctx); 934 struct igc_tx_queue *txq = &adapter->tx_queues[txqid]; 935 936 IGC_WRITE_REG(&adapter->hw, IGC_EIMS, txq->eims); 937 return (0); 938 } 939 940 /********************************************************************* 941 * 942 * MSI-X RX Interrupt Service routine 943 * 944 **********************************************************************/ 945 static int 946 igc_msix_que(void *arg) 947 { 948 struct igc_rx_queue *que = arg; 949 950 ++que->irqs; 951 952 return (FILTER_SCHEDULE_THREAD); 953 } 954 955 /********************************************************************* 956 * 957 * MSI-X Link Fast Interrupt Service routine 958 * 959 **********************************************************************/ 960 static int 961 igc_msix_link(void *arg) 962 { 963 struct igc_adapter *adapter = arg; 964 u32 reg_icr; 965 966 ++adapter->link_irq; 967 MPASS(adapter->hw.back != NULL); 968 reg_icr = IGC_READ_REG(&adapter->hw, IGC_ICR); 969 970 if (reg_icr & IGC_ICR_RXO) 971 adapter->rx_overruns++; 972 973 if (reg_icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) { 974 igc_handle_link(adapter->ctx); 975 } 976 977 IGC_WRITE_REG(&adapter->hw, IGC_IMS, IGC_IMS_LSC); 978 IGC_WRITE_REG(&adapter->hw, IGC_EIMS, adapter->link_mask); 979 980 return (FILTER_HANDLED); 981 } 982 983 static void 984 igc_handle_link(void *context) 985 { 986 if_ctx_t ctx = context; 987 struct igc_adapter *adapter = iflib_get_softc(ctx); 988 989 adapter->hw.mac.get_link_status = true; 990 iflib_admin_intr_deferred(ctx); 991 } 992 993 /********************************************************************* 994 * 995 * Media Ioctl callback 996 * 997 * This routine is called whenever the user queries the status of 998 * the interface using ifconfig. 999 * 1000 **********************************************************************/ 1001 static void 1002 igc_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 1003 { 1004 struct igc_adapter *adapter = iflib_get_softc(ctx); 1005 1006 INIT_DEBUGOUT("igc_if_media_status: begin"); 1007 1008 iflib_admin_intr_deferred(ctx); 1009 1010 ifmr->ifm_status = IFM_AVALID; 1011 ifmr->ifm_active = IFM_ETHER; 1012 1013 if (!adapter->link_active) { 1014 return; 1015 } 1016 1017 ifmr->ifm_status |= IFM_ACTIVE; 1018 1019 switch (adapter->link_speed) { 1020 case 10: 1021 ifmr->ifm_active |= IFM_10_T; 1022 break; 1023 case 100: 1024 ifmr->ifm_active |= IFM_100_TX; 1025 break; 1026 case 1000: 1027 ifmr->ifm_active |= IFM_1000_T; 1028 break; 1029 case 2500: 1030 ifmr->ifm_active |= IFM_2500_T; 1031 break; 1032 } 1033 1034 if (adapter->link_duplex == FULL_DUPLEX) 1035 ifmr->ifm_active |= IFM_FDX; 1036 else 1037 ifmr->ifm_active |= IFM_HDX; 1038 } 1039 1040 /********************************************************************* 1041 * 1042 * Media Ioctl callback 1043 * 1044 * This routine is called when the user changes speed/duplex using 1045 * media/mediopt option with ifconfig. 1046 * 1047 **********************************************************************/ 1048 static int 1049 igc_if_media_change(if_ctx_t ctx) 1050 { 1051 struct igc_adapter *adapter = iflib_get_softc(ctx); 1052 struct ifmedia *ifm = iflib_get_media(ctx); 1053 1054 INIT_DEBUGOUT("igc_if_media_change: begin"); 1055 1056 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1057 return (EINVAL); 1058 1059 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1060 1061 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1062 case IFM_AUTO: 1063 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1064 break; 1065 case IFM_2500_T: 1066 adapter->hw.phy.autoneg_advertised = ADVERTISE_2500_FULL; 1067 break; 1068 case IFM_1000_T: 1069 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1070 break; 1071 case IFM_100_TX: 1072 if ((ifm->ifm_media & IFM_GMASK) == IFM_HDX) 1073 adapter->hw.phy.autoneg_advertised = ADVERTISE_100_HALF; 1074 else 1075 adapter->hw.phy.autoneg_advertised = ADVERTISE_100_FULL; 1076 break; 1077 case IFM_10_T: 1078 if ((ifm->ifm_media & IFM_GMASK) == IFM_HDX) 1079 adapter->hw.phy.autoneg_advertised = ADVERTISE_10_HALF; 1080 else 1081 adapter->hw.phy.autoneg_advertised = ADVERTISE_10_FULL; 1082 break; 1083 default: 1084 device_printf(adapter->dev, "Unsupported media type\n"); 1085 } 1086 1087 igc_if_init(ctx); 1088 1089 return (0); 1090 } 1091 1092 static int 1093 igc_if_set_promisc(if_ctx_t ctx, int flags) 1094 { 1095 struct igc_adapter *adapter = iflib_get_softc(ctx); 1096 struct ifnet *ifp = iflib_get_ifp(ctx); 1097 u32 reg_rctl; 1098 int mcnt = 0; 1099 1100 reg_rctl = IGC_READ_REG(&adapter->hw, IGC_RCTL); 1101 reg_rctl &= ~(IGC_RCTL_SBP | IGC_RCTL_UPE); 1102 if (flags & IFF_ALLMULTI) 1103 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1104 else 1105 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1106 1107 /* Don't disable if in MAX groups */ 1108 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1109 reg_rctl &= (~IGC_RCTL_MPE); 1110 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, reg_rctl); 1111 1112 if (flags & IFF_PROMISC) { 1113 reg_rctl |= (IGC_RCTL_UPE | IGC_RCTL_MPE); 1114 /* Turn this on if you want to see bad packets */ 1115 if (igc_debug_sbp) 1116 reg_rctl |= IGC_RCTL_SBP; 1117 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, reg_rctl); 1118 } else if (flags & IFF_ALLMULTI) { 1119 reg_rctl |= IGC_RCTL_MPE; 1120 reg_rctl &= ~IGC_RCTL_UPE; 1121 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, reg_rctl); 1122 } 1123 return (0); 1124 } 1125 1126 static u_int 1127 igc_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1128 { 1129 u8 *mta = arg; 1130 1131 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1132 return (0); 1133 1134 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1135 1136 return (1); 1137 } 1138 1139 /********************************************************************* 1140 * Multicast Update 1141 * 1142 * This routine is called whenever multicast address list is updated. 1143 * 1144 **********************************************************************/ 1145 1146 static void 1147 igc_if_multi_set(if_ctx_t ctx) 1148 { 1149 struct igc_adapter *adapter = iflib_get_softc(ctx); 1150 struct ifnet *ifp = iflib_get_ifp(ctx); 1151 u8 *mta; /* Multicast array memory */ 1152 u32 reg_rctl = 0; 1153 int mcnt = 0; 1154 1155 IOCTL_DEBUGOUT("igc_set_multi: begin"); 1156 1157 mta = adapter->mta; 1158 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1159 1160 mcnt = if_foreach_llmaddr(ifp, igc_copy_maddr, mta); 1161 1162 reg_rctl = IGC_READ_REG(&adapter->hw, IGC_RCTL); 1163 1164 if (if_getflags(ifp) & IFF_PROMISC) { 1165 reg_rctl |= (IGC_RCTL_UPE | IGC_RCTL_MPE); 1166 /* Turn this on if you want to see bad packets */ 1167 if (igc_debug_sbp) 1168 reg_rctl |= IGC_RCTL_SBP; 1169 } else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1170 if_getflags(ifp) & IFF_ALLMULTI) { 1171 reg_rctl |= IGC_RCTL_MPE; 1172 reg_rctl &= ~IGC_RCTL_UPE; 1173 } else 1174 reg_rctl &= ~(IGC_RCTL_UPE | IGC_RCTL_MPE); 1175 1176 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1177 igc_update_mc_addr_list(&adapter->hw, mta, mcnt); 1178 1179 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, reg_rctl); 1180 } 1181 1182 /********************************************************************* 1183 * Timer routine 1184 * 1185 * This routine schedules igc_if_update_admin_status() to check for 1186 * link status and to gather statistics as well as to perform some 1187 * controller-specific hardware patting. 1188 * 1189 **********************************************************************/ 1190 static void 1191 igc_if_timer(if_ctx_t ctx, uint16_t qid) 1192 { 1193 1194 if (qid != 0) 1195 return; 1196 1197 iflib_admin_intr_deferred(ctx); 1198 } 1199 1200 static void 1201 igc_if_update_admin_status(if_ctx_t ctx) 1202 { 1203 struct igc_adapter *adapter = iflib_get_softc(ctx); 1204 struct igc_hw *hw = &adapter->hw; 1205 device_t dev = iflib_get_dev(ctx); 1206 u32 link_check, thstat, ctrl; 1207 1208 link_check = thstat = ctrl = 0; 1209 /* Get the cached link value or read phy for real */ 1210 switch (hw->phy.media_type) { 1211 case igc_media_type_copper: 1212 if (hw->mac.get_link_status == true) { 1213 /* Do the work to read phy */ 1214 igc_check_for_link(hw); 1215 link_check = !hw->mac.get_link_status; 1216 } else 1217 link_check = true; 1218 break; 1219 case igc_media_type_unknown: 1220 igc_check_for_link(hw); 1221 link_check = !hw->mac.get_link_status; 1222 /* FALLTHROUGH */ 1223 default: 1224 break; 1225 } 1226 1227 /* Now check for a transition */ 1228 if (link_check && (adapter->link_active == 0)) { 1229 igc_get_speed_and_duplex(hw, &adapter->link_speed, 1230 &adapter->link_duplex); 1231 if (bootverbose) 1232 device_printf(dev, "Link is up %d Mbps %s\n", 1233 adapter->link_speed, 1234 ((adapter->link_duplex == FULL_DUPLEX) ? 1235 "Full Duplex" : "Half Duplex")); 1236 adapter->link_active = 1; 1237 iflib_link_state_change(ctx, LINK_STATE_UP, 1238 IF_Mbps(adapter->link_speed)); 1239 } else if (!link_check && (adapter->link_active == 1)) { 1240 adapter->link_speed = 0; 1241 adapter->link_duplex = 0; 1242 adapter->link_active = 0; 1243 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1244 } 1245 igc_update_stats_counters(adapter); 1246 } 1247 1248 static void 1249 igc_if_watchdog_reset(if_ctx_t ctx) 1250 { 1251 struct igc_adapter *adapter = iflib_get_softc(ctx); 1252 1253 /* 1254 * Just count the event; iflib(4) will already trigger a 1255 * sufficient reset of the controller. 1256 */ 1257 adapter->watchdog_events++; 1258 } 1259 1260 /********************************************************************* 1261 * 1262 * This routine disables all traffic on the adapter by issuing a 1263 * global reset on the MAC. 1264 * 1265 **********************************************************************/ 1266 static void 1267 igc_if_stop(if_ctx_t ctx) 1268 { 1269 struct igc_adapter *adapter = iflib_get_softc(ctx); 1270 1271 INIT_DEBUGOUT("igc_if_stop: begin"); 1272 1273 igc_reset_hw(&adapter->hw); 1274 IGC_WRITE_REG(&adapter->hw, IGC_WUC, 0); 1275 } 1276 1277 /********************************************************************* 1278 * 1279 * Determine hardware revision. 1280 * 1281 **********************************************************************/ 1282 static void 1283 igc_identify_hardware(if_ctx_t ctx) 1284 { 1285 device_t dev = iflib_get_dev(ctx); 1286 struct igc_adapter *adapter = iflib_get_softc(ctx); 1287 1288 /* Make sure our PCI config space has the necessary stuff set */ 1289 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1290 1291 /* Save off the information about this board */ 1292 adapter->hw.vendor_id = pci_get_vendor(dev); 1293 adapter->hw.device_id = pci_get_device(dev); 1294 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1295 adapter->hw.subsystem_vendor_id = 1296 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1297 adapter->hw.subsystem_device_id = 1298 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1299 1300 /* Do Shared Code Init and Setup */ 1301 if (igc_set_mac_type(&adapter->hw)) { 1302 device_printf(dev, "Setup init failure\n"); 1303 return; 1304 } 1305 } 1306 1307 static int 1308 igc_allocate_pci_resources(if_ctx_t ctx) 1309 { 1310 struct igc_adapter *adapter = iflib_get_softc(ctx); 1311 device_t dev = iflib_get_dev(ctx); 1312 int rid; 1313 1314 rid = PCIR_BAR(0); 1315 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1316 &rid, RF_ACTIVE); 1317 if (adapter->memory == NULL) { 1318 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1319 return (ENXIO); 1320 } 1321 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1322 adapter->osdep.mem_bus_space_handle = 1323 rman_get_bushandle(adapter->memory); 1324 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1325 1326 adapter->hw.back = &adapter->osdep; 1327 1328 return (0); 1329 } 1330 1331 /********************************************************************* 1332 * 1333 * Set up the MSI-X Interrupt handlers 1334 * 1335 **********************************************************************/ 1336 static int 1337 igc_if_msix_intr_assign(if_ctx_t ctx, int msix) 1338 { 1339 struct igc_adapter *adapter = iflib_get_softc(ctx); 1340 struct igc_rx_queue *rx_que = adapter->rx_queues; 1341 struct igc_tx_queue *tx_que = adapter->tx_queues; 1342 int error, rid, i, vector = 0, rx_vectors; 1343 char buf[16]; 1344 1345 /* First set up ring resources */ 1346 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 1347 rid = vector + 1; 1348 snprintf(buf, sizeof(buf), "rxq%d", i); 1349 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, igc_msix_que, rx_que, rx_que->me, buf); 1350 if (error) { 1351 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 1352 adapter->rx_num_queues = i + 1; 1353 goto fail; 1354 } 1355 1356 rx_que->msix = vector; 1357 1358 /* 1359 * Set the bit to enable interrupt 1360 * in IGC_IMS -- bits 20 and 21 1361 * are for RX0 and RX1, note this has 1362 * NOTHING to do with the MSI-X vector 1363 */ 1364 rx_que->eims = 1 << vector; 1365 } 1366 rx_vectors = vector; 1367 1368 vector = 0; 1369 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 1370 snprintf(buf, sizeof(buf), "txq%d", i); 1371 tx_que = &adapter->tx_queues[i]; 1372 iflib_softirq_alloc_generic(ctx, 1373 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq, 1374 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 1375 1376 tx_que->msix = (vector % adapter->rx_num_queues); 1377 1378 /* 1379 * Set the bit to enable interrupt 1380 * in IGC_IMS -- bits 22 and 23 1381 * are for TX0 and TX1, note this has 1382 * NOTHING to do with the MSI-X vector 1383 */ 1384 tx_que->eims = 1 << i; 1385 } 1386 1387 /* Link interrupt */ 1388 rid = rx_vectors + 1; 1389 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, igc_msix_link, adapter, 0, "aq"); 1390 1391 if (error) { 1392 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 1393 goto fail; 1394 } 1395 adapter->linkvec = rx_vectors; 1396 return (0); 1397 fail: 1398 iflib_irq_free(ctx, &adapter->irq); 1399 rx_que = adapter->rx_queues; 1400 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 1401 iflib_irq_free(ctx, &rx_que->que_irq); 1402 return (error); 1403 } 1404 1405 static void 1406 igc_configure_queues(struct igc_adapter *adapter) 1407 { 1408 struct igc_hw *hw = &adapter->hw; 1409 struct igc_rx_queue *rx_que; 1410 struct igc_tx_queue *tx_que; 1411 u32 ivar = 0, newitr = 0; 1412 1413 /* First turn on RSS capability */ 1414 IGC_WRITE_REG(hw, IGC_GPIE, 1415 IGC_GPIE_MSIX_MODE | IGC_GPIE_EIAME | IGC_GPIE_PBA | 1416 IGC_GPIE_NSICR); 1417 1418 /* Turn on MSI-X */ 1419 /* RX entries */ 1420 for (int i = 0; i < adapter->rx_num_queues; i++) { 1421 u32 index = i >> 1; 1422 ivar = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, index); 1423 rx_que = &adapter->rx_queues[i]; 1424 if (i & 1) { 1425 ivar &= 0xFF00FFFF; 1426 ivar |= (rx_que->msix | IGC_IVAR_VALID) << 16; 1427 } else { 1428 ivar &= 0xFFFFFF00; 1429 ivar |= rx_que->msix | IGC_IVAR_VALID; 1430 } 1431 IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, index, ivar); 1432 } 1433 /* TX entries */ 1434 for (int i = 0; i < adapter->tx_num_queues; i++) { 1435 u32 index = i >> 1; 1436 ivar = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, index); 1437 tx_que = &adapter->tx_queues[i]; 1438 if (i & 1) { 1439 ivar &= 0x00FFFFFF; 1440 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 24; 1441 } else { 1442 ivar &= 0xFFFF00FF; 1443 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 8; 1444 } 1445 IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, index, ivar); 1446 adapter->que_mask |= tx_que->eims; 1447 } 1448 1449 /* And for the link interrupt */ 1450 ivar = (adapter->linkvec | IGC_IVAR_VALID) << 8; 1451 adapter->link_mask = 1 << adapter->linkvec; 1452 IGC_WRITE_REG(hw, IGC_IVAR_MISC, ivar); 1453 1454 /* Set the starting interrupt rate */ 1455 if (igc_max_interrupt_rate > 0) 1456 newitr = (4000000 / igc_max_interrupt_rate) & 0x7FFC; 1457 1458 newitr |= IGC_EITR_CNT_IGNR; 1459 1460 for (int i = 0; i < adapter->rx_num_queues; i++) { 1461 rx_que = &adapter->rx_queues[i]; 1462 IGC_WRITE_REG(hw, IGC_EITR(rx_que->msix), newitr); 1463 } 1464 1465 return; 1466 } 1467 1468 static void 1469 igc_free_pci_resources(if_ctx_t ctx) 1470 { 1471 struct igc_adapter *adapter = iflib_get_softc(ctx); 1472 struct igc_rx_queue *que = adapter->rx_queues; 1473 device_t dev = iflib_get_dev(ctx); 1474 1475 /* Release all MSI-X queue resources */ 1476 if (adapter->intr_type == IFLIB_INTR_MSIX) 1477 iflib_irq_free(ctx, &adapter->irq); 1478 1479 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 1480 iflib_irq_free(ctx, &que->que_irq); 1481 } 1482 1483 if (adapter->memory != NULL) { 1484 bus_release_resource(dev, SYS_RES_MEMORY, 1485 rman_get_rid(adapter->memory), adapter->memory); 1486 adapter->memory = NULL; 1487 } 1488 1489 if (adapter->flash != NULL) { 1490 bus_release_resource(dev, SYS_RES_MEMORY, 1491 rman_get_rid(adapter->flash), adapter->flash); 1492 adapter->flash = NULL; 1493 } 1494 1495 if (adapter->ioport != NULL) { 1496 bus_release_resource(dev, SYS_RES_IOPORT, 1497 rman_get_rid(adapter->ioport), adapter->ioport); 1498 adapter->ioport = NULL; 1499 } 1500 } 1501 1502 /* Set up MSI or MSI-X */ 1503 static int 1504 igc_setup_msix(if_ctx_t ctx) 1505 { 1506 return (0); 1507 } 1508 1509 /********************************************************************* 1510 * 1511 * Initialize the DMA Coalescing feature 1512 * 1513 **********************************************************************/ 1514 static void 1515 igc_init_dmac(struct igc_adapter *adapter, u32 pba) 1516 { 1517 device_t dev = adapter->dev; 1518 struct igc_hw *hw = &adapter->hw; 1519 u32 dmac, reg = ~IGC_DMACR_DMAC_EN; 1520 u16 hwm; 1521 u16 max_frame_size; 1522 int status; 1523 1524 max_frame_size = adapter->shared->isc_max_frame_size; 1525 1526 if (adapter->dmac == 0) { /* Disabling it */ 1527 IGC_WRITE_REG(hw, IGC_DMACR, reg); 1528 return; 1529 } else 1530 device_printf(dev, "DMA Coalescing enabled\n"); 1531 1532 /* Set starting threshold */ 1533 IGC_WRITE_REG(hw, IGC_DMCTXTH, 0); 1534 1535 hwm = 64 * pba - max_frame_size / 16; 1536 if (hwm < 64 * (pba - 6)) 1537 hwm = 64 * (pba - 6); 1538 reg = IGC_READ_REG(hw, IGC_FCRTC); 1539 reg &= ~IGC_FCRTC_RTH_COAL_MASK; 1540 reg |= ((hwm << IGC_FCRTC_RTH_COAL_SHIFT) 1541 & IGC_FCRTC_RTH_COAL_MASK); 1542 IGC_WRITE_REG(hw, IGC_FCRTC, reg); 1543 1544 dmac = pba - max_frame_size / 512; 1545 if (dmac < pba - 10) 1546 dmac = pba - 10; 1547 reg = IGC_READ_REG(hw, IGC_DMACR); 1548 reg &= ~IGC_DMACR_DMACTHR_MASK; 1549 reg |= ((dmac << IGC_DMACR_DMACTHR_SHIFT) 1550 & IGC_DMACR_DMACTHR_MASK); 1551 1552 /* transition to L0x or L1 if available..*/ 1553 reg |= (IGC_DMACR_DMAC_EN | IGC_DMACR_DMAC_LX_MASK); 1554 1555 /* Check if status is 2.5Gb backplane connection 1556 * before configuration of watchdog timer, which is 1557 * in msec values in 12.8usec intervals 1558 * watchdog timer= msec values in 32usec intervals 1559 * for non 2.5Gb connection 1560 */ 1561 status = IGC_READ_REG(hw, IGC_STATUS); 1562 if ((status & IGC_STATUS_2P5_SKU) && 1563 (!(status & IGC_STATUS_2P5_SKU_OVER))) 1564 reg |= ((adapter->dmac * 5) >> 6); 1565 else 1566 reg |= (adapter->dmac >> 5); 1567 1568 IGC_WRITE_REG(hw, IGC_DMACR, reg); 1569 1570 IGC_WRITE_REG(hw, IGC_DMCRTRH, 0); 1571 1572 /* Set the interval before transition */ 1573 reg = IGC_READ_REG(hw, IGC_DMCTLX); 1574 reg |= IGC_DMCTLX_DCFLUSH_DIS; 1575 1576 /* 1577 ** in 2.5Gb connection, TTLX unit is 0.4 usec 1578 ** which is 0x4*2 = 0xA. But delay is still 4 usec 1579 */ 1580 status = IGC_READ_REG(hw, IGC_STATUS); 1581 if ((status & IGC_STATUS_2P5_SKU) && 1582 (!(status & IGC_STATUS_2P5_SKU_OVER))) 1583 reg |= 0xA; 1584 else 1585 reg |= 0x4; 1586 1587 IGC_WRITE_REG(hw, IGC_DMCTLX, reg); 1588 1589 /* free space in tx packet buffer to wake from DMA coal */ 1590 IGC_WRITE_REG(hw, IGC_DMCTXTH, (IGC_TXPBSIZE - 1591 (2 * max_frame_size)) >> 6); 1592 1593 /* make low power state decision controlled by DMA coal */ 1594 reg = IGC_READ_REG(hw, IGC_PCIEMISC); 1595 reg &= ~IGC_PCIEMISC_LX_DECISION; 1596 IGC_WRITE_REG(hw, IGC_PCIEMISC, reg); 1597 } 1598 1599 /********************************************************************* 1600 * 1601 * Initialize the hardware to a configuration as specified by the 1602 * adapter structure. 1603 * 1604 **********************************************************************/ 1605 static void 1606 igc_reset(if_ctx_t ctx) 1607 { 1608 device_t dev = iflib_get_dev(ctx); 1609 struct igc_adapter *adapter = iflib_get_softc(ctx); 1610 struct igc_hw *hw = &adapter->hw; 1611 u16 rx_buffer_size; 1612 u32 pba; 1613 1614 INIT_DEBUGOUT("igc_reset: begin"); 1615 /* Let the firmware know the OS is in control */ 1616 igc_get_hw_control(adapter); 1617 1618 /* 1619 * Packet Buffer Allocation (PBA) 1620 * Writing PBA sets the receive portion of the buffer 1621 * the remainder is used for the transmit buffer. 1622 */ 1623 pba = IGC_PBA_34K; 1624 1625 INIT_DEBUGOUT1("igc_reset: pba=%dK",pba); 1626 1627 /* 1628 * These parameters control the automatic generation (Tx) and 1629 * response (Rx) to Ethernet PAUSE frames. 1630 * - High water mark should allow for at least two frames to be 1631 * received after sending an XOFF. 1632 * - Low water mark works best when it is very near the high water mark. 1633 * This allows the receiver to restart by sending XON when it has 1634 * drained a bit. Here we use an arbitrary value of 1500 which will 1635 * restart after one full frame is pulled from the buffer. There 1636 * could be several smaller frames in the buffer and if so they will 1637 * not trigger the XON until their total number reduces the buffer 1638 * by 1500. 1639 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 1640 */ 1641 rx_buffer_size = (pba & 0xffff) << 10; 1642 hw->fc.high_water = rx_buffer_size - 1643 roundup2(adapter->hw.mac.max_frame_size, 1024); 1644 /* 16-byte granularity */ 1645 hw->fc.low_water = hw->fc.high_water - 16; 1646 1647 if (adapter->fc) /* locally set flow control value? */ 1648 hw->fc.requested_mode = adapter->fc; 1649 else 1650 hw->fc.requested_mode = igc_fc_full; 1651 1652 hw->fc.pause_time = IGC_FC_PAUSE_TIME; 1653 1654 hw->fc.send_xon = true; 1655 1656 /* Issue a global reset */ 1657 igc_reset_hw(hw); 1658 IGC_WRITE_REG(hw, IGC_WUC, 0); 1659 1660 /* and a re-init */ 1661 if (igc_init_hw(hw) < 0) { 1662 device_printf(dev, "Hardware Initialization Failed\n"); 1663 return; 1664 } 1665 1666 /* Setup DMA Coalescing */ 1667 igc_init_dmac(adapter, pba); 1668 1669 IGC_WRITE_REG(hw, IGC_VET, ETHERTYPE_VLAN); 1670 igc_get_phy_info(hw); 1671 igc_check_for_link(hw); 1672 } 1673 1674 /* 1675 * Initialise the RSS mapping for NICs that support multiple transmit/ 1676 * receive rings. 1677 */ 1678 1679 #define RSSKEYLEN 10 1680 static void 1681 igc_initialize_rss_mapping(struct igc_adapter *adapter) 1682 { 1683 struct igc_hw *hw = &adapter->hw; 1684 int i; 1685 int queue_id; 1686 u32 reta; 1687 u32 rss_key[RSSKEYLEN], mrqc, shift = 0; 1688 1689 /* 1690 * The redirection table controls which destination 1691 * queue each bucket redirects traffic to. 1692 * Each DWORD represents four queues, with the LSB 1693 * being the first queue in the DWORD. 1694 * 1695 * This just allocates buckets to queues using round-robin 1696 * allocation. 1697 * 1698 * NOTE: It Just Happens to line up with the default 1699 * RSS allocation method. 1700 */ 1701 1702 /* Warning FM follows */ 1703 reta = 0; 1704 for (i = 0; i < 128; i++) { 1705 #ifdef RSS 1706 queue_id = rss_get_indirection_to_bucket(i); 1707 /* 1708 * If we have more queues than buckets, we'll 1709 * end up mapping buckets to a subset of the 1710 * queues. 1711 * 1712 * If we have more buckets than queues, we'll 1713 * end up instead assigning multiple buckets 1714 * to queues. 1715 * 1716 * Both are suboptimal, but we need to handle 1717 * the case so we don't go out of bounds 1718 * indexing arrays and such. 1719 */ 1720 queue_id = queue_id % adapter->rx_num_queues; 1721 #else 1722 queue_id = (i % adapter->rx_num_queues); 1723 #endif 1724 /* Adjust if required */ 1725 queue_id = queue_id << shift; 1726 1727 /* 1728 * The low 8 bits are for hash value (n+0); 1729 * The next 8 bits are for hash value (n+1), etc. 1730 */ 1731 reta = reta >> 8; 1732 reta = reta | ( ((uint32_t) queue_id) << 24); 1733 if ((i & 3) == 3) { 1734 IGC_WRITE_REG(hw, IGC_RETA(i >> 2), reta); 1735 reta = 0; 1736 } 1737 } 1738 1739 /* Now fill in hash table */ 1740 1741 /* 1742 * MRQC: Multiple Receive Queues Command 1743 * Set queuing to RSS control, number depends on the device. 1744 */ 1745 mrqc = IGC_MRQC_ENABLE_RSS_4Q; 1746 1747 #ifdef RSS 1748 /* XXX ew typecasting */ 1749 rss_getkey((uint8_t *) &rss_key); 1750 #else 1751 arc4rand(&rss_key, sizeof(rss_key), 0); 1752 #endif 1753 for (i = 0; i < RSSKEYLEN; i++) 1754 IGC_WRITE_REG_ARRAY(hw, IGC_RSSRK(0), i, rss_key[i]); 1755 1756 /* 1757 * Configure the RSS fields to hash upon. 1758 */ 1759 mrqc |= (IGC_MRQC_RSS_FIELD_IPV4 | 1760 IGC_MRQC_RSS_FIELD_IPV4_TCP); 1761 mrqc |= (IGC_MRQC_RSS_FIELD_IPV6 | 1762 IGC_MRQC_RSS_FIELD_IPV6_TCP); 1763 mrqc |=( IGC_MRQC_RSS_FIELD_IPV4_UDP | 1764 IGC_MRQC_RSS_FIELD_IPV6_UDP); 1765 mrqc |=( IGC_MRQC_RSS_FIELD_IPV6_UDP_EX | 1766 IGC_MRQC_RSS_FIELD_IPV6_TCP_EX); 1767 1768 IGC_WRITE_REG(hw, IGC_MRQC, mrqc); 1769 } 1770 1771 /********************************************************************* 1772 * 1773 * Setup networking device structure and register interface media. 1774 * 1775 **********************************************************************/ 1776 static int 1777 igc_setup_interface(if_ctx_t ctx) 1778 { 1779 struct ifnet *ifp = iflib_get_ifp(ctx); 1780 struct igc_adapter *adapter = iflib_get_softc(ctx); 1781 if_softc_ctx_t scctx = adapter->shared; 1782 1783 INIT_DEBUGOUT("igc_setup_interface: begin"); 1784 1785 /* Single Queue */ 1786 if (adapter->tx_num_queues == 1) { 1787 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 1788 if_setsendqready(ifp); 1789 } 1790 1791 /* 1792 * Specify the media types supported by this adapter and register 1793 * callbacks to update media and link information 1794 */ 1795 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 1796 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1797 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 1798 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1799 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1800 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 1801 ifmedia_add(adapter->media, IFM_ETHER | IFM_2500_T, 0, NULL); 1802 1803 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1804 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 1805 return (0); 1806 } 1807 1808 static int 1809 igc_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 1810 { 1811 struct igc_adapter *adapter = iflib_get_softc(ctx); 1812 if_softc_ctx_t scctx = adapter->shared; 1813 int error = IGC_SUCCESS; 1814 struct igc_tx_queue *que; 1815 int i, j; 1816 1817 MPASS(adapter->tx_num_queues > 0); 1818 MPASS(adapter->tx_num_queues == ntxqsets); 1819 1820 /* First allocate the top level queue structs */ 1821 if (!(adapter->tx_queues = 1822 (struct igc_tx_queue *) malloc(sizeof(struct igc_tx_queue) * 1823 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 1824 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 1825 return(ENOMEM); 1826 } 1827 1828 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 1829 /* Set up some basics */ 1830 1831 struct tx_ring *txr = &que->txr; 1832 txr->adapter = que->adapter = adapter; 1833 que->me = txr->me = i; 1834 1835 /* Allocate report status array */ 1836 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 1837 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 1838 error = ENOMEM; 1839 goto fail; 1840 } 1841 for (j = 0; j < scctx->isc_ntxd[0]; j++) 1842 txr->tx_rsq[j] = QIDX_INVALID; 1843 /* get the virtual and physical address of the hardware queues */ 1844 txr->tx_base = (struct igc_tx_desc *)vaddrs[i*ntxqs]; 1845 txr->tx_paddr = paddrs[i*ntxqs]; 1846 } 1847 1848 if (bootverbose) 1849 device_printf(iflib_get_dev(ctx), 1850 "allocated for %d tx_queues\n", adapter->tx_num_queues); 1851 return (0); 1852 fail: 1853 igc_if_queues_free(ctx); 1854 return (error); 1855 } 1856 1857 static int 1858 igc_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 1859 { 1860 struct igc_adapter *adapter = iflib_get_softc(ctx); 1861 int error = IGC_SUCCESS; 1862 struct igc_rx_queue *que; 1863 int i; 1864 1865 MPASS(adapter->rx_num_queues > 0); 1866 MPASS(adapter->rx_num_queues == nrxqsets); 1867 1868 /* First allocate the top level queue structs */ 1869 if (!(adapter->rx_queues = 1870 (struct igc_rx_queue *) malloc(sizeof(struct igc_rx_queue) * 1871 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 1872 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 1873 error = ENOMEM; 1874 goto fail; 1875 } 1876 1877 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 1878 /* Set up some basics */ 1879 struct rx_ring *rxr = &que->rxr; 1880 rxr->adapter = que->adapter = adapter; 1881 rxr->que = que; 1882 que->me = rxr->me = i; 1883 1884 /* get the virtual and physical address of the hardware queues */ 1885 rxr->rx_base = (union igc_rx_desc_extended *)vaddrs[i*nrxqs]; 1886 rxr->rx_paddr = paddrs[i*nrxqs]; 1887 } 1888 1889 if (bootverbose) 1890 device_printf(iflib_get_dev(ctx), 1891 "allocated for %d rx_queues\n", adapter->rx_num_queues); 1892 1893 return (0); 1894 fail: 1895 igc_if_queues_free(ctx); 1896 return (error); 1897 } 1898 1899 static void 1900 igc_if_queues_free(if_ctx_t ctx) 1901 { 1902 struct igc_adapter *adapter = iflib_get_softc(ctx); 1903 struct igc_tx_queue *tx_que = adapter->tx_queues; 1904 struct igc_rx_queue *rx_que = adapter->rx_queues; 1905 1906 if (tx_que != NULL) { 1907 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 1908 struct tx_ring *txr = &tx_que->txr; 1909 if (txr->tx_rsq == NULL) 1910 break; 1911 1912 free(txr->tx_rsq, M_DEVBUF); 1913 txr->tx_rsq = NULL; 1914 } 1915 free(adapter->tx_queues, M_DEVBUF); 1916 adapter->tx_queues = NULL; 1917 } 1918 1919 if (rx_que != NULL) { 1920 free(adapter->rx_queues, M_DEVBUF); 1921 adapter->rx_queues = NULL; 1922 } 1923 1924 igc_release_hw_control(adapter); 1925 1926 if (adapter->mta != NULL) { 1927 free(adapter->mta, M_DEVBUF); 1928 } 1929 } 1930 1931 /********************************************************************* 1932 * 1933 * Enable transmit unit. 1934 * 1935 **********************************************************************/ 1936 static void 1937 igc_initialize_transmit_unit(if_ctx_t ctx) 1938 { 1939 struct igc_adapter *adapter = iflib_get_softc(ctx); 1940 if_softc_ctx_t scctx = adapter->shared; 1941 struct igc_tx_queue *que; 1942 struct tx_ring *txr; 1943 struct igc_hw *hw = &adapter->hw; 1944 u32 tctl, txdctl = 0; 1945 1946 INIT_DEBUGOUT("igc_initialize_transmit_unit: begin"); 1947 1948 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 1949 u64 bus_addr; 1950 caddr_t offp, endp; 1951 1952 que = &adapter->tx_queues[i]; 1953 txr = &que->txr; 1954 bus_addr = txr->tx_paddr; 1955 1956 /* Clear checksum offload context. */ 1957 offp = (caddr_t)&txr->csum_flags; 1958 endp = (caddr_t)(txr + 1); 1959 bzero(offp, endp - offp); 1960 1961 /* Base and Len of TX Ring */ 1962 IGC_WRITE_REG(hw, IGC_TDLEN(i), 1963 scctx->isc_ntxd[0] * sizeof(struct igc_tx_desc)); 1964 IGC_WRITE_REG(hw, IGC_TDBAH(i), 1965 (u32)(bus_addr >> 32)); 1966 IGC_WRITE_REG(hw, IGC_TDBAL(i), 1967 (u32)bus_addr); 1968 /* Init the HEAD/TAIL indices */ 1969 IGC_WRITE_REG(hw, IGC_TDT(i), 0); 1970 IGC_WRITE_REG(hw, IGC_TDH(i), 0); 1971 1972 HW_DEBUGOUT2("Base = %x, Length = %x\n", 1973 IGC_READ_REG(&adapter->hw, IGC_TDBAL(i)), 1974 IGC_READ_REG(&adapter->hw, IGC_TDLEN(i))); 1975 1976 txdctl = 0; /* clear txdctl */ 1977 txdctl |= 0x1f; /* PTHRESH */ 1978 txdctl |= 1 << 8; /* HTHRESH */ 1979 txdctl |= 1 << 16;/* WTHRESH */ 1980 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 1981 txdctl |= IGC_TXDCTL_GRAN; 1982 txdctl |= 1 << 25; /* LWTHRESH */ 1983 1984 IGC_WRITE_REG(hw, IGC_TXDCTL(i), txdctl); 1985 } 1986 1987 /* Program the Transmit Control Register */ 1988 tctl = IGC_READ_REG(&adapter->hw, IGC_TCTL); 1989 tctl &= ~IGC_TCTL_CT; 1990 tctl |= (IGC_TCTL_PSP | IGC_TCTL_RTLC | IGC_TCTL_EN | 1991 (IGC_COLLISION_THRESHOLD << IGC_CT_SHIFT)); 1992 1993 /* This write will effectively turn on the transmit unit. */ 1994 IGC_WRITE_REG(&adapter->hw, IGC_TCTL, tctl); 1995 } 1996 1997 /********************************************************************* 1998 * 1999 * Enable receive unit. 2000 * 2001 **********************************************************************/ 2002 2003 static void 2004 igc_initialize_receive_unit(if_ctx_t ctx) 2005 { 2006 struct igc_adapter *adapter = iflib_get_softc(ctx); 2007 if_softc_ctx_t scctx = adapter->shared; 2008 struct ifnet *ifp = iflib_get_ifp(ctx); 2009 struct igc_hw *hw = &adapter->hw; 2010 struct igc_rx_queue *que; 2011 int i; 2012 u32 psize, rctl, rxcsum, srrctl = 0; 2013 2014 INIT_DEBUGOUT("igc_initialize_receive_units: begin"); 2015 2016 /* 2017 * Make sure receives are disabled while setting 2018 * up the descriptor ring 2019 */ 2020 rctl = IGC_READ_REG(hw, IGC_RCTL); 2021 IGC_WRITE_REG(hw, IGC_RCTL, rctl & ~IGC_RCTL_EN); 2022 2023 /* Setup the Receive Control Register */ 2024 rctl &= ~(3 << IGC_RCTL_MO_SHIFT); 2025 rctl |= IGC_RCTL_EN | IGC_RCTL_BAM | 2026 IGC_RCTL_LBM_NO | IGC_RCTL_RDMTS_HALF | 2027 (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT); 2028 2029 /* Do not store bad packets */ 2030 rctl &= ~IGC_RCTL_SBP; 2031 2032 /* Enable Long Packet receive */ 2033 if (if_getmtu(ifp) > ETHERMTU) 2034 rctl |= IGC_RCTL_LPE; 2035 else 2036 rctl &= ~IGC_RCTL_LPE; 2037 2038 /* Strip the CRC */ 2039 if (!igc_disable_crc_stripping) 2040 rctl |= IGC_RCTL_SECRC; 2041 2042 /* 2043 * Set the interrupt throttling rate. Value is calculated 2044 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 2045 */ 2046 IGC_WRITE_REG(hw, IGC_ITR, DEFAULT_ITR); 2047 2048 rxcsum = IGC_READ_REG(hw, IGC_RXCSUM); 2049 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 2050 rxcsum |= IGC_RXCSUM_CRCOFL; 2051 if (adapter->tx_num_queues > 1) 2052 rxcsum |= IGC_RXCSUM_PCSD; 2053 else 2054 rxcsum |= IGC_RXCSUM_IPPCSE; 2055 } else { 2056 if (adapter->tx_num_queues > 1) 2057 rxcsum |= IGC_RXCSUM_PCSD; 2058 else 2059 rxcsum &= ~IGC_RXCSUM_TUOFL; 2060 } 2061 IGC_WRITE_REG(hw, IGC_RXCSUM, rxcsum); 2062 2063 if (adapter->rx_num_queues > 1) 2064 igc_initialize_rss_mapping(adapter); 2065 2066 if (if_getmtu(ifp) > ETHERMTU) { 2067 /* Set maximum packet len */ 2068 if (adapter->rx_mbuf_sz <= 4096) { 2069 srrctl |= 4096 >> IGC_SRRCTL_BSIZEPKT_SHIFT; 2070 rctl |= IGC_RCTL_SZ_4096 | IGC_RCTL_BSEX; 2071 } else if (adapter->rx_mbuf_sz > 4096) { 2072 srrctl |= 8192 >> IGC_SRRCTL_BSIZEPKT_SHIFT; 2073 rctl |= IGC_RCTL_SZ_8192 | IGC_RCTL_BSEX; 2074 } 2075 psize = scctx->isc_max_frame_size; 2076 /* are we on a vlan? */ 2077 if (ifp->if_vlantrunk != NULL) 2078 psize += VLAN_TAG_SIZE; 2079 IGC_WRITE_REG(&adapter->hw, IGC_RLPML, psize); 2080 } else { 2081 srrctl |= 2048 >> IGC_SRRCTL_BSIZEPKT_SHIFT; 2082 rctl |= IGC_RCTL_SZ_2048; 2083 } 2084 2085 /* 2086 * If TX flow control is disabled and there's >1 queue defined, 2087 * enable DROP. 2088 * 2089 * This drops frames rather than hanging the RX MAC for all queues. 2090 */ 2091 if ((adapter->rx_num_queues > 1) && 2092 (adapter->fc == igc_fc_none || 2093 adapter->fc == igc_fc_rx_pause)) { 2094 srrctl |= IGC_SRRCTL_DROP_EN; 2095 } 2096 2097 /* Setup the Base and Length of the Rx Descriptor Rings */ 2098 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 2099 struct rx_ring *rxr = &que->rxr; 2100 u64 bus_addr = rxr->rx_paddr; 2101 u32 rxdctl; 2102 2103 #ifdef notyet 2104 /* Configure for header split? -- ignore for now */ 2105 rxr->hdr_split = igc_header_split; 2106 #else 2107 srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF; 2108 #endif 2109 2110 IGC_WRITE_REG(hw, IGC_RDLEN(i), 2111 scctx->isc_nrxd[0] * sizeof(struct igc_rx_desc)); 2112 IGC_WRITE_REG(hw, IGC_RDBAH(i), 2113 (uint32_t)(bus_addr >> 32)); 2114 IGC_WRITE_REG(hw, IGC_RDBAL(i), 2115 (uint32_t)bus_addr); 2116 IGC_WRITE_REG(hw, IGC_SRRCTL(i), srrctl); 2117 /* Setup the Head and Tail Descriptor Pointers */ 2118 IGC_WRITE_REG(hw, IGC_RDH(i), 0); 2119 IGC_WRITE_REG(hw, IGC_RDT(i), 0); 2120 /* Enable this Queue */ 2121 rxdctl = IGC_READ_REG(hw, IGC_RXDCTL(i)); 2122 rxdctl |= IGC_RXDCTL_QUEUE_ENABLE; 2123 rxdctl &= 0xFFF00000; 2124 rxdctl |= IGC_RX_PTHRESH; 2125 rxdctl |= IGC_RX_HTHRESH << 8; 2126 rxdctl |= IGC_RX_WTHRESH << 16; 2127 IGC_WRITE_REG(hw, IGC_RXDCTL(i), rxdctl); 2128 } 2129 2130 /* Make sure VLAN Filters are off */ 2131 rctl &= ~IGC_RCTL_VFE; 2132 2133 /* Write out the settings */ 2134 IGC_WRITE_REG(hw, IGC_RCTL, rctl); 2135 2136 return; 2137 } 2138 2139 static void 2140 igc_if_vlan_register(if_ctx_t ctx, u16 vtag) 2141 { 2142 struct igc_adapter *adapter = iflib_get_softc(ctx); 2143 u32 index, bit; 2144 2145 index = (vtag >> 5) & 0x7F; 2146 bit = vtag & 0x1F; 2147 adapter->shadow_vfta[index] |= (1 << bit); 2148 ++adapter->num_vlans; 2149 } 2150 2151 static void 2152 igc_if_vlan_unregister(if_ctx_t ctx, u16 vtag) 2153 { 2154 struct igc_adapter *adapter = iflib_get_softc(ctx); 2155 u32 index, bit; 2156 2157 index = (vtag >> 5) & 0x7F; 2158 bit = vtag & 0x1F; 2159 adapter->shadow_vfta[index] &= ~(1 << bit); 2160 --adapter->num_vlans; 2161 } 2162 2163 static void 2164 igc_setup_vlan_hw_support(struct igc_adapter *adapter) 2165 { 2166 struct igc_hw *hw = &adapter->hw; 2167 u32 reg; 2168 2169 /* 2170 * We get here thru init_locked, meaning 2171 * a soft reset, this has already cleared 2172 * the VFTA and other state, so if there 2173 * have been no vlan's registered do nothing. 2174 */ 2175 if (adapter->num_vlans == 0) 2176 return; 2177 2178 /* 2179 * A soft reset zero's out the VFTA, so 2180 * we need to repopulate it now. 2181 */ 2182 for (int i = 0; i < IGC_VFTA_SIZE; i++) 2183 if (adapter->shadow_vfta[i] != 0) 2184 IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, 2185 i, adapter->shadow_vfta[i]); 2186 2187 reg = IGC_READ_REG(hw, IGC_CTRL); 2188 reg |= IGC_CTRL_VME; 2189 IGC_WRITE_REG(hw, IGC_CTRL, reg); 2190 2191 /* Enable the Filter Table */ 2192 reg = IGC_READ_REG(hw, IGC_RCTL); 2193 reg &= ~IGC_RCTL_CFIEN; 2194 reg |= IGC_RCTL_VFE; 2195 IGC_WRITE_REG(hw, IGC_RCTL, reg); 2196 } 2197 2198 static void 2199 igc_if_intr_enable(if_ctx_t ctx) 2200 { 2201 struct igc_adapter *adapter = iflib_get_softc(ctx); 2202 struct igc_hw *hw = &adapter->hw; 2203 u32 mask; 2204 2205 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 2206 mask = (adapter->que_mask | adapter->link_mask); 2207 IGC_WRITE_REG(hw, IGC_EIAC, mask); 2208 IGC_WRITE_REG(hw, IGC_EIAM, mask); 2209 IGC_WRITE_REG(hw, IGC_EIMS, mask); 2210 IGC_WRITE_REG(hw, IGC_IMS, IGC_IMS_LSC); 2211 } else 2212 IGC_WRITE_REG(hw, IGC_IMS, IMS_ENABLE_MASK); 2213 IGC_WRITE_FLUSH(hw); 2214 } 2215 2216 static void 2217 igc_if_intr_disable(if_ctx_t ctx) 2218 { 2219 struct igc_adapter *adapter = iflib_get_softc(ctx); 2220 struct igc_hw *hw = &adapter->hw; 2221 2222 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 2223 IGC_WRITE_REG(hw, IGC_EIMC, 0xffffffff); 2224 IGC_WRITE_REG(hw, IGC_EIAC, 0); 2225 } 2226 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff); 2227 IGC_WRITE_FLUSH(hw); 2228 } 2229 2230 /* 2231 * igc_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 2232 * For ASF and Pass Through versions of f/w this means 2233 * that the driver is loaded. For AMT version type f/w 2234 * this means that the network i/f is open. 2235 */ 2236 static void 2237 igc_get_hw_control(struct igc_adapter *adapter) 2238 { 2239 u32 ctrl_ext; 2240 2241 if (adapter->vf_ifp) 2242 return; 2243 2244 ctrl_ext = IGC_READ_REG(&adapter->hw, IGC_CTRL_EXT); 2245 IGC_WRITE_REG(&adapter->hw, IGC_CTRL_EXT, 2246 ctrl_ext | IGC_CTRL_EXT_DRV_LOAD); 2247 } 2248 2249 /* 2250 * igc_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 2251 * For ASF and Pass Through versions of f/w this means that 2252 * the driver is no longer loaded. For AMT versions of the 2253 * f/w this means that the network i/f is closed. 2254 */ 2255 static void 2256 igc_release_hw_control(struct igc_adapter *adapter) 2257 { 2258 u32 ctrl_ext; 2259 2260 ctrl_ext = IGC_READ_REG(&adapter->hw, IGC_CTRL_EXT); 2261 IGC_WRITE_REG(&adapter->hw, IGC_CTRL_EXT, 2262 ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD); 2263 return; 2264 } 2265 2266 static int 2267 igc_is_valid_ether_addr(u8 *addr) 2268 { 2269 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 2270 2271 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 2272 return (false); 2273 } 2274 2275 return (true); 2276 } 2277 2278 /* 2279 ** Parse the interface capabilities with regard 2280 ** to both system management and wake-on-lan for 2281 ** later use. 2282 */ 2283 static void 2284 igc_get_wakeup(if_ctx_t ctx) 2285 { 2286 struct igc_adapter *adapter = iflib_get_softc(ctx); 2287 u16 eeprom_data = 0, apme_mask; 2288 2289 apme_mask = IGC_WUC_APME; 2290 eeprom_data = IGC_READ_REG(&adapter->hw, IGC_WUC); 2291 2292 if (eeprom_data & apme_mask) 2293 adapter->wol = IGC_WUFC_LNKC; 2294 } 2295 2296 2297 /* 2298 * Enable PCI Wake On Lan capability 2299 */ 2300 static void 2301 igc_enable_wakeup(if_ctx_t ctx) 2302 { 2303 struct igc_adapter *adapter = iflib_get_softc(ctx); 2304 device_t dev = iflib_get_dev(ctx); 2305 if_t ifp = iflib_get_ifp(ctx); 2306 int error = 0; 2307 u32 pmc, ctrl, rctl; 2308 u16 status; 2309 2310 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 2311 return; 2312 2313 /* 2314 * Determine type of Wakeup: note that wol 2315 * is set with all bits on by default. 2316 */ 2317 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 2318 adapter->wol &= ~IGC_WUFC_MAG; 2319 2320 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 2321 adapter->wol &= ~IGC_WUFC_EX; 2322 2323 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 2324 adapter->wol &= ~IGC_WUFC_MC; 2325 else { 2326 rctl = IGC_READ_REG(&adapter->hw, IGC_RCTL); 2327 rctl |= IGC_RCTL_MPE; 2328 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, rctl); 2329 } 2330 2331 if (!(adapter->wol & (IGC_WUFC_EX | IGC_WUFC_MAG | IGC_WUFC_MC))) 2332 goto pme; 2333 2334 /* Advertise the wakeup capability */ 2335 ctrl = IGC_READ_REG(&adapter->hw, IGC_CTRL); 2336 ctrl |= IGC_CTRL_ADVD3WUC; 2337 IGC_WRITE_REG(&adapter->hw, IGC_CTRL, ctrl); 2338 2339 /* Enable wakeup by the MAC */ 2340 IGC_WRITE_REG(&adapter->hw, IGC_WUC, IGC_WUC_PME_EN); 2341 IGC_WRITE_REG(&adapter->hw, IGC_WUFC, adapter->wol); 2342 2343 pme: 2344 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 2345 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2346 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 2347 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2348 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 2349 2350 return; 2351 } 2352 2353 /********************************************************************** 2354 * 2355 * Update the board statistics counters. 2356 * 2357 **********************************************************************/ 2358 static void 2359 igc_update_stats_counters(struct igc_adapter *adapter) 2360 { 2361 u64 prev_xoffrxc = adapter->stats.xoffrxc; 2362 2363 adapter->stats.crcerrs += IGC_READ_REG(&adapter->hw, IGC_CRCERRS); 2364 adapter->stats.mpc += IGC_READ_REG(&adapter->hw, IGC_MPC); 2365 adapter->stats.scc += IGC_READ_REG(&adapter->hw, IGC_SCC); 2366 adapter->stats.ecol += IGC_READ_REG(&adapter->hw, IGC_ECOL); 2367 2368 adapter->stats.mcc += IGC_READ_REG(&adapter->hw, IGC_MCC); 2369 adapter->stats.latecol += IGC_READ_REG(&adapter->hw, IGC_LATECOL); 2370 adapter->stats.colc += IGC_READ_REG(&adapter->hw, IGC_COLC); 2371 adapter->stats.colc += IGC_READ_REG(&adapter->hw, IGC_RERC); 2372 adapter->stats.dc += IGC_READ_REG(&adapter->hw, IGC_DC); 2373 adapter->stats.rlec += IGC_READ_REG(&adapter->hw, IGC_RLEC); 2374 adapter->stats.xonrxc += IGC_READ_REG(&adapter->hw, IGC_XONRXC); 2375 adapter->stats.xontxc += IGC_READ_REG(&adapter->hw, IGC_XONTXC); 2376 adapter->stats.xoffrxc += IGC_READ_REG(&adapter->hw, IGC_XOFFRXC); 2377 /* 2378 * For watchdog management we need to know if we have been 2379 * paused during the last interval, so capture that here. 2380 */ 2381 if (adapter->stats.xoffrxc != prev_xoffrxc) 2382 adapter->shared->isc_pause_frames = 1; 2383 adapter->stats.xofftxc += IGC_READ_REG(&adapter->hw, IGC_XOFFTXC); 2384 adapter->stats.fcruc += IGC_READ_REG(&adapter->hw, IGC_FCRUC); 2385 adapter->stats.prc64 += IGC_READ_REG(&adapter->hw, IGC_PRC64); 2386 adapter->stats.prc127 += IGC_READ_REG(&adapter->hw, IGC_PRC127); 2387 adapter->stats.prc255 += IGC_READ_REG(&adapter->hw, IGC_PRC255); 2388 adapter->stats.prc511 += IGC_READ_REG(&adapter->hw, IGC_PRC511); 2389 adapter->stats.prc1023 += IGC_READ_REG(&adapter->hw, IGC_PRC1023); 2390 adapter->stats.prc1522 += IGC_READ_REG(&adapter->hw, IGC_PRC1522); 2391 adapter->stats.tlpic += IGC_READ_REG(&adapter->hw, IGC_TLPIC); 2392 adapter->stats.rlpic += IGC_READ_REG(&adapter->hw, IGC_RLPIC); 2393 adapter->stats.gprc += IGC_READ_REG(&adapter->hw, IGC_GPRC); 2394 adapter->stats.bprc += IGC_READ_REG(&adapter->hw, IGC_BPRC); 2395 adapter->stats.mprc += IGC_READ_REG(&adapter->hw, IGC_MPRC); 2396 adapter->stats.gptc += IGC_READ_REG(&adapter->hw, IGC_GPTC); 2397 2398 /* For the 64-bit byte counters the low dword must be read first. */ 2399 /* Both registers clear on the read of the high dword */ 2400 2401 adapter->stats.gorc += IGC_READ_REG(&adapter->hw, IGC_GORCL) + 2402 ((u64)IGC_READ_REG(&adapter->hw, IGC_GORCH) << 32); 2403 adapter->stats.gotc += IGC_READ_REG(&adapter->hw, IGC_GOTCL) + 2404 ((u64)IGC_READ_REG(&adapter->hw, IGC_GOTCH) << 32); 2405 2406 adapter->stats.rnbc += IGC_READ_REG(&adapter->hw, IGC_RNBC); 2407 adapter->stats.ruc += IGC_READ_REG(&adapter->hw, IGC_RUC); 2408 adapter->stats.rfc += IGC_READ_REG(&adapter->hw, IGC_RFC); 2409 adapter->stats.roc += IGC_READ_REG(&adapter->hw, IGC_ROC); 2410 adapter->stats.rjc += IGC_READ_REG(&adapter->hw, IGC_RJC); 2411 2412 adapter->stats.tor += IGC_READ_REG(&adapter->hw, IGC_TORH); 2413 adapter->stats.tot += IGC_READ_REG(&adapter->hw, IGC_TOTH); 2414 2415 adapter->stats.tpr += IGC_READ_REG(&adapter->hw, IGC_TPR); 2416 adapter->stats.tpt += IGC_READ_REG(&adapter->hw, IGC_TPT); 2417 adapter->stats.ptc64 += IGC_READ_REG(&adapter->hw, IGC_PTC64); 2418 adapter->stats.ptc127 += IGC_READ_REG(&adapter->hw, IGC_PTC127); 2419 adapter->stats.ptc255 += IGC_READ_REG(&adapter->hw, IGC_PTC255); 2420 adapter->stats.ptc511 += IGC_READ_REG(&adapter->hw, IGC_PTC511); 2421 adapter->stats.ptc1023 += IGC_READ_REG(&adapter->hw, IGC_PTC1023); 2422 adapter->stats.ptc1522 += IGC_READ_REG(&adapter->hw, IGC_PTC1522); 2423 adapter->stats.mptc += IGC_READ_REG(&adapter->hw, IGC_MPTC); 2424 adapter->stats.bptc += IGC_READ_REG(&adapter->hw, IGC_BPTC); 2425 2426 /* Interrupt Counts */ 2427 adapter->stats.iac += IGC_READ_REG(&adapter->hw, IGC_IAC); 2428 adapter->stats.rxdmtc += IGC_READ_REG(&adapter->hw, IGC_RXDMTC); 2429 2430 adapter->stats.algnerrc += IGC_READ_REG(&adapter->hw, IGC_ALGNERRC); 2431 adapter->stats.tncrs += IGC_READ_REG(&adapter->hw, IGC_TNCRS); 2432 adapter->stats.htdpmc += IGC_READ_REG(&adapter->hw, IGC_HTDPMC); 2433 adapter->stats.tsctc += IGC_READ_REG(&adapter->hw, IGC_TSCTC); 2434 } 2435 2436 static uint64_t 2437 igc_if_get_counter(if_ctx_t ctx, ift_counter cnt) 2438 { 2439 struct igc_adapter *adapter = iflib_get_softc(ctx); 2440 struct ifnet *ifp = iflib_get_ifp(ctx); 2441 2442 switch (cnt) { 2443 case IFCOUNTER_COLLISIONS: 2444 return (adapter->stats.colc); 2445 case IFCOUNTER_IERRORS: 2446 return (adapter->dropped_pkts + adapter->stats.rxerrc + 2447 adapter->stats.crcerrs + adapter->stats.algnerrc + 2448 adapter->stats.ruc + adapter->stats.roc + 2449 adapter->stats.mpc + adapter->stats.htdpmc); 2450 case IFCOUNTER_OERRORS: 2451 return (adapter->stats.ecol + adapter->stats.latecol + 2452 adapter->watchdog_events); 2453 default: 2454 return (if_get_counter_default(ifp, cnt)); 2455 } 2456 } 2457 2458 /* igc_if_needs_restart - Tell iflib when the driver needs to be reinitialized 2459 * @ctx: iflib context 2460 * @event: event code to check 2461 * 2462 * Defaults to returning true for unknown events. 2463 * 2464 * @returns true if iflib needs to reinit the interface 2465 */ 2466 static bool 2467 igc_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 2468 { 2469 switch (event) { 2470 case IFLIB_RESTART_VLAN_CONFIG: 2471 default: 2472 return (true); 2473 } 2474 } 2475 2476 /* Export a single 32-bit register via a read-only sysctl. */ 2477 static int 2478 igc_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 2479 { 2480 struct igc_adapter *adapter; 2481 u_int val; 2482 2483 adapter = oidp->oid_arg1; 2484 val = IGC_READ_REG(&adapter->hw, oidp->oid_arg2); 2485 return (sysctl_handle_int(oidp, &val, 0, req)); 2486 } 2487 2488 /* 2489 * Add sysctl variables, one per statistic, to the system. 2490 */ 2491 static void 2492 igc_add_hw_stats(struct igc_adapter *adapter) 2493 { 2494 device_t dev = iflib_get_dev(adapter->ctx); 2495 struct igc_tx_queue *tx_que = adapter->tx_queues; 2496 struct igc_rx_queue *rx_que = adapter->rx_queues; 2497 2498 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 2499 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 2500 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 2501 struct igc_hw_stats *stats = &adapter->stats; 2502 2503 struct sysctl_oid *stat_node, *queue_node, *int_node; 2504 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 2505 2506 #define QUEUE_NAME_LEN 32 2507 char namebuf[QUEUE_NAME_LEN]; 2508 2509 /* Driver Statistics */ 2510 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 2511 CTLFLAG_RD, &adapter->dropped_pkts, 2512 "Driver dropped packets"); 2513 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 2514 CTLFLAG_RD, &adapter->link_irq, 2515 "Link MSI-X IRQ Handled"); 2516 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 2517 CTLFLAG_RD, &adapter->rx_overruns, 2518 "RX overruns"); 2519 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 2520 CTLFLAG_RD, &adapter->watchdog_events, 2521 "Watchdog timeouts"); 2522 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 2523 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 2524 adapter, IGC_CTRL, igc_sysctl_reg_handler, "IU", 2525 "Device Control Register"); 2526 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 2527 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 2528 adapter, IGC_RCTL, igc_sysctl_reg_handler, "IU", 2529 "Receiver Control Register"); 2530 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 2531 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 2532 "Flow Control High Watermark"); 2533 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 2534 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 2535 "Flow Control Low Watermark"); 2536 2537 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 2538 struct tx_ring *txr = &tx_que->txr; 2539 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 2540 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 2541 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 2542 queue_list = SYSCTL_CHILDREN(queue_node); 2543 2544 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 2545 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 2546 IGC_TDH(txr->me), igc_sysctl_reg_handler, "IU", 2547 "Transmit Descriptor Head"); 2548 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 2549 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 2550 IGC_TDT(txr->me), igc_sysctl_reg_handler, "IU", 2551 "Transmit Descriptor Tail"); 2552 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 2553 CTLFLAG_RD, &txr->tx_irq, 2554 "Queue MSI-X Transmit Interrupts"); 2555 } 2556 2557 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 2558 struct rx_ring *rxr = &rx_que->rxr; 2559 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 2560 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 2561 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 2562 queue_list = SYSCTL_CHILDREN(queue_node); 2563 2564 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 2565 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 2566 IGC_RDH(rxr->me), igc_sysctl_reg_handler, "IU", 2567 "Receive Descriptor Head"); 2568 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 2569 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 2570 IGC_RDT(rxr->me), igc_sysctl_reg_handler, "IU", 2571 "Receive Descriptor Tail"); 2572 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 2573 CTLFLAG_RD, &rxr->rx_irq, 2574 "Queue MSI-X Receive Interrupts"); 2575 } 2576 2577 /* MAC stats get their own sub node */ 2578 2579 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 2580 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 2581 stat_list = SYSCTL_CHILDREN(stat_node); 2582 2583 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 2584 CTLFLAG_RD, &stats->ecol, 2585 "Excessive collisions"); 2586 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 2587 CTLFLAG_RD, &stats->scc, 2588 "Single collisions"); 2589 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 2590 CTLFLAG_RD, &stats->mcc, 2591 "Multiple collisions"); 2592 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 2593 CTLFLAG_RD, &stats->latecol, 2594 "Late collisions"); 2595 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 2596 CTLFLAG_RD, &stats->colc, 2597 "Collision Count"); 2598 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 2599 CTLFLAG_RD, &adapter->stats.symerrs, 2600 "Symbol Errors"); 2601 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 2602 CTLFLAG_RD, &adapter->stats.sec, 2603 "Sequence Errors"); 2604 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 2605 CTLFLAG_RD, &adapter->stats.dc, 2606 "Defer Count"); 2607 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 2608 CTLFLAG_RD, &adapter->stats.mpc, 2609 "Missed Packets"); 2610 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 2611 CTLFLAG_RD, &adapter->stats.rnbc, 2612 "Receive No Buffers"); 2613 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 2614 CTLFLAG_RD, &adapter->stats.ruc, 2615 "Receive Undersize"); 2616 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 2617 CTLFLAG_RD, &adapter->stats.rfc, 2618 "Fragmented Packets Received "); 2619 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 2620 CTLFLAG_RD, &adapter->stats.roc, 2621 "Oversized Packets Received"); 2622 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 2623 CTLFLAG_RD, &adapter->stats.rjc, 2624 "Recevied Jabber"); 2625 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 2626 CTLFLAG_RD, &adapter->stats.rxerrc, 2627 "Receive Errors"); 2628 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 2629 CTLFLAG_RD, &adapter->stats.crcerrs, 2630 "CRC errors"); 2631 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 2632 CTLFLAG_RD, &adapter->stats.algnerrc, 2633 "Alignment Errors"); 2634 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 2635 CTLFLAG_RD, &adapter->stats.xonrxc, 2636 "XON Received"); 2637 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 2638 CTLFLAG_RD, &adapter->stats.xontxc, 2639 "XON Transmitted"); 2640 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 2641 CTLFLAG_RD, &adapter->stats.xoffrxc, 2642 "XOFF Received"); 2643 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 2644 CTLFLAG_RD, &adapter->stats.xofftxc, 2645 "XOFF Transmitted"); 2646 2647 /* Packet Reception Stats */ 2648 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 2649 CTLFLAG_RD, &adapter->stats.tpr, 2650 "Total Packets Received "); 2651 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 2652 CTLFLAG_RD, &adapter->stats.gprc, 2653 "Good Packets Received"); 2654 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 2655 CTLFLAG_RD, &adapter->stats.bprc, 2656 "Broadcast Packets Received"); 2657 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 2658 CTLFLAG_RD, &adapter->stats.mprc, 2659 "Multicast Packets Received"); 2660 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 2661 CTLFLAG_RD, &adapter->stats.prc64, 2662 "64 byte frames received "); 2663 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 2664 CTLFLAG_RD, &adapter->stats.prc127, 2665 "65-127 byte frames received"); 2666 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 2667 CTLFLAG_RD, &adapter->stats.prc255, 2668 "128-255 byte frames received"); 2669 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 2670 CTLFLAG_RD, &adapter->stats.prc511, 2671 "256-511 byte frames received"); 2672 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 2673 CTLFLAG_RD, &adapter->stats.prc1023, 2674 "512-1023 byte frames received"); 2675 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 2676 CTLFLAG_RD, &adapter->stats.prc1522, 2677 "1023-1522 byte frames received"); 2678 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 2679 CTLFLAG_RD, &adapter->stats.gorc, 2680 "Good Octets Received"); 2681 2682 /* Packet Transmission Stats */ 2683 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 2684 CTLFLAG_RD, &adapter->stats.gotc, 2685 "Good Octets Transmitted"); 2686 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 2687 CTLFLAG_RD, &adapter->stats.tpt, 2688 "Total Packets Transmitted"); 2689 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 2690 CTLFLAG_RD, &adapter->stats.gptc, 2691 "Good Packets Transmitted"); 2692 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 2693 CTLFLAG_RD, &adapter->stats.bptc, 2694 "Broadcast Packets Transmitted"); 2695 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 2696 CTLFLAG_RD, &adapter->stats.mptc, 2697 "Multicast Packets Transmitted"); 2698 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 2699 CTLFLAG_RD, &adapter->stats.ptc64, 2700 "64 byte frames transmitted "); 2701 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 2702 CTLFLAG_RD, &adapter->stats.ptc127, 2703 "65-127 byte frames transmitted"); 2704 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 2705 CTLFLAG_RD, &adapter->stats.ptc255, 2706 "128-255 byte frames transmitted"); 2707 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 2708 CTLFLAG_RD, &adapter->stats.ptc511, 2709 "256-511 byte frames transmitted"); 2710 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 2711 CTLFLAG_RD, &adapter->stats.ptc1023, 2712 "512-1023 byte frames transmitted"); 2713 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 2714 CTLFLAG_RD, &adapter->stats.ptc1522, 2715 "1024-1522 byte frames transmitted"); 2716 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 2717 CTLFLAG_RD, &adapter->stats.tsctc, 2718 "TSO Contexts Transmitted"); 2719 2720 /* Interrupt Stats */ 2721 2722 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 2723 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 2724 int_list = SYSCTL_CHILDREN(int_node); 2725 2726 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 2727 CTLFLAG_RD, &adapter->stats.iac, 2728 "Interrupt Assertion Count"); 2729 2730 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 2731 CTLFLAG_RD, &adapter->stats.rxdmtc, 2732 "Rx Desc Min Thresh Count"); 2733 } 2734 2735 /********************************************************************** 2736 * 2737 * This routine provides a way to dump out the adapter eeprom, 2738 * often a useful debug/service tool. This only dumps the first 2739 * 32 words, stuff that matters is in that extent. 2740 * 2741 **********************************************************************/ 2742 static int 2743 igc_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 2744 { 2745 struct igc_adapter *adapter = (struct igc_adapter *)arg1; 2746 int error; 2747 int result; 2748 2749 result = -1; 2750 error = sysctl_handle_int(oidp, &result, 0, req); 2751 2752 if (error || !req->newptr) 2753 return (error); 2754 2755 /* 2756 * This value will cause a hex dump of the 2757 * first 32 16-bit words of the EEPROM to 2758 * the screen. 2759 */ 2760 if (result == 1) 2761 igc_print_nvm_info(adapter); 2762 2763 return (error); 2764 } 2765 2766 static void 2767 igc_print_nvm_info(struct igc_adapter *adapter) 2768 { 2769 u16 eeprom_data; 2770 int i, j, row = 0; 2771 2772 /* Its a bit crude, but it gets the job done */ 2773 printf("\nInterface EEPROM Dump:\n"); 2774 printf("Offset\n0x0000 "); 2775 for (i = 0, j = 0; i < 32; i++, j++) { 2776 if (j == 8) { /* Make the offset block */ 2777 j = 0; ++row; 2778 printf("\n0x00%x0 ",row); 2779 } 2780 igc_read_nvm(&adapter->hw, i, 1, &eeprom_data); 2781 printf("%04x ", eeprom_data); 2782 } 2783 printf("\n"); 2784 } 2785 2786 static int 2787 igc_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 2788 { 2789 struct igc_int_delay_info *info; 2790 struct igc_adapter *adapter; 2791 u32 regval; 2792 int error, usecs, ticks; 2793 2794 info = (struct igc_int_delay_info *) arg1; 2795 usecs = info->value; 2796 error = sysctl_handle_int(oidp, &usecs, 0, req); 2797 if (error != 0 || req->newptr == NULL) 2798 return (error); 2799 if (usecs < 0 || usecs > IGC_TICKS_TO_USECS(65535)) 2800 return (EINVAL); 2801 info->value = usecs; 2802 ticks = IGC_USECS_TO_TICKS(usecs); 2803 if (info->offset == IGC_ITR) /* units are 256ns here */ 2804 ticks *= 4; 2805 2806 adapter = info->adapter; 2807 2808 regval = IGC_READ_OFFSET(&adapter->hw, info->offset); 2809 regval = (regval & ~0xffff) | (ticks & 0xffff); 2810 /* Handle a few special cases. */ 2811 switch (info->offset) { 2812 case IGC_RDTR: 2813 break; 2814 case IGC_TIDV: 2815 if (ticks == 0) { 2816 adapter->txd_cmd &= ~IGC_TXD_CMD_IDE; 2817 /* Don't write 0 into the TIDV register. */ 2818 regval++; 2819 } else 2820 adapter->txd_cmd |= IGC_TXD_CMD_IDE; 2821 break; 2822 } 2823 IGC_WRITE_OFFSET(&adapter->hw, info->offset, regval); 2824 return (0); 2825 } 2826 2827 static void 2828 igc_add_int_delay_sysctl(struct igc_adapter *adapter, const char *name, 2829 const char *description, struct igc_int_delay_info *info, 2830 int offset, int value) 2831 { 2832 info->adapter = adapter; 2833 info->offset = offset; 2834 info->value = value; 2835 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 2836 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 2837 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 2838 info, 0, igc_sysctl_int_delay, "I", description); 2839 } 2840 2841 /* 2842 * Set flow control using sysctl: 2843 * Flow control values: 2844 * 0 - off 2845 * 1 - rx pause 2846 * 2 - tx pause 2847 * 3 - full 2848 */ 2849 static int 2850 igc_set_flowcntl(SYSCTL_HANDLER_ARGS) 2851 { 2852 int error; 2853 static int input = 3; /* default is full */ 2854 struct igc_adapter *adapter = (struct igc_adapter *) arg1; 2855 2856 error = sysctl_handle_int(oidp, &input, 0, req); 2857 2858 if ((error) || (req->newptr == NULL)) 2859 return (error); 2860 2861 if (input == adapter->fc) /* no change? */ 2862 return (error); 2863 2864 switch (input) { 2865 case igc_fc_rx_pause: 2866 case igc_fc_tx_pause: 2867 case igc_fc_full: 2868 case igc_fc_none: 2869 adapter->hw.fc.requested_mode = input; 2870 adapter->fc = input; 2871 break; 2872 default: 2873 /* Do nothing */ 2874 return (error); 2875 } 2876 2877 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 2878 igc_force_mac_fc(&adapter->hw); 2879 return (error); 2880 } 2881 2882 /* 2883 * Manage Energy Efficient Ethernet: 2884 * Control values: 2885 * 0/1 - enabled/disabled 2886 */ 2887 static int 2888 igc_sysctl_eee(SYSCTL_HANDLER_ARGS) 2889 { 2890 struct igc_adapter *adapter = (struct igc_adapter *) arg1; 2891 int error, value; 2892 2893 value = adapter->hw.dev_spec._i225.eee_disable; 2894 error = sysctl_handle_int(oidp, &value, 0, req); 2895 if (error || req->newptr == NULL) 2896 return (error); 2897 2898 adapter->hw.dev_spec._i225.eee_disable = (value != 0); 2899 igc_if_init(adapter->ctx); 2900 2901 return (0); 2902 } 2903 2904 static int 2905 igc_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 2906 { 2907 struct igc_adapter *adapter; 2908 int error; 2909 int result; 2910 2911 result = -1; 2912 error = sysctl_handle_int(oidp, &result, 0, req); 2913 2914 if (error || !req->newptr) 2915 return (error); 2916 2917 if (result == 1) { 2918 adapter = (struct igc_adapter *) arg1; 2919 igc_print_debug_info(adapter); 2920 } 2921 2922 return (error); 2923 } 2924 2925 static int 2926 igc_get_rs(SYSCTL_HANDLER_ARGS) 2927 { 2928 struct igc_adapter *adapter = (struct igc_adapter *) arg1; 2929 int error; 2930 int result; 2931 2932 result = 0; 2933 error = sysctl_handle_int(oidp, &result, 0, req); 2934 2935 if (error || !req->newptr || result != 1) 2936 return (error); 2937 igc_dump_rs(adapter); 2938 2939 return (error); 2940 } 2941 2942 static void 2943 igc_if_debug(if_ctx_t ctx) 2944 { 2945 igc_dump_rs(iflib_get_softc(ctx)); 2946 } 2947 2948 /* 2949 * This routine is meant to be fluid, add whatever is 2950 * needed for debugging a problem. -jfv 2951 */ 2952 static void 2953 igc_print_debug_info(struct igc_adapter *adapter) 2954 { 2955 device_t dev = iflib_get_dev(adapter->ctx); 2956 struct ifnet *ifp = iflib_get_ifp(adapter->ctx); 2957 struct tx_ring *txr = &adapter->tx_queues->txr; 2958 struct rx_ring *rxr = &adapter->rx_queues->rxr; 2959 2960 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2961 printf("Interface is RUNNING "); 2962 else 2963 printf("Interface is NOT RUNNING\n"); 2964 2965 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 2966 printf("and INACTIVE\n"); 2967 else 2968 printf("and ACTIVE\n"); 2969 2970 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 2971 device_printf(dev, "TX Queue %d ------\n", i); 2972 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 2973 IGC_READ_REG(&adapter->hw, IGC_TDH(i)), 2974 IGC_READ_REG(&adapter->hw, IGC_TDT(i))); 2975 2976 } 2977 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 2978 device_printf(dev, "RX Queue %d ------\n", j); 2979 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 2980 IGC_READ_REG(&adapter->hw, IGC_RDH(j)), 2981 IGC_READ_REG(&adapter->hw, IGC_RDT(j))); 2982 } 2983 } 2984