1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * Copyright (c) 2021 Rubicon Communications, LLC (Netgate) 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 #include "if_igc.h" 32 #include <sys/sbuf.h> 33 #include <machine/_inttypes.h> 34 35 #ifdef RSS 36 #include <net/rss_config.h> 37 #include <netinet/in_rss.h> 38 #endif 39 40 /********************************************************************* 41 * PCI Device ID Table 42 * 43 * Used by probe to select devices to load on 44 * Last entry must be all 0s 45 * 46 * { Vendor ID, Device ID, String } 47 *********************************************************************/ 48 49 static const pci_vendor_info_t igc_vendor_info_array[] = 50 { 51 /* Intel(R) PRO/1000 Network Connection - igc */ 52 PVID(0x8086, IGC_DEV_ID_I225_LM, "Intel(R) Ethernet Controller I225-LM"), 53 PVID(0x8086, IGC_DEV_ID_I225_V, "Intel(R) Ethernet Controller I225-V"), 54 PVID(0x8086, IGC_DEV_ID_I225_K, "Intel(R) Ethernet Controller I225-K"), 55 PVID(0x8086, IGC_DEV_ID_I225_I, "Intel(R) Ethernet Controller I225-I"), 56 PVID(0x8086, IGC_DEV_ID_I220_V, "Intel(R) Ethernet Controller I220-V"), 57 PVID(0x8086, IGC_DEV_ID_I225_K2, "Intel(R) Ethernet Controller I225-K(2)"), 58 PVID(0x8086, IGC_DEV_ID_I225_LMVP, "Intel(R) Ethernet Controller I225-LMvP(2)"), 59 PVID(0x8086, IGC_DEV_ID_I226_K, "Intel(R) Ethernet Controller I226-K"), 60 PVID(0x8086, IGC_DEV_ID_I226_LMVP, "Intel(R) Ethernet Controller I226-LMvP"), 61 PVID(0x8086, IGC_DEV_ID_I225_IT, "Intel(R) Ethernet Controller I225-IT(2)"), 62 PVID(0x8086, IGC_DEV_ID_I226_LM, "Intel(R) Ethernet Controller I226-LM"), 63 PVID(0x8086, IGC_DEV_ID_I226_V, "Intel(R) Ethernet Controller I226-V"), 64 PVID(0x8086, IGC_DEV_ID_I226_IT, "Intel(R) Ethernet Controller I226-IT"), 65 PVID(0x8086, IGC_DEV_ID_I221_V, "Intel(R) Ethernet Controller I221-V"), 66 PVID(0x8086, IGC_DEV_ID_I226_BLANK_NVM, "Intel(R) Ethernet Controller I226(blankNVM)"), 67 PVID(0x8086, IGC_DEV_ID_I225_BLANK_NVM, "Intel(R) Ethernet Controller I225(blankNVM)"), 68 /* required last entry */ 69 PVID_END 70 }; 71 72 /********************************************************************* 73 * Function prototypes 74 *********************************************************************/ 75 static void *igc_register(device_t dev); 76 static int igc_if_attach_pre(if_ctx_t ctx); 77 static int igc_if_attach_post(if_ctx_t ctx); 78 static int igc_if_detach(if_ctx_t ctx); 79 static int igc_if_shutdown(if_ctx_t ctx); 80 static int igc_if_suspend(if_ctx_t ctx); 81 static int igc_if_resume(if_ctx_t ctx); 82 83 static int igc_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets); 84 static int igc_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets); 85 static void igc_if_queues_free(if_ctx_t ctx); 86 87 static uint64_t igc_if_get_counter(if_ctx_t, ift_counter); 88 static void igc_if_init(if_ctx_t ctx); 89 static void igc_if_stop(if_ctx_t ctx); 90 static void igc_if_media_status(if_ctx_t, struct ifmediareq *); 91 static int igc_if_media_change(if_ctx_t ctx); 92 static int igc_if_mtu_set(if_ctx_t ctx, uint32_t mtu); 93 static void igc_if_timer(if_ctx_t ctx, uint16_t qid); 94 static void igc_if_watchdog_reset(if_ctx_t ctx); 95 static bool igc_if_needs_restart(if_ctx_t ctx, enum iflib_restart_event event); 96 97 static void igc_identify_hardware(if_ctx_t ctx); 98 static int igc_allocate_pci_resources(if_ctx_t ctx); 99 static void igc_free_pci_resources(if_ctx_t ctx); 100 static void igc_reset(if_ctx_t ctx); 101 static int igc_setup_interface(if_ctx_t ctx); 102 static int igc_setup_msix(if_ctx_t ctx); 103 104 static void igc_initialize_transmit_unit(if_ctx_t ctx); 105 static void igc_initialize_receive_unit(if_ctx_t ctx); 106 107 static void igc_if_intr_enable(if_ctx_t ctx); 108 static void igc_if_intr_disable(if_ctx_t ctx); 109 static int igc_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid); 110 static int igc_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid); 111 static void igc_if_multi_set(if_ctx_t ctx); 112 static void igc_if_update_admin_status(if_ctx_t ctx); 113 static void igc_if_debug(if_ctx_t ctx); 114 static void igc_update_stats_counters(struct igc_adapter *); 115 static void igc_add_hw_stats(struct igc_adapter *adapter); 116 static int igc_if_set_promisc(if_ctx_t ctx, int flags); 117 static void igc_setup_vlan_hw_support(if_ctx_t ctx); 118 static int igc_sysctl_nvm_info(SYSCTL_HANDLER_ARGS); 119 static void igc_print_nvm_info(struct igc_adapter *); 120 static int igc_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 121 static int igc_get_rs(SYSCTL_HANDLER_ARGS); 122 static void igc_print_debug_info(struct igc_adapter *); 123 static int igc_is_valid_ether_addr(u8 *); 124 static int igc_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 125 static void igc_add_int_delay_sysctl(struct igc_adapter *, const char *, 126 const char *, struct igc_int_delay_info *, int, int); 127 /* Management and WOL Support */ 128 static void igc_get_hw_control(struct igc_adapter *); 129 static void igc_release_hw_control(struct igc_adapter *); 130 static void igc_get_wakeup(if_ctx_t ctx); 131 static void igc_enable_wakeup(if_ctx_t ctx); 132 133 int igc_intr(void *arg); 134 135 /* MSI-X handlers */ 136 static int igc_if_msix_intr_assign(if_ctx_t, int); 137 static int igc_msix_link(void *); 138 static void igc_handle_link(void *context); 139 140 static int igc_set_flowcntl(SYSCTL_HANDLER_ARGS); 141 static int igc_sysctl_eee(SYSCTL_HANDLER_ARGS); 142 143 static int igc_get_regs(SYSCTL_HANDLER_ARGS); 144 145 static void igc_configure_queues(struct igc_adapter *adapter); 146 147 148 /********************************************************************* 149 * FreeBSD Device Interface Entry Points 150 *********************************************************************/ 151 static device_method_t igc_methods[] = { 152 /* Device interface */ 153 DEVMETHOD(device_register, igc_register), 154 DEVMETHOD(device_probe, iflib_device_probe), 155 DEVMETHOD(device_attach, iflib_device_attach), 156 DEVMETHOD(device_detach, iflib_device_detach), 157 DEVMETHOD(device_shutdown, iflib_device_shutdown), 158 DEVMETHOD(device_suspend, iflib_device_suspend), 159 DEVMETHOD(device_resume, iflib_device_resume), 160 DEVMETHOD_END 161 }; 162 163 static driver_t igc_driver = { 164 "igc", igc_methods, sizeof(struct igc_adapter), 165 }; 166 167 DRIVER_MODULE(igc, pci, igc_driver, 0, 0); 168 169 MODULE_DEPEND(igc, pci, 1, 1, 1); 170 MODULE_DEPEND(igc, ether, 1, 1, 1); 171 MODULE_DEPEND(igc, iflib, 1, 1, 1); 172 173 IFLIB_PNP_INFO(pci, igc, igc_vendor_info_array); 174 175 static device_method_t igc_if_methods[] = { 176 DEVMETHOD(ifdi_attach_pre, igc_if_attach_pre), 177 DEVMETHOD(ifdi_attach_post, igc_if_attach_post), 178 DEVMETHOD(ifdi_detach, igc_if_detach), 179 DEVMETHOD(ifdi_shutdown, igc_if_shutdown), 180 DEVMETHOD(ifdi_suspend, igc_if_suspend), 181 DEVMETHOD(ifdi_resume, igc_if_resume), 182 DEVMETHOD(ifdi_init, igc_if_init), 183 DEVMETHOD(ifdi_stop, igc_if_stop), 184 DEVMETHOD(ifdi_msix_intr_assign, igc_if_msix_intr_assign), 185 DEVMETHOD(ifdi_intr_enable, igc_if_intr_enable), 186 DEVMETHOD(ifdi_intr_disable, igc_if_intr_disable), 187 DEVMETHOD(ifdi_tx_queues_alloc, igc_if_tx_queues_alloc), 188 DEVMETHOD(ifdi_rx_queues_alloc, igc_if_rx_queues_alloc), 189 DEVMETHOD(ifdi_queues_free, igc_if_queues_free), 190 DEVMETHOD(ifdi_update_admin_status, igc_if_update_admin_status), 191 DEVMETHOD(ifdi_multi_set, igc_if_multi_set), 192 DEVMETHOD(ifdi_media_status, igc_if_media_status), 193 DEVMETHOD(ifdi_media_change, igc_if_media_change), 194 DEVMETHOD(ifdi_mtu_set, igc_if_mtu_set), 195 DEVMETHOD(ifdi_promisc_set, igc_if_set_promisc), 196 DEVMETHOD(ifdi_timer, igc_if_timer), 197 DEVMETHOD(ifdi_watchdog_reset, igc_if_watchdog_reset), 198 DEVMETHOD(ifdi_get_counter, igc_if_get_counter), 199 DEVMETHOD(ifdi_rx_queue_intr_enable, igc_if_rx_queue_intr_enable), 200 DEVMETHOD(ifdi_tx_queue_intr_enable, igc_if_tx_queue_intr_enable), 201 DEVMETHOD(ifdi_debug, igc_if_debug), 202 DEVMETHOD(ifdi_needs_restart, igc_if_needs_restart), 203 DEVMETHOD_END 204 }; 205 206 static driver_t igc_if_driver = { 207 "igc_if", igc_if_methods, sizeof(struct igc_adapter) 208 }; 209 210 /********************************************************************* 211 * Tunable default values. 212 *********************************************************************/ 213 214 #define IGC_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 215 #define IGC_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 216 217 #define MAX_INTS_PER_SEC 8000 218 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 219 220 /* Allow common code without TSO */ 221 #ifndef CSUM_TSO 222 #define CSUM_TSO 0 223 #endif 224 225 static SYSCTL_NODE(_hw, OID_AUTO, igc, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 226 "igc driver parameters"); 227 228 static int igc_disable_crc_stripping = 0; 229 SYSCTL_INT(_hw_igc, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN, 230 &igc_disable_crc_stripping, 0, "Disable CRC Stripping"); 231 232 static int igc_tx_int_delay_dflt = IGC_TICKS_TO_USECS(IGC_TIDV_VAL); 233 static int igc_rx_int_delay_dflt = IGC_TICKS_TO_USECS(IGC_RDTR_VAL); 234 SYSCTL_INT(_hw_igc, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &igc_tx_int_delay_dflt, 235 0, "Default transmit interrupt delay in usecs"); 236 SYSCTL_INT(_hw_igc, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &igc_rx_int_delay_dflt, 237 0, "Default receive interrupt delay in usecs"); 238 239 static int igc_tx_abs_int_delay_dflt = IGC_TICKS_TO_USECS(IGC_TADV_VAL); 240 static int igc_rx_abs_int_delay_dflt = IGC_TICKS_TO_USECS(IGC_RADV_VAL); 241 SYSCTL_INT(_hw_igc, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN, 242 &igc_tx_abs_int_delay_dflt, 0, 243 "Default transmit interrupt delay limit in usecs"); 244 SYSCTL_INT(_hw_igc, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN, 245 &igc_rx_abs_int_delay_dflt, 0, 246 "Default receive interrupt delay limit in usecs"); 247 248 static int igc_smart_pwr_down = false; 249 SYSCTL_INT(_hw_igc, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &igc_smart_pwr_down, 250 0, "Set to true to leave smart power down enabled on newer adapters"); 251 252 /* Controls whether promiscuous also shows bad packets */ 253 static int igc_debug_sbp = true; 254 SYSCTL_INT(_hw_igc, OID_AUTO, sbp, CTLFLAG_RDTUN, &igc_debug_sbp, 0, 255 "Show bad packets in promiscuous mode"); 256 257 /* How many packets rxeof tries to clean at a time */ 258 static int igc_rx_process_limit = 100; 259 SYSCTL_INT(_hw_igc, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, 260 &igc_rx_process_limit, 0, 261 "Maximum number of received packets to process " 262 "at a time, -1 means unlimited"); 263 264 /* Energy efficient ethernet - default to OFF */ 265 static int igc_eee_setting = 1; 266 SYSCTL_INT(_hw_igc, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &igc_eee_setting, 0, 267 "Enable Energy Efficient Ethernet"); 268 269 /* 270 ** Tuneable Interrupt rate 271 */ 272 static int igc_max_interrupt_rate = 20000; 273 SYSCTL_INT(_hw_igc, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN, 274 &igc_max_interrupt_rate, 0, "Maximum interrupts per second"); 275 276 extern struct if_txrx igc_txrx; 277 278 static struct if_shared_ctx igc_sctx_init = { 279 .isc_magic = IFLIB_MAGIC, 280 .isc_q_align = PAGE_SIZE, 281 .isc_tx_maxsize = IGC_TSO_SIZE + sizeof(struct ether_vlan_header), 282 .isc_tx_maxsegsize = PAGE_SIZE, 283 .isc_tso_maxsize = IGC_TSO_SIZE + sizeof(struct ether_vlan_header), 284 .isc_tso_maxsegsize = IGC_TSO_SEG_SIZE, 285 .isc_rx_maxsize = MAX_JUMBO_FRAME_SIZE, 286 .isc_rx_nsegments = 1, 287 .isc_rx_maxsegsize = MJUM9BYTES, 288 .isc_nfl = 1, 289 .isc_nrxqs = 1, 290 .isc_ntxqs = 1, 291 .isc_admin_intrcnt = 1, 292 .isc_vendor_info = igc_vendor_info_array, 293 .isc_driver_version = "1", 294 .isc_driver = &igc_if_driver, 295 .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM, 296 297 .isc_nrxd_min = {IGC_MIN_RXD}, 298 .isc_ntxd_min = {IGC_MIN_TXD}, 299 .isc_nrxd_max = {IGC_MAX_RXD}, 300 .isc_ntxd_max = {IGC_MAX_TXD}, 301 .isc_nrxd_default = {IGC_DEFAULT_RXD}, 302 .isc_ntxd_default = {IGC_DEFAULT_TXD}, 303 }; 304 305 /***************************************************************** 306 * 307 * Dump Registers 308 * 309 ****************************************************************/ 310 #define IGC_REGS_LEN 739 311 312 static int igc_get_regs(SYSCTL_HANDLER_ARGS) 313 { 314 struct igc_adapter *adapter = (struct igc_adapter *)arg1; 315 struct igc_hw *hw = &adapter->hw; 316 struct sbuf *sb; 317 u32 *regs_buff; 318 int rc; 319 320 regs_buff = malloc(sizeof(u32) * IGC_REGS_LEN, M_DEVBUF, M_WAITOK); 321 memset(regs_buff, 0, IGC_REGS_LEN * sizeof(u32)); 322 323 rc = sysctl_wire_old_buffer(req, 0); 324 MPASS(rc == 0); 325 if (rc != 0) { 326 free(regs_buff, M_DEVBUF); 327 return (rc); 328 } 329 330 sb = sbuf_new_for_sysctl(NULL, NULL, 32*400, req); 331 MPASS(sb != NULL); 332 if (sb == NULL) { 333 free(regs_buff, M_DEVBUF); 334 return (ENOMEM); 335 } 336 337 /* General Registers */ 338 regs_buff[0] = IGC_READ_REG(hw, IGC_CTRL); 339 regs_buff[1] = IGC_READ_REG(hw, IGC_STATUS); 340 regs_buff[2] = IGC_READ_REG(hw, IGC_CTRL_EXT); 341 regs_buff[3] = IGC_READ_REG(hw, IGC_ICR); 342 regs_buff[4] = IGC_READ_REG(hw, IGC_RCTL); 343 regs_buff[5] = IGC_READ_REG(hw, IGC_RDLEN(0)); 344 regs_buff[6] = IGC_READ_REG(hw, IGC_RDH(0)); 345 regs_buff[7] = IGC_READ_REG(hw, IGC_RDT(0)); 346 regs_buff[8] = IGC_READ_REG(hw, IGC_RXDCTL(0)); 347 regs_buff[9] = IGC_READ_REG(hw, IGC_RDBAL(0)); 348 regs_buff[10] = IGC_READ_REG(hw, IGC_RDBAH(0)); 349 regs_buff[11] = IGC_READ_REG(hw, IGC_TCTL); 350 regs_buff[12] = IGC_READ_REG(hw, IGC_TDBAL(0)); 351 regs_buff[13] = IGC_READ_REG(hw, IGC_TDBAH(0)); 352 regs_buff[14] = IGC_READ_REG(hw, IGC_TDLEN(0)); 353 regs_buff[15] = IGC_READ_REG(hw, IGC_TDH(0)); 354 regs_buff[16] = IGC_READ_REG(hw, IGC_TDT(0)); 355 regs_buff[17] = IGC_READ_REG(hw, IGC_TXDCTL(0)); 356 357 sbuf_printf(sb, "General Registers\n"); 358 sbuf_printf(sb, "\tCTRL\t %08x\n", regs_buff[0]); 359 sbuf_printf(sb, "\tSTATUS\t %08x\n", regs_buff[1]); 360 sbuf_printf(sb, "\tCTRL_EXIT\t %08x\n\n", regs_buff[2]); 361 362 sbuf_printf(sb, "Interrupt Registers\n"); 363 sbuf_printf(sb, "\tICR\t %08x\n\n", regs_buff[3]); 364 365 sbuf_printf(sb, "RX Registers\n"); 366 sbuf_printf(sb, "\tRCTL\t %08x\n", regs_buff[4]); 367 sbuf_printf(sb, "\tRDLEN\t %08x\n", regs_buff[5]); 368 sbuf_printf(sb, "\tRDH\t %08x\n", regs_buff[6]); 369 sbuf_printf(sb, "\tRDT\t %08x\n", regs_buff[7]); 370 sbuf_printf(sb, "\tRXDCTL\t %08x\n", regs_buff[8]); 371 sbuf_printf(sb, "\tRDBAL\t %08x\n", regs_buff[9]); 372 sbuf_printf(sb, "\tRDBAH\t %08x\n\n", regs_buff[10]); 373 374 sbuf_printf(sb, "TX Registers\n"); 375 sbuf_printf(sb, "\tTCTL\t %08x\n", regs_buff[11]); 376 sbuf_printf(sb, "\tTDBAL\t %08x\n", regs_buff[12]); 377 sbuf_printf(sb, "\tTDBAH\t %08x\n", regs_buff[13]); 378 sbuf_printf(sb, "\tTDLEN\t %08x\n", regs_buff[14]); 379 sbuf_printf(sb, "\tTDH\t %08x\n", regs_buff[15]); 380 sbuf_printf(sb, "\tTDT\t %08x\n", regs_buff[16]); 381 sbuf_printf(sb, "\tTXDCTL\t %08x\n", regs_buff[17]); 382 sbuf_printf(sb, "\tTDFH\t %08x\n", regs_buff[18]); 383 sbuf_printf(sb, "\tTDFT\t %08x\n", regs_buff[19]); 384 sbuf_printf(sb, "\tTDFHS\t %08x\n", regs_buff[20]); 385 sbuf_printf(sb, "\tTDFPC\t %08x\n\n", regs_buff[21]); 386 387 free(regs_buff, M_DEVBUF); 388 389 #ifdef DUMP_DESCS 390 { 391 if_softc_ctx_t scctx = adapter->shared; 392 struct rx_ring *rxr = &rx_que->rxr; 393 struct tx_ring *txr = &tx_que->txr; 394 int ntxd = scctx->isc_ntxd[0]; 395 int nrxd = scctx->isc_nrxd[0]; 396 int j; 397 398 for (j = 0; j < nrxd; j++) { 399 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error); 400 u32 length = le32toh(rxr->rx_base[j].wb.upper.length); 401 sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length); 402 } 403 404 for (j = 0; j < min(ntxd, 256); j++) { 405 unsigned int *ptr = (unsigned int *)&txr->tx_base[j]; 406 407 sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n", 408 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop, 409 buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & IGC_TXD_STAT_DD : 0); 410 411 } 412 } 413 #endif 414 415 rc = sbuf_finish(sb); 416 sbuf_delete(sb); 417 return(rc); 418 } 419 420 static void * 421 igc_register(device_t dev) 422 { 423 return (&igc_sctx_init); 424 } 425 426 static int 427 igc_set_num_queues(if_ctx_t ctx) 428 { 429 int maxqueues; 430 431 maxqueues = 4; 432 433 return (maxqueues); 434 } 435 436 #define IGC_CAPS \ 437 IFCAP_HWCSUM | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 438 IFCAP_VLAN_HWCSUM | IFCAP_WOL | IFCAP_TSO4 | IFCAP_LRO | \ 439 IFCAP_VLAN_HWTSO | IFCAP_JUMBO_MTU | IFCAP_HWCSUM_IPV6 | IFCAP_TSO6 440 441 /********************************************************************* 442 * Device initialization routine 443 * 444 * The attach entry point is called when the driver is being loaded. 445 * This routine identifies the type of hardware, allocates all resources 446 * and initializes the hardware. 447 * 448 * return 0 on success, positive on failure 449 *********************************************************************/ 450 static int 451 igc_if_attach_pre(if_ctx_t ctx) 452 { 453 struct igc_adapter *adapter; 454 if_softc_ctx_t scctx; 455 device_t dev; 456 struct igc_hw *hw; 457 int error = 0; 458 459 INIT_DEBUGOUT("igc_if_attach_pre: begin"); 460 dev = iflib_get_dev(ctx); 461 adapter = iflib_get_softc(ctx); 462 463 adapter->ctx = adapter->osdep.ctx = ctx; 464 adapter->dev = adapter->osdep.dev = dev; 465 scctx = adapter->shared = iflib_get_softc_ctx(ctx); 466 adapter->media = iflib_get_media(ctx); 467 hw = &adapter->hw; 468 469 adapter->tx_process_limit = scctx->isc_ntxd[0]; 470 471 /* SYSCTL stuff */ 472 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 473 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 474 OID_AUTO, "nvm", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 475 adapter, 0, igc_sysctl_nvm_info, "I", "NVM Information"); 476 477 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 478 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 479 OID_AUTO, "debug", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 480 adapter, 0, igc_sysctl_debug_info, "I", "Debug Information"); 481 482 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 483 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 484 OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 485 adapter, 0, igc_set_flowcntl, "I", "Flow Control"); 486 487 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 488 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 489 OID_AUTO, "reg_dump", 490 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 0, 491 igc_get_regs, "A", "Dump Registers"); 492 493 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 494 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 495 OID_AUTO, "rs_dump", 496 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, adapter, 0, 497 igc_get_rs, "I", "Dump RS indexes"); 498 499 /* Determine hardware and mac info */ 500 igc_identify_hardware(ctx); 501 502 scctx->isc_tx_nsegments = IGC_MAX_SCATTER; 503 scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = igc_set_num_queues(ctx); 504 if (bootverbose) 505 device_printf(dev, "attach_pre capping queues at %d\n", 506 scctx->isc_ntxqsets_max); 507 508 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union igc_adv_tx_desc), IGC_DBA_ALIGN); 509 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union igc_adv_rx_desc), IGC_DBA_ALIGN); 510 scctx->isc_txd_size[0] = sizeof(union igc_adv_tx_desc); 511 scctx->isc_rxd_size[0] = sizeof(union igc_adv_rx_desc); 512 scctx->isc_txrx = &igc_txrx; 513 scctx->isc_tx_tso_segments_max = IGC_MAX_SCATTER; 514 scctx->isc_tx_tso_size_max = IGC_TSO_SIZE; 515 scctx->isc_tx_tso_segsize_max = IGC_TSO_SEG_SIZE; 516 scctx->isc_capabilities = scctx->isc_capenable = IGC_CAPS; 517 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO | 518 CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_SCTP | CSUM_IP6_SCTP; 519 520 /* 521 ** Some new devices, as with ixgbe, now may 522 ** use a different BAR, so we need to keep 523 ** track of which is used. 524 */ 525 scctx->isc_msix_bar = PCIR_BAR(IGC_MSIX_BAR); 526 if (pci_read_config(dev, scctx->isc_msix_bar, 4) == 0) 527 scctx->isc_msix_bar += 4; 528 529 /* Setup PCI resources */ 530 if (igc_allocate_pci_resources(ctx)) { 531 device_printf(dev, "Allocation of PCI resources failed\n"); 532 error = ENXIO; 533 goto err_pci; 534 } 535 536 /* Do Shared Code initialization */ 537 error = igc_setup_init_funcs(hw, true); 538 if (error) { 539 device_printf(dev, "Setup of Shared code failed, error %d\n", 540 error); 541 error = ENXIO; 542 goto err_pci; 543 } 544 545 igc_setup_msix(ctx); 546 igc_get_bus_info(hw); 547 548 /* Set up some sysctls for the tunable interrupt delays */ 549 igc_add_int_delay_sysctl(adapter, "rx_int_delay", 550 "receive interrupt delay in usecs", &adapter->rx_int_delay, 551 IGC_REGISTER(hw, IGC_RDTR), igc_rx_int_delay_dflt); 552 igc_add_int_delay_sysctl(adapter, "tx_int_delay", 553 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 554 IGC_REGISTER(hw, IGC_TIDV), igc_tx_int_delay_dflt); 555 igc_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 556 "receive interrupt delay limit in usecs", 557 &adapter->rx_abs_int_delay, 558 IGC_REGISTER(hw, IGC_RADV), 559 igc_rx_abs_int_delay_dflt); 560 igc_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 561 "transmit interrupt delay limit in usecs", 562 &adapter->tx_abs_int_delay, 563 IGC_REGISTER(hw, IGC_TADV), 564 igc_tx_abs_int_delay_dflt); 565 igc_add_int_delay_sysctl(adapter, "itr", 566 "interrupt delay limit in usecs/4", 567 &adapter->tx_itr, 568 IGC_REGISTER(hw, IGC_ITR), 569 DEFAULT_ITR); 570 571 hw->mac.autoneg = DO_AUTO_NEG; 572 hw->phy.autoneg_wait_to_complete = false; 573 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 574 575 /* Copper options */ 576 if (hw->phy.media_type == igc_media_type_copper) { 577 hw->phy.mdix = AUTO_ALL_MODES; 578 } 579 580 /* 581 * Set the frame limits assuming 582 * standard ethernet sized frames. 583 */ 584 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 585 ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 586 587 /* Allocate multicast array memory. */ 588 adapter->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN * 589 MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT); 590 if (adapter->mta == NULL) { 591 device_printf(dev, "Can not allocate multicast setup array\n"); 592 error = ENOMEM; 593 goto err_late; 594 } 595 596 /* Check SOL/IDER usage */ 597 if (igc_check_reset_block(hw)) 598 device_printf(dev, "PHY reset is blocked" 599 " due to SOL/IDER session.\n"); 600 601 /* Sysctl for setting Energy Efficient Ethernet */ 602 adapter->hw.dev_spec._i225.eee_disable = igc_eee_setting; 603 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 604 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 605 OID_AUTO, "eee_control", 606 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 607 adapter, 0, igc_sysctl_eee, "I", 608 "Disable Energy Efficient Ethernet"); 609 610 /* 611 ** Start from a known state, this is 612 ** important in reading the nvm and 613 ** mac from that. 614 */ 615 igc_reset_hw(hw); 616 617 /* Make sure we have a good EEPROM before we read from it */ 618 if (igc_validate_nvm_checksum(hw) < 0) { 619 /* 620 ** Some PCI-E parts fail the first check due to 621 ** the link being in sleep state, call it again, 622 ** if it fails a second time its a real issue. 623 */ 624 if (igc_validate_nvm_checksum(hw) < 0) { 625 device_printf(dev, 626 "The EEPROM Checksum Is Not Valid\n"); 627 error = EIO; 628 goto err_late; 629 } 630 } 631 632 /* Copy the permanent MAC address out of the EEPROM */ 633 if (igc_read_mac_addr(hw) < 0) { 634 device_printf(dev, "EEPROM read error while reading MAC" 635 " address\n"); 636 error = EIO; 637 goto err_late; 638 } 639 640 if (!igc_is_valid_ether_addr(hw->mac.addr)) { 641 device_printf(dev, "Invalid MAC address\n"); 642 error = EIO; 643 goto err_late; 644 } 645 646 /* 647 * Get Wake-on-Lan and Management info for later use 648 */ 649 igc_get_wakeup(ctx); 650 651 /* Enable only WOL MAGIC by default */ 652 scctx->isc_capenable &= ~IFCAP_WOL; 653 if (adapter->wol != 0) 654 scctx->isc_capenable |= IFCAP_WOL_MAGIC; 655 656 iflib_set_mac(ctx, hw->mac.addr); 657 658 return (0); 659 660 err_late: 661 igc_release_hw_control(adapter); 662 err_pci: 663 igc_free_pci_resources(ctx); 664 free(adapter->mta, M_DEVBUF); 665 666 return (error); 667 } 668 669 static int 670 igc_if_attach_post(if_ctx_t ctx) 671 { 672 struct igc_adapter *adapter = iflib_get_softc(ctx); 673 struct igc_hw *hw = &adapter->hw; 674 int error = 0; 675 676 /* Setup OS specific network interface */ 677 error = igc_setup_interface(ctx); 678 if (error != 0) { 679 goto err_late; 680 } 681 682 igc_reset(ctx); 683 684 /* Initialize statistics */ 685 igc_update_stats_counters(adapter); 686 hw->mac.get_link_status = true; 687 igc_if_update_admin_status(ctx); 688 igc_add_hw_stats(adapter); 689 690 /* the driver can now take control from firmware */ 691 igc_get_hw_control(adapter); 692 693 INIT_DEBUGOUT("igc_if_attach_post: end"); 694 695 return (error); 696 697 err_late: 698 igc_release_hw_control(adapter); 699 igc_free_pci_resources(ctx); 700 igc_if_queues_free(ctx); 701 free(adapter->mta, M_DEVBUF); 702 703 return (error); 704 } 705 706 /********************************************************************* 707 * Device removal routine 708 * 709 * The detach entry point is called when the driver is being removed. 710 * This routine stops the adapter and deallocates all the resources 711 * that were allocated for driver operation. 712 * 713 * return 0 on success, positive on failure 714 *********************************************************************/ 715 static int 716 igc_if_detach(if_ctx_t ctx) 717 { 718 struct igc_adapter *adapter = iflib_get_softc(ctx); 719 720 INIT_DEBUGOUT("igc_if_detach: begin"); 721 722 igc_phy_hw_reset(&adapter->hw); 723 724 igc_release_hw_control(adapter); 725 igc_free_pci_resources(ctx); 726 727 return (0); 728 } 729 730 /********************************************************************* 731 * 732 * Shutdown entry point 733 * 734 **********************************************************************/ 735 736 static int 737 igc_if_shutdown(if_ctx_t ctx) 738 { 739 return igc_if_suspend(ctx); 740 } 741 742 /* 743 * Suspend/resume device methods. 744 */ 745 static int 746 igc_if_suspend(if_ctx_t ctx) 747 { 748 struct igc_adapter *adapter = iflib_get_softc(ctx); 749 750 igc_release_hw_control(adapter); 751 igc_enable_wakeup(ctx); 752 return (0); 753 } 754 755 static int 756 igc_if_resume(if_ctx_t ctx) 757 { 758 igc_if_init(ctx); 759 760 return(0); 761 } 762 763 static int 764 igc_if_mtu_set(if_ctx_t ctx, uint32_t mtu) 765 { 766 int max_frame_size; 767 struct igc_adapter *adapter = iflib_get_softc(ctx); 768 if_softc_ctx_t scctx = iflib_get_softc_ctx(ctx); 769 770 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 771 772 /* 9K Jumbo Frame size */ 773 max_frame_size = 9234; 774 775 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) { 776 return (EINVAL); 777 } 778 779 scctx->isc_max_frame_size = adapter->hw.mac.max_frame_size = 780 mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 781 return (0); 782 } 783 784 /********************************************************************* 785 * Init entry point 786 * 787 * This routine is used in two ways. It is used by the stack as 788 * init entry point in network interface structure. It is also used 789 * by the driver as a hw/sw initialization routine to get to a 790 * consistent state. 791 * 792 **********************************************************************/ 793 static void 794 igc_if_init(if_ctx_t ctx) 795 { 796 struct igc_adapter *adapter = iflib_get_softc(ctx); 797 if_softc_ctx_t scctx = adapter->shared; 798 if_t ifp = iflib_get_ifp(ctx); 799 struct igc_tx_queue *tx_que; 800 int i; 801 802 INIT_DEBUGOUT("igc_if_init: begin"); 803 804 /* Get the latest mac address, User can use a LAA */ 805 bcopy(if_getlladdr(ifp), adapter->hw.mac.addr, 806 ETHER_ADDR_LEN); 807 808 /* Put the address into the Receive Address Array */ 809 igc_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 810 811 /* Initialize the hardware */ 812 igc_reset(ctx); 813 igc_if_update_admin_status(ctx); 814 815 for (i = 0, tx_que = adapter->tx_queues; i < adapter->tx_num_queues; i++, tx_que++) { 816 struct tx_ring *txr = &tx_que->txr; 817 818 txr->tx_rs_cidx = txr->tx_rs_pidx; 819 820 /* Initialize the last processed descriptor to be the end of 821 * the ring, rather than the start, so that we avoid an 822 * off-by-one error when calculating how many descriptors are 823 * done in the credits_update function. 824 */ 825 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1; 826 } 827 828 /* Setup VLAN support, basic and offload if available */ 829 IGC_WRITE_REG(&adapter->hw, IGC_VET, ETHERTYPE_VLAN); 830 831 /* Prepare transmit descriptors and buffers */ 832 igc_initialize_transmit_unit(ctx); 833 834 /* Setup Multicast table */ 835 igc_if_multi_set(ctx); 836 837 adapter->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx); 838 igc_initialize_receive_unit(ctx); 839 840 /* Set up VLAN support */ 841 igc_setup_vlan_hw_support(ctx); 842 843 /* Don't lose promiscuous settings */ 844 igc_if_set_promisc(ctx, if_getflags(ifp)); 845 igc_clear_hw_cntrs_base_generic(&adapter->hw); 846 847 if (adapter->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */ 848 igc_configure_queues(adapter); 849 850 /* this clears any pending interrupts */ 851 IGC_READ_REG(&adapter->hw, IGC_ICR); 852 IGC_WRITE_REG(&adapter->hw, IGC_ICS, IGC_ICS_LSC); 853 854 /* the driver can now take control from firmware */ 855 igc_get_hw_control(adapter); 856 857 /* Set Energy Efficient Ethernet */ 858 igc_set_eee_i225(&adapter->hw, true, true, true); 859 } 860 861 /********************************************************************* 862 * 863 * Fast Legacy/MSI Combined Interrupt Service routine 864 * 865 *********************************************************************/ 866 int 867 igc_intr(void *arg) 868 { 869 struct igc_adapter *adapter = arg; 870 if_ctx_t ctx = adapter->ctx; 871 u32 reg_icr; 872 873 reg_icr = IGC_READ_REG(&adapter->hw, IGC_ICR); 874 875 /* Hot eject? */ 876 if (reg_icr == 0xffffffff) 877 return FILTER_STRAY; 878 879 /* Definitely not our interrupt. */ 880 if (reg_icr == 0x0) 881 return FILTER_STRAY; 882 883 if ((reg_icr & IGC_ICR_INT_ASSERTED) == 0) 884 return FILTER_STRAY; 885 886 /* 887 * Only MSI-X interrupts have one-shot behavior by taking advantage 888 * of the EIAC register. Thus, explicitly disable interrupts. This 889 * also works around the MSI message reordering errata on certain 890 * systems. 891 */ 892 IFDI_INTR_DISABLE(ctx); 893 894 /* Link status change */ 895 if (reg_icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) 896 igc_handle_link(ctx); 897 898 if (reg_icr & IGC_ICR_RXO) 899 adapter->rx_overruns++; 900 901 return (FILTER_SCHEDULE_THREAD); 902 } 903 904 static int 905 igc_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t rxqid) 906 { 907 struct igc_adapter *adapter = iflib_get_softc(ctx); 908 struct igc_rx_queue *rxq = &adapter->rx_queues[rxqid]; 909 910 IGC_WRITE_REG(&adapter->hw, IGC_EIMS, rxq->eims); 911 return (0); 912 } 913 914 static int 915 igc_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t txqid) 916 { 917 struct igc_adapter *adapter = iflib_get_softc(ctx); 918 struct igc_tx_queue *txq = &adapter->tx_queues[txqid]; 919 920 IGC_WRITE_REG(&adapter->hw, IGC_EIMS, txq->eims); 921 return (0); 922 } 923 924 /********************************************************************* 925 * 926 * MSI-X RX Interrupt Service routine 927 * 928 **********************************************************************/ 929 static int 930 igc_msix_que(void *arg) 931 { 932 struct igc_rx_queue *que = arg; 933 934 ++que->irqs; 935 936 return (FILTER_SCHEDULE_THREAD); 937 } 938 939 /********************************************************************* 940 * 941 * MSI-X Link Fast Interrupt Service routine 942 * 943 **********************************************************************/ 944 static int 945 igc_msix_link(void *arg) 946 { 947 struct igc_adapter *adapter = arg; 948 u32 reg_icr; 949 950 ++adapter->link_irq; 951 MPASS(adapter->hw.back != NULL); 952 reg_icr = IGC_READ_REG(&adapter->hw, IGC_ICR); 953 954 if (reg_icr & IGC_ICR_RXO) 955 adapter->rx_overruns++; 956 957 if (reg_icr & (IGC_ICR_RXSEQ | IGC_ICR_LSC)) { 958 igc_handle_link(adapter->ctx); 959 } 960 961 IGC_WRITE_REG(&adapter->hw, IGC_IMS, IGC_IMS_LSC); 962 IGC_WRITE_REG(&adapter->hw, IGC_EIMS, adapter->link_mask); 963 964 return (FILTER_HANDLED); 965 } 966 967 static void 968 igc_handle_link(void *context) 969 { 970 if_ctx_t ctx = context; 971 struct igc_adapter *adapter = iflib_get_softc(ctx); 972 973 adapter->hw.mac.get_link_status = true; 974 iflib_admin_intr_deferred(ctx); 975 } 976 977 /********************************************************************* 978 * 979 * Media Ioctl callback 980 * 981 * This routine is called whenever the user queries the status of 982 * the interface using ifconfig. 983 * 984 **********************************************************************/ 985 static void 986 igc_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr) 987 { 988 struct igc_adapter *adapter = iflib_get_softc(ctx); 989 990 INIT_DEBUGOUT("igc_if_media_status: begin"); 991 992 iflib_admin_intr_deferred(ctx); 993 994 ifmr->ifm_status = IFM_AVALID; 995 ifmr->ifm_active = IFM_ETHER; 996 997 if (!adapter->link_active) { 998 return; 999 } 1000 1001 ifmr->ifm_status |= IFM_ACTIVE; 1002 1003 switch (adapter->link_speed) { 1004 case 10: 1005 ifmr->ifm_active |= IFM_10_T; 1006 break; 1007 case 100: 1008 ifmr->ifm_active |= IFM_100_TX; 1009 break; 1010 case 1000: 1011 ifmr->ifm_active |= IFM_1000_T; 1012 break; 1013 case 2500: 1014 ifmr->ifm_active |= IFM_2500_T; 1015 break; 1016 } 1017 1018 if (adapter->link_duplex == FULL_DUPLEX) 1019 ifmr->ifm_active |= IFM_FDX; 1020 else 1021 ifmr->ifm_active |= IFM_HDX; 1022 } 1023 1024 /********************************************************************* 1025 * 1026 * Media Ioctl callback 1027 * 1028 * This routine is called when the user changes speed/duplex using 1029 * media/mediopt option with ifconfig. 1030 * 1031 **********************************************************************/ 1032 static int 1033 igc_if_media_change(if_ctx_t ctx) 1034 { 1035 struct igc_adapter *adapter = iflib_get_softc(ctx); 1036 struct ifmedia *ifm = iflib_get_media(ctx); 1037 1038 INIT_DEBUGOUT("igc_if_media_change: begin"); 1039 1040 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1041 return (EINVAL); 1042 1043 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1044 1045 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1046 case IFM_AUTO: 1047 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1048 break; 1049 case IFM_2500_T: 1050 adapter->hw.phy.autoneg_advertised = ADVERTISE_2500_FULL; 1051 break; 1052 case IFM_1000_T: 1053 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1054 break; 1055 case IFM_100_TX: 1056 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1057 adapter->hw.phy.autoneg_advertised = ADVERTISE_100_FULL; 1058 else 1059 adapter->hw.phy.autoneg_advertised = ADVERTISE_100_HALF; 1060 break; 1061 case IFM_10_T: 1062 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1063 adapter->hw.phy.autoneg_advertised = ADVERTISE_10_FULL; 1064 else 1065 adapter->hw.phy.autoneg_advertised = ADVERTISE_10_HALF; 1066 break; 1067 default: 1068 device_printf(adapter->dev, "Unsupported media type\n"); 1069 } 1070 1071 igc_if_init(ctx); 1072 1073 return (0); 1074 } 1075 1076 static int 1077 igc_if_set_promisc(if_ctx_t ctx, int flags) 1078 { 1079 struct igc_adapter *adapter = iflib_get_softc(ctx); 1080 if_t ifp = iflib_get_ifp(ctx); 1081 u32 reg_rctl; 1082 int mcnt = 0; 1083 1084 reg_rctl = IGC_READ_REG(&adapter->hw, IGC_RCTL); 1085 reg_rctl &= ~(IGC_RCTL_SBP | IGC_RCTL_UPE); 1086 if (flags & IFF_ALLMULTI) 1087 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 1088 else 1089 mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES); 1090 1091 /* Don't disable if in MAX groups */ 1092 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1093 reg_rctl &= (~IGC_RCTL_MPE); 1094 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, reg_rctl); 1095 1096 if (flags & IFF_PROMISC) { 1097 reg_rctl |= (IGC_RCTL_UPE | IGC_RCTL_MPE); 1098 /* Turn this on if you want to see bad packets */ 1099 if (igc_debug_sbp) 1100 reg_rctl |= IGC_RCTL_SBP; 1101 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, reg_rctl); 1102 } else if (flags & IFF_ALLMULTI) { 1103 reg_rctl |= IGC_RCTL_MPE; 1104 reg_rctl &= ~IGC_RCTL_UPE; 1105 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, reg_rctl); 1106 } 1107 return (0); 1108 } 1109 1110 static u_int 1111 igc_copy_maddr(void *arg, struct sockaddr_dl *sdl, u_int idx) 1112 { 1113 u8 *mta = arg; 1114 1115 if (idx == MAX_NUM_MULTICAST_ADDRESSES) 1116 return (0); 1117 1118 bcopy(LLADDR(sdl), &mta[idx * ETHER_ADDR_LEN], ETHER_ADDR_LEN); 1119 1120 return (1); 1121 } 1122 1123 /********************************************************************* 1124 * Multicast Update 1125 * 1126 * This routine is called whenever multicast address list is updated. 1127 * 1128 **********************************************************************/ 1129 1130 static void 1131 igc_if_multi_set(if_ctx_t ctx) 1132 { 1133 struct igc_adapter *adapter = iflib_get_softc(ctx); 1134 if_t ifp = iflib_get_ifp(ctx); 1135 u8 *mta; /* Multicast array memory */ 1136 u32 reg_rctl = 0; 1137 int mcnt = 0; 1138 1139 IOCTL_DEBUGOUT("igc_set_multi: begin"); 1140 1141 mta = adapter->mta; 1142 bzero(mta, sizeof(u8) * ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES); 1143 1144 mcnt = if_foreach_llmaddr(ifp, igc_copy_maddr, mta); 1145 1146 reg_rctl = IGC_READ_REG(&adapter->hw, IGC_RCTL); 1147 1148 if (if_getflags(ifp) & IFF_PROMISC) { 1149 reg_rctl |= (IGC_RCTL_UPE | IGC_RCTL_MPE); 1150 /* Turn this on if you want to see bad packets */ 1151 if (igc_debug_sbp) 1152 reg_rctl |= IGC_RCTL_SBP; 1153 } else if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES || 1154 if_getflags(ifp) & IFF_ALLMULTI) { 1155 reg_rctl |= IGC_RCTL_MPE; 1156 reg_rctl &= ~IGC_RCTL_UPE; 1157 } else 1158 reg_rctl &= ~(IGC_RCTL_UPE | IGC_RCTL_MPE); 1159 1160 if (mcnt < MAX_NUM_MULTICAST_ADDRESSES) 1161 igc_update_mc_addr_list(&adapter->hw, mta, mcnt); 1162 1163 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, reg_rctl); 1164 } 1165 1166 /********************************************************************* 1167 * Timer routine 1168 * 1169 * This routine schedules igc_if_update_admin_status() to check for 1170 * link status and to gather statistics as well as to perform some 1171 * controller-specific hardware patting. 1172 * 1173 **********************************************************************/ 1174 static void 1175 igc_if_timer(if_ctx_t ctx, uint16_t qid) 1176 { 1177 1178 if (qid != 0) 1179 return; 1180 1181 iflib_admin_intr_deferred(ctx); 1182 } 1183 1184 static void 1185 igc_if_update_admin_status(if_ctx_t ctx) 1186 { 1187 struct igc_adapter *adapter = iflib_get_softc(ctx); 1188 struct igc_hw *hw = &adapter->hw; 1189 device_t dev = iflib_get_dev(ctx); 1190 u32 link_check, thstat, ctrl; 1191 1192 link_check = thstat = ctrl = 0; 1193 /* Get the cached link value or read phy for real */ 1194 switch (hw->phy.media_type) { 1195 case igc_media_type_copper: 1196 if (hw->mac.get_link_status == true) { 1197 /* Do the work to read phy */ 1198 igc_check_for_link(hw); 1199 link_check = !hw->mac.get_link_status; 1200 } else 1201 link_check = true; 1202 break; 1203 case igc_media_type_unknown: 1204 igc_check_for_link(hw); 1205 link_check = !hw->mac.get_link_status; 1206 /* FALLTHROUGH */ 1207 default: 1208 break; 1209 } 1210 1211 /* Now check for a transition */ 1212 if (link_check && (adapter->link_active == 0)) { 1213 igc_get_speed_and_duplex(hw, &adapter->link_speed, 1214 &adapter->link_duplex); 1215 if (bootverbose) 1216 device_printf(dev, "Link is up %d Mbps %s\n", 1217 adapter->link_speed, 1218 ((adapter->link_duplex == FULL_DUPLEX) ? 1219 "Full Duplex" : "Half Duplex")); 1220 adapter->link_active = 1; 1221 iflib_link_state_change(ctx, LINK_STATE_UP, 1222 IF_Mbps(adapter->link_speed)); 1223 } else if (!link_check && (adapter->link_active == 1)) { 1224 adapter->link_speed = 0; 1225 adapter->link_duplex = 0; 1226 adapter->link_active = 0; 1227 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0); 1228 } 1229 igc_update_stats_counters(adapter); 1230 } 1231 1232 static void 1233 igc_if_watchdog_reset(if_ctx_t ctx) 1234 { 1235 struct igc_adapter *adapter = iflib_get_softc(ctx); 1236 1237 /* 1238 * Just count the event; iflib(4) will already trigger a 1239 * sufficient reset of the controller. 1240 */ 1241 adapter->watchdog_events++; 1242 } 1243 1244 /********************************************************************* 1245 * 1246 * This routine disables all traffic on the adapter by issuing a 1247 * global reset on the MAC. 1248 * 1249 **********************************************************************/ 1250 static void 1251 igc_if_stop(if_ctx_t ctx) 1252 { 1253 struct igc_adapter *adapter = iflib_get_softc(ctx); 1254 1255 INIT_DEBUGOUT("igc_if_stop: begin"); 1256 1257 igc_reset_hw(&adapter->hw); 1258 IGC_WRITE_REG(&adapter->hw, IGC_WUC, 0); 1259 } 1260 1261 /********************************************************************* 1262 * 1263 * Determine hardware revision. 1264 * 1265 **********************************************************************/ 1266 static void 1267 igc_identify_hardware(if_ctx_t ctx) 1268 { 1269 device_t dev = iflib_get_dev(ctx); 1270 struct igc_adapter *adapter = iflib_get_softc(ctx); 1271 1272 /* Make sure our PCI config space has the necessary stuff set */ 1273 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 1274 1275 /* Save off the information about this board */ 1276 adapter->hw.vendor_id = pci_get_vendor(dev); 1277 adapter->hw.device_id = pci_get_device(dev); 1278 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 1279 adapter->hw.subsystem_vendor_id = 1280 pci_read_config(dev, PCIR_SUBVEND_0, 2); 1281 adapter->hw.subsystem_device_id = 1282 pci_read_config(dev, PCIR_SUBDEV_0, 2); 1283 1284 /* Do Shared Code Init and Setup */ 1285 if (igc_set_mac_type(&adapter->hw)) { 1286 device_printf(dev, "Setup init failure\n"); 1287 return; 1288 } 1289 } 1290 1291 static int 1292 igc_allocate_pci_resources(if_ctx_t ctx) 1293 { 1294 struct igc_adapter *adapter = iflib_get_softc(ctx); 1295 device_t dev = iflib_get_dev(ctx); 1296 int rid; 1297 1298 rid = PCIR_BAR(0); 1299 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1300 &rid, RF_ACTIVE); 1301 if (adapter->memory == NULL) { 1302 device_printf(dev, "Unable to allocate bus resource: memory\n"); 1303 return (ENXIO); 1304 } 1305 adapter->osdep.mem_bus_space_tag = rman_get_bustag(adapter->memory); 1306 adapter->osdep.mem_bus_space_handle = 1307 rman_get_bushandle(adapter->memory); 1308 adapter->hw.hw_addr = (u8 *)&adapter->osdep.mem_bus_space_handle; 1309 1310 adapter->hw.back = &adapter->osdep; 1311 1312 return (0); 1313 } 1314 1315 /********************************************************************* 1316 * 1317 * Set up the MSI-X Interrupt handlers 1318 * 1319 **********************************************************************/ 1320 static int 1321 igc_if_msix_intr_assign(if_ctx_t ctx, int msix) 1322 { 1323 struct igc_adapter *adapter = iflib_get_softc(ctx); 1324 struct igc_rx_queue *rx_que = adapter->rx_queues; 1325 struct igc_tx_queue *tx_que = adapter->tx_queues; 1326 int error, rid, i, vector = 0, rx_vectors; 1327 char buf[16]; 1328 1329 /* First set up ring resources */ 1330 for (i = 0; i < adapter->rx_num_queues; i++, rx_que++, vector++) { 1331 rid = vector + 1; 1332 snprintf(buf, sizeof(buf), "rxq%d", i); 1333 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, igc_msix_que, rx_que, rx_que->me, buf); 1334 if (error) { 1335 device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error); 1336 adapter->rx_num_queues = i + 1; 1337 goto fail; 1338 } 1339 1340 rx_que->msix = vector; 1341 1342 /* 1343 * Set the bit to enable interrupt 1344 * in IGC_IMS -- bits 20 and 21 1345 * are for RX0 and RX1, note this has 1346 * NOTHING to do with the MSI-X vector 1347 */ 1348 rx_que->eims = 1 << vector; 1349 } 1350 rx_vectors = vector; 1351 1352 vector = 0; 1353 for (i = 0; i < adapter->tx_num_queues; i++, tx_que++, vector++) { 1354 snprintf(buf, sizeof(buf), "txq%d", i); 1355 tx_que = &adapter->tx_queues[i]; 1356 iflib_softirq_alloc_generic(ctx, 1357 &adapter->rx_queues[i % adapter->rx_num_queues].que_irq, 1358 IFLIB_INTR_TX, tx_que, tx_que->me, buf); 1359 1360 tx_que->msix = (vector % adapter->rx_num_queues); 1361 1362 /* 1363 * Set the bit to enable interrupt 1364 * in IGC_IMS -- bits 22 and 23 1365 * are for TX0 and TX1, note this has 1366 * NOTHING to do with the MSI-X vector 1367 */ 1368 tx_que->eims = 1 << i; 1369 } 1370 1371 /* Link interrupt */ 1372 rid = rx_vectors + 1; 1373 error = iflib_irq_alloc_generic(ctx, &adapter->irq, rid, IFLIB_INTR_ADMIN, igc_msix_link, adapter, 0, "aq"); 1374 1375 if (error) { 1376 device_printf(iflib_get_dev(ctx), "Failed to register admin handler"); 1377 goto fail; 1378 } 1379 adapter->linkvec = rx_vectors; 1380 return (0); 1381 fail: 1382 iflib_irq_free(ctx, &adapter->irq); 1383 rx_que = adapter->rx_queues; 1384 for (int i = 0; i < adapter->rx_num_queues; i++, rx_que++) 1385 iflib_irq_free(ctx, &rx_que->que_irq); 1386 return (error); 1387 } 1388 1389 static void 1390 igc_configure_queues(struct igc_adapter *adapter) 1391 { 1392 struct igc_hw *hw = &adapter->hw; 1393 struct igc_rx_queue *rx_que; 1394 struct igc_tx_queue *tx_que; 1395 u32 ivar = 0, newitr = 0; 1396 1397 /* First turn on RSS capability */ 1398 IGC_WRITE_REG(hw, IGC_GPIE, 1399 IGC_GPIE_MSIX_MODE | IGC_GPIE_EIAME | IGC_GPIE_PBA | 1400 IGC_GPIE_NSICR); 1401 1402 /* Turn on MSI-X */ 1403 /* RX entries */ 1404 for (int i = 0; i < adapter->rx_num_queues; i++) { 1405 u32 index = i >> 1; 1406 ivar = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, index); 1407 rx_que = &adapter->rx_queues[i]; 1408 if (i & 1) { 1409 ivar &= 0xFF00FFFF; 1410 ivar |= (rx_que->msix | IGC_IVAR_VALID) << 16; 1411 } else { 1412 ivar &= 0xFFFFFF00; 1413 ivar |= rx_que->msix | IGC_IVAR_VALID; 1414 } 1415 IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, index, ivar); 1416 } 1417 /* TX entries */ 1418 for (int i = 0; i < adapter->tx_num_queues; i++) { 1419 u32 index = i >> 1; 1420 ivar = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, index); 1421 tx_que = &adapter->tx_queues[i]; 1422 if (i & 1) { 1423 ivar &= 0x00FFFFFF; 1424 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 24; 1425 } else { 1426 ivar &= 0xFFFF00FF; 1427 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 8; 1428 } 1429 IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, index, ivar); 1430 adapter->que_mask |= tx_que->eims; 1431 } 1432 1433 /* And for the link interrupt */ 1434 ivar = (adapter->linkvec | IGC_IVAR_VALID) << 8; 1435 adapter->link_mask = 1 << adapter->linkvec; 1436 IGC_WRITE_REG(hw, IGC_IVAR_MISC, ivar); 1437 1438 /* Set the starting interrupt rate */ 1439 if (igc_max_interrupt_rate > 0) 1440 newitr = (4000000 / igc_max_interrupt_rate) & 0x7FFC; 1441 1442 newitr |= IGC_EITR_CNT_IGNR; 1443 1444 for (int i = 0; i < adapter->rx_num_queues; i++) { 1445 rx_que = &adapter->rx_queues[i]; 1446 IGC_WRITE_REG(hw, IGC_EITR(rx_que->msix), newitr); 1447 } 1448 1449 return; 1450 } 1451 1452 static void 1453 igc_free_pci_resources(if_ctx_t ctx) 1454 { 1455 struct igc_adapter *adapter = iflib_get_softc(ctx); 1456 struct igc_rx_queue *que = adapter->rx_queues; 1457 device_t dev = iflib_get_dev(ctx); 1458 1459 /* Release all MSI-X queue resources */ 1460 if (adapter->intr_type == IFLIB_INTR_MSIX) 1461 iflib_irq_free(ctx, &adapter->irq); 1462 1463 for (int i = 0; i < adapter->rx_num_queues; i++, que++) { 1464 iflib_irq_free(ctx, &que->que_irq); 1465 } 1466 1467 if (adapter->memory != NULL) { 1468 bus_release_resource(dev, SYS_RES_MEMORY, 1469 rman_get_rid(adapter->memory), adapter->memory); 1470 adapter->memory = NULL; 1471 } 1472 1473 if (adapter->flash != NULL) { 1474 bus_release_resource(dev, SYS_RES_MEMORY, 1475 rman_get_rid(adapter->flash), adapter->flash); 1476 adapter->flash = NULL; 1477 } 1478 1479 if (adapter->ioport != NULL) { 1480 bus_release_resource(dev, SYS_RES_IOPORT, 1481 rman_get_rid(adapter->ioport), adapter->ioport); 1482 adapter->ioport = NULL; 1483 } 1484 } 1485 1486 /* Set up MSI or MSI-X */ 1487 static int 1488 igc_setup_msix(if_ctx_t ctx) 1489 { 1490 return (0); 1491 } 1492 1493 /********************************************************************* 1494 * 1495 * Initialize the DMA Coalescing feature 1496 * 1497 **********************************************************************/ 1498 static void 1499 igc_init_dmac(struct igc_adapter *adapter, u32 pba) 1500 { 1501 device_t dev = adapter->dev; 1502 struct igc_hw *hw = &adapter->hw; 1503 u32 dmac, reg = ~IGC_DMACR_DMAC_EN; 1504 u16 hwm; 1505 u16 max_frame_size; 1506 int status; 1507 1508 max_frame_size = adapter->shared->isc_max_frame_size; 1509 1510 if (adapter->dmac == 0) { /* Disabling it */ 1511 IGC_WRITE_REG(hw, IGC_DMACR, reg); 1512 return; 1513 } else 1514 device_printf(dev, "DMA Coalescing enabled\n"); 1515 1516 /* Set starting threshold */ 1517 IGC_WRITE_REG(hw, IGC_DMCTXTH, 0); 1518 1519 hwm = 64 * pba - max_frame_size / 16; 1520 if (hwm < 64 * (pba - 6)) 1521 hwm = 64 * (pba - 6); 1522 reg = IGC_READ_REG(hw, IGC_FCRTC); 1523 reg &= ~IGC_FCRTC_RTH_COAL_MASK; 1524 reg |= ((hwm << IGC_FCRTC_RTH_COAL_SHIFT) 1525 & IGC_FCRTC_RTH_COAL_MASK); 1526 IGC_WRITE_REG(hw, IGC_FCRTC, reg); 1527 1528 dmac = pba - max_frame_size / 512; 1529 if (dmac < pba - 10) 1530 dmac = pba - 10; 1531 reg = IGC_READ_REG(hw, IGC_DMACR); 1532 reg &= ~IGC_DMACR_DMACTHR_MASK; 1533 reg |= ((dmac << IGC_DMACR_DMACTHR_SHIFT) 1534 & IGC_DMACR_DMACTHR_MASK); 1535 1536 /* transition to L0x or L1 if available..*/ 1537 reg |= (IGC_DMACR_DMAC_EN | IGC_DMACR_DMAC_LX_MASK); 1538 1539 /* Check if status is 2.5Gb backplane connection 1540 * before configuration of watchdog timer, which is 1541 * in msec values in 12.8usec intervals 1542 * watchdog timer= msec values in 32usec intervals 1543 * for non 2.5Gb connection 1544 */ 1545 status = IGC_READ_REG(hw, IGC_STATUS); 1546 if ((status & IGC_STATUS_2P5_SKU) && 1547 (!(status & IGC_STATUS_2P5_SKU_OVER))) 1548 reg |= ((adapter->dmac * 5) >> 6); 1549 else 1550 reg |= (adapter->dmac >> 5); 1551 1552 IGC_WRITE_REG(hw, IGC_DMACR, reg); 1553 1554 IGC_WRITE_REG(hw, IGC_DMCRTRH, 0); 1555 1556 /* Set the interval before transition */ 1557 reg = IGC_READ_REG(hw, IGC_DMCTLX); 1558 reg |= IGC_DMCTLX_DCFLUSH_DIS; 1559 1560 /* 1561 ** in 2.5Gb connection, TTLX unit is 0.4 usec 1562 ** which is 0x4*2 = 0xA. But delay is still 4 usec 1563 */ 1564 status = IGC_READ_REG(hw, IGC_STATUS); 1565 if ((status & IGC_STATUS_2P5_SKU) && 1566 (!(status & IGC_STATUS_2P5_SKU_OVER))) 1567 reg |= 0xA; 1568 else 1569 reg |= 0x4; 1570 1571 IGC_WRITE_REG(hw, IGC_DMCTLX, reg); 1572 1573 /* free space in tx packet buffer to wake from DMA coal */ 1574 IGC_WRITE_REG(hw, IGC_DMCTXTH, (IGC_TXPBSIZE - 1575 (2 * max_frame_size)) >> 6); 1576 1577 /* make low power state decision controlled by DMA coal */ 1578 reg = IGC_READ_REG(hw, IGC_PCIEMISC); 1579 reg &= ~IGC_PCIEMISC_LX_DECISION; 1580 IGC_WRITE_REG(hw, IGC_PCIEMISC, reg); 1581 } 1582 1583 /********************************************************************* 1584 * 1585 * Initialize the hardware to a configuration as specified by the 1586 * adapter structure. 1587 * 1588 **********************************************************************/ 1589 static void 1590 igc_reset(if_ctx_t ctx) 1591 { 1592 device_t dev = iflib_get_dev(ctx); 1593 struct igc_adapter *adapter = iflib_get_softc(ctx); 1594 struct igc_hw *hw = &adapter->hw; 1595 u32 rx_buffer_size; 1596 u32 pba; 1597 1598 INIT_DEBUGOUT("igc_reset: begin"); 1599 /* Let the firmware know the OS is in control */ 1600 igc_get_hw_control(adapter); 1601 1602 /* 1603 * Packet Buffer Allocation (PBA) 1604 * Writing PBA sets the receive portion of the buffer 1605 * the remainder is used for the transmit buffer. 1606 */ 1607 pba = IGC_PBA_34K; 1608 1609 INIT_DEBUGOUT1("igc_reset: pba=%dK",pba); 1610 1611 /* 1612 * These parameters control the automatic generation (Tx) and 1613 * response (Rx) to Ethernet PAUSE frames. 1614 * - High water mark should allow for at least two frames to be 1615 * received after sending an XOFF. 1616 * - Low water mark works best when it is very near the high water mark. 1617 * This allows the receiver to restart by sending XON when it has 1618 * drained a bit. Here we use an arbitrary value of 1500 which will 1619 * restart after one full frame is pulled from the buffer. There 1620 * could be several smaller frames in the buffer and if so they will 1621 * not trigger the XON until their total number reduces the buffer 1622 * by 1500. 1623 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 1624 */ 1625 rx_buffer_size = (pba & 0xffff) << 10; 1626 hw->fc.high_water = rx_buffer_size - 1627 roundup2(adapter->hw.mac.max_frame_size, 1024); 1628 /* 16-byte granularity */ 1629 hw->fc.low_water = hw->fc.high_water - 16; 1630 1631 if (adapter->fc) /* locally set flow control value? */ 1632 hw->fc.requested_mode = adapter->fc; 1633 else 1634 hw->fc.requested_mode = igc_fc_full; 1635 1636 hw->fc.pause_time = IGC_FC_PAUSE_TIME; 1637 1638 hw->fc.send_xon = true; 1639 1640 /* Issue a global reset */ 1641 igc_reset_hw(hw); 1642 IGC_WRITE_REG(hw, IGC_WUC, 0); 1643 1644 /* and a re-init */ 1645 if (igc_init_hw(hw) < 0) { 1646 device_printf(dev, "Hardware Initialization Failed\n"); 1647 return; 1648 } 1649 1650 /* Setup DMA Coalescing */ 1651 igc_init_dmac(adapter, pba); 1652 1653 IGC_WRITE_REG(hw, IGC_VET, ETHERTYPE_VLAN); 1654 igc_get_phy_info(hw); 1655 igc_check_for_link(hw); 1656 } 1657 1658 /* 1659 * Initialise the RSS mapping for NICs that support multiple transmit/ 1660 * receive rings. 1661 */ 1662 1663 #define RSSKEYLEN 10 1664 static void 1665 igc_initialize_rss_mapping(struct igc_adapter *adapter) 1666 { 1667 struct igc_hw *hw = &adapter->hw; 1668 int i; 1669 int queue_id; 1670 u32 reta; 1671 u32 rss_key[RSSKEYLEN], mrqc, shift = 0; 1672 1673 /* 1674 * The redirection table controls which destination 1675 * queue each bucket redirects traffic to. 1676 * Each DWORD represents four queues, with the LSB 1677 * being the first queue in the DWORD. 1678 * 1679 * This just allocates buckets to queues using round-robin 1680 * allocation. 1681 * 1682 * NOTE: It Just Happens to line up with the default 1683 * RSS allocation method. 1684 */ 1685 1686 /* Warning FM follows */ 1687 reta = 0; 1688 for (i = 0; i < 128; i++) { 1689 #ifdef RSS 1690 queue_id = rss_get_indirection_to_bucket(i); 1691 /* 1692 * If we have more queues than buckets, we'll 1693 * end up mapping buckets to a subset of the 1694 * queues. 1695 * 1696 * If we have more buckets than queues, we'll 1697 * end up instead assigning multiple buckets 1698 * to queues. 1699 * 1700 * Both are suboptimal, but we need to handle 1701 * the case so we don't go out of bounds 1702 * indexing arrays and such. 1703 */ 1704 queue_id = queue_id % adapter->rx_num_queues; 1705 #else 1706 queue_id = (i % adapter->rx_num_queues); 1707 #endif 1708 /* Adjust if required */ 1709 queue_id = queue_id << shift; 1710 1711 /* 1712 * The low 8 bits are for hash value (n+0); 1713 * The next 8 bits are for hash value (n+1), etc. 1714 */ 1715 reta = reta >> 8; 1716 reta = reta | ( ((uint32_t) queue_id) << 24); 1717 if ((i & 3) == 3) { 1718 IGC_WRITE_REG(hw, IGC_RETA(i >> 2), reta); 1719 reta = 0; 1720 } 1721 } 1722 1723 /* Now fill in hash table */ 1724 1725 /* 1726 * MRQC: Multiple Receive Queues Command 1727 * Set queuing to RSS control, number depends on the device. 1728 */ 1729 mrqc = IGC_MRQC_ENABLE_RSS_4Q; 1730 1731 #ifdef RSS 1732 /* XXX ew typecasting */ 1733 rss_getkey((uint8_t *) &rss_key); 1734 #else 1735 arc4rand(&rss_key, sizeof(rss_key), 0); 1736 #endif 1737 for (i = 0; i < RSSKEYLEN; i++) 1738 IGC_WRITE_REG_ARRAY(hw, IGC_RSSRK(0), i, rss_key[i]); 1739 1740 /* 1741 * Configure the RSS fields to hash upon. 1742 */ 1743 mrqc |= (IGC_MRQC_RSS_FIELD_IPV4 | 1744 IGC_MRQC_RSS_FIELD_IPV4_TCP); 1745 mrqc |= (IGC_MRQC_RSS_FIELD_IPV6 | 1746 IGC_MRQC_RSS_FIELD_IPV6_TCP); 1747 mrqc |=( IGC_MRQC_RSS_FIELD_IPV4_UDP | 1748 IGC_MRQC_RSS_FIELD_IPV6_UDP); 1749 mrqc |=( IGC_MRQC_RSS_FIELD_IPV6_UDP_EX | 1750 IGC_MRQC_RSS_FIELD_IPV6_TCP_EX); 1751 1752 IGC_WRITE_REG(hw, IGC_MRQC, mrqc); 1753 } 1754 1755 /********************************************************************* 1756 * 1757 * Setup networking device structure and register interface media. 1758 * 1759 **********************************************************************/ 1760 static int 1761 igc_setup_interface(if_ctx_t ctx) 1762 { 1763 if_t ifp = iflib_get_ifp(ctx); 1764 struct igc_adapter *adapter = iflib_get_softc(ctx); 1765 if_softc_ctx_t scctx = adapter->shared; 1766 1767 INIT_DEBUGOUT("igc_setup_interface: begin"); 1768 1769 /* Single Queue */ 1770 if (adapter->tx_num_queues == 1) { 1771 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1); 1772 if_setsendqready(ifp); 1773 } 1774 1775 /* 1776 * Specify the media types supported by this adapter and register 1777 * callbacks to update media and link information 1778 */ 1779 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 1780 ifmedia_add(adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1781 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX, 0, NULL); 1782 ifmedia_add(adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1783 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1784 ifmedia_add(adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL); 1785 ifmedia_add(adapter->media, IFM_ETHER | IFM_2500_T, 0, NULL); 1786 1787 ifmedia_add(adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 1788 ifmedia_set(adapter->media, IFM_ETHER | IFM_AUTO); 1789 return (0); 1790 } 1791 1792 static int 1793 igc_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets) 1794 { 1795 struct igc_adapter *adapter = iflib_get_softc(ctx); 1796 if_softc_ctx_t scctx = adapter->shared; 1797 int error = IGC_SUCCESS; 1798 struct igc_tx_queue *que; 1799 int i, j; 1800 1801 MPASS(adapter->tx_num_queues > 0); 1802 MPASS(adapter->tx_num_queues == ntxqsets); 1803 1804 /* First allocate the top level queue structs */ 1805 if (!(adapter->tx_queues = 1806 (struct igc_tx_queue *) malloc(sizeof(struct igc_tx_queue) * 1807 adapter->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 1808 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 1809 return(ENOMEM); 1810 } 1811 1812 for (i = 0, que = adapter->tx_queues; i < adapter->tx_num_queues; i++, que++) { 1813 /* Set up some basics */ 1814 1815 struct tx_ring *txr = &que->txr; 1816 txr->adapter = que->adapter = adapter; 1817 que->me = txr->me = i; 1818 1819 /* Allocate report status array */ 1820 if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) { 1821 device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n"); 1822 error = ENOMEM; 1823 goto fail; 1824 } 1825 for (j = 0; j < scctx->isc_ntxd[0]; j++) 1826 txr->tx_rsq[j] = QIDX_INVALID; 1827 /* get the virtual and physical address of the hardware queues */ 1828 txr->tx_base = (struct igc_tx_desc *)vaddrs[i*ntxqs]; 1829 txr->tx_paddr = paddrs[i*ntxqs]; 1830 } 1831 1832 if (bootverbose) 1833 device_printf(iflib_get_dev(ctx), 1834 "allocated for %d tx_queues\n", adapter->tx_num_queues); 1835 return (0); 1836 fail: 1837 igc_if_queues_free(ctx); 1838 return (error); 1839 } 1840 1841 static int 1842 igc_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets) 1843 { 1844 struct igc_adapter *adapter = iflib_get_softc(ctx); 1845 int error = IGC_SUCCESS; 1846 struct igc_rx_queue *que; 1847 int i; 1848 1849 MPASS(adapter->rx_num_queues > 0); 1850 MPASS(adapter->rx_num_queues == nrxqsets); 1851 1852 /* First allocate the top level queue structs */ 1853 if (!(adapter->rx_queues = 1854 (struct igc_rx_queue *) malloc(sizeof(struct igc_rx_queue) * 1855 adapter->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) { 1856 device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n"); 1857 error = ENOMEM; 1858 goto fail; 1859 } 1860 1861 for (i = 0, que = adapter->rx_queues; i < nrxqsets; i++, que++) { 1862 /* Set up some basics */ 1863 struct rx_ring *rxr = &que->rxr; 1864 rxr->adapter = que->adapter = adapter; 1865 rxr->que = que; 1866 que->me = rxr->me = i; 1867 1868 /* get the virtual and physical address of the hardware queues */ 1869 rxr->rx_base = (union igc_rx_desc_extended *)vaddrs[i*nrxqs]; 1870 rxr->rx_paddr = paddrs[i*nrxqs]; 1871 } 1872 1873 if (bootverbose) 1874 device_printf(iflib_get_dev(ctx), 1875 "allocated for %d rx_queues\n", adapter->rx_num_queues); 1876 1877 return (0); 1878 fail: 1879 igc_if_queues_free(ctx); 1880 return (error); 1881 } 1882 1883 static void 1884 igc_if_queues_free(if_ctx_t ctx) 1885 { 1886 struct igc_adapter *adapter = iflib_get_softc(ctx); 1887 struct igc_tx_queue *tx_que = adapter->tx_queues; 1888 struct igc_rx_queue *rx_que = adapter->rx_queues; 1889 1890 if (tx_que != NULL) { 1891 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 1892 struct tx_ring *txr = &tx_que->txr; 1893 if (txr->tx_rsq == NULL) 1894 break; 1895 1896 free(txr->tx_rsq, M_DEVBUF); 1897 txr->tx_rsq = NULL; 1898 } 1899 free(adapter->tx_queues, M_DEVBUF); 1900 adapter->tx_queues = NULL; 1901 } 1902 1903 if (rx_que != NULL) { 1904 free(adapter->rx_queues, M_DEVBUF); 1905 adapter->rx_queues = NULL; 1906 } 1907 1908 igc_release_hw_control(adapter); 1909 1910 if (adapter->mta != NULL) { 1911 free(adapter->mta, M_DEVBUF); 1912 } 1913 } 1914 1915 /********************************************************************* 1916 * 1917 * Enable transmit unit. 1918 * 1919 **********************************************************************/ 1920 static void 1921 igc_initialize_transmit_unit(if_ctx_t ctx) 1922 { 1923 struct igc_adapter *adapter = iflib_get_softc(ctx); 1924 if_softc_ctx_t scctx = adapter->shared; 1925 struct igc_tx_queue *que; 1926 struct tx_ring *txr; 1927 struct igc_hw *hw = &adapter->hw; 1928 u32 tctl, txdctl = 0; 1929 1930 INIT_DEBUGOUT("igc_initialize_transmit_unit: begin"); 1931 1932 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 1933 u64 bus_addr; 1934 caddr_t offp, endp; 1935 1936 que = &adapter->tx_queues[i]; 1937 txr = &que->txr; 1938 bus_addr = txr->tx_paddr; 1939 1940 /* Clear checksum offload context. */ 1941 offp = (caddr_t)&txr->csum_flags; 1942 endp = (caddr_t)(txr + 1); 1943 bzero(offp, endp - offp); 1944 1945 /* Base and Len of TX Ring */ 1946 IGC_WRITE_REG(hw, IGC_TDLEN(i), 1947 scctx->isc_ntxd[0] * sizeof(struct igc_tx_desc)); 1948 IGC_WRITE_REG(hw, IGC_TDBAH(i), 1949 (u32)(bus_addr >> 32)); 1950 IGC_WRITE_REG(hw, IGC_TDBAL(i), 1951 (u32)bus_addr); 1952 /* Init the HEAD/TAIL indices */ 1953 IGC_WRITE_REG(hw, IGC_TDT(i), 0); 1954 IGC_WRITE_REG(hw, IGC_TDH(i), 0); 1955 1956 HW_DEBUGOUT2("Base = %x, Length = %x\n", 1957 IGC_READ_REG(&adapter->hw, IGC_TDBAL(i)), 1958 IGC_READ_REG(&adapter->hw, IGC_TDLEN(i))); 1959 1960 txdctl = 0; /* clear txdctl */ 1961 txdctl |= 0x1f; /* PTHRESH */ 1962 txdctl |= 1 << 8; /* HTHRESH */ 1963 txdctl |= 1 << 16;/* WTHRESH */ 1964 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ 1965 txdctl |= IGC_TXDCTL_GRAN; 1966 txdctl |= 1 << 25; /* LWTHRESH */ 1967 1968 IGC_WRITE_REG(hw, IGC_TXDCTL(i), txdctl); 1969 } 1970 1971 /* Program the Transmit Control Register */ 1972 tctl = IGC_READ_REG(&adapter->hw, IGC_TCTL); 1973 tctl &= ~IGC_TCTL_CT; 1974 tctl |= (IGC_TCTL_PSP | IGC_TCTL_RTLC | IGC_TCTL_EN | 1975 (IGC_COLLISION_THRESHOLD << IGC_CT_SHIFT)); 1976 1977 /* This write will effectively turn on the transmit unit. */ 1978 IGC_WRITE_REG(&adapter->hw, IGC_TCTL, tctl); 1979 } 1980 1981 /********************************************************************* 1982 * 1983 * Enable receive unit. 1984 * 1985 **********************************************************************/ 1986 #define BSIZEPKT_ROUNDUP ((1<<IGC_SRRCTL_BSIZEPKT_SHIFT)-1) 1987 1988 static void 1989 igc_initialize_receive_unit(if_ctx_t ctx) 1990 { 1991 struct igc_adapter *adapter = iflib_get_softc(ctx); 1992 if_softc_ctx_t scctx = adapter->shared; 1993 if_t ifp = iflib_get_ifp(ctx); 1994 struct igc_hw *hw = &adapter->hw; 1995 struct igc_rx_queue *que; 1996 int i; 1997 u32 psize, rctl, rxcsum, srrctl = 0; 1998 1999 INIT_DEBUGOUT("igc_initialize_receive_units: begin"); 2000 2001 /* 2002 * Make sure receives are disabled while setting 2003 * up the descriptor ring 2004 */ 2005 rctl = IGC_READ_REG(hw, IGC_RCTL); 2006 IGC_WRITE_REG(hw, IGC_RCTL, rctl & ~IGC_RCTL_EN); 2007 2008 /* Setup the Receive Control Register */ 2009 rctl &= ~(3 << IGC_RCTL_MO_SHIFT); 2010 rctl |= IGC_RCTL_EN | IGC_RCTL_BAM | 2011 IGC_RCTL_LBM_NO | IGC_RCTL_RDMTS_HALF | 2012 (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT); 2013 2014 /* Do not store bad packets */ 2015 rctl &= ~IGC_RCTL_SBP; 2016 2017 /* Enable Long Packet receive */ 2018 if (if_getmtu(ifp) > ETHERMTU) 2019 rctl |= IGC_RCTL_LPE; 2020 else 2021 rctl &= ~IGC_RCTL_LPE; 2022 2023 /* Strip the CRC */ 2024 if (!igc_disable_crc_stripping) 2025 rctl |= IGC_RCTL_SECRC; 2026 2027 /* 2028 * Set the interrupt throttling rate. Value is calculated 2029 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 2030 */ 2031 IGC_WRITE_REG(hw, IGC_ITR, DEFAULT_ITR); 2032 2033 rxcsum = IGC_READ_REG(hw, IGC_RXCSUM); 2034 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 2035 rxcsum |= IGC_RXCSUM_CRCOFL; 2036 if (adapter->tx_num_queues > 1) 2037 rxcsum |= IGC_RXCSUM_PCSD; 2038 else 2039 rxcsum |= IGC_RXCSUM_IPPCSE; 2040 } else { 2041 if (adapter->tx_num_queues > 1) 2042 rxcsum |= IGC_RXCSUM_PCSD; 2043 else 2044 rxcsum &= ~IGC_RXCSUM_TUOFL; 2045 } 2046 IGC_WRITE_REG(hw, IGC_RXCSUM, rxcsum); 2047 2048 if (adapter->rx_num_queues > 1) 2049 igc_initialize_rss_mapping(adapter); 2050 2051 if (if_getmtu(ifp) > ETHERMTU) { 2052 psize = scctx->isc_max_frame_size; 2053 /* are we on a vlan? */ 2054 if (if_vlantrunkinuse(ifp)) 2055 psize += VLAN_TAG_SIZE; 2056 IGC_WRITE_REG(&adapter->hw, IGC_RLPML, psize); 2057 } 2058 2059 /* Set maximum packet buffer len */ 2060 srrctl |= (adapter->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >> 2061 IGC_SRRCTL_BSIZEPKT_SHIFT; 2062 /* srrctl above overrides this but set the register to a sane value */ 2063 rctl |= IGC_RCTL_SZ_2048; 2064 2065 /* 2066 * If TX flow control is disabled and there's >1 queue defined, 2067 * enable DROP. 2068 * 2069 * This drops frames rather than hanging the RX MAC for all queues. 2070 */ 2071 if ((adapter->rx_num_queues > 1) && 2072 (adapter->fc == igc_fc_none || 2073 adapter->fc == igc_fc_rx_pause)) { 2074 srrctl |= IGC_SRRCTL_DROP_EN; 2075 } 2076 2077 /* Setup the Base and Length of the Rx Descriptor Rings */ 2078 for (i = 0, que = adapter->rx_queues; i < adapter->rx_num_queues; i++, que++) { 2079 struct rx_ring *rxr = &que->rxr; 2080 u64 bus_addr = rxr->rx_paddr; 2081 u32 rxdctl; 2082 2083 #ifdef notyet 2084 /* Configure for header split? -- ignore for now */ 2085 rxr->hdr_split = igc_header_split; 2086 #else 2087 srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF; 2088 #endif 2089 2090 IGC_WRITE_REG(hw, IGC_RDLEN(i), 2091 scctx->isc_nrxd[0] * sizeof(struct igc_rx_desc)); 2092 IGC_WRITE_REG(hw, IGC_RDBAH(i), 2093 (uint32_t)(bus_addr >> 32)); 2094 IGC_WRITE_REG(hw, IGC_RDBAL(i), 2095 (uint32_t)bus_addr); 2096 IGC_WRITE_REG(hw, IGC_SRRCTL(i), srrctl); 2097 /* Setup the Head and Tail Descriptor Pointers */ 2098 IGC_WRITE_REG(hw, IGC_RDH(i), 0); 2099 IGC_WRITE_REG(hw, IGC_RDT(i), 0); 2100 /* Enable this Queue */ 2101 rxdctl = IGC_READ_REG(hw, IGC_RXDCTL(i)); 2102 rxdctl |= IGC_RXDCTL_QUEUE_ENABLE; 2103 rxdctl &= 0xFFF00000; 2104 rxdctl |= IGC_RX_PTHRESH; 2105 rxdctl |= IGC_RX_HTHRESH << 8; 2106 rxdctl |= IGC_RX_WTHRESH << 16; 2107 IGC_WRITE_REG(hw, IGC_RXDCTL(i), rxdctl); 2108 } 2109 2110 /* Make sure VLAN Filters are off */ 2111 rctl &= ~IGC_RCTL_VFE; 2112 2113 /* Write out the settings */ 2114 IGC_WRITE_REG(hw, IGC_RCTL, rctl); 2115 2116 return; 2117 } 2118 2119 static void 2120 igc_setup_vlan_hw_support(if_ctx_t ctx) 2121 { 2122 struct igc_adapter *adapter = iflib_get_softc(ctx); 2123 struct igc_hw *hw = &adapter->hw; 2124 struct ifnet *ifp = iflib_get_ifp(ctx); 2125 u32 reg; 2126 2127 /* igc hardware doesn't seem to implement VFTA for HWFILTER */ 2128 2129 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING && 2130 !igc_disable_crc_stripping) { 2131 reg = IGC_READ_REG(hw, IGC_CTRL); 2132 reg |= IGC_CTRL_VME; 2133 IGC_WRITE_REG(hw, IGC_CTRL, reg); 2134 } else { 2135 reg = IGC_READ_REG(hw, IGC_CTRL); 2136 reg &= ~IGC_CTRL_VME; 2137 IGC_WRITE_REG(hw, IGC_CTRL, reg); 2138 } 2139 } 2140 2141 static void 2142 igc_if_intr_enable(if_ctx_t ctx) 2143 { 2144 struct igc_adapter *adapter = iflib_get_softc(ctx); 2145 struct igc_hw *hw = &adapter->hw; 2146 u32 mask; 2147 2148 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 2149 mask = (adapter->que_mask | adapter->link_mask); 2150 IGC_WRITE_REG(hw, IGC_EIAC, mask); 2151 IGC_WRITE_REG(hw, IGC_EIAM, mask); 2152 IGC_WRITE_REG(hw, IGC_EIMS, mask); 2153 IGC_WRITE_REG(hw, IGC_IMS, IGC_IMS_LSC); 2154 } else 2155 IGC_WRITE_REG(hw, IGC_IMS, IMS_ENABLE_MASK); 2156 IGC_WRITE_FLUSH(hw); 2157 } 2158 2159 static void 2160 igc_if_intr_disable(if_ctx_t ctx) 2161 { 2162 struct igc_adapter *adapter = iflib_get_softc(ctx); 2163 struct igc_hw *hw = &adapter->hw; 2164 2165 if (__predict_true(adapter->intr_type == IFLIB_INTR_MSIX)) { 2166 IGC_WRITE_REG(hw, IGC_EIMC, 0xffffffff); 2167 IGC_WRITE_REG(hw, IGC_EIAC, 0); 2168 } 2169 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff); 2170 IGC_WRITE_FLUSH(hw); 2171 } 2172 2173 /* 2174 * igc_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit. 2175 * For ASF and Pass Through versions of f/w this means 2176 * that the driver is loaded. For AMT version type f/w 2177 * this means that the network i/f is open. 2178 */ 2179 static void 2180 igc_get_hw_control(struct igc_adapter *adapter) 2181 { 2182 u32 ctrl_ext; 2183 2184 if (adapter->vf_ifp) 2185 return; 2186 2187 ctrl_ext = IGC_READ_REG(&adapter->hw, IGC_CTRL_EXT); 2188 IGC_WRITE_REG(&adapter->hw, IGC_CTRL_EXT, 2189 ctrl_ext | IGC_CTRL_EXT_DRV_LOAD); 2190 } 2191 2192 /* 2193 * igc_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 2194 * For ASF and Pass Through versions of f/w this means that 2195 * the driver is no longer loaded. For AMT versions of the 2196 * f/w this means that the network i/f is closed. 2197 */ 2198 static void 2199 igc_release_hw_control(struct igc_adapter *adapter) 2200 { 2201 u32 ctrl_ext; 2202 2203 ctrl_ext = IGC_READ_REG(&adapter->hw, IGC_CTRL_EXT); 2204 IGC_WRITE_REG(&adapter->hw, IGC_CTRL_EXT, 2205 ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD); 2206 return; 2207 } 2208 2209 static int 2210 igc_is_valid_ether_addr(u8 *addr) 2211 { 2212 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 2213 2214 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 2215 return (false); 2216 } 2217 2218 return (true); 2219 } 2220 2221 /* 2222 ** Parse the interface capabilities with regard 2223 ** to both system management and wake-on-lan for 2224 ** later use. 2225 */ 2226 static void 2227 igc_get_wakeup(if_ctx_t ctx) 2228 { 2229 struct igc_adapter *adapter = iflib_get_softc(ctx); 2230 u16 eeprom_data = 0, apme_mask; 2231 2232 apme_mask = IGC_WUC_APME; 2233 eeprom_data = IGC_READ_REG(&adapter->hw, IGC_WUC); 2234 2235 if (eeprom_data & apme_mask) 2236 adapter->wol = IGC_WUFC_LNKC; 2237 } 2238 2239 2240 /* 2241 * Enable PCI Wake On Lan capability 2242 */ 2243 static void 2244 igc_enable_wakeup(if_ctx_t ctx) 2245 { 2246 struct igc_adapter *adapter = iflib_get_softc(ctx); 2247 device_t dev = iflib_get_dev(ctx); 2248 if_t ifp = iflib_get_ifp(ctx); 2249 int error = 0; 2250 u32 pmc, ctrl, rctl; 2251 u16 status; 2252 2253 if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0) 2254 return; 2255 2256 /* 2257 * Determine type of Wakeup: note that wol 2258 * is set with all bits on by default. 2259 */ 2260 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) == 0) 2261 adapter->wol &= ~IGC_WUFC_MAG; 2262 2263 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) == 0) 2264 adapter->wol &= ~IGC_WUFC_EX; 2265 2266 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) == 0) 2267 adapter->wol &= ~IGC_WUFC_MC; 2268 else { 2269 rctl = IGC_READ_REG(&adapter->hw, IGC_RCTL); 2270 rctl |= IGC_RCTL_MPE; 2271 IGC_WRITE_REG(&adapter->hw, IGC_RCTL, rctl); 2272 } 2273 2274 if (!(adapter->wol & (IGC_WUFC_EX | IGC_WUFC_MAG | IGC_WUFC_MC))) 2275 goto pme; 2276 2277 /* Advertise the wakeup capability */ 2278 ctrl = IGC_READ_REG(&adapter->hw, IGC_CTRL); 2279 ctrl |= IGC_CTRL_ADVD3WUC; 2280 IGC_WRITE_REG(&adapter->hw, IGC_CTRL, ctrl); 2281 2282 /* Enable wakeup by the MAC */ 2283 IGC_WRITE_REG(&adapter->hw, IGC_WUC, IGC_WUC_PME_EN); 2284 IGC_WRITE_REG(&adapter->hw, IGC_WUFC, adapter->wol); 2285 2286 pme: 2287 status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2); 2288 status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2289 if (!error && (if_getcapenable(ifp) & IFCAP_WOL)) 2290 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2291 pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2); 2292 2293 return; 2294 } 2295 2296 /********************************************************************** 2297 * 2298 * Update the board statistics counters. 2299 * 2300 **********************************************************************/ 2301 static void 2302 igc_update_stats_counters(struct igc_adapter *adapter) 2303 { 2304 u64 prev_xoffrxc = adapter->stats.xoffrxc; 2305 2306 adapter->stats.crcerrs += IGC_READ_REG(&adapter->hw, IGC_CRCERRS); 2307 adapter->stats.mpc += IGC_READ_REG(&adapter->hw, IGC_MPC); 2308 adapter->stats.scc += IGC_READ_REG(&adapter->hw, IGC_SCC); 2309 adapter->stats.ecol += IGC_READ_REG(&adapter->hw, IGC_ECOL); 2310 2311 adapter->stats.mcc += IGC_READ_REG(&adapter->hw, IGC_MCC); 2312 adapter->stats.latecol += IGC_READ_REG(&adapter->hw, IGC_LATECOL); 2313 adapter->stats.colc += IGC_READ_REG(&adapter->hw, IGC_COLC); 2314 adapter->stats.colc += IGC_READ_REG(&adapter->hw, IGC_RERC); 2315 adapter->stats.dc += IGC_READ_REG(&adapter->hw, IGC_DC); 2316 adapter->stats.rlec += IGC_READ_REG(&adapter->hw, IGC_RLEC); 2317 adapter->stats.xonrxc += IGC_READ_REG(&adapter->hw, IGC_XONRXC); 2318 adapter->stats.xontxc += IGC_READ_REG(&adapter->hw, IGC_XONTXC); 2319 adapter->stats.xoffrxc += IGC_READ_REG(&adapter->hw, IGC_XOFFRXC); 2320 /* 2321 * For watchdog management we need to know if we have been 2322 * paused during the last interval, so capture that here. 2323 */ 2324 if (adapter->stats.xoffrxc != prev_xoffrxc) 2325 adapter->shared->isc_pause_frames = 1; 2326 adapter->stats.xofftxc += IGC_READ_REG(&adapter->hw, IGC_XOFFTXC); 2327 adapter->stats.fcruc += IGC_READ_REG(&adapter->hw, IGC_FCRUC); 2328 adapter->stats.prc64 += IGC_READ_REG(&adapter->hw, IGC_PRC64); 2329 adapter->stats.prc127 += IGC_READ_REG(&adapter->hw, IGC_PRC127); 2330 adapter->stats.prc255 += IGC_READ_REG(&adapter->hw, IGC_PRC255); 2331 adapter->stats.prc511 += IGC_READ_REG(&adapter->hw, IGC_PRC511); 2332 adapter->stats.prc1023 += IGC_READ_REG(&adapter->hw, IGC_PRC1023); 2333 adapter->stats.prc1522 += IGC_READ_REG(&adapter->hw, IGC_PRC1522); 2334 adapter->stats.tlpic += IGC_READ_REG(&adapter->hw, IGC_TLPIC); 2335 adapter->stats.rlpic += IGC_READ_REG(&adapter->hw, IGC_RLPIC); 2336 adapter->stats.gprc += IGC_READ_REG(&adapter->hw, IGC_GPRC); 2337 adapter->stats.bprc += IGC_READ_REG(&adapter->hw, IGC_BPRC); 2338 adapter->stats.mprc += IGC_READ_REG(&adapter->hw, IGC_MPRC); 2339 adapter->stats.gptc += IGC_READ_REG(&adapter->hw, IGC_GPTC); 2340 2341 /* For the 64-bit byte counters the low dword must be read first. */ 2342 /* Both registers clear on the read of the high dword */ 2343 2344 adapter->stats.gorc += IGC_READ_REG(&adapter->hw, IGC_GORCL) + 2345 ((u64)IGC_READ_REG(&adapter->hw, IGC_GORCH) << 32); 2346 adapter->stats.gotc += IGC_READ_REG(&adapter->hw, IGC_GOTCL) + 2347 ((u64)IGC_READ_REG(&adapter->hw, IGC_GOTCH) << 32); 2348 2349 adapter->stats.rnbc += IGC_READ_REG(&adapter->hw, IGC_RNBC); 2350 adapter->stats.ruc += IGC_READ_REG(&adapter->hw, IGC_RUC); 2351 adapter->stats.rfc += IGC_READ_REG(&adapter->hw, IGC_RFC); 2352 adapter->stats.roc += IGC_READ_REG(&adapter->hw, IGC_ROC); 2353 adapter->stats.rjc += IGC_READ_REG(&adapter->hw, IGC_RJC); 2354 2355 adapter->stats.tor += IGC_READ_REG(&adapter->hw, IGC_TORH); 2356 adapter->stats.tot += IGC_READ_REG(&adapter->hw, IGC_TOTH); 2357 2358 adapter->stats.tpr += IGC_READ_REG(&adapter->hw, IGC_TPR); 2359 adapter->stats.tpt += IGC_READ_REG(&adapter->hw, IGC_TPT); 2360 adapter->stats.ptc64 += IGC_READ_REG(&adapter->hw, IGC_PTC64); 2361 adapter->stats.ptc127 += IGC_READ_REG(&adapter->hw, IGC_PTC127); 2362 adapter->stats.ptc255 += IGC_READ_REG(&adapter->hw, IGC_PTC255); 2363 adapter->stats.ptc511 += IGC_READ_REG(&adapter->hw, IGC_PTC511); 2364 adapter->stats.ptc1023 += IGC_READ_REG(&adapter->hw, IGC_PTC1023); 2365 adapter->stats.ptc1522 += IGC_READ_REG(&adapter->hw, IGC_PTC1522); 2366 adapter->stats.mptc += IGC_READ_REG(&adapter->hw, IGC_MPTC); 2367 adapter->stats.bptc += IGC_READ_REG(&adapter->hw, IGC_BPTC); 2368 2369 /* Interrupt Counts */ 2370 adapter->stats.iac += IGC_READ_REG(&adapter->hw, IGC_IAC); 2371 adapter->stats.rxdmtc += IGC_READ_REG(&adapter->hw, IGC_RXDMTC); 2372 2373 adapter->stats.algnerrc += IGC_READ_REG(&adapter->hw, IGC_ALGNERRC); 2374 adapter->stats.tncrs += IGC_READ_REG(&adapter->hw, IGC_TNCRS); 2375 adapter->stats.htdpmc += IGC_READ_REG(&adapter->hw, IGC_HTDPMC); 2376 adapter->stats.tsctc += IGC_READ_REG(&adapter->hw, IGC_TSCTC); 2377 } 2378 2379 static uint64_t 2380 igc_if_get_counter(if_ctx_t ctx, ift_counter cnt) 2381 { 2382 struct igc_adapter *adapter = iflib_get_softc(ctx); 2383 if_t ifp = iflib_get_ifp(ctx); 2384 2385 switch (cnt) { 2386 case IFCOUNTER_COLLISIONS: 2387 return (adapter->stats.colc); 2388 case IFCOUNTER_IERRORS: 2389 return (adapter->dropped_pkts + adapter->stats.rxerrc + 2390 adapter->stats.crcerrs + adapter->stats.algnerrc + 2391 adapter->stats.ruc + adapter->stats.roc + 2392 adapter->stats.mpc + adapter->stats.htdpmc); 2393 case IFCOUNTER_OERRORS: 2394 return (adapter->stats.ecol + adapter->stats.latecol + 2395 adapter->watchdog_events); 2396 default: 2397 return (if_get_counter_default(ifp, cnt)); 2398 } 2399 } 2400 2401 /* igc_if_needs_restart - Tell iflib when the driver needs to be reinitialized 2402 * @ctx: iflib context 2403 * @event: event code to check 2404 * 2405 * Defaults to returning true for unknown events. 2406 * 2407 * @returns true if iflib needs to reinit the interface 2408 */ 2409 static bool 2410 igc_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event) 2411 { 2412 switch (event) { 2413 case IFLIB_RESTART_VLAN_CONFIG: 2414 return (false); 2415 default: 2416 return (true); 2417 } 2418 } 2419 2420 /* Export a single 32-bit register via a read-only sysctl. */ 2421 static int 2422 igc_sysctl_reg_handler(SYSCTL_HANDLER_ARGS) 2423 { 2424 struct igc_adapter *adapter; 2425 u_int val; 2426 2427 adapter = oidp->oid_arg1; 2428 val = IGC_READ_REG(&adapter->hw, oidp->oid_arg2); 2429 return (sysctl_handle_int(oidp, &val, 0, req)); 2430 } 2431 2432 /* 2433 * Add sysctl variables, one per statistic, to the system. 2434 */ 2435 static void 2436 igc_add_hw_stats(struct igc_adapter *adapter) 2437 { 2438 device_t dev = iflib_get_dev(adapter->ctx); 2439 struct igc_tx_queue *tx_que = adapter->tx_queues; 2440 struct igc_rx_queue *rx_que = adapter->rx_queues; 2441 2442 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 2443 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 2444 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); 2445 struct igc_hw_stats *stats = &adapter->stats; 2446 2447 struct sysctl_oid *stat_node, *queue_node, *int_node; 2448 struct sysctl_oid_list *stat_list, *queue_list, *int_list; 2449 2450 #define QUEUE_NAME_LEN 32 2451 char namebuf[QUEUE_NAME_LEN]; 2452 2453 /* Driver Statistics */ 2454 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped", 2455 CTLFLAG_RD, &adapter->dropped_pkts, 2456 "Driver dropped packets"); 2457 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq", 2458 CTLFLAG_RD, &adapter->link_irq, 2459 "Link MSI-X IRQ Handled"); 2460 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns", 2461 CTLFLAG_RD, &adapter->rx_overruns, 2462 "RX overruns"); 2463 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts", 2464 CTLFLAG_RD, &adapter->watchdog_events, 2465 "Watchdog timeouts"); 2466 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control", 2467 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 2468 adapter, IGC_CTRL, igc_sysctl_reg_handler, "IU", 2469 "Device Control Register"); 2470 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control", 2471 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 2472 adapter, IGC_RCTL, igc_sysctl_reg_handler, "IU", 2473 "Receiver Control Register"); 2474 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water", 2475 CTLFLAG_RD, &adapter->hw.fc.high_water, 0, 2476 "Flow Control High Watermark"); 2477 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water", 2478 CTLFLAG_RD, &adapter->hw.fc.low_water, 0, 2479 "Flow Control Low Watermark"); 2480 2481 for (int i = 0; i < adapter->tx_num_queues; i++, tx_que++) { 2482 struct tx_ring *txr = &tx_que->txr; 2483 snprintf(namebuf, QUEUE_NAME_LEN, "queue_tx_%d", i); 2484 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 2485 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name"); 2486 queue_list = SYSCTL_CHILDREN(queue_node); 2487 2488 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head", 2489 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 2490 IGC_TDH(txr->me), igc_sysctl_reg_handler, "IU", 2491 "Transmit Descriptor Head"); 2492 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail", 2493 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 2494 IGC_TDT(txr->me), igc_sysctl_reg_handler, "IU", 2495 "Transmit Descriptor Tail"); 2496 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq", 2497 CTLFLAG_RD, &txr->tx_irq, 2498 "Queue MSI-X Transmit Interrupts"); 2499 } 2500 2501 for (int j = 0; j < adapter->rx_num_queues; j++, rx_que++) { 2502 struct rx_ring *rxr = &rx_que->rxr; 2503 snprintf(namebuf, QUEUE_NAME_LEN, "queue_rx_%d", j); 2504 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf, 2505 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name"); 2506 queue_list = SYSCTL_CHILDREN(queue_node); 2507 2508 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head", 2509 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 2510 IGC_RDH(rxr->me), igc_sysctl_reg_handler, "IU", 2511 "Receive Descriptor Head"); 2512 SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail", 2513 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, adapter, 2514 IGC_RDT(rxr->me), igc_sysctl_reg_handler, "IU", 2515 "Receive Descriptor Tail"); 2516 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq", 2517 CTLFLAG_RD, &rxr->rx_irq, 2518 "Queue MSI-X Receive Interrupts"); 2519 } 2520 2521 /* MAC stats get their own sub node */ 2522 2523 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", 2524 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics"); 2525 stat_list = SYSCTL_CHILDREN(stat_node); 2526 2527 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll", 2528 CTLFLAG_RD, &stats->ecol, 2529 "Excessive collisions"); 2530 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll", 2531 CTLFLAG_RD, &stats->scc, 2532 "Single collisions"); 2533 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll", 2534 CTLFLAG_RD, &stats->mcc, 2535 "Multiple collisions"); 2536 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll", 2537 CTLFLAG_RD, &stats->latecol, 2538 "Late collisions"); 2539 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count", 2540 CTLFLAG_RD, &stats->colc, 2541 "Collision Count"); 2542 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors", 2543 CTLFLAG_RD, &adapter->stats.symerrs, 2544 "Symbol Errors"); 2545 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors", 2546 CTLFLAG_RD, &adapter->stats.sec, 2547 "Sequence Errors"); 2548 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count", 2549 CTLFLAG_RD, &adapter->stats.dc, 2550 "Defer Count"); 2551 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets", 2552 CTLFLAG_RD, &adapter->stats.mpc, 2553 "Missed Packets"); 2554 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff", 2555 CTLFLAG_RD, &adapter->stats.rnbc, 2556 "Receive No Buffers"); 2557 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize", 2558 CTLFLAG_RD, &adapter->stats.ruc, 2559 "Receive Undersize"); 2560 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented", 2561 CTLFLAG_RD, &adapter->stats.rfc, 2562 "Fragmented Packets Received "); 2563 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize", 2564 CTLFLAG_RD, &adapter->stats.roc, 2565 "Oversized Packets Received"); 2566 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber", 2567 CTLFLAG_RD, &adapter->stats.rjc, 2568 "Recevied Jabber"); 2569 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs", 2570 CTLFLAG_RD, &adapter->stats.rxerrc, 2571 "Receive Errors"); 2572 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs", 2573 CTLFLAG_RD, &adapter->stats.crcerrs, 2574 "CRC errors"); 2575 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs", 2576 CTLFLAG_RD, &adapter->stats.algnerrc, 2577 "Alignment Errors"); 2578 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd", 2579 CTLFLAG_RD, &adapter->stats.xonrxc, 2580 "XON Received"); 2581 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd", 2582 CTLFLAG_RD, &adapter->stats.xontxc, 2583 "XON Transmitted"); 2584 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd", 2585 CTLFLAG_RD, &adapter->stats.xoffrxc, 2586 "XOFF Received"); 2587 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd", 2588 CTLFLAG_RD, &adapter->stats.xofftxc, 2589 "XOFF Transmitted"); 2590 2591 /* Packet Reception Stats */ 2592 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd", 2593 CTLFLAG_RD, &adapter->stats.tpr, 2594 "Total Packets Received "); 2595 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd", 2596 CTLFLAG_RD, &adapter->stats.gprc, 2597 "Good Packets Received"); 2598 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd", 2599 CTLFLAG_RD, &adapter->stats.bprc, 2600 "Broadcast Packets Received"); 2601 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd", 2602 CTLFLAG_RD, &adapter->stats.mprc, 2603 "Multicast Packets Received"); 2604 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64", 2605 CTLFLAG_RD, &adapter->stats.prc64, 2606 "64 byte frames received "); 2607 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127", 2608 CTLFLAG_RD, &adapter->stats.prc127, 2609 "65-127 byte frames received"); 2610 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255", 2611 CTLFLAG_RD, &adapter->stats.prc255, 2612 "128-255 byte frames received"); 2613 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511", 2614 CTLFLAG_RD, &adapter->stats.prc511, 2615 "256-511 byte frames received"); 2616 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023", 2617 CTLFLAG_RD, &adapter->stats.prc1023, 2618 "512-1023 byte frames received"); 2619 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522", 2620 CTLFLAG_RD, &adapter->stats.prc1522, 2621 "1023-1522 byte frames received"); 2622 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd", 2623 CTLFLAG_RD, &adapter->stats.gorc, 2624 "Good Octets Received"); 2625 2626 /* Packet Transmission Stats */ 2627 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd", 2628 CTLFLAG_RD, &adapter->stats.gotc, 2629 "Good Octets Transmitted"); 2630 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd", 2631 CTLFLAG_RD, &adapter->stats.tpt, 2632 "Total Packets Transmitted"); 2633 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd", 2634 CTLFLAG_RD, &adapter->stats.gptc, 2635 "Good Packets Transmitted"); 2636 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd", 2637 CTLFLAG_RD, &adapter->stats.bptc, 2638 "Broadcast Packets Transmitted"); 2639 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd", 2640 CTLFLAG_RD, &adapter->stats.mptc, 2641 "Multicast Packets Transmitted"); 2642 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64", 2643 CTLFLAG_RD, &adapter->stats.ptc64, 2644 "64 byte frames transmitted "); 2645 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127", 2646 CTLFLAG_RD, &adapter->stats.ptc127, 2647 "65-127 byte frames transmitted"); 2648 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255", 2649 CTLFLAG_RD, &adapter->stats.ptc255, 2650 "128-255 byte frames transmitted"); 2651 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511", 2652 CTLFLAG_RD, &adapter->stats.ptc511, 2653 "256-511 byte frames transmitted"); 2654 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023", 2655 CTLFLAG_RD, &adapter->stats.ptc1023, 2656 "512-1023 byte frames transmitted"); 2657 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522", 2658 CTLFLAG_RD, &adapter->stats.ptc1522, 2659 "1024-1522 byte frames transmitted"); 2660 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd", 2661 CTLFLAG_RD, &adapter->stats.tsctc, 2662 "TSO Contexts Transmitted"); 2663 2664 /* Interrupt Stats */ 2665 2666 int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts", 2667 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics"); 2668 int_list = SYSCTL_CHILDREN(int_node); 2669 2670 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts", 2671 CTLFLAG_RD, &adapter->stats.iac, 2672 "Interrupt Assertion Count"); 2673 2674 SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh", 2675 CTLFLAG_RD, &adapter->stats.rxdmtc, 2676 "Rx Desc Min Thresh Count"); 2677 } 2678 2679 /********************************************************************** 2680 * 2681 * This routine provides a way to dump out the adapter eeprom, 2682 * often a useful debug/service tool. This only dumps the first 2683 * 32 words, stuff that matters is in that extent. 2684 * 2685 **********************************************************************/ 2686 static int 2687 igc_sysctl_nvm_info(SYSCTL_HANDLER_ARGS) 2688 { 2689 struct igc_adapter *adapter = (struct igc_adapter *)arg1; 2690 int error; 2691 int result; 2692 2693 result = -1; 2694 error = sysctl_handle_int(oidp, &result, 0, req); 2695 2696 if (error || !req->newptr) 2697 return (error); 2698 2699 /* 2700 * This value will cause a hex dump of the 2701 * first 32 16-bit words of the EEPROM to 2702 * the screen. 2703 */ 2704 if (result == 1) 2705 igc_print_nvm_info(adapter); 2706 2707 return (error); 2708 } 2709 2710 static void 2711 igc_print_nvm_info(struct igc_adapter *adapter) 2712 { 2713 u16 eeprom_data; 2714 int i, j, row = 0; 2715 2716 /* Its a bit crude, but it gets the job done */ 2717 printf("\nInterface EEPROM Dump:\n"); 2718 printf("Offset\n0x0000 "); 2719 for (i = 0, j = 0; i < 32; i++, j++) { 2720 if (j == 8) { /* Make the offset block */ 2721 j = 0; ++row; 2722 printf("\n0x00%x0 ",row); 2723 } 2724 igc_read_nvm(&adapter->hw, i, 1, &eeprom_data); 2725 printf("%04x ", eeprom_data); 2726 } 2727 printf("\n"); 2728 } 2729 2730 static int 2731 igc_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 2732 { 2733 struct igc_int_delay_info *info; 2734 struct igc_adapter *adapter; 2735 u32 regval; 2736 int error, usecs, ticks; 2737 2738 info = (struct igc_int_delay_info *) arg1; 2739 usecs = info->value; 2740 error = sysctl_handle_int(oidp, &usecs, 0, req); 2741 if (error != 0 || req->newptr == NULL) 2742 return (error); 2743 if (usecs < 0 || usecs > IGC_TICKS_TO_USECS(65535)) 2744 return (EINVAL); 2745 info->value = usecs; 2746 ticks = IGC_USECS_TO_TICKS(usecs); 2747 if (info->offset == IGC_ITR) /* units are 256ns here */ 2748 ticks *= 4; 2749 2750 adapter = info->adapter; 2751 2752 regval = IGC_READ_OFFSET(&adapter->hw, info->offset); 2753 regval = (regval & ~0xffff) | (ticks & 0xffff); 2754 /* Handle a few special cases. */ 2755 switch (info->offset) { 2756 case IGC_RDTR: 2757 break; 2758 case IGC_TIDV: 2759 if (ticks == 0) { 2760 adapter->txd_cmd &= ~IGC_TXD_CMD_IDE; 2761 /* Don't write 0 into the TIDV register. */ 2762 regval++; 2763 } else 2764 adapter->txd_cmd |= IGC_TXD_CMD_IDE; 2765 break; 2766 } 2767 IGC_WRITE_OFFSET(&adapter->hw, info->offset, regval); 2768 return (0); 2769 } 2770 2771 static void 2772 igc_add_int_delay_sysctl(struct igc_adapter *adapter, const char *name, 2773 const char *description, struct igc_int_delay_info *info, 2774 int offset, int value) 2775 { 2776 info->adapter = adapter; 2777 info->offset = offset; 2778 info->value = value; 2779 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 2780 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 2781 OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 2782 info, 0, igc_sysctl_int_delay, "I", description); 2783 } 2784 2785 /* 2786 * Set flow control using sysctl: 2787 * Flow control values: 2788 * 0 - off 2789 * 1 - rx pause 2790 * 2 - tx pause 2791 * 3 - full 2792 */ 2793 static int 2794 igc_set_flowcntl(SYSCTL_HANDLER_ARGS) 2795 { 2796 int error; 2797 static int input = 3; /* default is full */ 2798 struct igc_adapter *adapter = (struct igc_adapter *) arg1; 2799 2800 error = sysctl_handle_int(oidp, &input, 0, req); 2801 2802 if ((error) || (req->newptr == NULL)) 2803 return (error); 2804 2805 if (input == adapter->fc) /* no change? */ 2806 return (error); 2807 2808 switch (input) { 2809 case igc_fc_rx_pause: 2810 case igc_fc_tx_pause: 2811 case igc_fc_full: 2812 case igc_fc_none: 2813 adapter->hw.fc.requested_mode = input; 2814 adapter->fc = input; 2815 break; 2816 default: 2817 /* Do nothing */ 2818 return (error); 2819 } 2820 2821 adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode; 2822 igc_force_mac_fc(&adapter->hw); 2823 return (error); 2824 } 2825 2826 /* 2827 * Manage Energy Efficient Ethernet: 2828 * Control values: 2829 * 0/1 - enabled/disabled 2830 */ 2831 static int 2832 igc_sysctl_eee(SYSCTL_HANDLER_ARGS) 2833 { 2834 struct igc_adapter *adapter = (struct igc_adapter *) arg1; 2835 int error, value; 2836 2837 value = adapter->hw.dev_spec._i225.eee_disable; 2838 error = sysctl_handle_int(oidp, &value, 0, req); 2839 if (error || req->newptr == NULL) 2840 return (error); 2841 2842 adapter->hw.dev_spec._i225.eee_disable = (value != 0); 2843 igc_if_init(adapter->ctx); 2844 2845 return (0); 2846 } 2847 2848 static int 2849 igc_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 2850 { 2851 struct igc_adapter *adapter; 2852 int error; 2853 int result; 2854 2855 result = -1; 2856 error = sysctl_handle_int(oidp, &result, 0, req); 2857 2858 if (error || !req->newptr) 2859 return (error); 2860 2861 if (result == 1) { 2862 adapter = (struct igc_adapter *) arg1; 2863 igc_print_debug_info(adapter); 2864 } 2865 2866 return (error); 2867 } 2868 2869 static int 2870 igc_get_rs(SYSCTL_HANDLER_ARGS) 2871 { 2872 struct igc_adapter *adapter = (struct igc_adapter *) arg1; 2873 int error; 2874 int result; 2875 2876 result = 0; 2877 error = sysctl_handle_int(oidp, &result, 0, req); 2878 2879 if (error || !req->newptr || result != 1) 2880 return (error); 2881 igc_dump_rs(adapter); 2882 2883 return (error); 2884 } 2885 2886 static void 2887 igc_if_debug(if_ctx_t ctx) 2888 { 2889 igc_dump_rs(iflib_get_softc(ctx)); 2890 } 2891 2892 /* 2893 * This routine is meant to be fluid, add whatever is 2894 * needed for debugging a problem. -jfv 2895 */ 2896 static void 2897 igc_print_debug_info(struct igc_adapter *adapter) 2898 { 2899 device_t dev = iflib_get_dev(adapter->ctx); 2900 if_t ifp = iflib_get_ifp(adapter->ctx); 2901 struct tx_ring *txr = &adapter->tx_queues->txr; 2902 struct rx_ring *rxr = &adapter->rx_queues->rxr; 2903 2904 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2905 printf("Interface is RUNNING "); 2906 else 2907 printf("Interface is NOT RUNNING\n"); 2908 2909 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) 2910 printf("and INACTIVE\n"); 2911 else 2912 printf("and ACTIVE\n"); 2913 2914 for (int i = 0; i < adapter->tx_num_queues; i++, txr++) { 2915 device_printf(dev, "TX Queue %d ------\n", i); 2916 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 2917 IGC_READ_REG(&adapter->hw, IGC_TDH(i)), 2918 IGC_READ_REG(&adapter->hw, IGC_TDT(i))); 2919 2920 } 2921 for (int j=0; j < adapter->rx_num_queues; j++, rxr++) { 2922 device_printf(dev, "RX Queue %d ------\n", j); 2923 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 2924 IGC_READ_REG(&adapter->hw, IGC_RDH(j)), 2925 IGC_READ_REG(&adapter->hw, IGC_RDT(j))); 2926 } 2927 } 2928