1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2004 Texas A&M University 5 * All rights reserved. 6 * 7 * Developer: Wm. Daryl Hawkins 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Intel ICH Watchdog Timer (WDT) driver 33 * 34 * Originally developed by Wm. Daryl Hawkins of Texas A&M 35 * Heavily modified by <des@FreeBSD.org> 36 * 37 * This is a tricky one. The ICH WDT can't be treated as a regular PCI 38 * device as it's actually an integrated function of the ICH LPC interface 39 * bridge. Detection is also awkward, because we can only infer the 40 * presence of the watchdog timer from the fact that the machine has an 41 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT' 42 * ACPI table (although this driver does not support the ACPI detection 43 * method). 44 * 45 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no 46 * way of knowing if the WDT is permanently disabled (either by the BIOS 47 * or in hardware). 48 * 49 * The WDT is programmed through I/O registers in the ACPI I/O space. 50 * Intel swears it's always at offset 0x60, so we use that. 51 * 52 * For details about the ICH WDT, see Intel Application Note AP-725 53 * (document no. 292273-001). The WDT is also described in the individual 54 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet 55 * (document no. 252516-001) sections 9.10 and 9.11. 56 * 57 * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp> 58 * SoC PMC support by Denir Li <denir.li@cas-well.com> 59 */ 60 61 #include <sys/cdefs.h> 62 __FBSDID("$FreeBSD$"); 63 64 #include <sys/param.h> 65 #include <sys/eventhandler.h> 66 #include <sys/kernel.h> 67 #include <sys/module.h> 68 #include <sys/systm.h> 69 #include <sys/bus.h> 70 #include <machine/bus.h> 71 #include <sys/rman.h> 72 #include <machine/resource.h> 73 #include <sys/watchdog.h> 74 75 #include <isa/isavar.h> 76 #include <dev/pci/pcivar.h> 77 78 #include <dev/ichwd/ichwd.h> 79 80 #include <x86/pci_cfgreg.h> 81 #include <dev/pci/pcivar.h> 82 #include <dev/pci/pci_private.h> 83 84 static struct ichwd_device ichwd_devices[] = { 85 { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1, 1 }, 86 { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1, 1 }, 87 { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2, 1 }, 88 { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2, 1 }, 89 { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3, 1 }, 90 { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3, 1 }, 91 { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4, 1 }, 92 { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4, 1 }, 93 { DEVICEID_82801E, "Intel 82801E watchdog timer", 5, 1 }, 94 { DEVICEID_82801EB, "Intel 82801EB watchdog timer", 5, 1 }, 95 { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5, 1 }, 96 { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5, 1 }, 97 { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6, 2 }, 98 { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6, 2 }, 99 { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6, 2 }, 100 { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7, 2 }, 101 { DEVICEID_ICH7DH, "Intel ICH7DH watchdog timer", 7, 2 }, 102 { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7, 2 }, 103 { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7, 2 }, 104 { DEVICEID_NM10, "Intel NM10 watchdog timer", 7, 2 }, 105 { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8, 2 }, 106 { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8, 2 }, 107 { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8, 2 }, 108 { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8, 2 }, 109 { DEVICEID_ICH8ME, "Intel ICH8M-E watchdog timer", 8, 2 }, 110 { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8, 2 }, 111 { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9, 2 }, 112 { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9, 2 }, 113 { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9, 2 }, 114 { DEVICEID_ICH9M, "Intel ICH9M watchdog timer", 9, 2 }, 115 { DEVICEID_ICH9ME, "Intel ICH9M-E watchdog timer", 9, 2 }, 116 { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9, 2 }, 117 { DEVICEID_ICH10, "Intel ICH10 watchdog timer", 10, 2 }, 118 { DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10, 2 }, 119 { DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10, 2 }, 120 { DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10, 2 }, 121 { DEVICEID_PCH, "Intel PCH watchdog timer", 10, 2 }, 122 { DEVICEID_PCHM, "Intel PCH watchdog timer", 10, 2 }, 123 { DEVICEID_P55, "Intel P55 watchdog timer", 10, 2 }, 124 { DEVICEID_PM55, "Intel PM55 watchdog timer", 10, 2 }, 125 { DEVICEID_H55, "Intel H55 watchdog timer", 10, 2 }, 126 { DEVICEID_QM57, "Intel QM57 watchdog timer", 10, 2 }, 127 { DEVICEID_H57, "Intel H57 watchdog timer", 10, 2 }, 128 { DEVICEID_HM55, "Intel HM55 watchdog timer", 10, 2 }, 129 { DEVICEID_Q57, "Intel Q57 watchdog timer", 10, 2 }, 130 { DEVICEID_HM57, "Intel HM57 watchdog timer", 10, 2 }, 131 { DEVICEID_PCHMSFF, "Intel PCHMSFF watchdog timer", 10, 2 }, 132 { DEVICEID_QS57, "Intel QS57 watchdog timer", 10, 2 }, 133 { DEVICEID_3400, "Intel 3400 watchdog timer", 10, 2 }, 134 { DEVICEID_3420, "Intel 3420 watchdog timer", 10, 2 }, 135 { DEVICEID_3450, "Intel 3450 watchdog timer", 10, 2 }, 136 { DEVICEID_CPT0, "Intel Cougar Point watchdog timer", 10, 2 }, 137 { DEVICEID_CPT1, "Intel Cougar Point watchdog timer", 10, 2 }, 138 { DEVICEID_CPT2, "Intel Cougar Point watchdog timer", 10, 2 }, 139 { DEVICEID_CPT3, "Intel Cougar Point watchdog timer", 10, 2 }, 140 { DEVICEID_CPT4, "Intel Cougar Point watchdog timer", 10, 2 }, 141 { DEVICEID_CPT5, "Intel Cougar Point watchdog timer", 10, 2 }, 142 { DEVICEID_CPT6, "Intel Cougar Point watchdog timer", 10, 2 }, 143 { DEVICEID_CPT7, "Intel Cougar Point watchdog timer", 10, 2 }, 144 { DEVICEID_CPT8, "Intel Cougar Point watchdog timer", 10, 2 }, 145 { DEVICEID_CPT9, "Intel Cougar Point watchdog timer", 10, 2 }, 146 { DEVICEID_CPT10, "Intel Cougar Point watchdog timer", 10, 2 }, 147 { DEVICEID_CPT11, "Intel Cougar Point watchdog timer", 10, 2 }, 148 { DEVICEID_CPT12, "Intel Cougar Point watchdog timer", 10, 2 }, 149 { DEVICEID_CPT13, "Intel Cougar Point watchdog timer", 10, 2 }, 150 { DEVICEID_CPT14, "Intel Cougar Point watchdog timer", 10, 2 }, 151 { DEVICEID_CPT15, "Intel Cougar Point watchdog timer", 10, 2 }, 152 { DEVICEID_CPT16, "Intel Cougar Point watchdog timer", 10, 2 }, 153 { DEVICEID_CPT17, "Intel Cougar Point watchdog timer", 10, 2 }, 154 { DEVICEID_CPT18, "Intel Cougar Point watchdog timer", 10, 2 }, 155 { DEVICEID_CPT19, "Intel Cougar Point watchdog timer", 10, 2 }, 156 { DEVICEID_CPT20, "Intel Cougar Point watchdog timer", 10, 2 }, 157 { DEVICEID_CPT21, "Intel Cougar Point watchdog timer", 10, 2 }, 158 { DEVICEID_CPT22, "Intel Cougar Point watchdog timer", 10, 2 }, 159 { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10, 2 }, 160 { DEVICEID_CPT24, "Intel Cougar Point watchdog timer", 10, 2 }, 161 { DEVICEID_CPT25, "Intel Cougar Point watchdog timer", 10, 2 }, 162 { DEVICEID_CPT26, "Intel Cougar Point watchdog timer", 10, 2 }, 163 { DEVICEID_CPT27, "Intel Cougar Point watchdog timer", 10, 2 }, 164 { DEVICEID_CPT28, "Intel Cougar Point watchdog timer", 10, 2 }, 165 { DEVICEID_CPT29, "Intel Cougar Point watchdog timer", 10, 2 }, 166 { DEVICEID_CPT30, "Intel Cougar Point watchdog timer", 10, 2 }, 167 { DEVICEID_CPT31, "Intel Cougar Point watchdog timer", 10, 2 }, 168 { DEVICEID_PATSBURG_LPC1, "Intel Patsburg watchdog timer", 10, 2 }, 169 { DEVICEID_PATSBURG_LPC2, "Intel Patsburg watchdog timer", 10, 2 }, 170 { DEVICEID_PPT0, "Intel Panther Point watchdog timer", 10, 2 }, 171 { DEVICEID_PPT1, "Intel Panther Point watchdog timer", 10, 2 }, 172 { DEVICEID_PPT2, "Intel Panther Point watchdog timer", 10, 2 }, 173 { DEVICEID_PPT3, "Intel Panther Point watchdog timer", 10, 2 }, 174 { DEVICEID_PPT4, "Intel Panther Point watchdog timer", 10, 2 }, 175 { DEVICEID_PPT5, "Intel Panther Point watchdog timer", 10, 2 }, 176 { DEVICEID_PPT6, "Intel Panther Point watchdog timer", 10, 2 }, 177 { DEVICEID_PPT7, "Intel Panther Point watchdog timer", 10, 2 }, 178 { DEVICEID_PPT8, "Intel Panther Point watchdog timer", 10, 2 }, 179 { DEVICEID_PPT9, "Intel Panther Point watchdog timer", 10, 2 }, 180 { DEVICEID_PPT10, "Intel Panther Point watchdog timer", 10, 2 }, 181 { DEVICEID_PPT11, "Intel Panther Point watchdog timer", 10, 2 }, 182 { DEVICEID_PPT12, "Intel Panther Point watchdog timer", 10, 2 }, 183 { DEVICEID_PPT13, "Intel Panther Point watchdog timer", 10, 2 }, 184 { DEVICEID_PPT14, "Intel Panther Point watchdog timer", 10, 2 }, 185 { DEVICEID_PPT15, "Intel Panther Point watchdog timer", 10, 2 }, 186 { DEVICEID_PPT16, "Intel Panther Point watchdog timer", 10, 2 }, 187 { DEVICEID_PPT17, "Intel Panther Point watchdog timer", 10, 2 }, 188 { DEVICEID_PPT18, "Intel Panther Point watchdog timer", 10, 2 }, 189 { DEVICEID_PPT19, "Intel Panther Point watchdog timer", 10, 2 }, 190 { DEVICEID_PPT20, "Intel Panther Point watchdog timer", 10, 2 }, 191 { DEVICEID_PPT21, "Intel Panther Point watchdog timer", 10, 2 }, 192 { DEVICEID_PPT22, "Intel Panther Point watchdog timer", 10, 2 }, 193 { DEVICEID_PPT23, "Intel Panther Point watchdog timer", 10, 2 }, 194 { DEVICEID_PPT24, "Intel Panther Point watchdog timer", 10, 2 }, 195 { DEVICEID_PPT25, "Intel Panther Point watchdog timer", 10, 2 }, 196 { DEVICEID_PPT26, "Intel Panther Point watchdog timer", 10, 2 }, 197 { DEVICEID_PPT27, "Intel Panther Point watchdog timer", 10, 2 }, 198 { DEVICEID_PPT28, "Intel Panther Point watchdog timer", 10, 2 }, 199 { DEVICEID_PPT29, "Intel Panther Point watchdog timer", 10, 2 }, 200 { DEVICEID_PPT30, "Intel Panther Point watchdog timer", 10, 2 }, 201 { DEVICEID_PPT31, "Intel Panther Point watchdog timer", 10, 2 }, 202 { DEVICEID_LPT0, "Intel Lynx Point watchdog timer", 10, 2 }, 203 { DEVICEID_LPT1, "Intel Lynx Point watchdog timer", 10, 2 }, 204 { DEVICEID_LPT2, "Intel Lynx Point watchdog timer", 10, 2 }, 205 { DEVICEID_LPT3, "Intel Lynx Point watchdog timer", 10, 2 }, 206 { DEVICEID_LPT4, "Intel Lynx Point watchdog timer", 10, 2 }, 207 { DEVICEID_LPT5, "Intel Lynx Point watchdog timer", 10, 2 }, 208 { DEVICEID_LPT6, "Intel Lynx Point watchdog timer", 10, 2 }, 209 { DEVICEID_LPT7, "Intel Lynx Point watchdog timer", 10, 2 }, 210 { DEVICEID_LPT8, "Intel Lynx Point watchdog timer", 10, 2 }, 211 { DEVICEID_LPT9, "Intel Lynx Point watchdog timer", 10, 2 }, 212 { DEVICEID_LPT10, "Intel Lynx Point watchdog timer", 10, 2 }, 213 { DEVICEID_LPT11, "Intel Lynx Point watchdog timer", 10, 2 }, 214 { DEVICEID_LPT12, "Intel Lynx Point watchdog timer", 10, 2 }, 215 { DEVICEID_LPT13, "Intel Lynx Point watchdog timer", 10, 2 }, 216 { DEVICEID_LPT14, "Intel Lynx Point watchdog timer", 10, 2 }, 217 { DEVICEID_LPT15, "Intel Lynx Point watchdog timer", 10, 2 }, 218 { DEVICEID_LPT16, "Intel Lynx Point watchdog timer", 10, 2 }, 219 { DEVICEID_LPT17, "Intel Lynx Point watchdog timer", 10, 2 }, 220 { DEVICEID_LPT18, "Intel Lynx Point watchdog timer", 10, 2 }, 221 { DEVICEID_LPT19, "Intel Lynx Point watchdog timer", 10, 2 }, 222 { DEVICEID_LPT20, "Intel Lynx Point watchdog timer", 10, 2 }, 223 { DEVICEID_LPT21, "Intel Lynx Point watchdog timer", 10, 2 }, 224 { DEVICEID_LPT22, "Intel Lynx Point watchdog timer", 10, 2 }, 225 { DEVICEID_LPT23, "Intel Lynx Point watchdog timer", 10, 2 }, 226 { DEVICEID_LPT24, "Intel Lynx Point watchdog timer", 10, 2 }, 227 { DEVICEID_LPT25, "Intel Lynx Point watchdog timer", 10, 2 }, 228 { DEVICEID_LPT26, "Intel Lynx Point watchdog timer", 10, 2 }, 229 { DEVICEID_LPT27, "Intel Lynx Point watchdog timer", 10, 2 }, 230 { DEVICEID_LPT28, "Intel Lynx Point watchdog timer", 10, 2 }, 231 { DEVICEID_LPT29, "Intel Lynx Point watchdog timer", 10, 2 }, 232 { DEVICEID_LPT30, "Intel Lynx Point watchdog timer", 10, 2 }, 233 { DEVICEID_LPT31, "Intel Lynx Point watchdog timer", 10, 2 }, 234 { DEVICEID_WCPT1, "Intel Wildcat Point watchdog timer", 10, 2 }, 235 { DEVICEID_WCPT2, "Intel Wildcat Point watchdog timer", 10, 2 }, 236 { DEVICEID_WCPT3, "Intel Wildcat Point watchdog timer", 10, 2 }, 237 { DEVICEID_WCPT4, "Intel Wildcat Point watchdog timer", 10, 2 }, 238 { DEVICEID_WCPT6, "Intel Wildcat Point watchdog timer", 10, 2 }, 239 { DEVICEID_WBG0, "Intel Wellsburg watchdog timer", 10, 2 }, 240 { DEVICEID_WBG1, "Intel Wellsburg watchdog timer", 10, 2 }, 241 { DEVICEID_WBG2, "Intel Wellsburg watchdog timer", 10, 2 }, 242 { DEVICEID_WBG3, "Intel Wellsburg watchdog timer", 10, 2 }, 243 { DEVICEID_WBG4, "Intel Wellsburg watchdog timer", 10, 2 }, 244 { DEVICEID_WBG5, "Intel Wellsburg watchdog timer", 10, 2 }, 245 { DEVICEID_WBG6, "Intel Wellsburg watchdog timer", 10, 2 }, 246 { DEVICEID_WBG7, "Intel Wellsburg watchdog timer", 10, 2 }, 247 { DEVICEID_WBG8, "Intel Wellsburg watchdog timer", 10, 2 }, 248 { DEVICEID_WBG9, "Intel Wellsburg watchdog timer", 10, 2 }, 249 { DEVICEID_WBG10, "Intel Wellsburg watchdog timer", 10, 2 }, 250 { DEVICEID_WBG11, "Intel Wellsburg watchdog timer", 10, 2 }, 251 { DEVICEID_WBG12, "Intel Wellsburg watchdog timer", 10, 2 }, 252 { DEVICEID_WBG13, "Intel Wellsburg watchdog timer", 10, 2 }, 253 { DEVICEID_WBG14, "Intel Wellsburg watchdog timer", 10, 2 }, 254 { DEVICEID_WBG15, "Intel Wellsburg watchdog timer", 10, 2 }, 255 { DEVICEID_WBG16, "Intel Wellsburg watchdog timer", 10, 2 }, 256 { DEVICEID_WBG17, "Intel Wellsburg watchdog timer", 10, 2 }, 257 { DEVICEID_WBG18, "Intel Wellsburg watchdog timer", 10, 2 }, 258 { DEVICEID_WBG19, "Intel Wellsburg watchdog timer", 10, 2 }, 259 { DEVICEID_WBG20, "Intel Wellsburg watchdog timer", 10, 2 }, 260 { DEVICEID_WBG21, "Intel Wellsburg watchdog timer", 10, 2 }, 261 { DEVICEID_WBG22, "Intel Wellsburg watchdog timer", 10, 2 }, 262 { DEVICEID_WBG23, "Intel Wellsburg watchdog timer", 10, 2 }, 263 { DEVICEID_WBG24, "Intel Wellsburg watchdog timer", 10, 2 }, 264 { DEVICEID_WBG25, "Intel Wellsburg watchdog timer", 10, 2 }, 265 { DEVICEID_WBG26, "Intel Wellsburg watchdog timer", 10, 2 }, 266 { DEVICEID_WBG27, "Intel Wellsburg watchdog timer", 10, 2 }, 267 { DEVICEID_WBG28, "Intel Wellsburg watchdog timer", 10, 2 }, 268 { DEVICEID_WBG29, "Intel Wellsburg watchdog timer", 10, 2 }, 269 { DEVICEID_WBG30, "Intel Wellsburg watchdog timer", 10, 2 }, 270 { DEVICEID_WBG31, "Intel Wellsburg watchdog timer", 10, 2 }, 271 { DEVICEID_LPT_LP0, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 272 { DEVICEID_LPT_LP1, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 273 { DEVICEID_LPT_LP2, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 274 { DEVICEID_LPT_LP3, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 275 { DEVICEID_LPT_LP4, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 276 { DEVICEID_LPT_LP5, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 277 { DEVICEID_LPT_LP6, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 278 { DEVICEID_LPT_LP7, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 279 { DEVICEID_WCPT_LP1, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 280 { DEVICEID_WCPT_LP2, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 281 { DEVICEID_WCPT_LP3, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 282 { DEVICEID_WCPT_LP5, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 283 { DEVICEID_WCPT_LP6, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 284 { DEVICEID_WCPT_LP7, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 285 { DEVICEID_WCPT_LP9, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 286 { DEVICEID_DH89XXCC_LPC, "Intel DH89xxCC watchdog timer", 10, 2 }, 287 { DEVICEID_COLETOCRK_LPC, "Intel Coleto Creek watchdog timer", 10, 2 }, 288 { DEVICEID_AVN0, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 289 { DEVICEID_AVN1, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 290 { DEVICEID_AVN2, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 291 { DEVICEID_AVN3, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 292 { DEVICEID_BAYTRAIL, "Intel Bay Trail SoC watchdog timer", 10, 3 }, 293 { DEVICEID_BRASWELL, "Intel Braswell SoC watchdog timer", 10, 3 }, 294 { 0, NULL, 0, 0 }, 295 }; 296 297 static struct ichwd_device ichwd_smb_devices[] = { 298 { DEVICEID_LEWISBURG_SMB, "Lewisburg watchdog timer", 10, 4 }, 299 { DEVICEID_LEWISBURG_SMB_SSKU, "Lewisburg watchdog timer", 10, 4 }, 300 { DEVICEID_CANNON_SMB, "Cannon Lake watchdog timer", 10, 4, PMC_HIDDEN}, 301 { DEVICEID_COMET_SMB, "Comet Lake watchdog timer", 10, 4, PMC_HIDDEN}, 302 { DEVICEID_SRPTLP_SMB, "Sunrise Point-LP watchdog timer", 10, 4 }, 303 { DEVICEID_C3000, "Intel Atom C3000 watchdog timer", 10, 4 }, 304 { 0, NULL, 0, 0 }, 305 }; 306 307 static devclass_t ichwd_devclass; 308 309 #define ichwd_read_tco_1(sc, off) \ 310 bus_read_1((sc)->tco_res, (off)) 311 #define ichwd_read_tco_2(sc, off) \ 312 bus_read_2((sc)->tco_res, (off)) 313 #define ichwd_read_tco_4(sc, off) \ 314 bus_read_4((sc)->tco_res, (off)) 315 #define ichwd_read_smi_4(sc, off) \ 316 bus_read_4((sc)->smi_res, (off)) 317 #define ichwd_read_gcs_4(sc, off) \ 318 bus_read_4((sc)->gcs_res, (off)) 319 /* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */ 320 #define ichwd_read_pmc_4(sc, off) \ 321 bus_read_4((sc)->gcs_res, (off)) 322 #define ichwd_read_gc_4(sc, off) \ 323 bus_read_4((sc)->gc_res, (off)) 324 325 #define ichwd_write_tco_1(sc, off, val) \ 326 bus_write_1((sc)->tco_res, (off), (val)) 327 #define ichwd_write_tco_2(sc, off, val) \ 328 bus_write_2((sc)->tco_res, (off), (val)) 329 #define ichwd_write_tco_4(sc, off, val) \ 330 bus_write_4((sc)->tco_res, (off), (val)) 331 #define ichwd_write_smi_4(sc, off, val) \ 332 bus_write_4((sc)->smi_res, (off), (val)) 333 #define ichwd_write_gcs_4(sc, off, val) \ 334 bus_write_4((sc)->gcs_res, (off), (val)) 335 /* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */ 336 #define ichwd_write_pmc_4(sc, off, val) \ 337 bus_write_4((sc)->gcs_res, (off), (val)) 338 #define ichwd_write_gc_4(sc, off, val) \ 339 bus_write_4((sc)->gc_res, (off), (val)) 340 341 #define ichwd_verbose_printf(dev, ...) \ 342 do { \ 343 if (bootverbose) \ 344 device_printf(dev, __VA_ARGS__);\ 345 } while (0) 346 347 /* 348 * Disable the watchdog timeout SMI handler. 349 * 350 * Apparently, some BIOSes install handlers that reset or disable the 351 * watchdog timer instead of resetting the system, so we disable the SMI 352 * (by clearing the SMI_TCO_EN bit of the SMI_EN register) to prevent this 353 * from happening. 354 */ 355 static __inline void 356 ichwd_smi_disable(struct ichwd_softc *sc) 357 { 358 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN); 359 } 360 361 /* 362 * Enable the watchdog timeout SMI handler. See above for details. 363 */ 364 static __inline void 365 ichwd_smi_enable(struct ichwd_softc *sc) 366 { 367 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN); 368 } 369 370 /* 371 * Check if the watchdog SMI triggering is enabled. 372 */ 373 static __inline int 374 ichwd_smi_is_enabled(struct ichwd_softc *sc) 375 { 376 return ((ichwd_read_smi_4(sc, SMI_EN) & SMI_TCO_EN) != 0); 377 } 378 379 /* 380 * Reset the watchdog status bits. 381 */ 382 static __inline void 383 ichwd_sts_reset(struct ichwd_softc *sc) 384 { 385 /* 386 * The watchdog status bits are set to 1 by the hardware to 387 * indicate various conditions. They can be cleared by software 388 * by writing a 1, not a 0. 389 */ 390 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT); 391 /* 392 * According to Intel's docs, clearing SECOND_TO_STS and BOOT_STS must 393 * be done in two separate operations. 394 */ 395 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS); 396 if (sc->tco_version < 4) 397 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS); 398 } 399 400 /* 401 * Enable the watchdog timer by clearing the TCO_TMR_HALT bit in the 402 * TCO1_CNT register. This is complicated by the need to preserve bit 9 403 * of that same register, and the requirement that all other bits must be 404 * written back as zero. 405 */ 406 static __inline void 407 ichwd_tmr_enable(struct ichwd_softc *sc) 408 { 409 uint16_t cnt; 410 411 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 412 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT); 413 sc->active = 1; 414 ichwd_verbose_printf(sc->device, "timer enabled\n"); 415 } 416 417 /* 418 * Disable the watchdog timer. See above for details. 419 */ 420 static __inline void 421 ichwd_tmr_disable(struct ichwd_softc *sc) 422 { 423 uint16_t cnt; 424 425 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 426 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT); 427 sc->active = 0; 428 ichwd_verbose_printf(sc->device, "timer disabled\n"); 429 } 430 431 /* 432 * Reload the watchdog timer: writing anything to any of the lower five 433 * bits of the TCO_RLD register reloads the timer from the last value 434 * written to TCO_TMR. 435 */ 436 static __inline void 437 ichwd_tmr_reload(struct ichwd_softc *sc) 438 { 439 if (sc->tco_version == 1) 440 ichwd_write_tco_1(sc, TCO_RLD, 1); 441 else 442 ichwd_write_tco_2(sc, TCO_RLD, 1); 443 } 444 445 /* 446 * Set the initial timeout value. Note that this must always be followed 447 * by a reload. 448 */ 449 static __inline void 450 ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout) 451 { 452 453 if (timeout < TCO_RLD_TMR_MIN) 454 timeout = TCO_RLD_TMR_MIN; 455 456 if (sc->tco_version == 1) { 457 uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1); 458 459 tmr_val8 &= (~TCO_RLD1_TMR_MAX & 0xff); 460 if (timeout > TCO_RLD1_TMR_MAX) 461 timeout = TCO_RLD1_TMR_MAX; 462 tmr_val8 |= timeout; 463 ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8); 464 } else { 465 uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2); 466 467 tmr_val16 &= (~TCO_RLD2_TMR_MAX & 0xffff); 468 if (timeout > TCO_RLD2_TMR_MAX) 469 timeout = TCO_RLD2_TMR_MAX; 470 tmr_val16 |= timeout; 471 ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16); 472 } 473 474 sc->timeout = timeout; 475 476 ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout); 477 } 478 479 static __inline int 480 ichwd_clear_noreboot(struct ichwd_softc *sc) 481 { 482 uint32_t status; 483 int rc = 0; 484 485 /* try to clear the NO_REBOOT bit */ 486 switch (sc->tco_version) { 487 case 1: 488 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 489 status &= ~ICH_GEN_STA_NO_REBOOT; 490 pci_write_config(sc->ich, ICH_GEN_STA, status, 1); 491 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 492 if (status & ICH_GEN_STA_NO_REBOOT) 493 rc = EIO; 494 break; 495 case 2: 496 status = ichwd_read_gcs_4(sc, 0); 497 status &= ~ICH_GCS_NO_REBOOT; 498 ichwd_write_gcs_4(sc, 0, status); 499 status = ichwd_read_gcs_4(sc, 0); 500 if (status & ICH_GCS_NO_REBOOT) 501 rc = EIO; 502 break; 503 case 3: 504 status = ichwd_read_pmc_4(sc, 0); 505 status &= ~ICH_PMC_NO_REBOOT; 506 ichwd_write_pmc_4(sc, 0, status); 507 status = ichwd_read_pmc_4(sc, 0); 508 if (status & ICH_PMC_NO_REBOOT) 509 rc = EIO; 510 break; 511 case 4: 512 status = ichwd_read_gc_4(sc, 0); 513 status &= ~SMB_GC_NO_REBOOT; 514 ichwd_write_gc_4(sc, 0, status); 515 status = ichwd_read_gc_4(sc, 0); 516 if (status & SMB_GC_NO_REBOOT) 517 rc = EIO; 518 break; 519 default: 520 ichwd_verbose_printf(sc->device, 521 "Unknown TCO Version: %d, can't set NO_REBOOT.\n", 522 sc->tco_version); 523 break; 524 } 525 526 if (rc) 527 device_printf(sc->device, 528 "ICH WDT present but disabled in BIOS or hardware\n"); 529 530 return (rc); 531 } 532 533 /* 534 * Watchdog event handler - called by the framework to enable or disable 535 * the watchdog or change the initial timeout value. 536 */ 537 static void 538 ichwd_event(void *arg, unsigned int cmd, int *error) 539 { 540 struct ichwd_softc *sc = arg; 541 unsigned int timeout; 542 543 /* convert from power-of-two-ns to WDT ticks */ 544 cmd &= WD_INTERVAL; 545 546 if (sc->tco_version == 3) { 547 timeout = ((uint64_t)1 << cmd) / ICHWD_TCO_V3_TICK; 548 } else { 549 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK; 550 } 551 552 if (cmd) { 553 if (!sc->active) 554 ichwd_tmr_enable(sc); 555 if (timeout != sc->timeout) 556 ichwd_tmr_set(sc, timeout); 557 ichwd_tmr_reload(sc); 558 *error = 0; 559 } else { 560 if (sc->active) 561 ichwd_tmr_disable(sc); 562 } 563 } 564 565 static device_t 566 ichwd_find_ich_lpc_bridge(device_t isa, struct ichwd_device **id_p) 567 { 568 struct ichwd_device *id; 569 device_t isab, pci; 570 uint16_t devid; 571 572 /* Check whether parent ISA bridge looks familiar. */ 573 isab = device_get_parent(isa); 574 pci = device_get_parent(isab); 575 if (pci == NULL || device_get_devclass(pci) != devclass_find("pci")) 576 return (NULL); 577 if (pci_get_vendor(isab) != VENDORID_INTEL) 578 return (NULL); 579 devid = pci_get_device(isab); 580 for (id = ichwd_devices; id->desc != NULL; ++id) { 581 if (devid == id->device) { 582 if (id_p != NULL) 583 *id_p = id; 584 return (isab); 585 } 586 } 587 588 return (NULL); 589 } 590 591 static device_t 592 ichwd_find_smb_dev(device_t isa, struct ichwd_device **id_p) 593 { 594 struct ichwd_device *id; 595 device_t isab, smb; 596 uint16_t devid; 597 598 /* 599 * Check if SMBus controller provides TCO configuration. 600 * The controller's device and function are fixed and we expect 601 * it to be on the same bus as ISA bridge. 602 */ 603 isab = device_get_parent(isa); 604 smb = pci_find_dbsf(pci_get_domain(isab), pci_get_bus(isab), 31, 4); 605 if (smb == NULL) 606 return (NULL); 607 if (pci_get_vendor(smb) != VENDORID_INTEL) 608 return (NULL); 609 devid = pci_get_device(smb); 610 for (id = ichwd_smb_devices; id->desc != NULL; ++id) { 611 if (devid == id->device) { 612 if (id_p != NULL) 613 *id_p = id; 614 return (smb); 615 } 616 } 617 618 return (NULL); 619 } 620 621 /* 622 * Look for an ICH LPC interface bridge. If one is found, register an 623 * ichwd device. There can be only one. 624 */ 625 static void 626 ichwd_identify(driver_t *driver, device_t parent) 627 { 628 struct ichwd_device *id_p; 629 device_t ich, smb; 630 device_t dev; 631 uint64_t base_address64; 632 uint32_t base_address; 633 uint32_t ctl; 634 int rc; 635 636 ich = ichwd_find_ich_lpc_bridge(parent, &id_p); 637 if (ich == NULL) { 638 smb = ichwd_find_smb_dev(parent, &id_p); 639 if (smb == NULL) 640 return; 641 } 642 643 KASSERT(id_p->tco_version >= 1, 644 ("unexpected TCO version %d", id_p->tco_version)); 645 KASSERT(id_p->tco_version != 4 || smb != NULL, 646 ("could not find PCI SMBus device for TCOv4")); 647 KASSERT(id_p->tco_version >= 4 || ich != NULL, 648 ("could not find PCI LPC bridge device for TCOv1-3")); 649 650 /* good, add child to bus */ 651 if ((dev = device_find_child(parent, driver->name, 0)) == NULL) 652 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0); 653 654 if (dev == NULL) 655 return; 656 657 switch (id_p->tco_version) { 658 case 1: 659 break; 660 case 2: 661 /* get RCBA (root complex base address) */ 662 base_address = pci_read_config(ich, ICH_RCBA, 4); 663 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 664 (base_address & 0xffffc000) + ICH_GCS_OFFSET, 665 ICH_GCS_SIZE); 666 if (rc) 667 ichwd_verbose_printf(dev, 668 "Can not set TCO v%d memory resource for RCBA\n", 669 id_p->tco_version); 670 break; 671 case 3: 672 /* get PBASE (Power Management Controller base address) */ 673 base_address = pci_read_config(ich, ICH_PBASE, 4); 674 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 675 (base_address & 0xfffffe00) + ICH_PMC_OFFSET, 676 ICH_PMC_SIZE); 677 if (rc) 678 ichwd_verbose_printf(dev, 679 "Can not set TCO v%d memory resource for PBASE\n", 680 id_p->tco_version); 681 break; 682 case 4: 683 /* Get TCO base address. */ 684 ctl = pci_read_config(smb, ICH_TCOCTL, 4); 685 if ((ctl & ICH_TCOCTL_TCO_BASE_EN) == 0) { 686 ichwd_verbose_printf(dev, 687 "TCO v%d decoding is not enabled\n", 688 id_p->tco_version); 689 break; 690 } 691 base_address = pci_read_config(smb, ICH_TCOBASE, 4); 692 rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, 693 base_address & ICH_TCOBASE_ADDRMASK, ICH_TCOBASE_SIZE); 694 if (rc != 0) { 695 ichwd_verbose_printf(dev, 696 "Can not set TCO v%d I/O resource (err = %d)\n", 697 id_p->tco_version, rc); 698 } 699 700 /* 701 * Unhide Primary to Sideband Bridge (P2SB) PCI device, so that 702 * we can discover the base address of Private Configuration 703 * Space via the bridge's BAR. 704 * Then hide back the bridge. 705 */ 706 pci_cfgregwrite(0, 31, 1, 0xe1, 0, 1); 707 base_address64 = pci_cfgregread(0, 31, 1, SBREG_BAR + 4, 4); 708 base_address64 <<= 32; 709 base_address64 |= pci_cfgregread(0, 31, 1, SBREG_BAR, 4); 710 base_address64 &= ~0xfull; 711 pci_cfgregwrite(0, 31, 1, 0xe1, 1, 1); 712 713 /* 714 * No Reboot bit is in General Control register, offset 0xc, 715 * within the SMBus target port, ID 0xc6. 716 */ 717 base_address64 += PCR_REG_OFF(SMB_PORT_ID, SMB_GC_REG); 718 rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, base_address64, 719 SMB_GC_SIZE); 720 if (rc != 0) { 721 ichwd_verbose_printf(dev, 722 "Can not set TCO v%d PCR I/O resource (err = %d)\n", 723 id_p->tco_version, rc); 724 } 725 726 break; 727 default: 728 ichwd_verbose_printf(dev, 729 "Can not set unknown TCO v%d memory resource for unknown base address\n", 730 id_p->tco_version); 731 break; 732 } 733 } 734 735 static int 736 ichwd_probe(device_t dev) 737 { 738 struct ichwd_device *id_p; 739 740 /* Do not claim some ISA PnP device by accident. */ 741 if (isa_get_logicalid(dev) != 0) 742 return (ENXIO); 743 744 if (ichwd_find_ich_lpc_bridge(device_get_parent(dev), &id_p) == NULL && 745 ichwd_find_smb_dev(device_get_parent(dev), &id_p) == NULL) 746 return (ENXIO); 747 748 device_set_desc_copy(dev, id_p->desc); 749 return (0); 750 } 751 752 static int 753 ichwd_smb_attach(device_t dev) 754 { 755 struct ichwd_softc *sc; 756 struct ichwd_device *id_p; 757 device_t isab, pmdev; 758 device_t smb; 759 uint32_t acpi_base; 760 761 sc = device_get_softc(dev); 762 smb = ichwd_find_smb_dev(device_get_parent(dev), &id_p); 763 if (smb == NULL) 764 return (ENXIO); 765 766 sc->ich_version = id_p->ich_version; 767 sc->tco_version = id_p->tco_version; 768 769 /* Allocate TCO control I/O register space. */ 770 sc->tco_rid = 0; 771 sc->tco_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->tco_rid, 772 RF_ACTIVE | RF_SHAREABLE); 773 if (sc->tco_res == NULL) { 774 device_printf(dev, "unable to reserve TCO registers\n"); 775 return (ENXIO); 776 } 777 778 /* 779 * Allocate General Control I/O register in PCH 780 * Private Configuration Space (PCR). 781 */ 782 sc->gc_rid = 1; 783 sc->gc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->gc_rid, 784 RF_ACTIVE | RF_SHAREABLE); 785 if (sc->gc_res == NULL) { 786 device_printf(dev, "unable to reserve hidden P2SB registers\n"); 787 return (ENXIO); 788 } 789 790 /* Get ACPI base address. */ 791 isab = device_get_parent(device_get_parent(dev)); 792 pmdev = pci_find_dbsf(pci_get_domain(isab), pci_get_bus(isab), 31, 2); 793 if (pmdev == NULL) { 794 if (id_p->quirks & PMC_HIDDEN) { 795 /* 796 * Since the PMC is hidden, we take the default value for the 797 * given device, which happens to be the same for the ones we 798 * support. 799 */ 800 acpi_base = ACPI_DEFAULT_CANNON; 801 } else { 802 device_printf(dev, "unable to find Power Management device\n"); 803 return (ENXIO); 804 } 805 } else { 806 acpi_base = pci_read_config(pmdev, ICH_PMBASE, 4) & 0xffffff00; 807 if (acpi_base == 0) { 808 device_printf(dev, "ACPI base address is not set\n"); 809 return (ENXIO); 810 } 811 } 812 813 /* Allocate SMI control I/O register space. */ 814 sc->smi_rid = 2; 815 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 816 acpi_base + SMI_BASE, acpi_base + SMI_BASE + SMI_LEN - 1, SMI_LEN, 817 RF_ACTIVE | RF_SHAREABLE); 818 if (sc->smi_res == NULL) { 819 device_printf(dev, "unable to reserve SMI registers\n"); 820 return (ENXIO); 821 } 822 823 return (0); 824 } 825 826 static int 827 ichwd_lpc_attach(device_t dev) 828 { 829 struct ichwd_softc *sc; 830 struct ichwd_device *id_p; 831 device_t ich; 832 unsigned int pmbase = 0; 833 834 sc = device_get_softc(dev); 835 836 ich = ichwd_find_ich_lpc_bridge(device_get_parent(dev), &id_p); 837 if (ich == NULL) 838 return (ENXIO); 839 840 sc->ich = ich; 841 sc->ich_version = id_p->ich_version; 842 sc->tco_version = id_p->tco_version; 843 844 /* get ACPI base address */ 845 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK; 846 if (pmbase == 0) { 847 device_printf(dev, "ICH PMBASE register is empty\n"); 848 return (ENXIO); 849 } 850 851 /* allocate I/O register space */ 852 sc->smi_rid = 0; 853 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 854 pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN, 855 RF_ACTIVE | RF_SHAREABLE); 856 if (sc->smi_res == NULL) { 857 device_printf(dev, "unable to reserve SMI registers\n"); 858 return (ENXIO); 859 } 860 861 sc->tco_rid = 1; 862 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid, 863 pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN, 864 RF_ACTIVE | RF_SHAREABLE); 865 if (sc->tco_res == NULL) { 866 device_printf(dev, "unable to reserve TCO registers\n"); 867 return (ENXIO); 868 } 869 870 sc->gcs_rid = 0; 871 if (sc->tco_version >= 2) { 872 sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY, 873 &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE); 874 if (sc->gcs_res == NULL) { 875 device_printf(dev, "unable to reserve GCS registers\n"); 876 return (ENXIO); 877 } 878 } 879 880 return (0); 881 } 882 883 static int 884 ichwd_attach(device_t dev) 885 { 886 struct ichwd_softc *sc; 887 888 sc = device_get_softc(dev); 889 sc->device = dev; 890 891 if (ichwd_lpc_attach(dev) != 0 && ichwd_smb_attach(dev) != 0) 892 goto fail; 893 894 if (ichwd_clear_noreboot(sc) != 0) 895 goto fail; 896 897 /* 898 * Determine if we are coming up after a watchdog-induced reset. Some 899 * BIOSes may clear this bit at bootup, preventing us from reporting 900 * this case on such systems. We clear this bit in ichwd_sts_reset(). 901 */ 902 if ((ichwd_read_tco_2(sc, TCO2_STS) & TCO_SECOND_TO_STS) != 0) 903 device_printf(dev, 904 "resuming after hardware watchdog timeout\n"); 905 906 /* reset the watchdog status registers */ 907 ichwd_sts_reset(sc); 908 909 /* make sure the WDT starts out inactive */ 910 ichwd_tmr_disable(sc); 911 912 /* register the watchdog event handler */ 913 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0); 914 915 /* disable the SMI handler */ 916 sc->smi_enabled = ichwd_smi_is_enabled(sc); 917 ichwd_smi_disable(sc); 918 919 return (0); 920 fail: 921 sc = device_get_softc(dev); 922 if (sc->tco_res != NULL) 923 bus_release_resource(dev, SYS_RES_IOPORT, 924 sc->tco_rid, sc->tco_res); 925 if (sc->smi_res != NULL) 926 bus_release_resource(dev, SYS_RES_IOPORT, 927 sc->smi_rid, sc->smi_res); 928 if (sc->gcs_res != NULL) 929 bus_release_resource(sc->ich, SYS_RES_MEMORY, 930 sc->gcs_rid, sc->gcs_res); 931 if (sc->gc_res != NULL) 932 bus_release_resource(dev, SYS_RES_MEMORY, 933 sc->gc_rid, sc->gc_res); 934 935 return (ENXIO); 936 } 937 938 static int 939 ichwd_detach(device_t dev) 940 { 941 struct ichwd_softc *sc; 942 943 sc = device_get_softc(dev); 944 945 /* halt the watchdog timer */ 946 if (sc->active) 947 ichwd_tmr_disable(sc); 948 949 /* enable the SMI handler */ 950 if (sc->smi_enabled != 0) 951 ichwd_smi_enable(sc); 952 953 /* deregister event handler */ 954 if (sc->ev_tag != NULL) 955 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 956 sc->ev_tag = NULL; 957 958 /* reset the watchdog status registers */ 959 ichwd_sts_reset(sc); 960 961 /* deallocate I/O register space */ 962 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res); 963 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res); 964 965 /* deallocate memory resource */ 966 if (sc->gcs_res) 967 bus_release_resource(sc->ich, SYS_RES_MEMORY, sc->gcs_rid, 968 sc->gcs_res); 969 if (sc->gc_res) 970 bus_release_resource(dev, SYS_RES_MEMORY, sc->gc_rid, 971 sc->gc_res); 972 973 return (0); 974 } 975 976 static device_method_t ichwd_methods[] = { 977 DEVMETHOD(device_identify, ichwd_identify), 978 DEVMETHOD(device_probe, ichwd_probe), 979 DEVMETHOD(device_attach, ichwd_attach), 980 DEVMETHOD(device_detach, ichwd_detach), 981 DEVMETHOD(device_shutdown, ichwd_detach), 982 {0,0} 983 }; 984 985 static driver_t ichwd_driver = { 986 "ichwd", 987 ichwd_methods, 988 sizeof(struct ichwd_softc), 989 }; 990 991 DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, NULL, NULL); 992