1 /*- 2 * Copyright (c) 2004 Texas A&M University 3 * All rights reserved. 4 * 5 * Developer: Wm. Daryl Hawkins 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Intel ICH Watchdog Timer (WDT) driver 31 * 32 * Originally developed by Wm. Daryl Hawkins of Texas A&M 33 * Heavily modified by <des@FreeBSD.org> 34 * 35 * This is a tricky one. The ICH WDT can't be treated as a regular PCI 36 * device as it's actually an integrated function of the ICH LPC interface 37 * bridge. Detection is also awkward, because we can only infer the 38 * presence of the watchdog timer from the fact that the machine has an 39 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT' 40 * ACPI table (although this driver does not support the ACPI detection 41 * method). 42 * 43 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no 44 * way of knowing if the WDT is permanently disabled (either by the BIOS 45 * or in hardware). 46 * 47 * The WDT is programmed through I/O registers in the ACPI I/O space. 48 * Intel swears it's always at offset 0x60, so we use that. 49 * 50 * For details about the ICH WDT, see Intel Application Note AP-725 51 * (document no. 292273-001). The WDT is also described in the individual 52 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet 53 * (document no. 252516-001) sections 9.10 and 9.11. 54 */ 55 56 #include <sys/cdefs.h> 57 __FBSDID("$FreeBSD$"); 58 59 #include <sys/param.h> 60 #include <sys/kernel.h> 61 #include <sys/module.h> 62 #include <sys/systm.h> 63 #include <sys/bus.h> 64 #include <machine/bus.h> 65 #include <sys/rman.h> 66 #include <machine/resource.h> 67 #include <sys/watchdog.h> 68 69 #include <dev/pci/pcivar.h> 70 71 #include <dev/ichwd/ichwd.h> 72 73 static struct ichwd_device ichwd_devices[] = { 74 { VENDORID_INTEL, DEVICEID_82801AA, "Intel 82801AA watchdog timer" }, 75 { VENDORID_INTEL, DEVICEID_82801AB, "Intel 82801AB watchdog timer" }, 76 { VENDORID_INTEL, DEVICEID_82801BA, "Intel 82801BA watchdog timer" }, 77 { VENDORID_INTEL, DEVICEID_82801BAM, "Intel 82801BAM watchdog timer" }, 78 { VENDORID_INTEL, DEVICEID_82801CA, "Intel 82801CA watchdog timer" }, 79 { VENDORID_INTEL, DEVICEID_82801CAM, "Intel 82801CAM watchdog timer" }, 80 { VENDORID_INTEL, DEVICEID_82801DB, "Intel 82801DB watchdog timer" }, 81 { VENDORID_INTEL, DEVICEID_82801DBM, "Intel 82801DBM watchdog timer" }, 82 { VENDORID_INTEL, DEVICEID_82801E, "Intel 82801E watchdog timer" }, 83 { VENDORID_INTEL, DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer" }, 84 { VENDORID_INTEL, DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer" }, 85 { VENDORID_INTEL, DEVICEID_ICH5, "Intel ICH5 watchdog timer"}, 86 { VENDORID_INTEL, DEVICEID_6300ESB, "Intel 6300ESB watchdog timer"}, 87 { 0, 0, NULL }, 88 }; 89 90 static devclass_t ichwd_devclass; 91 92 #define ichwd_read_tco_1(sc, off) \ 93 bus_space_read_1((sc)->tco_bst, (sc)->tco_bsh, (off)) 94 #define ichwd_read_tco_2(sc, off) \ 95 bus_space_read_2((sc)->tco_bst, (sc)->tco_bsh, (off)) 96 #define ichwd_read_tco_4(sc, off) \ 97 bus_space_read_4((sc)->tco_bst, (sc)->tco_bsh, (off)) 98 99 #define ichwd_write_tco_1(sc, off, val) \ 100 bus_space_write_1((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 101 #define ichwd_write_tco_2(sc, off, val) \ 102 bus_space_write_2((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 103 #define ichwd_write_tco_4(sc, off, val) \ 104 bus_space_write_4((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 105 106 #define ichwd_read_smi_4(sc, off) \ 107 bus_space_read_4((sc)->smi_bst, (sc)->smi_bsh, (off)) 108 #define ichwd_write_smi_4(sc, off, val) \ 109 bus_space_write_4((sc)->smi_bst, (sc)->smi_bsh, (off), (val)) 110 111 static __inline void 112 ichwd_intr_enable(struct ichwd_softc *sc) 113 { 114 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN); 115 } 116 117 static __inline void 118 ichwd_intr_disable(struct ichwd_softc *sc) 119 { 120 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN); 121 } 122 123 static __inline void 124 ichwd_sts_reset(struct ichwd_softc *sc) 125 { 126 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT); 127 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS); 128 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS); 129 } 130 131 static __inline void 132 ichwd_tmr_enable(struct ichwd_softc *sc) 133 { 134 uint16_t cnt; 135 136 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 137 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT); 138 sc->active = 1; 139 if (bootverbose) 140 device_printf(sc->device, "timer enabled\n"); 141 } 142 143 static __inline void 144 ichwd_tmr_disable(struct ichwd_softc *sc) 145 { 146 uint16_t cnt; 147 148 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 149 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT); 150 sc->active = 0; 151 if (bootverbose) 152 device_printf(sc->device, "timer disabled\n"); 153 } 154 155 static __inline void 156 ichwd_tmr_reload(struct ichwd_softc *sc) 157 { 158 ichwd_write_tco_1(sc, TCO_RLD, 1); 159 if (bootverbose) 160 device_printf(sc->device, "timer reloaded\n"); 161 } 162 163 static __inline void 164 ichwd_tmr_set(struct ichwd_softc *sc, uint8_t timeout) 165 { 166 ichwd_write_tco_1(sc, TCO_TMR, timeout); 167 sc->timeout = timeout; 168 if (bootverbose) 169 device_printf(sc->device, "timeout set to %u ticks\n", timeout); 170 } 171 172 /* 173 * Watchdog event handler. 174 */ 175 static void 176 ichwd_event(void *arg, unsigned int cmd, int *error) 177 { 178 struct ichwd_softc *sc = arg; 179 unsigned int timeout; 180 181 /* convert from power-of-two-ns to WDT ticks */ 182 cmd &= WD_INTERVAL; 183 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK; 184 if (cmd > 0 && cmd <= 63 185 && timeout >= ICHWD_MIN_TIMEOUT && timeout <= ICHWD_MAX_TIMEOUT) { 186 if (timeout != sc->timeout) { 187 if (!sc->active) 188 ichwd_tmr_enable(sc); 189 ichwd_tmr_set(sc, timeout); 190 } 191 192 ichwd_tmr_reload(sc); 193 *error = 0; 194 } else { 195 if (sc->active) 196 ichwd_tmr_disable(sc); 197 } 198 } 199 200 static unsigned int pmbase = 0; 201 202 /* 203 * Look for an ICH LPC interface bridge. If one is found, register an 204 * ichwd device. There can be only one. 205 */ 206 static void 207 ichwd_identify(driver_t *driver, device_t parent) 208 { 209 struct ichwd_device *id; 210 device_t ich = NULL; 211 device_t dev; 212 213 /* look for an ICH LPC interface bridge */ 214 for (id = ichwd_devices; id->desc != NULL; ++id) 215 if ((ich = pci_find_device(id->vendor, id->device)) != NULL) 216 break; 217 if (ich == NULL) 218 return; 219 220 if (bootverbose) 221 printf("%s(): found ICH chipset: %s\n", __func__, id->desc); 222 223 /* get for ACPI base address */ 224 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK; 225 if (pmbase == 0) { 226 if (bootverbose) 227 printf("%s(): ICH PMBASE register is empty\n", 228 __func__); 229 return; 230 } 231 232 /* try to clear the NO_REBOOT bit */ 233 pci_write_config(ich, ICH_GEN_STA, 0x00, 1); 234 if (pci_read_config(ich, ICH_GEN_STA, 1) & ICH_GEN_STA_NO_REBOOT) { 235 if (bootverbose) 236 printf("%s(): ICH WDT present but disabled\n", 237 __func__); 238 return; 239 } 240 241 /* good, add child to bus */ 242 if ((dev = device_find_child(parent, driver->name, 0)) == NULL) 243 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0); 244 245 if (dev != NULL) 246 device_set_desc_copy(dev, id->desc); 247 } 248 249 static int 250 ichwd_probe(device_t dev) 251 { 252 (void)dev; 253 return (0); 254 } 255 256 static int 257 ichwd_attach(device_t dev) 258 { 259 struct ichwd_softc *sc; 260 261 sc = device_get_softc(dev); 262 sc->device = dev; 263 264 if (pmbase == 0) { 265 printf("Not found\n"); 266 } 267 268 /* allocate I/O register space */ 269 sc->smi_rid = 0; 270 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 271 pmbase + SMI_BASE, ~0ul, SMI_LEN, 272 RF_ACTIVE | RF_SHAREABLE); 273 if (sc->smi_res == NULL) { 274 device_printf(dev, "unable to reserve SMI registers\n"); 275 goto fail; 276 } 277 sc->smi_bst = rman_get_bustag(sc->smi_res); 278 sc->smi_bsh = rman_get_bushandle(sc->smi_res); 279 280 sc->tco_rid = 1; 281 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid, 282 pmbase + TCO_BASE, ~0ul, TCO_LEN, 283 RF_ACTIVE | RF_SHAREABLE); 284 if (sc->tco_res == NULL) { 285 device_printf(dev, "unable to reserve TCO registers\n"); 286 goto fail; 287 } 288 sc->tco_bst = rman_get_bustag(sc->tco_res); 289 sc->tco_bsh = rman_get_bushandle(sc->tco_res); 290 /* reset the watchdog status registers */ 291 292 ichwd_sts_reset(sc); 293 294 /* make sure the WDT starts out inactive */ 295 ichwd_tmr_disable(sc); 296 297 /* register the watchdog event handler */ 298 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0); 299 300 /* enable watchdog timeout interrupts */ 301 ichwd_intr_enable(sc); 302 303 return (0); 304 fail: 305 sc = device_get_softc(dev); 306 if (sc->tco_res != NULL) 307 bus_release_resource(dev, SYS_RES_IOPORT, 308 sc->tco_rid, sc->tco_res); 309 if (sc->smi_res != NULL) 310 bus_release_resource(dev, SYS_RES_IOPORT, 311 sc->smi_rid, sc->smi_res); 312 return (ENXIO); 313 } 314 315 static int 316 ichwd_detach(device_t dev) 317 { 318 struct ichwd_softc *sc; 319 320 sc = device_get_softc(dev); 321 322 /* halt the watchdog timer */ 323 if (sc->active) 324 ichwd_tmr_disable(sc); 325 326 /* disable watchdog timeout interrupts */ 327 ichwd_intr_disable(sc); 328 329 /* deregister event handler */ 330 if (sc->ev_tag != NULL) 331 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 332 sc->ev_tag = NULL; 333 334 /* reset the watchdog status registers */ 335 ichwd_sts_reset(sc); 336 337 /* deallocate I/O register space */ 338 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res); 339 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res); 340 341 return (0); 342 } 343 344 static device_method_t ichwd_methods[] = { 345 DEVMETHOD(device_identify, ichwd_identify), 346 DEVMETHOD(device_probe, ichwd_probe), 347 DEVMETHOD(device_attach, ichwd_attach), 348 DEVMETHOD(device_detach, ichwd_detach), 349 DEVMETHOD(device_shutdown, ichwd_detach), 350 {0,0} 351 }; 352 353 static driver_t ichwd_driver = { 354 "ichwd", 355 ichwd_methods, 356 sizeof(struct ichwd_softc), 357 }; 358 359 static int 360 ichwd_modevent(module_t mode, int type, void *data) 361 { 362 int error = 0; 363 364 switch (type) { 365 case MOD_LOAD: 366 printf("ichwd module loaded\n"); 367 break; 368 case MOD_UNLOAD: 369 printf("ichwd module unloaded\n"); 370 break; 371 case MOD_SHUTDOWN: 372 printf("ichwd module shutting down\n"); 373 break; 374 } 375 return (error); 376 } 377 378 DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, ichwd_modevent, NULL); 379