1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2004 Texas A&M University 5 * All rights reserved. 6 * 7 * Developer: Wm. Daryl Hawkins 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Intel ICH Watchdog Timer (WDT) driver 33 * 34 * Originally developed by Wm. Daryl Hawkins of Texas A&M 35 * Heavily modified by <des@FreeBSD.org> 36 * 37 * This is a tricky one. The ICH WDT can't be treated as a regular PCI 38 * device as it's actually an integrated function of the ICH LPC interface 39 * bridge. Detection is also awkward, because we can only infer the 40 * presence of the watchdog timer from the fact that the machine has an 41 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT' 42 * ACPI table (although this driver does not support the ACPI detection 43 * method). 44 * 45 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no 46 * way of knowing if the WDT is permanently disabled (either by the BIOS 47 * or in hardware). 48 * 49 * The WDT is programmed through I/O registers in the ACPI I/O space. 50 * Intel swears it's always at offset 0x60, so we use that. 51 * 52 * For details about the ICH WDT, see Intel Application Note AP-725 53 * (document no. 292273-001). The WDT is also described in the individual 54 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet 55 * (document no. 252516-001) sections 9.10 and 9.11. 56 * 57 * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp> 58 * SoC PMC support by Denir Li <denir.li@cas-well.com> 59 */ 60 61 #include <sys/param.h> 62 #include <sys/eventhandler.h> 63 #include <sys/kernel.h> 64 #include <sys/module.h> 65 #include <sys/systm.h> 66 #include <sys/bus.h> 67 #include <machine/bus.h> 68 #include <sys/rman.h> 69 #include <machine/resource.h> 70 #include <sys/watchdog.h> 71 72 #include <isa/isavar.h> 73 #include <dev/pci/pcivar.h> 74 75 #include <dev/ichwd/ichwd.h> 76 77 #include <x86/pci_cfgreg.h> 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/pci_private.h> 80 81 static struct ichwd_device ichwd_devices[] = { 82 { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1, 1 }, 83 { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1, 1 }, 84 { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2, 1 }, 85 { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2, 1 }, 86 { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3, 1 }, 87 { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3, 1 }, 88 { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4, 1 }, 89 { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4, 1 }, 90 { DEVICEID_82801E, "Intel 82801E watchdog timer", 5, 1 }, 91 { DEVICEID_82801EB, "Intel 82801EB watchdog timer", 5, 1 }, 92 { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5, 1 }, 93 { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5, 1 }, 94 { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6, 2 }, 95 { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6, 2 }, 96 { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6, 2 }, 97 { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7, 2 }, 98 { DEVICEID_ICH7DH, "Intel ICH7DH watchdog timer", 7, 2 }, 99 { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7, 2 }, 100 { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7, 2 }, 101 { DEVICEID_NM10, "Intel NM10 watchdog timer", 7, 2 }, 102 { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8, 2 }, 103 { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8, 2 }, 104 { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8, 2 }, 105 { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8, 2 }, 106 { DEVICEID_ICH8ME, "Intel ICH8M-E watchdog timer", 8, 2 }, 107 { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8, 2 }, 108 { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9, 2 }, 109 { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9, 2 }, 110 { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9, 2 }, 111 { DEVICEID_ICH9M, "Intel ICH9M watchdog timer", 9, 2 }, 112 { DEVICEID_ICH9ME, "Intel ICH9M-E watchdog timer", 9, 2 }, 113 { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9, 2 }, 114 { DEVICEID_ICH10, "Intel ICH10 watchdog timer", 10, 2 }, 115 { DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10, 2 }, 116 { DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10, 2 }, 117 { DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10, 2 }, 118 { DEVICEID_PCH, "Intel PCH watchdog timer", 10, 2 }, 119 { DEVICEID_PCHM, "Intel PCH watchdog timer", 10, 2 }, 120 { DEVICEID_P55, "Intel P55 watchdog timer", 10, 2 }, 121 { DEVICEID_PM55, "Intel PM55 watchdog timer", 10, 2 }, 122 { DEVICEID_H55, "Intel H55 watchdog timer", 10, 2 }, 123 { DEVICEID_QM57, "Intel QM57 watchdog timer", 10, 2 }, 124 { DEVICEID_H57, "Intel H57 watchdog timer", 10, 2 }, 125 { DEVICEID_HM55, "Intel HM55 watchdog timer", 10, 2 }, 126 { DEVICEID_Q57, "Intel Q57 watchdog timer", 10, 2 }, 127 { DEVICEID_HM57, "Intel HM57 watchdog timer", 10, 2 }, 128 { DEVICEID_PCHMSFF, "Intel PCHMSFF watchdog timer", 10, 2 }, 129 { DEVICEID_QS57, "Intel QS57 watchdog timer", 10, 2 }, 130 { DEVICEID_3400, "Intel 3400 watchdog timer", 10, 2 }, 131 { DEVICEID_3420, "Intel 3420 watchdog timer", 10, 2 }, 132 { DEVICEID_3450, "Intel 3450 watchdog timer", 10, 2 }, 133 { DEVICEID_CPT0, "Intel Cougar Point watchdog timer", 10, 2 }, 134 { DEVICEID_CPT1, "Intel Cougar Point watchdog timer", 10, 2 }, 135 { DEVICEID_CPT2, "Intel Cougar Point watchdog timer", 10, 2 }, 136 { DEVICEID_CPT3, "Intel Cougar Point watchdog timer", 10, 2 }, 137 { DEVICEID_CPT4, "Intel Cougar Point watchdog timer", 10, 2 }, 138 { DEVICEID_CPT5, "Intel Cougar Point watchdog timer", 10, 2 }, 139 { DEVICEID_CPT6, "Intel Cougar Point watchdog timer", 10, 2 }, 140 { DEVICEID_CPT7, "Intel Cougar Point watchdog timer", 10, 2 }, 141 { DEVICEID_CPT8, "Intel Cougar Point watchdog timer", 10, 2 }, 142 { DEVICEID_CPT9, "Intel Cougar Point watchdog timer", 10, 2 }, 143 { DEVICEID_CPT10, "Intel Cougar Point watchdog timer", 10, 2 }, 144 { DEVICEID_CPT11, "Intel Cougar Point watchdog timer", 10, 2 }, 145 { DEVICEID_CPT12, "Intel Cougar Point watchdog timer", 10, 2 }, 146 { DEVICEID_CPT13, "Intel Cougar Point watchdog timer", 10, 2 }, 147 { DEVICEID_CPT14, "Intel Cougar Point watchdog timer", 10, 2 }, 148 { DEVICEID_CPT15, "Intel Cougar Point watchdog timer", 10, 2 }, 149 { DEVICEID_CPT16, "Intel Cougar Point watchdog timer", 10, 2 }, 150 { DEVICEID_CPT17, "Intel Cougar Point watchdog timer", 10, 2 }, 151 { DEVICEID_CPT18, "Intel Cougar Point watchdog timer", 10, 2 }, 152 { DEVICEID_CPT19, "Intel Cougar Point watchdog timer", 10, 2 }, 153 { DEVICEID_CPT20, "Intel Cougar Point watchdog timer", 10, 2 }, 154 { DEVICEID_CPT21, "Intel Cougar Point watchdog timer", 10, 2 }, 155 { DEVICEID_CPT22, "Intel Cougar Point watchdog timer", 10, 2 }, 156 { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10, 2 }, 157 { DEVICEID_CPT24, "Intel Cougar Point watchdog timer", 10, 2 }, 158 { DEVICEID_CPT25, "Intel Cougar Point watchdog timer", 10, 2 }, 159 { DEVICEID_CPT26, "Intel Cougar Point watchdog timer", 10, 2 }, 160 { DEVICEID_CPT27, "Intel Cougar Point watchdog timer", 10, 2 }, 161 { DEVICEID_CPT28, "Intel Cougar Point watchdog timer", 10, 2 }, 162 { DEVICEID_CPT29, "Intel Cougar Point watchdog timer", 10, 2 }, 163 { DEVICEID_CPT30, "Intel Cougar Point watchdog timer", 10, 2 }, 164 { DEVICEID_CPT31, "Intel Cougar Point watchdog timer", 10, 2 }, 165 { DEVICEID_PATSBURG_LPC1, "Intel Patsburg watchdog timer", 10, 2 }, 166 { DEVICEID_PATSBURG_LPC2, "Intel Patsburg watchdog timer", 10, 2 }, 167 { DEVICEID_PPT0, "Intel Panther Point watchdog timer", 10, 2 }, 168 { DEVICEID_PPT1, "Intel Panther Point watchdog timer", 10, 2 }, 169 { DEVICEID_PPT2, "Intel Panther Point watchdog timer", 10, 2 }, 170 { DEVICEID_PPT3, "Intel Panther Point watchdog timer", 10, 2 }, 171 { DEVICEID_PPT4, "Intel Panther Point watchdog timer", 10, 2 }, 172 { DEVICEID_PPT5, "Intel Panther Point watchdog timer", 10, 2 }, 173 { DEVICEID_PPT6, "Intel Panther Point watchdog timer", 10, 2 }, 174 { DEVICEID_PPT7, "Intel Panther Point watchdog timer", 10, 2 }, 175 { DEVICEID_PPT8, "Intel Panther Point watchdog timer", 10, 2 }, 176 { DEVICEID_PPT9, "Intel Panther Point watchdog timer", 10, 2 }, 177 { DEVICEID_PPT10, "Intel Panther Point watchdog timer", 10, 2 }, 178 { DEVICEID_PPT11, "Intel Panther Point watchdog timer", 10, 2 }, 179 { DEVICEID_PPT12, "Intel Panther Point watchdog timer", 10, 2 }, 180 { DEVICEID_PPT13, "Intel Panther Point watchdog timer", 10, 2 }, 181 { DEVICEID_PPT14, "Intel Panther Point watchdog timer", 10, 2 }, 182 { DEVICEID_PPT15, "Intel Panther Point watchdog timer", 10, 2 }, 183 { DEVICEID_PPT16, "Intel Panther Point watchdog timer", 10, 2 }, 184 { DEVICEID_PPT17, "Intel Panther Point watchdog timer", 10, 2 }, 185 { DEVICEID_PPT18, "Intel Panther Point watchdog timer", 10, 2 }, 186 { DEVICEID_PPT19, "Intel Panther Point watchdog timer", 10, 2 }, 187 { DEVICEID_PPT20, "Intel Panther Point watchdog timer", 10, 2 }, 188 { DEVICEID_PPT21, "Intel Panther Point watchdog timer", 10, 2 }, 189 { DEVICEID_PPT22, "Intel Panther Point watchdog timer", 10, 2 }, 190 { DEVICEID_PPT23, "Intel Panther Point watchdog timer", 10, 2 }, 191 { DEVICEID_PPT24, "Intel Panther Point watchdog timer", 10, 2 }, 192 { DEVICEID_PPT25, "Intel Panther Point watchdog timer", 10, 2 }, 193 { DEVICEID_PPT26, "Intel Panther Point watchdog timer", 10, 2 }, 194 { DEVICEID_PPT27, "Intel Panther Point watchdog timer", 10, 2 }, 195 { DEVICEID_PPT28, "Intel Panther Point watchdog timer", 10, 2 }, 196 { DEVICEID_PPT29, "Intel Panther Point watchdog timer", 10, 2 }, 197 { DEVICEID_PPT30, "Intel Panther Point watchdog timer", 10, 2 }, 198 { DEVICEID_PPT31, "Intel Panther Point watchdog timer", 10, 2 }, 199 { DEVICEID_LPT0, "Intel Lynx Point watchdog timer", 10, 2 }, 200 { DEVICEID_LPT1, "Intel Lynx Point watchdog timer", 10, 2 }, 201 { DEVICEID_LPT2, "Intel Lynx Point watchdog timer", 10, 2 }, 202 { DEVICEID_LPT3, "Intel Lynx Point watchdog timer", 10, 2 }, 203 { DEVICEID_LPT4, "Intel Lynx Point watchdog timer", 10, 2 }, 204 { DEVICEID_LPT5, "Intel Lynx Point watchdog timer", 10, 2 }, 205 { DEVICEID_LPT6, "Intel Lynx Point watchdog timer", 10, 2 }, 206 { DEVICEID_LPT7, "Intel Lynx Point watchdog timer", 10, 2 }, 207 { DEVICEID_LPT8, "Intel Lynx Point watchdog timer", 10, 2 }, 208 { DEVICEID_LPT9, "Intel Lynx Point watchdog timer", 10, 2 }, 209 { DEVICEID_LPT10, "Intel Lynx Point watchdog timer", 10, 2 }, 210 { DEVICEID_LPT11, "Intel Lynx Point watchdog timer", 10, 2 }, 211 { DEVICEID_LPT12, "Intel Lynx Point watchdog timer", 10, 2 }, 212 { DEVICEID_LPT13, "Intel Lynx Point watchdog timer", 10, 2 }, 213 { DEVICEID_LPT14, "Intel Lynx Point watchdog timer", 10, 2 }, 214 { DEVICEID_LPT15, "Intel Lynx Point watchdog timer", 10, 2 }, 215 { DEVICEID_LPT16, "Intel Lynx Point watchdog timer", 10, 2 }, 216 { DEVICEID_LPT17, "Intel Lynx Point watchdog timer", 10, 2 }, 217 { DEVICEID_LPT18, "Intel Lynx Point watchdog timer", 10, 2 }, 218 { DEVICEID_LPT19, "Intel Lynx Point watchdog timer", 10, 2 }, 219 { DEVICEID_LPT20, "Intel Lynx Point watchdog timer", 10, 2 }, 220 { DEVICEID_LPT21, "Intel Lynx Point watchdog timer", 10, 2 }, 221 { DEVICEID_LPT22, "Intel Lynx Point watchdog timer", 10, 2 }, 222 { DEVICEID_LPT23, "Intel Lynx Point watchdog timer", 10, 2 }, 223 { DEVICEID_LPT24, "Intel Lynx Point watchdog timer", 10, 2 }, 224 { DEVICEID_LPT25, "Intel Lynx Point watchdog timer", 10, 2 }, 225 { DEVICEID_LPT26, "Intel Lynx Point watchdog timer", 10, 2 }, 226 { DEVICEID_LPT27, "Intel Lynx Point watchdog timer", 10, 2 }, 227 { DEVICEID_LPT28, "Intel Lynx Point watchdog timer", 10, 2 }, 228 { DEVICEID_LPT29, "Intel Lynx Point watchdog timer", 10, 2 }, 229 { DEVICEID_LPT30, "Intel Lynx Point watchdog timer", 10, 2 }, 230 { DEVICEID_LPT31, "Intel Lynx Point watchdog timer", 10, 2 }, 231 { DEVICEID_WCPT1, "Intel Wildcat Point watchdog timer", 10, 2 }, 232 { DEVICEID_WCPT2, "Intel Wildcat Point watchdog timer", 10, 2 }, 233 { DEVICEID_WCPT3, "Intel Wildcat Point watchdog timer", 10, 2 }, 234 { DEVICEID_WCPT4, "Intel Wildcat Point watchdog timer", 10, 2 }, 235 { DEVICEID_WCPT6, "Intel Wildcat Point watchdog timer", 10, 2 }, 236 { DEVICEID_WBG0, "Intel Wellsburg watchdog timer", 10, 2 }, 237 { DEVICEID_WBG1, "Intel Wellsburg watchdog timer", 10, 2 }, 238 { DEVICEID_WBG2, "Intel Wellsburg watchdog timer", 10, 2 }, 239 { DEVICEID_WBG3, "Intel Wellsburg watchdog timer", 10, 2 }, 240 { DEVICEID_WBG4, "Intel Wellsburg watchdog timer", 10, 2 }, 241 { DEVICEID_WBG5, "Intel Wellsburg watchdog timer", 10, 2 }, 242 { DEVICEID_WBG6, "Intel Wellsburg watchdog timer", 10, 2 }, 243 { DEVICEID_WBG7, "Intel Wellsburg watchdog timer", 10, 2 }, 244 { DEVICEID_WBG8, "Intel Wellsburg watchdog timer", 10, 2 }, 245 { DEVICEID_WBG9, "Intel Wellsburg watchdog timer", 10, 2 }, 246 { DEVICEID_WBG10, "Intel Wellsburg watchdog timer", 10, 2 }, 247 { DEVICEID_WBG11, "Intel Wellsburg watchdog timer", 10, 2 }, 248 { DEVICEID_WBG12, "Intel Wellsburg watchdog timer", 10, 2 }, 249 { DEVICEID_WBG13, "Intel Wellsburg watchdog timer", 10, 2 }, 250 { DEVICEID_WBG14, "Intel Wellsburg watchdog timer", 10, 2 }, 251 { DEVICEID_WBG15, "Intel Wellsburg watchdog timer", 10, 2 }, 252 { DEVICEID_WBG16, "Intel Wellsburg watchdog timer", 10, 2 }, 253 { DEVICEID_WBG17, "Intel Wellsburg watchdog timer", 10, 2 }, 254 { DEVICEID_WBG18, "Intel Wellsburg watchdog timer", 10, 2 }, 255 { DEVICEID_WBG19, "Intel Wellsburg watchdog timer", 10, 2 }, 256 { DEVICEID_WBG20, "Intel Wellsburg watchdog timer", 10, 2 }, 257 { DEVICEID_WBG21, "Intel Wellsburg watchdog timer", 10, 2 }, 258 { DEVICEID_WBG22, "Intel Wellsburg watchdog timer", 10, 2 }, 259 { DEVICEID_WBG23, "Intel Wellsburg watchdog timer", 10, 2 }, 260 { DEVICEID_WBG24, "Intel Wellsburg watchdog timer", 10, 2 }, 261 { DEVICEID_WBG25, "Intel Wellsburg watchdog timer", 10, 2 }, 262 { DEVICEID_WBG26, "Intel Wellsburg watchdog timer", 10, 2 }, 263 { DEVICEID_WBG27, "Intel Wellsburg watchdog timer", 10, 2 }, 264 { DEVICEID_WBG28, "Intel Wellsburg watchdog timer", 10, 2 }, 265 { DEVICEID_WBG29, "Intel Wellsburg watchdog timer", 10, 2 }, 266 { DEVICEID_WBG30, "Intel Wellsburg watchdog timer", 10, 2 }, 267 { DEVICEID_WBG31, "Intel Wellsburg watchdog timer", 10, 2 }, 268 { DEVICEID_LPT_LP0, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 269 { DEVICEID_LPT_LP1, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 270 { DEVICEID_LPT_LP2, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 271 { DEVICEID_LPT_LP3, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 272 { DEVICEID_LPT_LP4, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 273 { DEVICEID_LPT_LP5, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 274 { DEVICEID_LPT_LP6, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 275 { DEVICEID_LPT_LP7, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 276 { DEVICEID_WCPT_LP1, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 277 { DEVICEID_WCPT_LP2, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 278 { DEVICEID_WCPT_LP3, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 279 { DEVICEID_WCPT_LP5, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 280 { DEVICEID_WCPT_LP6, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 281 { DEVICEID_WCPT_LP7, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 282 { DEVICEID_WCPT_LP9, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 283 { DEVICEID_DH89XXCC_LPC, "Intel DH89xxCC watchdog timer", 10, 2 }, 284 { DEVICEID_COLETOCRK_LPC, "Intel Coleto Creek watchdog timer", 10, 2 }, 285 { DEVICEID_AVN0, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 286 { DEVICEID_AVN1, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 287 { DEVICEID_AVN2, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 288 { DEVICEID_AVN3, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 289 { DEVICEID_BAYTRAIL, "Intel Bay Trail SoC watchdog timer", 10, 3 }, 290 { DEVICEID_BRASWELL, "Intel Braswell SoC watchdog timer", 10, 3 }, 291 { 0, NULL, 0, 0 }, 292 }; 293 294 static struct ichwd_device ichwd_smb_devices[] = { 295 { DEVICEID_LEWISBURG_SMB, "Lewisburg watchdog timer", 10, 4 }, 296 { DEVICEID_LEWISBURG_SMB_SSKU, "Lewisburg watchdog timer", 10, 4 }, 297 { DEVICEID_CANNON_SMB, "Cannon Lake watchdog timer", 10, 4, PMC_HIDDEN}, 298 { DEVICEID_COMET_SMB, "Comet Lake watchdog timer", 10, 4, PMC_HIDDEN}, 299 { DEVICEID_SRPTLP_SMB, "Sunrise Point-LP watchdog timer", 10, 4 }, 300 { DEVICEID_C3000, "Intel Atom C3000 watchdog timer", 10, 4 }, 301 { 0, NULL, 0, 0 }, 302 }; 303 304 #define ichwd_read_tco_1(sc, off) \ 305 bus_read_1((sc)->tco_res, (off)) 306 #define ichwd_read_tco_2(sc, off) \ 307 bus_read_2((sc)->tco_res, (off)) 308 #define ichwd_read_tco_4(sc, off) \ 309 bus_read_4((sc)->tco_res, (off)) 310 #define ichwd_read_smi_4(sc, off) \ 311 bus_read_4((sc)->smi_res, (off)) 312 #define ichwd_read_gcs_4(sc, off) \ 313 bus_read_4((sc)->gcs_res, (off)) 314 /* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */ 315 #define ichwd_read_pmc_4(sc, off) \ 316 bus_read_4((sc)->gcs_res, (off)) 317 #define ichwd_read_gc_4(sc, off) \ 318 bus_read_4((sc)->gc_res, (off)) 319 320 #define ichwd_write_tco_1(sc, off, val) \ 321 bus_write_1((sc)->tco_res, (off), (val)) 322 #define ichwd_write_tco_2(sc, off, val) \ 323 bus_write_2((sc)->tco_res, (off), (val)) 324 #define ichwd_write_tco_4(sc, off, val) \ 325 bus_write_4((sc)->tco_res, (off), (val)) 326 #define ichwd_write_smi_4(sc, off, val) \ 327 bus_write_4((sc)->smi_res, (off), (val)) 328 #define ichwd_write_gcs_4(sc, off, val) \ 329 bus_write_4((sc)->gcs_res, (off), (val)) 330 /* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */ 331 #define ichwd_write_pmc_4(sc, off, val) \ 332 bus_write_4((sc)->gcs_res, (off), (val)) 333 #define ichwd_write_gc_4(sc, off, val) \ 334 bus_write_4((sc)->gc_res, (off), (val)) 335 336 #define ichwd_verbose_printf(dev, ...) \ 337 do { \ 338 if (bootverbose) \ 339 device_printf(dev, __VA_ARGS__);\ 340 } while (0) 341 342 /* 343 * Disable the watchdog timeout SMI handler. 344 * 345 * Apparently, some BIOSes install handlers that reset or disable the 346 * watchdog timer instead of resetting the system, so we disable the SMI 347 * (by clearing the SMI_TCO_EN bit of the SMI_EN register) to prevent this 348 * from happening. 349 */ 350 static __inline void 351 ichwd_smi_disable(struct ichwd_softc *sc) 352 { 353 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN); 354 } 355 356 /* 357 * Enable the watchdog timeout SMI handler. See above for details. 358 */ 359 static __inline void 360 ichwd_smi_enable(struct ichwd_softc *sc) 361 { 362 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN); 363 } 364 365 /* 366 * Check if the watchdog SMI triggering is enabled. 367 */ 368 static __inline int 369 ichwd_smi_is_enabled(struct ichwd_softc *sc) 370 { 371 return ((ichwd_read_smi_4(sc, SMI_EN) & SMI_TCO_EN) != 0); 372 } 373 374 /* 375 * Reset the watchdog status bits. 376 */ 377 static __inline void 378 ichwd_sts_reset(struct ichwd_softc *sc) 379 { 380 /* 381 * The watchdog status bits are set to 1 by the hardware to 382 * indicate various conditions. They can be cleared by software 383 * by writing a 1, not a 0. 384 */ 385 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT); 386 /* 387 * According to Intel's docs, clearing SECOND_TO_STS and BOOT_STS must 388 * be done in two separate operations. 389 */ 390 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS); 391 if (sc->tco_version < 4) 392 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS); 393 } 394 395 /* 396 * Enable the watchdog timer by clearing the TCO_TMR_HALT bit in the 397 * TCO1_CNT register. This is complicated by the need to preserve bit 9 398 * of that same register, and the requirement that all other bits must be 399 * written back as zero. 400 */ 401 static __inline void 402 ichwd_tmr_enable(struct ichwd_softc *sc) 403 { 404 uint16_t cnt; 405 406 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 407 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT); 408 sc->active = 1; 409 ichwd_verbose_printf(sc->device, "timer enabled\n"); 410 } 411 412 /* 413 * Disable the watchdog timer. See above for details. 414 */ 415 static __inline void 416 ichwd_tmr_disable(struct ichwd_softc *sc) 417 { 418 uint16_t cnt; 419 420 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 421 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT); 422 sc->active = 0; 423 ichwd_verbose_printf(sc->device, "timer disabled\n"); 424 } 425 426 /* 427 * Reload the watchdog timer: writing anything to any of the lower five 428 * bits of the TCO_RLD register reloads the timer from the last value 429 * written to TCO_TMR. 430 */ 431 static __inline void 432 ichwd_tmr_reload(struct ichwd_softc *sc) 433 { 434 if (sc->tco_version == 1) 435 ichwd_write_tco_1(sc, TCO_RLD, 1); 436 else 437 ichwd_write_tco_2(sc, TCO_RLD, 1); 438 } 439 440 /* 441 * Set the initial timeout value. Note that this must always be followed 442 * by a reload. 443 */ 444 static __inline void 445 ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout) 446 { 447 448 if (timeout < TCO_RLD_TMR_MIN) 449 timeout = TCO_RLD_TMR_MIN; 450 451 if (sc->tco_version == 1) { 452 uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1); 453 454 tmr_val8 &= (~TCO_RLD1_TMR_MAX & 0xff); 455 if (timeout > TCO_RLD1_TMR_MAX) 456 timeout = TCO_RLD1_TMR_MAX; 457 tmr_val8 |= timeout; 458 ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8); 459 } else { 460 uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2); 461 462 tmr_val16 &= (~TCO_RLD2_TMR_MAX & 0xffff); 463 if (timeout > TCO_RLD2_TMR_MAX) 464 timeout = TCO_RLD2_TMR_MAX; 465 tmr_val16 |= timeout; 466 ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16); 467 } 468 469 sc->timeout = timeout; 470 471 ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout); 472 } 473 474 static __inline int 475 ichwd_clear_noreboot(struct ichwd_softc *sc) 476 { 477 uint32_t status; 478 int rc = 0; 479 480 /* try to clear the NO_REBOOT bit */ 481 switch (sc->tco_version) { 482 case 1: 483 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 484 status &= ~ICH_GEN_STA_NO_REBOOT; 485 pci_write_config(sc->ich, ICH_GEN_STA, status, 1); 486 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 487 if (status & ICH_GEN_STA_NO_REBOOT) 488 rc = EIO; 489 break; 490 case 2: 491 status = ichwd_read_gcs_4(sc, 0); 492 status &= ~ICH_GCS_NO_REBOOT; 493 ichwd_write_gcs_4(sc, 0, status); 494 status = ichwd_read_gcs_4(sc, 0); 495 if (status & ICH_GCS_NO_REBOOT) 496 rc = EIO; 497 break; 498 case 3: 499 status = ichwd_read_pmc_4(sc, 0); 500 status &= ~ICH_PMC_NO_REBOOT; 501 ichwd_write_pmc_4(sc, 0, status); 502 status = ichwd_read_pmc_4(sc, 0); 503 if (status & ICH_PMC_NO_REBOOT) 504 rc = EIO; 505 break; 506 case 4: 507 status = ichwd_read_gc_4(sc, 0); 508 status &= ~SMB_GC_NO_REBOOT; 509 ichwd_write_gc_4(sc, 0, status); 510 status = ichwd_read_gc_4(sc, 0); 511 if (status & SMB_GC_NO_REBOOT) 512 rc = EIO; 513 break; 514 default: 515 ichwd_verbose_printf(sc->device, 516 "Unknown TCO Version: %d, can't set NO_REBOOT.\n", 517 sc->tco_version); 518 break; 519 } 520 521 if (rc) 522 device_printf(sc->device, 523 "ICH WDT present but disabled in BIOS or hardware\n"); 524 525 return (rc); 526 } 527 528 /* 529 * Watchdog event handler - called by the framework to enable or disable 530 * the watchdog or change the initial timeout value. 531 */ 532 static void 533 ichwd_event(void *arg, unsigned int cmd, int *error) 534 { 535 struct ichwd_softc *sc = arg; 536 unsigned int timeout; 537 538 /* convert from power-of-two-ns to WDT ticks */ 539 cmd &= WD_INTERVAL; 540 541 if (sc->tco_version == 3) { 542 timeout = ((uint64_t)1 << cmd) / ICHWD_TCO_V3_TICK; 543 } else { 544 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK; 545 } 546 547 if (cmd) { 548 if (!sc->active) 549 ichwd_tmr_enable(sc); 550 if (timeout != sc->timeout) 551 ichwd_tmr_set(sc, timeout); 552 ichwd_tmr_reload(sc); 553 *error = 0; 554 } else { 555 if (sc->active) 556 ichwd_tmr_disable(sc); 557 } 558 } 559 560 static device_t 561 ichwd_find_ich_lpc_bridge(device_t isa, struct ichwd_device **id_p) 562 { 563 struct ichwd_device *id; 564 device_t isab, pci; 565 uint16_t devid; 566 567 /* Check whether parent ISA bridge looks familiar. */ 568 isab = device_get_parent(isa); 569 pci = device_get_parent(isab); 570 if (pci == NULL || device_get_devclass(pci) != devclass_find("pci")) 571 return (NULL); 572 if (pci_get_vendor(isab) != VENDORID_INTEL) 573 return (NULL); 574 devid = pci_get_device(isab); 575 for (id = ichwd_devices; id->desc != NULL; ++id) { 576 if (devid == id->device) { 577 if (id_p != NULL) 578 *id_p = id; 579 return (isab); 580 } 581 } 582 583 return (NULL); 584 } 585 586 static device_t 587 ichwd_find_smb_dev(device_t isa, struct ichwd_device **id_p) 588 { 589 struct ichwd_device *id; 590 device_t isab, smb; 591 uint16_t devid; 592 593 /* 594 * Check if SMBus controller provides TCO configuration. 595 * The controller's device and function are fixed and we expect 596 * it to be on the same bus as ISA bridge. 597 */ 598 isab = device_get_parent(isa); 599 smb = pci_find_dbsf(pci_get_domain(isab), pci_get_bus(isab), 31, 4); 600 if (smb == NULL) 601 return (NULL); 602 if (pci_get_vendor(smb) != VENDORID_INTEL) 603 return (NULL); 604 devid = pci_get_device(smb); 605 for (id = ichwd_smb_devices; id->desc != NULL; ++id) { 606 if (devid == id->device) { 607 if (id_p != NULL) 608 *id_p = id; 609 return (smb); 610 } 611 } 612 613 return (NULL); 614 } 615 616 /* 617 * Look for an ICH LPC interface bridge. If one is found, register an 618 * ichwd device. There can be only one. 619 */ 620 static void 621 ichwd_identify(driver_t *driver, device_t parent) 622 { 623 struct ichwd_device *id_p; 624 device_t ich, smb; 625 device_t dev; 626 uint64_t base_address64; 627 uint32_t base_address; 628 uint32_t ctl; 629 int rc; 630 631 ich = ichwd_find_ich_lpc_bridge(parent, &id_p); 632 if (ich == NULL) { 633 smb = ichwd_find_smb_dev(parent, &id_p); 634 if (smb == NULL) 635 return; 636 } 637 638 KASSERT(id_p->tco_version >= 1, 639 ("unexpected TCO version %d", id_p->tco_version)); 640 KASSERT(id_p->tco_version != 4 || smb != NULL, 641 ("could not find PCI SMBus device for TCOv4")); 642 KASSERT(id_p->tco_version >= 4 || ich != NULL, 643 ("could not find PCI LPC bridge device for TCOv1-3")); 644 645 /* good, add child to bus */ 646 if ((dev = device_find_child(parent, driver->name, 0)) == NULL) 647 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0); 648 649 if (dev == NULL) 650 return; 651 652 switch (id_p->tco_version) { 653 case 1: 654 break; 655 case 2: 656 /* get RCBA (root complex base address) */ 657 base_address = pci_read_config(ich, ICH_RCBA, 4); 658 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 659 (base_address & 0xffffc000) + ICH_GCS_OFFSET, 660 ICH_GCS_SIZE); 661 if (rc) 662 ichwd_verbose_printf(dev, 663 "Can not set TCO v%d memory resource for RCBA\n", 664 id_p->tco_version); 665 break; 666 case 3: 667 /* get PBASE (Power Management Controller base address) */ 668 base_address = pci_read_config(ich, ICH_PBASE, 4); 669 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 670 (base_address & 0xfffffe00) + ICH_PMC_OFFSET, 671 ICH_PMC_SIZE); 672 if (rc) 673 ichwd_verbose_printf(dev, 674 "Can not set TCO v%d memory resource for PBASE\n", 675 id_p->tco_version); 676 break; 677 case 4: 678 /* Get TCO base address. */ 679 ctl = pci_read_config(smb, ICH_TCOCTL, 4); 680 if ((ctl & ICH_TCOCTL_TCO_BASE_EN) == 0) { 681 ichwd_verbose_printf(dev, 682 "TCO v%d decoding is not enabled\n", 683 id_p->tco_version); 684 break; 685 } 686 base_address = pci_read_config(smb, ICH_TCOBASE, 4); 687 rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, 688 base_address & ICH_TCOBASE_ADDRMASK, ICH_TCOBASE_SIZE); 689 if (rc != 0) { 690 ichwd_verbose_printf(dev, 691 "Can not set TCO v%d I/O resource (err = %d)\n", 692 id_p->tco_version, rc); 693 } 694 695 /* 696 * Unhide Primary to Sideband Bridge (P2SB) PCI device, so that 697 * we can discover the base address of Private Configuration 698 * Space via the bridge's BAR. 699 * Then hide back the bridge. 700 */ 701 pci_cfgregwrite(0, 0, 31, 1, 0xe1, 0, 1); 702 base_address64 = pci_cfgregread(0, 0, 31, 1, SBREG_BAR + 4, 4); 703 base_address64 <<= 32; 704 base_address64 |= pci_cfgregread(0, 0, 31, 1, SBREG_BAR, 4); 705 base_address64 &= ~0xfull; 706 pci_cfgregwrite(0, 0, 31, 1, 0xe1, 1, 1); 707 708 /* 709 * No Reboot bit is in General Control register, offset 0xc, 710 * within the SMBus target port, ID 0xc6. 711 */ 712 base_address64 += PCR_REG_OFF(SMB_PORT_ID, SMB_GC_REG); 713 rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, base_address64, 714 SMB_GC_SIZE); 715 if (rc != 0) { 716 ichwd_verbose_printf(dev, 717 "Can not set TCO v%d PCR I/O resource (err = %d)\n", 718 id_p->tco_version, rc); 719 } 720 721 break; 722 default: 723 ichwd_verbose_printf(dev, 724 "Can not set unknown TCO v%d memory resource for unknown base address\n", 725 id_p->tco_version); 726 break; 727 } 728 } 729 730 static int 731 ichwd_probe(device_t dev) 732 { 733 struct ichwd_device *id_p; 734 735 /* Do not claim some ISA PnP device by accident. */ 736 if (isa_get_logicalid(dev) != 0) 737 return (ENXIO); 738 739 if (ichwd_find_ich_lpc_bridge(device_get_parent(dev), &id_p) == NULL && 740 ichwd_find_smb_dev(device_get_parent(dev), &id_p) == NULL) 741 return (ENXIO); 742 743 device_set_desc_copy(dev, id_p->desc); 744 return (0); 745 } 746 747 static int 748 ichwd_smb_attach(device_t dev) 749 { 750 struct ichwd_softc *sc; 751 struct ichwd_device *id_p; 752 device_t isab, pmdev; 753 device_t smb; 754 uint32_t acpi_base; 755 756 sc = device_get_softc(dev); 757 smb = ichwd_find_smb_dev(device_get_parent(dev), &id_p); 758 if (smb == NULL) 759 return (ENXIO); 760 761 sc->ich_version = id_p->ich_version; 762 sc->tco_version = id_p->tco_version; 763 764 /* Allocate TCO control I/O register space. */ 765 sc->tco_rid = 0; 766 sc->tco_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->tco_rid, 767 RF_ACTIVE | RF_SHAREABLE); 768 if (sc->tco_res == NULL) { 769 device_printf(dev, "unable to reserve TCO registers\n"); 770 return (ENXIO); 771 } 772 773 /* 774 * Allocate General Control I/O register in PCH 775 * Private Configuration Space (PCR). 776 */ 777 sc->gc_rid = 1; 778 sc->gc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->gc_rid, 779 RF_ACTIVE | RF_SHAREABLE); 780 if (sc->gc_res == NULL) { 781 device_printf(dev, "unable to reserve hidden P2SB registers\n"); 782 return (ENXIO); 783 } 784 785 /* Get ACPI base address. */ 786 isab = device_get_parent(device_get_parent(dev)); 787 pmdev = pci_find_dbsf(pci_get_domain(isab), pci_get_bus(isab), 31, 2); 788 if (pmdev == NULL) { 789 if (id_p->quirks & PMC_HIDDEN) { 790 /* 791 * Since the PMC is hidden, we take the default value for the 792 * given device, which happens to be the same for the ones we 793 * support. 794 */ 795 acpi_base = ACPI_DEFAULT_CANNON; 796 } else { 797 device_printf(dev, "unable to find Power Management device\n"); 798 return (ENXIO); 799 } 800 } else { 801 acpi_base = pci_read_config(pmdev, ICH_PMBASE, 4) & 0xffffff00; 802 if (acpi_base == 0) { 803 device_printf(dev, "ACPI base address is not set\n"); 804 return (ENXIO); 805 } 806 } 807 808 /* Allocate SMI control I/O register space. */ 809 sc->smi_rid = 2; 810 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 811 acpi_base + SMI_BASE, acpi_base + SMI_BASE + SMI_LEN - 1, SMI_LEN, 812 RF_ACTIVE | RF_SHAREABLE); 813 if (sc->smi_res == NULL) { 814 device_printf(dev, "unable to reserve SMI registers\n"); 815 return (ENXIO); 816 } 817 818 return (0); 819 } 820 821 static int 822 ichwd_lpc_attach(device_t dev) 823 { 824 struct ichwd_softc *sc; 825 struct ichwd_device *id_p; 826 device_t ich; 827 unsigned int pmbase = 0; 828 829 sc = device_get_softc(dev); 830 831 ich = ichwd_find_ich_lpc_bridge(device_get_parent(dev), &id_p); 832 if (ich == NULL) 833 return (ENXIO); 834 835 sc->ich = ich; 836 sc->ich_version = id_p->ich_version; 837 sc->tco_version = id_p->tco_version; 838 839 /* get ACPI base address */ 840 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK; 841 if (pmbase == 0) { 842 device_printf(dev, "ICH PMBASE register is empty\n"); 843 return (ENXIO); 844 } 845 846 /* allocate I/O register space */ 847 sc->smi_rid = 0; 848 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 849 pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN, 850 RF_ACTIVE | RF_SHAREABLE); 851 if (sc->smi_res == NULL) { 852 device_printf(dev, "unable to reserve SMI registers\n"); 853 return (ENXIO); 854 } 855 856 sc->tco_rid = 1; 857 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid, 858 pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN, 859 RF_ACTIVE | RF_SHAREABLE); 860 if (sc->tco_res == NULL) { 861 device_printf(dev, "unable to reserve TCO registers\n"); 862 return (ENXIO); 863 } 864 865 sc->gcs_rid = 0; 866 if (sc->tco_version >= 2) { 867 sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY, 868 &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE); 869 if (sc->gcs_res == NULL) { 870 device_printf(dev, "unable to reserve GCS registers\n"); 871 return (ENXIO); 872 } 873 } 874 875 return (0); 876 } 877 878 static int 879 ichwd_attach(device_t dev) 880 { 881 struct ichwd_softc *sc; 882 883 sc = device_get_softc(dev); 884 sc->device = dev; 885 886 if (ichwd_lpc_attach(dev) != 0 && ichwd_smb_attach(dev) != 0) 887 goto fail; 888 889 if (ichwd_clear_noreboot(sc) != 0) 890 goto fail; 891 892 /* 893 * Determine if we are coming up after a watchdog-induced reset. Some 894 * BIOSes may clear this bit at bootup, preventing us from reporting 895 * this case on such systems. We clear this bit in ichwd_sts_reset(). 896 */ 897 if ((ichwd_read_tco_2(sc, TCO2_STS) & TCO_SECOND_TO_STS) != 0) 898 device_printf(dev, 899 "resuming after hardware watchdog timeout\n"); 900 901 /* reset the watchdog status registers */ 902 ichwd_sts_reset(sc); 903 904 /* make sure the WDT starts out inactive */ 905 ichwd_tmr_disable(sc); 906 907 /* register the watchdog event handler */ 908 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0); 909 910 /* disable the SMI handler */ 911 sc->smi_enabled = ichwd_smi_is_enabled(sc); 912 ichwd_smi_disable(sc); 913 914 return (0); 915 fail: 916 sc = device_get_softc(dev); 917 if (sc->tco_res != NULL) 918 bus_release_resource(dev, SYS_RES_IOPORT, 919 sc->tco_rid, sc->tco_res); 920 if (sc->smi_res != NULL) 921 bus_release_resource(dev, SYS_RES_IOPORT, 922 sc->smi_rid, sc->smi_res); 923 if (sc->gcs_res != NULL) 924 bus_release_resource(sc->ich, SYS_RES_MEMORY, 925 sc->gcs_rid, sc->gcs_res); 926 if (sc->gc_res != NULL) 927 bus_release_resource(dev, SYS_RES_MEMORY, 928 sc->gc_rid, sc->gc_res); 929 930 return (ENXIO); 931 } 932 933 static int 934 ichwd_detach(device_t dev) 935 { 936 struct ichwd_softc *sc; 937 938 sc = device_get_softc(dev); 939 940 /* halt the watchdog timer */ 941 if (sc->active) 942 ichwd_tmr_disable(sc); 943 944 /* enable the SMI handler */ 945 if (sc->smi_enabled != 0) 946 ichwd_smi_enable(sc); 947 948 /* deregister event handler */ 949 if (sc->ev_tag != NULL) 950 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 951 sc->ev_tag = NULL; 952 953 /* reset the watchdog status registers */ 954 ichwd_sts_reset(sc); 955 956 /* deallocate I/O register space */ 957 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res); 958 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res); 959 960 /* deallocate memory resource */ 961 if (sc->gcs_res) 962 bus_release_resource(sc->ich, SYS_RES_MEMORY, sc->gcs_rid, 963 sc->gcs_res); 964 if (sc->gc_res) 965 bus_release_resource(dev, SYS_RES_MEMORY, sc->gc_rid, 966 sc->gc_res); 967 968 return (0); 969 } 970 971 static device_method_t ichwd_methods[] = { 972 DEVMETHOD(device_identify, ichwd_identify), 973 DEVMETHOD(device_probe, ichwd_probe), 974 DEVMETHOD(device_attach, ichwd_attach), 975 DEVMETHOD(device_detach, ichwd_detach), 976 DEVMETHOD(device_shutdown, ichwd_detach), 977 {0,0} 978 }; 979 980 static driver_t ichwd_driver = { 981 "ichwd", 982 ichwd_methods, 983 sizeof(struct ichwd_softc), 984 }; 985 986 DRIVER_MODULE(ichwd, isa, ichwd_driver, NULL, NULL); 987