1 /*- 2 * Copyright (c) 2004 Texas A&M University 3 * All rights reserved. 4 * 5 * Developer: Wm. Daryl Hawkins 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Intel ICH Watchdog Timer (WDT) driver 31 * 32 * Originally developed by Wm. Daryl Hawkins of Texas A&M 33 * Heavily modified by <des@FreeBSD.org> 34 * 35 * This is a tricky one. The ICH WDT can't be treated as a regular PCI 36 * device as it's actually an integrated function of the ICH LPC interface 37 * bridge. Detection is also awkward, because we can only infer the 38 * presence of the watchdog timer from the fact that the machine has an 39 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT' 40 * ACPI table (although this driver does not support the ACPI detection 41 * method). 42 * 43 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no 44 * way of knowing if the WDT is permanently disabled (either by the BIOS 45 * or in hardware). 46 * 47 * The WDT is programmed through I/O registers in the ACPI I/O space. 48 * Intel swears it's always at offset 0x60, so we use that. 49 * 50 * For details about the ICH WDT, see Intel Application Note AP-725 51 * (document no. 292273-001). The WDT is also described in the individual 52 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet 53 * (document no. 252516-001) sections 9.10 and 9.11. 54 * 55 * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp> 56 */ 57 58 #include <sys/cdefs.h> 59 __FBSDID("$FreeBSD$"); 60 61 #include <sys/param.h> 62 #include <sys/kernel.h> 63 #include <sys/module.h> 64 #include <sys/systm.h> 65 #include <sys/bus.h> 66 #include <machine/bus.h> 67 #include <sys/rman.h> 68 #include <machine/resource.h> 69 #include <sys/watchdog.h> 70 71 #include <isa/isavar.h> 72 #include <dev/pci/pcivar.h> 73 74 #include <dev/ichwd/ichwd.h> 75 76 static struct ichwd_device ichwd_devices[] = { 77 { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1 }, 78 { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1 }, 79 { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2 }, 80 { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2 }, 81 { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3 }, 82 { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3 }, 83 { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4 }, 84 { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4 }, 85 { DEVICEID_82801E, "Intel 82801E watchdog timer", 5 }, 86 { DEVICEID_82801EB, "Intel 82801EB watchdog timer", 5 }, 87 { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5 }, 88 { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5 }, 89 { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6 }, 90 { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6 }, 91 { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6 }, 92 { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7 }, 93 { DEVICEID_ICH7DH, "Intel ICH7DH watchdog timer", 7 }, 94 { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7 }, 95 { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7 }, 96 { DEVICEID_NM10, "Intel NM10 watchdog timer", 7 }, 97 { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8 }, 98 { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8 }, 99 { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8 }, 100 { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8 }, 101 { DEVICEID_ICH8ME, "Intel ICH8M-E watchdog timer", 8 }, 102 { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8 }, 103 { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9 }, 104 { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9 }, 105 { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9 }, 106 { DEVICEID_ICH9M, "Intel ICH9M watchdog timer", 9 }, 107 { DEVICEID_ICH9ME, "Intel ICH9M-E watchdog timer", 9 }, 108 { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9 }, 109 { DEVICEID_ICH10, "Intel ICH10 watchdog timer", 10 }, 110 { DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10 }, 111 { DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10 }, 112 { DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10 }, 113 { DEVICEID_PCH, "Intel PCH watchdog timer", 10 }, 114 { DEVICEID_PCHM, "Intel PCH watchdog timer", 10 }, 115 { DEVICEID_P55, "Intel P55 watchdog timer", 10 }, 116 { DEVICEID_PM55, "Intel PM55 watchdog timer", 10 }, 117 { DEVICEID_H55, "Intel H55 watchdog timer", 10 }, 118 { DEVICEID_QM57, "Intel QM57 watchdog timer", 10 }, 119 { DEVICEID_H57, "Intel H57 watchdog timer", 10 }, 120 { DEVICEID_HM55, "Intel HM55 watchdog timer", 10 }, 121 { DEVICEID_Q57, "Intel Q57 watchdog timer", 10 }, 122 { DEVICEID_HM57, "Intel HM57 watchdog timer", 10 }, 123 { DEVICEID_PCHMSFF, "Intel PCHMSFF watchdog timer", 10 }, 124 { DEVICEID_QS57, "Intel QS57 watchdog timer", 10 }, 125 { DEVICEID_3400, "Intel 3400 watchdog timer", 10 }, 126 { DEVICEID_3420, "Intel 3420 watchdog timer", 10 }, 127 { DEVICEID_3450, "Intel 3450 watchdog timer", 10 }, 128 { DEVICEID_CPT0, "Intel Cougar Point watchdog timer", 10 }, 129 { DEVICEID_CPT1, "Intel Cougar Point watchdog timer", 10 }, 130 { DEVICEID_CPT2, "Intel Cougar Point watchdog timer", 10 }, 131 { DEVICEID_CPT3, "Intel Cougar Point watchdog timer", 10 }, 132 { DEVICEID_CPT4, "Intel Cougar Point watchdog timer", 10 }, 133 { DEVICEID_CPT5, "Intel Cougar Point watchdog timer", 10 }, 134 { DEVICEID_CPT6, "Intel Cougar Point watchdog timer", 10 }, 135 { DEVICEID_CPT7, "Intel Cougar Point watchdog timer", 10 }, 136 { DEVICEID_CPT8, "Intel Cougar Point watchdog timer", 10 }, 137 { DEVICEID_CPT9, "Intel Cougar Point watchdog timer", 10 }, 138 { DEVICEID_CPT10, "Intel Cougar Point watchdog timer", 10 }, 139 { DEVICEID_CPT11, "Intel Cougar Point watchdog timer", 10 }, 140 { DEVICEID_CPT12, "Intel Cougar Point watchdog timer", 10 }, 141 { DEVICEID_CPT13, "Intel Cougar Point watchdog timer", 10 }, 142 { DEVICEID_CPT14, "Intel Cougar Point watchdog timer", 10 }, 143 { DEVICEID_CPT15, "Intel Cougar Point watchdog timer", 10 }, 144 { DEVICEID_CPT16, "Intel Cougar Point watchdog timer", 10 }, 145 { DEVICEID_CPT17, "Intel Cougar Point watchdog timer", 10 }, 146 { DEVICEID_CPT18, "Intel Cougar Point watchdog timer", 10 }, 147 { DEVICEID_CPT19, "Intel Cougar Point watchdog timer", 10 }, 148 { DEVICEID_CPT20, "Intel Cougar Point watchdog timer", 10 }, 149 { DEVICEID_CPT21, "Intel Cougar Point watchdog timer", 10 }, 150 { DEVICEID_CPT22, "Intel Cougar Point watchdog timer", 10 }, 151 { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10 }, 152 { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10 }, 153 { DEVICEID_CPT25, "Intel Cougar Point watchdog timer", 10 }, 154 { DEVICEID_CPT26, "Intel Cougar Point watchdog timer", 10 }, 155 { DEVICEID_CPT27, "Intel Cougar Point watchdog timer", 10 }, 156 { DEVICEID_CPT28, "Intel Cougar Point watchdog timer", 10 }, 157 { DEVICEID_CPT29, "Intel Cougar Point watchdog timer", 10 }, 158 { DEVICEID_CPT30, "Intel Cougar Point watchdog timer", 10 }, 159 { DEVICEID_CPT31, "Intel Cougar Point watchdog timer", 10 }, 160 { DEVICEID_PATSBURG_LPC1, "Intel Patsburg watchdog timer", 10 }, 161 { DEVICEID_PATSBURG_LPC2, "Intel Patsburg watchdog timer", 10 }, 162 { DEVICEID_PPT0, "Intel Panther Point watchdog timer", 10 }, 163 { DEVICEID_PPT1, "Intel Panther Point watchdog timer", 10 }, 164 { DEVICEID_PPT2, "Intel Panther Point watchdog timer", 10 }, 165 { DEVICEID_PPT3, "Intel Panther Point watchdog timer", 10 }, 166 { DEVICEID_PPT4, "Intel Panther Point watchdog timer", 10 }, 167 { DEVICEID_PPT5, "Intel Panther Point watchdog timer", 10 }, 168 { DEVICEID_PPT6, "Intel Panther Point watchdog timer", 10 }, 169 { DEVICEID_PPT7, "Intel Panther Point watchdog timer", 10 }, 170 { DEVICEID_PPT8, "Intel Panther Point watchdog timer", 10 }, 171 { DEVICEID_PPT9, "Intel Panther Point watchdog timer", 10 }, 172 { DEVICEID_PPT10, "Intel Panther Point watchdog timer", 10 }, 173 { DEVICEID_PPT11, "Intel Panther Point watchdog timer", 10 }, 174 { DEVICEID_PPT12, "Intel Panther Point watchdog timer", 10 }, 175 { DEVICEID_PPT13, "Intel Panther Point watchdog timer", 10 }, 176 { DEVICEID_PPT14, "Intel Panther Point watchdog timer", 10 }, 177 { DEVICEID_PPT15, "Intel Panther Point watchdog timer", 10 }, 178 { DEVICEID_PPT16, "Intel Panther Point watchdog timer", 10 }, 179 { DEVICEID_PPT17, "Intel Panther Point watchdog timer", 10 }, 180 { DEVICEID_PPT18, "Intel Panther Point watchdog timer", 10 }, 181 { DEVICEID_PPT19, "Intel Panther Point watchdog timer", 10 }, 182 { DEVICEID_PPT20, "Intel Panther Point watchdog timer", 10 }, 183 { DEVICEID_PPT21, "Intel Panther Point watchdog timer", 10 }, 184 { DEVICEID_PPT22, "Intel Panther Point watchdog timer", 10 }, 185 { DEVICEID_PPT23, "Intel Panther Point watchdog timer", 10 }, 186 { DEVICEID_PPT24, "Intel Panther Point watchdog timer", 10 }, 187 { DEVICEID_PPT25, "Intel Panther Point watchdog timer", 10 }, 188 { DEVICEID_PPT26, "Intel Panther Point watchdog timer", 10 }, 189 { DEVICEID_PPT27, "Intel Panther Point watchdog timer", 10 }, 190 { DEVICEID_PPT28, "Intel Panther Point watchdog timer", 10 }, 191 { DEVICEID_PPT29, "Intel Panther Point watchdog timer", 10 }, 192 { DEVICEID_PPT30, "Intel Panther Point watchdog timer", 10 }, 193 { DEVICEID_PPT31, "Intel Panther Point watchdog timer", 10 }, 194 { DEVICEID_LPT0, "Intel Lynx Point watchdog timer", 10 }, 195 { DEVICEID_LPT1, "Intel Lynx Point watchdog timer", 10 }, 196 { DEVICEID_LPT2, "Intel Lynx Point watchdog timer", 10 }, 197 { DEVICEID_DH89XXCC_LPC, "Intel DH89xxCC watchdog timer", 10 }, 198 { DEVICEID_COLETOCRK_LPC, "Intel Coleto Creek watchdog timer", 10 }, 199 { 0, NULL, 0 }, 200 }; 201 202 static devclass_t ichwd_devclass; 203 204 #define ichwd_read_tco_1(sc, off) \ 205 bus_read_1((sc)->tco_res, (off)) 206 #define ichwd_read_tco_2(sc, off) \ 207 bus_read_2((sc)->tco_res, (off)) 208 #define ichwd_read_tco_4(sc, off) \ 209 bus_read_4((sc)->tco_res, (off)) 210 #define ichwd_read_smi_4(sc, off) \ 211 bus_read_4((sc)->smi_res, (off)) 212 #define ichwd_read_gcs_4(sc, off) \ 213 bus_read_4((sc)->gcs_res, (off)) 214 215 #define ichwd_write_tco_1(sc, off, val) \ 216 bus_write_1((sc)->tco_res, (off), (val)) 217 #define ichwd_write_tco_2(sc, off, val) \ 218 bus_write_2((sc)->tco_res, (off), (val)) 219 #define ichwd_write_tco_4(sc, off, val) \ 220 bus_write_4((sc)->tco_res, (off), (val)) 221 #define ichwd_write_smi_4(sc, off, val) \ 222 bus_write_4((sc)->smi_res, (off), (val)) 223 #define ichwd_write_gcs_4(sc, off, val) \ 224 bus_write_4((sc)->gcs_res, (off), (val)) 225 226 #define ichwd_verbose_printf(dev, ...) \ 227 do { \ 228 if (bootverbose) \ 229 device_printf(dev, __VA_ARGS__);\ 230 } while (0) 231 232 /* 233 * Disable the watchdog timeout SMI handler. 234 * 235 * Apparently, some BIOSes install handlers that reset or disable the 236 * watchdog timer instead of resetting the system, so we disable the SMI 237 * (by clearing the SMI_TCO_EN bit of the SMI_EN register) to prevent this 238 * from happening. 239 */ 240 static __inline void 241 ichwd_smi_disable(struct ichwd_softc *sc) 242 { 243 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN); 244 } 245 246 /* 247 * Enable the watchdog timeout SMI handler. See above for details. 248 */ 249 static __inline void 250 ichwd_smi_enable(struct ichwd_softc *sc) 251 { 252 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN); 253 } 254 255 /* 256 * Check if the watchdog SMI triggering is enabled. 257 */ 258 static __inline int 259 ichwd_smi_is_enabled(struct ichwd_softc *sc) 260 { 261 return ((ichwd_read_smi_4(sc, SMI_EN) & SMI_TCO_EN) != 0); 262 } 263 264 /* 265 * Reset the watchdog status bits. 266 */ 267 static __inline void 268 ichwd_sts_reset(struct ichwd_softc *sc) 269 { 270 /* 271 * The watchdog status bits are set to 1 by the hardware to 272 * indicate various conditions. They can be cleared by software 273 * by writing a 1, not a 0. 274 */ 275 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT); 276 /* 277 * According to Intel's docs, clearing SECOND_TO_STS and BOOT_STS must 278 * be done in two separate operations. 279 */ 280 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS); 281 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS); 282 } 283 284 /* 285 * Enable the watchdog timer by clearing the TCO_TMR_HALT bit in the 286 * TCO1_CNT register. This is complicated by the need to preserve bit 9 287 * of that same register, and the requirement that all other bits must be 288 * written back as zero. 289 */ 290 static __inline void 291 ichwd_tmr_enable(struct ichwd_softc *sc) 292 { 293 uint16_t cnt; 294 295 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 296 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT); 297 sc->active = 1; 298 ichwd_verbose_printf(sc->device, "timer enabled\n"); 299 } 300 301 /* 302 * Disable the watchdog timer. See above for details. 303 */ 304 static __inline void 305 ichwd_tmr_disable(struct ichwd_softc *sc) 306 { 307 uint16_t cnt; 308 309 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 310 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT); 311 sc->active = 0; 312 ichwd_verbose_printf(sc->device, "timer disabled\n"); 313 } 314 315 /* 316 * Reload the watchdog timer: writing anything to any of the lower five 317 * bits of the TCO_RLD register reloads the timer from the last value 318 * written to TCO_TMR. 319 */ 320 static __inline void 321 ichwd_tmr_reload(struct ichwd_softc *sc) 322 { 323 if (sc->ich_version <= 5) 324 ichwd_write_tco_1(sc, TCO_RLD, 1); 325 else 326 ichwd_write_tco_2(sc, TCO_RLD, 1); 327 } 328 329 /* 330 * Set the initial timeout value. Note that this must always be followed 331 * by a reload. 332 */ 333 static __inline void 334 ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout) 335 { 336 337 if (timeout < TCO_RLD_TMR_MIN) 338 timeout = TCO_RLD_TMR_MIN; 339 340 if (sc->ich_version <= 5) { 341 uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1); 342 343 tmr_val8 &= (~TCO_RLD1_TMR_MAX & 0xff); 344 if (timeout > TCO_RLD1_TMR_MAX) 345 timeout = TCO_RLD1_TMR_MAX; 346 tmr_val8 |= timeout; 347 ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8); 348 } else { 349 uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2); 350 351 tmr_val16 &= (~TCO_RLD2_TMR_MAX & 0xffff); 352 if (timeout > TCO_RLD2_TMR_MAX) 353 timeout = TCO_RLD2_TMR_MAX; 354 tmr_val16 |= timeout; 355 ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16); 356 } 357 358 sc->timeout = timeout; 359 360 ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout); 361 } 362 363 static __inline int 364 ichwd_clear_noreboot(struct ichwd_softc *sc) 365 { 366 uint32_t status; 367 int rc = 0; 368 369 /* try to clear the NO_REBOOT bit */ 370 if (sc->ich_version <= 5) { 371 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 372 status &= ~ICH_GEN_STA_NO_REBOOT; 373 pci_write_config(sc->ich, ICH_GEN_STA, status, 1); 374 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 375 if (status & ICH_GEN_STA_NO_REBOOT) 376 rc = EIO; 377 } else { 378 status = ichwd_read_gcs_4(sc, 0); 379 status &= ~ICH_GCS_NO_REBOOT; 380 ichwd_write_gcs_4(sc, 0, status); 381 status = ichwd_read_gcs_4(sc, 0); 382 if (status & ICH_GCS_NO_REBOOT) 383 rc = EIO; 384 } 385 386 if (rc) 387 device_printf(sc->device, 388 "ICH WDT present but disabled in BIOS or hardware\n"); 389 390 return (rc); 391 } 392 393 /* 394 * Watchdog event handler - called by the framework to enable or disable 395 * the watchdog or change the initial timeout value. 396 */ 397 static void 398 ichwd_event(void *arg, unsigned int cmd, int *error) 399 { 400 struct ichwd_softc *sc = arg; 401 unsigned int timeout; 402 403 /* convert from power-of-two-ns to WDT ticks */ 404 cmd &= WD_INTERVAL; 405 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK; 406 if (cmd) { 407 if (!sc->active) 408 ichwd_tmr_enable(sc); 409 if (timeout != sc->timeout) 410 ichwd_tmr_set(sc, timeout); 411 ichwd_tmr_reload(sc); 412 *error = 0; 413 } else { 414 if (sc->active) 415 ichwd_tmr_disable(sc); 416 } 417 } 418 419 static device_t 420 ichwd_find_ich_lpc_bridge(struct ichwd_device **id_p) 421 { 422 struct ichwd_device *id; 423 device_t ich = NULL; 424 425 /* look for an ICH LPC interface bridge */ 426 for (id = ichwd_devices; id->desc != NULL; ++id) 427 if ((ich = pci_find_device(VENDORID_INTEL, id->device)) != NULL) 428 break; 429 430 if (ich == NULL) 431 return (NULL); 432 433 ichwd_verbose_printf(ich, "found ICH%d or equivalent chipset: %s\n", 434 id->version, id->desc); 435 436 if (id_p) 437 *id_p = id; 438 439 return (ich); 440 } 441 442 /* 443 * Look for an ICH LPC interface bridge. If one is found, register an 444 * ichwd device. There can be only one. 445 */ 446 static void 447 ichwd_identify(driver_t *driver, device_t parent) 448 { 449 struct ichwd_device *id_p; 450 device_t ich = NULL; 451 device_t dev; 452 uint32_t rcba; 453 int rc; 454 455 ich = ichwd_find_ich_lpc_bridge(&id_p); 456 if (ich == NULL) 457 return; 458 459 /* good, add child to bus */ 460 if ((dev = device_find_child(parent, driver->name, 0)) == NULL) 461 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0); 462 463 if (dev == NULL) 464 return; 465 466 device_set_desc_copy(dev, id_p->desc); 467 468 if (id_p->version >= 6) { 469 /* get RCBA (root complex base address) */ 470 rcba = pci_read_config(ich, ICH_RCBA, 4); 471 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 472 (rcba & 0xffffc000) + ICH_GCS_OFFSET, ICH_GCS_SIZE); 473 if (rc) 474 ichwd_verbose_printf(dev, 475 "Can not set memory resource for RCBA\n"); 476 } 477 } 478 479 static int 480 ichwd_probe(device_t dev) 481 { 482 483 /* Do not claim some ISA PnP device by accident. */ 484 if (isa_get_logicalid(dev) != 0) 485 return (ENXIO); 486 return (0); 487 } 488 489 static int 490 ichwd_attach(device_t dev) 491 { 492 struct ichwd_softc *sc; 493 struct ichwd_device *id_p; 494 device_t ich; 495 unsigned int pmbase = 0; 496 497 sc = device_get_softc(dev); 498 sc->device = dev; 499 500 ich = ichwd_find_ich_lpc_bridge(&id_p); 501 if (ich == NULL) { 502 device_printf(sc->device, "Can not find ICH device.\n"); 503 goto fail; 504 } 505 sc->ich = ich; 506 sc->ich_version = id_p->version; 507 508 /* get ACPI base address */ 509 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK; 510 if (pmbase == 0) { 511 device_printf(dev, "ICH PMBASE register is empty\n"); 512 goto fail; 513 } 514 515 /* allocate I/O register space */ 516 sc->smi_rid = 0; 517 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 518 pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN, 519 RF_ACTIVE | RF_SHAREABLE); 520 if (sc->smi_res == NULL) { 521 device_printf(dev, "unable to reserve SMI registers\n"); 522 goto fail; 523 } 524 525 sc->tco_rid = 1; 526 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid, 527 pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN, 528 RF_ACTIVE | RF_SHAREABLE); 529 if (sc->tco_res == NULL) { 530 device_printf(dev, "unable to reserve TCO registers\n"); 531 goto fail; 532 } 533 534 sc->gcs_rid = 0; 535 if (sc->ich_version >= 6) { 536 sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY, 537 &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE); 538 if (sc->gcs_res == NULL) { 539 device_printf(dev, "unable to reserve GCS registers\n"); 540 goto fail; 541 } 542 } 543 544 if (ichwd_clear_noreboot(sc) != 0) 545 goto fail; 546 547 ichwd_verbose_printf(dev, "%s (ICH%d or equivalent)\n", 548 device_get_desc(dev), sc->ich_version); 549 550 /* 551 * Determine if we are coming up after a watchdog-induced reset. Some 552 * BIOSes may clear this bit at bootup, preventing us from reporting 553 * this case on such systems. We clear this bit in ichwd_sts_reset(). 554 */ 555 if ((ichwd_read_tco_2(sc, TCO2_STS) & TCO_SECOND_TO_STS) != 0) 556 device_printf(dev, 557 "resuming after hardware watchdog timeout\n"); 558 559 /* reset the watchdog status registers */ 560 ichwd_sts_reset(sc); 561 562 /* make sure the WDT starts out inactive */ 563 ichwd_tmr_disable(sc); 564 565 /* register the watchdog event handler */ 566 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0); 567 568 /* disable the SMI handler */ 569 sc->smi_enabled = ichwd_smi_is_enabled(sc); 570 ichwd_smi_disable(sc); 571 572 return (0); 573 fail: 574 sc = device_get_softc(dev); 575 if (sc->tco_res != NULL) 576 bus_release_resource(dev, SYS_RES_IOPORT, 577 sc->tco_rid, sc->tco_res); 578 if (sc->smi_res != NULL) 579 bus_release_resource(dev, SYS_RES_IOPORT, 580 sc->smi_rid, sc->smi_res); 581 if (sc->gcs_res != NULL) 582 bus_release_resource(ich, SYS_RES_MEMORY, 583 sc->gcs_rid, sc->gcs_res); 584 585 return (ENXIO); 586 } 587 588 static int 589 ichwd_detach(device_t dev) 590 { 591 struct ichwd_softc *sc; 592 device_t ich = NULL; 593 594 sc = device_get_softc(dev); 595 596 /* halt the watchdog timer */ 597 if (sc->active) 598 ichwd_tmr_disable(sc); 599 600 /* enable the SMI handler */ 601 if (sc->smi_enabled != 0) 602 ichwd_smi_enable(sc); 603 604 /* deregister event handler */ 605 if (sc->ev_tag != NULL) 606 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 607 sc->ev_tag = NULL; 608 609 /* reset the watchdog status registers */ 610 ichwd_sts_reset(sc); 611 612 /* deallocate I/O register space */ 613 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res); 614 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res); 615 616 /* deallocate memory resource */ 617 ich = ichwd_find_ich_lpc_bridge(NULL); 618 if (sc->gcs_res && ich) 619 bus_release_resource(ich, SYS_RES_MEMORY, sc->gcs_rid, sc->gcs_res); 620 621 return (0); 622 } 623 624 static device_method_t ichwd_methods[] = { 625 DEVMETHOD(device_identify, ichwd_identify), 626 DEVMETHOD(device_probe, ichwd_probe), 627 DEVMETHOD(device_attach, ichwd_attach), 628 DEVMETHOD(device_detach, ichwd_detach), 629 DEVMETHOD(device_shutdown, ichwd_detach), 630 {0,0} 631 }; 632 633 static driver_t ichwd_driver = { 634 "ichwd", 635 ichwd_methods, 636 sizeof(struct ichwd_softc), 637 }; 638 639 DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, NULL, NULL); 640