1 /*- 2 * Copyright (c) 2004 Texas A&M University 3 * All rights reserved. 4 * 5 * Developer: Wm. Daryl Hawkins 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Intel ICH Watchdog Timer (WDT) driver 31 * 32 * Originally developed by Wm. Daryl Hawkins of Texas A&M 33 * Heavily modified by <des@FreeBSD.org> 34 * 35 * This is a tricky one. The ICH WDT can't be treated as a regular PCI 36 * device as it's actually an integrated function of the ICH LPC interface 37 * bridge. Detection is also awkward, because we can only infer the 38 * presence of the watchdog timer from the fact that the machine has an 39 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT' 40 * ACPI table (although this driver does not support the ACPI detection 41 * method). 42 * 43 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no 44 * way of knowing if the WDT is permanently disabled (either by the BIOS 45 * or in hardware). 46 * 47 * The WDT is programmed through I/O registers in the ACPI I/O space. 48 * Intel swears it's always at offset 0x60, so we use that. 49 * 50 * For details about the ICH WDT, see Intel Application Note AP-725 51 * (document no. 292273-001). The WDT is also described in the individual 52 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet 53 * (document no. 252516-001) sections 9.10 and 9.11. 54 * 55 * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp> 56 */ 57 58 #include <sys/cdefs.h> 59 __FBSDID("$FreeBSD$"); 60 61 #include <sys/param.h> 62 #include <sys/kernel.h> 63 #include <sys/module.h> 64 #include <sys/systm.h> 65 #include <sys/bus.h> 66 #include <machine/bus.h> 67 #include <sys/rman.h> 68 #include <machine/resource.h> 69 #include <sys/watchdog.h> 70 71 #include <isa/isavar.h> 72 #include <dev/pci/pcivar.h> 73 74 #include <dev/ichwd/ichwd.h> 75 76 static struct ichwd_device ichwd_devices[] = { 77 { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1 }, 78 { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1 }, 79 { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2 }, 80 { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2 }, 81 { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3 }, 82 { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3 }, 83 { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4 }, 84 { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4 }, 85 { DEVICEID_82801E, "Intel 82801E watchdog timer", 5 }, 86 { DEVICEID_82801EB, "Intel 82801EB watchdog timer", 5 }, 87 { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5 }, 88 { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5 }, 89 { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6 }, 90 { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6 }, 91 { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6 }, 92 { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7 }, 93 { DEVICEID_ICH7DH, "Intel ICH7DH watchdog timer", 7 }, 94 { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7 }, 95 { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7 }, 96 { DEVICEID_NM10, "Intel NM10 watchdog timer", 7 }, 97 { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8 }, 98 { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8 }, 99 { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8 }, 100 { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8 }, 101 { DEVICEID_ICH8ME, "Intel ICH8M-E watchdog timer", 8 }, 102 { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8 }, 103 { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9 }, 104 { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9 }, 105 { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9 }, 106 { DEVICEID_ICH9M, "Intel ICH9M watchdog timer", 9 }, 107 { DEVICEID_ICH9ME, "Intel ICH9M-E watchdog timer", 9 }, 108 { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9 }, 109 { DEVICEID_ICH10, "Intel ICH10 watchdog timer", 10 }, 110 { DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10 }, 111 { DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10 }, 112 { DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10 }, 113 { DEVICEID_PCH, "Intel PCH watchdog timer", 10 }, 114 { DEVICEID_PCHM, "Intel PCH watchdog timer", 10 }, 115 { DEVICEID_P55, "Intel P55 watchdog timer", 10 }, 116 { DEVICEID_PM55, "Intel PM55 watchdog timer", 10 }, 117 { DEVICEID_H55, "Intel H55 watchdog timer", 10 }, 118 { DEVICEID_QM57, "Intel QM57 watchdog timer", 10 }, 119 { DEVICEID_H57, "Intel H57 watchdog timer", 10 }, 120 { DEVICEID_HM55, "Intel HM55 watchdog timer", 10 }, 121 { DEVICEID_Q57, "Intel Q57 watchdog timer", 10 }, 122 { DEVICEID_HM57, "Intel HM57 watchdog timer", 10 }, 123 { DEVICEID_PCHMSFF, "Intel PCHMSFF watchdog timer", 10 }, 124 { DEVICEID_QS57, "Intel QS57 watchdog timer", 10 }, 125 { DEVICEID_3400, "Intel 3400 watchdog timer", 10 }, 126 { DEVICEID_3420, "Intel 3420 watchdog timer", 10 }, 127 { DEVICEID_3450, "Intel 3450 watchdog timer", 10 }, 128 { DEVICEID_CPT0, "Intel Cougar Point watchdog timer", 10 }, 129 { DEVICEID_CPT1, "Intel Cougar Point watchdog timer", 10 }, 130 { DEVICEID_CPT2, "Intel Cougar Point watchdog timer", 10 }, 131 { DEVICEID_CPT3, "Intel Cougar Point watchdog timer", 10 }, 132 { DEVICEID_CPT4, "Intel Cougar Point watchdog timer", 10 }, 133 { DEVICEID_CPT5, "Intel Cougar Point watchdog timer", 10 }, 134 { DEVICEID_CPT6, "Intel Cougar Point watchdog timer", 10 }, 135 { DEVICEID_CPT7, "Intel Cougar Point watchdog timer", 10 }, 136 { DEVICEID_CPT8, "Intel Cougar Point watchdog timer", 10 }, 137 { DEVICEID_CPT9, "Intel Cougar Point watchdog timer", 10 }, 138 { DEVICEID_CPT10, "Intel Cougar Point watchdog timer", 10 }, 139 { DEVICEID_CPT11, "Intel Cougar Point watchdog timer", 10 }, 140 { DEVICEID_CPT12, "Intel Cougar Point watchdog timer", 10 }, 141 { DEVICEID_CPT13, "Intel Cougar Point watchdog timer", 10 }, 142 { DEVICEID_CPT14, "Intel Cougar Point watchdog timer", 10 }, 143 { DEVICEID_CPT15, "Intel Cougar Point watchdog timer", 10 }, 144 { DEVICEID_CPT16, "Intel Cougar Point watchdog timer", 10 }, 145 { DEVICEID_CPT17, "Intel Cougar Point watchdog timer", 10 }, 146 { DEVICEID_CPT18, "Intel Cougar Point watchdog timer", 10 }, 147 { DEVICEID_CPT19, "Intel Cougar Point watchdog timer", 10 }, 148 { DEVICEID_CPT20, "Intel Cougar Point watchdog timer", 10 }, 149 { DEVICEID_CPT21, "Intel Cougar Point watchdog timer", 10 }, 150 { DEVICEID_CPT22, "Intel Cougar Point watchdog timer", 10 }, 151 { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10 }, 152 { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10 }, 153 { DEVICEID_CPT25, "Intel Cougar Point watchdog timer", 10 }, 154 { DEVICEID_CPT26, "Intel Cougar Point watchdog timer", 10 }, 155 { DEVICEID_CPT27, "Intel Cougar Point watchdog timer", 10 }, 156 { DEVICEID_CPT28, "Intel Cougar Point watchdog timer", 10 }, 157 { DEVICEID_CPT29, "Intel Cougar Point watchdog timer", 10 }, 158 { DEVICEID_CPT30, "Intel Cougar Point watchdog timer", 10 }, 159 { DEVICEID_CPT31, "Intel Cougar Point watchdog timer", 10 }, 160 { DEVICEID_PATSBURG_LPC1, "Intel Patsburg watchdog timer", 10 }, 161 { DEVICEID_PATSBURG_LPC2, "Intel Patsburg watchdog timer", 10 }, 162 { DEVICEID_PPT0, "Intel Panther Point watchdog timer", 10 }, 163 { DEVICEID_PPT1, "Intel Panther Point watchdog timer", 10 }, 164 { DEVICEID_PPT2, "Intel Panther Point watchdog timer", 10 }, 165 { DEVICEID_PPT3, "Intel Panther Point watchdog timer", 10 }, 166 { DEVICEID_PPT4, "Intel Panther Point watchdog timer", 10 }, 167 { DEVICEID_PPT5, "Intel Panther Point watchdog timer", 10 }, 168 { DEVICEID_PPT6, "Intel Panther Point watchdog timer", 10 }, 169 { DEVICEID_PPT7, "Intel Panther Point watchdog timer", 10 }, 170 { DEVICEID_PPT8, "Intel Panther Point watchdog timer", 10 }, 171 { DEVICEID_PPT9, "Intel Panther Point watchdog timer", 10 }, 172 { DEVICEID_PPT10, "Intel Panther Point watchdog timer", 10 }, 173 { DEVICEID_PPT11, "Intel Panther Point watchdog timer", 10 }, 174 { DEVICEID_PPT12, "Intel Panther Point watchdog timer", 10 }, 175 { DEVICEID_PPT13, "Intel Panther Point watchdog timer", 10 }, 176 { DEVICEID_PPT14, "Intel Panther Point watchdog timer", 10 }, 177 { DEVICEID_PPT15, "Intel Panther Point watchdog timer", 10 }, 178 { DEVICEID_PPT16, "Intel Panther Point watchdog timer", 10 }, 179 { DEVICEID_PPT17, "Intel Panther Point watchdog timer", 10 }, 180 { DEVICEID_PPT18, "Intel Panther Point watchdog timer", 10 }, 181 { DEVICEID_PPT19, "Intel Panther Point watchdog timer", 10 }, 182 { DEVICEID_PPT20, "Intel Panther Point watchdog timer", 10 }, 183 { DEVICEID_PPT21, "Intel Panther Point watchdog timer", 10 }, 184 { DEVICEID_PPT22, "Intel Panther Point watchdog timer", 10 }, 185 { DEVICEID_PPT23, "Intel Panther Point watchdog timer", 10 }, 186 { DEVICEID_PPT24, "Intel Panther Point watchdog timer", 10 }, 187 { DEVICEID_PPT25, "Intel Panther Point watchdog timer", 10 }, 188 { DEVICEID_PPT26, "Intel Panther Point watchdog timer", 10 }, 189 { DEVICEID_PPT27, "Intel Panther Point watchdog timer", 10 }, 190 { DEVICEID_PPT28, "Intel Panther Point watchdog timer", 10 }, 191 { DEVICEID_PPT29, "Intel Panther Point watchdog timer", 10 }, 192 { DEVICEID_PPT30, "Intel Panther Point watchdog timer", 10 }, 193 { DEVICEID_PPT31, "Intel Panther Point watchdog timer", 10 }, 194 { DEVICEID_LPT0, "Intel Lynx Point watchdog timer", 10 }, 195 { DEVICEID_LPT1, "Intel Lynx Point watchdog timer", 10 }, 196 { DEVICEID_LPT2, "Intel Lynx Point watchdog timer", 10 }, 197 { DEVICEID_LPT3, "Intel Lynx Point watchdog timer", 10 }, 198 { DEVICEID_LPT4, "Intel Lynx Point watchdog timer", 10 }, 199 { DEVICEID_LPT5, "Intel Lynx Point watchdog timer", 10 }, 200 { DEVICEID_LPT6, "Intel Lynx Point watchdog timer", 10 }, 201 { DEVICEID_LPT7, "Intel Lynx Point watchdog timer", 10 }, 202 { DEVICEID_LPT8, "Intel Lynx Point watchdog timer", 10 }, 203 { DEVICEID_LPT9, "Intel Lynx Point watchdog timer", 10 }, 204 { DEVICEID_LPT10, "Intel Lynx Point watchdog timer", 10 }, 205 { DEVICEID_LPT11, "Intel Lynx Point watchdog timer", 10 }, 206 { DEVICEID_LPT12, "Intel Lynx Point watchdog timer", 10 }, 207 { DEVICEID_LPT13, "Intel Lynx Point watchdog timer", 10 }, 208 { DEVICEID_LPT14, "Intel Lynx Point watchdog timer", 10 }, 209 { DEVICEID_LPT15, "Intel Lynx Point watchdog timer", 10 }, 210 { DEVICEID_LPT16, "Intel Lynx Point watchdog timer", 10 }, 211 { DEVICEID_LPT17, "Intel Lynx Point watchdog timer", 10 }, 212 { DEVICEID_LPT18, "Intel Lynx Point watchdog timer", 10 }, 213 { DEVICEID_LPT19, "Intel Lynx Point watchdog timer", 10 }, 214 { DEVICEID_LPT20, "Intel Lynx Point watchdog timer", 10 }, 215 { DEVICEID_LPT21, "Intel Lynx Point watchdog timer", 10 }, 216 { DEVICEID_LPT22, "Intel Lynx Point watchdog timer", 10 }, 217 { DEVICEID_LPT23, "Intel Lynx Point watchdog timer", 10 }, 218 { DEVICEID_LPT24, "Intel Lynx Point watchdog timer", 10 }, 219 { DEVICEID_LPT25, "Intel Lynx Point watchdog timer", 10 }, 220 { DEVICEID_LPT26, "Intel Lynx Point watchdog timer", 10 }, 221 { DEVICEID_LPT27, "Intel Lynx Point watchdog timer", 10 }, 222 { DEVICEID_LPT28, "Intel Lynx Point watchdog timer", 10 }, 223 { DEVICEID_LPT29, "Intel Lynx Point watchdog timer", 10 }, 224 { DEVICEID_LPT30, "Intel Lynx Point watchdog timer", 10 }, 225 { DEVICEID_LPT31, "Intel Lynx Point watchdog timer", 10 }, 226 { DEVICEID_WCPT2, "Intel Wildcat Point watchdog timer", 10 }, 227 { DEVICEID_WCPT4, "Intel Wildcat Point watchdog timer", 10 }, 228 { DEVICEID_WCPT6, "Intel Wildcat Point watchdog timer", 10 }, 229 { DEVICEID_DH89XXCC_LPC, "Intel DH89xxCC watchdog timer", 10 }, 230 { DEVICEID_COLETOCRK_LPC, "Intel Coleto Creek watchdog timer", 10 }, 231 { 0, NULL, 0 }, 232 }; 233 234 static devclass_t ichwd_devclass; 235 236 #define ichwd_read_tco_1(sc, off) \ 237 bus_read_1((sc)->tco_res, (off)) 238 #define ichwd_read_tco_2(sc, off) \ 239 bus_read_2((sc)->tco_res, (off)) 240 #define ichwd_read_tco_4(sc, off) \ 241 bus_read_4((sc)->tco_res, (off)) 242 #define ichwd_read_smi_4(sc, off) \ 243 bus_read_4((sc)->smi_res, (off)) 244 #define ichwd_read_gcs_4(sc, off) \ 245 bus_read_4((sc)->gcs_res, (off)) 246 247 #define ichwd_write_tco_1(sc, off, val) \ 248 bus_write_1((sc)->tco_res, (off), (val)) 249 #define ichwd_write_tco_2(sc, off, val) \ 250 bus_write_2((sc)->tco_res, (off), (val)) 251 #define ichwd_write_tco_4(sc, off, val) \ 252 bus_write_4((sc)->tco_res, (off), (val)) 253 #define ichwd_write_smi_4(sc, off, val) \ 254 bus_write_4((sc)->smi_res, (off), (val)) 255 #define ichwd_write_gcs_4(sc, off, val) \ 256 bus_write_4((sc)->gcs_res, (off), (val)) 257 258 #define ichwd_verbose_printf(dev, ...) \ 259 do { \ 260 if (bootverbose) \ 261 device_printf(dev, __VA_ARGS__);\ 262 } while (0) 263 264 /* 265 * Disable the watchdog timeout SMI handler. 266 * 267 * Apparently, some BIOSes install handlers that reset or disable the 268 * watchdog timer instead of resetting the system, so we disable the SMI 269 * (by clearing the SMI_TCO_EN bit of the SMI_EN register) to prevent this 270 * from happening. 271 */ 272 static __inline void 273 ichwd_smi_disable(struct ichwd_softc *sc) 274 { 275 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN); 276 } 277 278 /* 279 * Enable the watchdog timeout SMI handler. See above for details. 280 */ 281 static __inline void 282 ichwd_smi_enable(struct ichwd_softc *sc) 283 { 284 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN); 285 } 286 287 /* 288 * Check if the watchdog SMI triggering is enabled. 289 */ 290 static __inline int 291 ichwd_smi_is_enabled(struct ichwd_softc *sc) 292 { 293 return ((ichwd_read_smi_4(sc, SMI_EN) & SMI_TCO_EN) != 0); 294 } 295 296 /* 297 * Reset the watchdog status bits. 298 */ 299 static __inline void 300 ichwd_sts_reset(struct ichwd_softc *sc) 301 { 302 /* 303 * The watchdog status bits are set to 1 by the hardware to 304 * indicate various conditions. They can be cleared by software 305 * by writing a 1, not a 0. 306 */ 307 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT); 308 /* 309 * According to Intel's docs, clearing SECOND_TO_STS and BOOT_STS must 310 * be done in two separate operations. 311 */ 312 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS); 313 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS); 314 } 315 316 /* 317 * Enable the watchdog timer by clearing the TCO_TMR_HALT bit in the 318 * TCO1_CNT register. This is complicated by the need to preserve bit 9 319 * of that same register, and the requirement that all other bits must be 320 * written back as zero. 321 */ 322 static __inline void 323 ichwd_tmr_enable(struct ichwd_softc *sc) 324 { 325 uint16_t cnt; 326 327 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 328 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT); 329 sc->active = 1; 330 ichwd_verbose_printf(sc->device, "timer enabled\n"); 331 } 332 333 /* 334 * Disable the watchdog timer. See above for details. 335 */ 336 static __inline void 337 ichwd_tmr_disable(struct ichwd_softc *sc) 338 { 339 uint16_t cnt; 340 341 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 342 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT); 343 sc->active = 0; 344 ichwd_verbose_printf(sc->device, "timer disabled\n"); 345 } 346 347 /* 348 * Reload the watchdog timer: writing anything to any of the lower five 349 * bits of the TCO_RLD register reloads the timer from the last value 350 * written to TCO_TMR. 351 */ 352 static __inline void 353 ichwd_tmr_reload(struct ichwd_softc *sc) 354 { 355 if (sc->ich_version <= 5) 356 ichwd_write_tco_1(sc, TCO_RLD, 1); 357 else 358 ichwd_write_tco_2(sc, TCO_RLD, 1); 359 } 360 361 /* 362 * Set the initial timeout value. Note that this must always be followed 363 * by a reload. 364 */ 365 static __inline void 366 ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout) 367 { 368 369 if (timeout < TCO_RLD_TMR_MIN) 370 timeout = TCO_RLD_TMR_MIN; 371 372 if (sc->ich_version <= 5) { 373 uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1); 374 375 tmr_val8 &= (~TCO_RLD1_TMR_MAX & 0xff); 376 if (timeout > TCO_RLD1_TMR_MAX) 377 timeout = TCO_RLD1_TMR_MAX; 378 tmr_val8 |= timeout; 379 ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8); 380 } else { 381 uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2); 382 383 tmr_val16 &= (~TCO_RLD2_TMR_MAX & 0xffff); 384 if (timeout > TCO_RLD2_TMR_MAX) 385 timeout = TCO_RLD2_TMR_MAX; 386 tmr_val16 |= timeout; 387 ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16); 388 } 389 390 sc->timeout = timeout; 391 392 ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout); 393 } 394 395 static __inline int 396 ichwd_clear_noreboot(struct ichwd_softc *sc) 397 { 398 uint32_t status; 399 int rc = 0; 400 401 /* try to clear the NO_REBOOT bit */ 402 if (sc->ich_version <= 5) { 403 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 404 status &= ~ICH_GEN_STA_NO_REBOOT; 405 pci_write_config(sc->ich, ICH_GEN_STA, status, 1); 406 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 407 if (status & ICH_GEN_STA_NO_REBOOT) 408 rc = EIO; 409 } else { 410 status = ichwd_read_gcs_4(sc, 0); 411 status &= ~ICH_GCS_NO_REBOOT; 412 ichwd_write_gcs_4(sc, 0, status); 413 status = ichwd_read_gcs_4(sc, 0); 414 if (status & ICH_GCS_NO_REBOOT) 415 rc = EIO; 416 } 417 418 if (rc) 419 device_printf(sc->device, 420 "ICH WDT present but disabled in BIOS or hardware\n"); 421 422 return (rc); 423 } 424 425 /* 426 * Watchdog event handler - called by the framework to enable or disable 427 * the watchdog or change the initial timeout value. 428 */ 429 static void 430 ichwd_event(void *arg, unsigned int cmd, int *error) 431 { 432 struct ichwd_softc *sc = arg; 433 unsigned int timeout; 434 435 /* convert from power-of-two-ns to WDT ticks */ 436 cmd &= WD_INTERVAL; 437 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK; 438 if (cmd) { 439 if (!sc->active) 440 ichwd_tmr_enable(sc); 441 if (timeout != sc->timeout) 442 ichwd_tmr_set(sc, timeout); 443 ichwd_tmr_reload(sc); 444 *error = 0; 445 } else { 446 if (sc->active) 447 ichwd_tmr_disable(sc); 448 } 449 } 450 451 static device_t 452 ichwd_find_ich_lpc_bridge(struct ichwd_device **id_p) 453 { 454 struct ichwd_device *id; 455 device_t ich = NULL; 456 457 /* look for an ICH LPC interface bridge */ 458 for (id = ichwd_devices; id->desc != NULL; ++id) 459 if ((ich = pci_find_device(VENDORID_INTEL, id->device)) != NULL) 460 break; 461 462 if (ich == NULL) 463 return (NULL); 464 465 ichwd_verbose_printf(ich, "found ICH%d or equivalent chipset: %s\n", 466 id->version, id->desc); 467 468 if (id_p) 469 *id_p = id; 470 471 return (ich); 472 } 473 474 /* 475 * Look for an ICH LPC interface bridge. If one is found, register an 476 * ichwd device. There can be only one. 477 */ 478 static void 479 ichwd_identify(driver_t *driver, device_t parent) 480 { 481 struct ichwd_device *id_p; 482 device_t ich = NULL; 483 device_t dev; 484 uint32_t rcba; 485 int rc; 486 487 ich = ichwd_find_ich_lpc_bridge(&id_p); 488 if (ich == NULL) 489 return; 490 491 /* good, add child to bus */ 492 if ((dev = device_find_child(parent, driver->name, 0)) == NULL) 493 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0); 494 495 if (dev == NULL) 496 return; 497 498 device_set_desc_copy(dev, id_p->desc); 499 500 if (id_p->version >= 6) { 501 /* get RCBA (root complex base address) */ 502 rcba = pci_read_config(ich, ICH_RCBA, 4); 503 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 504 (rcba & 0xffffc000) + ICH_GCS_OFFSET, ICH_GCS_SIZE); 505 if (rc) 506 ichwd_verbose_printf(dev, 507 "Can not set memory resource for RCBA\n"); 508 } 509 } 510 511 static int 512 ichwd_probe(device_t dev) 513 { 514 515 /* Do not claim some ISA PnP device by accident. */ 516 if (isa_get_logicalid(dev) != 0) 517 return (ENXIO); 518 return (0); 519 } 520 521 static int 522 ichwd_attach(device_t dev) 523 { 524 struct ichwd_softc *sc; 525 struct ichwd_device *id_p; 526 device_t ich; 527 unsigned int pmbase = 0; 528 529 sc = device_get_softc(dev); 530 sc->device = dev; 531 532 ich = ichwd_find_ich_lpc_bridge(&id_p); 533 if (ich == NULL) { 534 device_printf(sc->device, "Can not find ICH device.\n"); 535 goto fail; 536 } 537 sc->ich = ich; 538 sc->ich_version = id_p->version; 539 540 /* get ACPI base address */ 541 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK; 542 if (pmbase == 0) { 543 device_printf(dev, "ICH PMBASE register is empty\n"); 544 goto fail; 545 } 546 547 /* allocate I/O register space */ 548 sc->smi_rid = 0; 549 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 550 pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN, 551 RF_ACTIVE | RF_SHAREABLE); 552 if (sc->smi_res == NULL) { 553 device_printf(dev, "unable to reserve SMI registers\n"); 554 goto fail; 555 } 556 557 sc->tco_rid = 1; 558 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid, 559 pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN, 560 RF_ACTIVE | RF_SHAREABLE); 561 if (sc->tco_res == NULL) { 562 device_printf(dev, "unable to reserve TCO registers\n"); 563 goto fail; 564 } 565 566 sc->gcs_rid = 0; 567 if (sc->ich_version >= 6) { 568 sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY, 569 &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE); 570 if (sc->gcs_res == NULL) { 571 device_printf(dev, "unable to reserve GCS registers\n"); 572 goto fail; 573 } 574 } 575 576 if (ichwd_clear_noreboot(sc) != 0) 577 goto fail; 578 579 ichwd_verbose_printf(dev, "%s (ICH%d or equivalent)\n", 580 device_get_desc(dev), sc->ich_version); 581 582 /* 583 * Determine if we are coming up after a watchdog-induced reset. Some 584 * BIOSes may clear this bit at bootup, preventing us from reporting 585 * this case on such systems. We clear this bit in ichwd_sts_reset(). 586 */ 587 if ((ichwd_read_tco_2(sc, TCO2_STS) & TCO_SECOND_TO_STS) != 0) 588 device_printf(dev, 589 "resuming after hardware watchdog timeout\n"); 590 591 /* reset the watchdog status registers */ 592 ichwd_sts_reset(sc); 593 594 /* make sure the WDT starts out inactive */ 595 ichwd_tmr_disable(sc); 596 597 /* register the watchdog event handler */ 598 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0); 599 600 /* disable the SMI handler */ 601 sc->smi_enabled = ichwd_smi_is_enabled(sc); 602 ichwd_smi_disable(sc); 603 604 return (0); 605 fail: 606 sc = device_get_softc(dev); 607 if (sc->tco_res != NULL) 608 bus_release_resource(dev, SYS_RES_IOPORT, 609 sc->tco_rid, sc->tco_res); 610 if (sc->smi_res != NULL) 611 bus_release_resource(dev, SYS_RES_IOPORT, 612 sc->smi_rid, sc->smi_res); 613 if (sc->gcs_res != NULL) 614 bus_release_resource(ich, SYS_RES_MEMORY, 615 sc->gcs_rid, sc->gcs_res); 616 617 return (ENXIO); 618 } 619 620 static int 621 ichwd_detach(device_t dev) 622 { 623 struct ichwd_softc *sc; 624 device_t ich = NULL; 625 626 sc = device_get_softc(dev); 627 628 /* halt the watchdog timer */ 629 if (sc->active) 630 ichwd_tmr_disable(sc); 631 632 /* enable the SMI handler */ 633 if (sc->smi_enabled != 0) 634 ichwd_smi_enable(sc); 635 636 /* deregister event handler */ 637 if (sc->ev_tag != NULL) 638 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 639 sc->ev_tag = NULL; 640 641 /* reset the watchdog status registers */ 642 ichwd_sts_reset(sc); 643 644 /* deallocate I/O register space */ 645 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res); 646 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res); 647 648 /* deallocate memory resource */ 649 ich = ichwd_find_ich_lpc_bridge(NULL); 650 if (sc->gcs_res && ich) 651 bus_release_resource(ich, SYS_RES_MEMORY, sc->gcs_rid, sc->gcs_res); 652 653 return (0); 654 } 655 656 static device_method_t ichwd_methods[] = { 657 DEVMETHOD(device_identify, ichwd_identify), 658 DEVMETHOD(device_probe, ichwd_probe), 659 DEVMETHOD(device_attach, ichwd_attach), 660 DEVMETHOD(device_detach, ichwd_detach), 661 DEVMETHOD(device_shutdown, ichwd_detach), 662 {0,0} 663 }; 664 665 static driver_t ichwd_driver = { 666 "ichwd", 667 ichwd_methods, 668 sizeof(struct ichwd_softc), 669 }; 670 671 DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, NULL, NULL); 672