1 /*- 2 * Copyright (c) 2004 Texas A&M University 3 * All rights reserved. 4 * 5 * Developer: Wm. Daryl Hawkins 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Intel ICH Watchdog Timer (WDT) driver 31 * 32 * Originally developed by Wm. Daryl Hawkins of Texas A&M 33 * Heavily modified by <des@FreeBSD.org> 34 * 35 * This is a tricky one. The ICH WDT can't be treated as a regular PCI 36 * device as it's actually an integrated function of the ICH LPC interface 37 * bridge. Detection is also awkward, because we can only infer the 38 * presence of the watchdog timer from the fact that the machine has an 39 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT' 40 * ACPI table (although this driver does not support the ACPI detection 41 * method). 42 * 43 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no 44 * way of knowing if the WDT is permanently disabled (either by the BIOS 45 * or in hardware). 46 * 47 * The WDT is programmed through I/O registers in the ACPI I/O space. 48 * Intel swears it's always at offset 0x60, so we use that. 49 * 50 * For details about the ICH WDT, see Intel Application Note AP-725 51 * (document no. 292273-001). The WDT is also described in the individual 52 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet 53 * (document no. 252516-001) sections 9.10 and 9.11. 54 * 55 * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp> 56 */ 57 58 #include <sys/cdefs.h> 59 __FBSDID("$FreeBSD$"); 60 61 #include <sys/param.h> 62 #include <sys/kernel.h> 63 #include <sys/module.h> 64 #include <sys/systm.h> 65 #include <sys/bus.h> 66 #include <machine/bus.h> 67 #include <sys/rman.h> 68 #include <machine/resource.h> 69 #include <sys/watchdog.h> 70 71 #include <isa/isavar.h> 72 #include <dev/pci/pcivar.h> 73 74 #include <dev/ichwd/ichwd.h> 75 76 static struct ichwd_device ichwd_devices[] = { 77 { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1 }, 78 { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1 }, 79 { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2 }, 80 { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2 }, 81 { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3 }, 82 { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3 }, 83 { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4 }, 84 { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4 }, 85 { DEVICEID_82801E, "Intel 82801E watchdog timer", 5 }, 86 { DEVICEID_82801EB, "Intel 82801EB watchdog timer", 5 }, 87 { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5 }, 88 { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5 }, 89 { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6 }, 90 { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6 }, 91 { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6 }, 92 { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7 }, 93 { DEVICEID_ICH7DH, "Intel ICH7DH watchdog timer", 7 }, 94 { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7 }, 95 { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7 }, 96 { DEVICEID_NM10, "Intel NM10 watchdog timer", 7 }, 97 { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8 }, 98 { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8 }, 99 { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8 }, 100 { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8 }, 101 { DEVICEID_ICH8ME, "Intel ICH8M-E watchdog timer", 8 }, 102 { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8 }, 103 { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9 }, 104 { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9 }, 105 { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9 }, 106 { DEVICEID_ICH9M, "Intel ICH9M watchdog timer", 9 }, 107 { DEVICEID_ICH9ME, "Intel ICH9M-E watchdog timer", 9 }, 108 { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9 }, 109 { DEVICEID_ICH10, "Intel ICH10 watchdog timer", 10 }, 110 { DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10 }, 111 { DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10 }, 112 { DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10 }, 113 { DEVICEID_PCH, "Intel PCH watchdog timer", 10 }, 114 { DEVICEID_PCHM, "Intel PCH watchdog timer", 10 }, 115 { DEVICEID_P55, "Intel P55 watchdog timer", 10 }, 116 { DEVICEID_PM55, "Intel PM55 watchdog timer", 10 }, 117 { DEVICEID_H55, "Intel H55 watchdog timer", 10 }, 118 { DEVICEID_QM57, "Intel QM57 watchdog timer", 10 }, 119 { DEVICEID_H57, "Intel H57 watchdog timer", 10 }, 120 { DEVICEID_HM55, "Intel HM55 watchdog timer", 10 }, 121 { DEVICEID_Q57, "Intel Q57 watchdog timer", 10 }, 122 { DEVICEID_HM57, "Intel HM57 watchdog timer", 10 }, 123 { DEVICEID_PCHMSFF, "Intel PCHMSFF watchdog timer", 10 }, 124 { DEVICEID_QS57, "Intel QS57 watchdog timer", 10 }, 125 { DEVICEID_3400, "Intel 3400 watchdog timer", 10 }, 126 { DEVICEID_3420, "Intel 3420 watchdog timer", 10 }, 127 { DEVICEID_3450, "Intel 3450 watchdog timer", 10 }, 128 { DEVICEID_CPT0, "Intel Cougar Point watchdog timer", 10 }, 129 { DEVICEID_CPT1, "Intel Cougar Point watchdog timer", 10 }, 130 { DEVICEID_CPT2, "Intel Cougar Point watchdog timer", 10 }, 131 { DEVICEID_CPT3, "Intel Cougar Point watchdog timer", 10 }, 132 { DEVICEID_CPT4, "Intel Cougar Point watchdog timer", 10 }, 133 { DEVICEID_CPT5, "Intel Cougar Point watchdog timer", 10 }, 134 { DEVICEID_CPT6, "Intel Cougar Point watchdog timer", 10 }, 135 { DEVICEID_CPT7, "Intel Cougar Point watchdog timer", 10 }, 136 { DEVICEID_CPT8, "Intel Cougar Point watchdog timer", 10 }, 137 { DEVICEID_CPT9, "Intel Cougar Point watchdog timer", 10 }, 138 { DEVICEID_CPT10, "Intel Cougar Point watchdog timer", 10 }, 139 { DEVICEID_CPT11, "Intel Cougar Point watchdog timer", 10 }, 140 { DEVICEID_CPT12, "Intel Cougar Point watchdog timer", 10 }, 141 { DEVICEID_CPT13, "Intel Cougar Point watchdog timer", 10 }, 142 { DEVICEID_CPT14, "Intel Cougar Point watchdog timer", 10 }, 143 { DEVICEID_CPT15, "Intel Cougar Point watchdog timer", 10 }, 144 { DEVICEID_CPT16, "Intel Cougar Point watchdog timer", 10 }, 145 { DEVICEID_CPT17, "Intel Cougar Point watchdog timer", 10 }, 146 { DEVICEID_CPT18, "Intel Cougar Point watchdog timer", 10 }, 147 { DEVICEID_CPT19, "Intel Cougar Point watchdog timer", 10 }, 148 { DEVICEID_CPT20, "Intel Cougar Point watchdog timer", 10 }, 149 { DEVICEID_CPT21, "Intel Cougar Point watchdog timer", 10 }, 150 { DEVICEID_CPT22, "Intel Cougar Point watchdog timer", 10 }, 151 { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10 }, 152 { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10 }, 153 { DEVICEID_CPT25, "Intel Cougar Point watchdog timer", 10 }, 154 { DEVICEID_CPT26, "Intel Cougar Point watchdog timer", 10 }, 155 { DEVICEID_CPT27, "Intel Cougar Point watchdog timer", 10 }, 156 { DEVICEID_CPT28, "Intel Cougar Point watchdog timer", 10 }, 157 { DEVICEID_CPT29, "Intel Cougar Point watchdog timer", 10 }, 158 { DEVICEID_CPT30, "Intel Cougar Point watchdog timer", 10 }, 159 { DEVICEID_CPT31, "Intel Cougar Point watchdog timer", 10 }, 160 { 0, NULL, 0 }, 161 }; 162 163 static devclass_t ichwd_devclass; 164 165 #define ichwd_read_tco_1(sc, off) \ 166 bus_space_read_1((sc)->tco_bst, (sc)->tco_bsh, (off)) 167 #define ichwd_read_tco_2(sc, off) \ 168 bus_space_read_2((sc)->tco_bst, (sc)->tco_bsh, (off)) 169 #define ichwd_read_tco_4(sc, off) \ 170 bus_space_read_4((sc)->tco_bst, (sc)->tco_bsh, (off)) 171 #define ichwd_read_smi_4(sc, off) \ 172 bus_space_read_4((sc)->smi_bst, (sc)->smi_bsh, (off)) 173 #define ichwd_read_gcs_4(sc, off) \ 174 bus_space_read_4((sc)->gcs_bst, (sc)->gcs_bsh, (off)) 175 176 #define ichwd_write_tco_1(sc, off, val) \ 177 bus_space_write_1((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 178 #define ichwd_write_tco_2(sc, off, val) \ 179 bus_space_write_2((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 180 #define ichwd_write_tco_4(sc, off, val) \ 181 bus_space_write_4((sc)->tco_bst, (sc)->tco_bsh, (off), (val)) 182 #define ichwd_write_smi_4(sc, off, val) \ 183 bus_space_write_4((sc)->smi_bst, (sc)->smi_bsh, (off), (val)) 184 #define ichwd_write_gcs_4(sc, off, val) \ 185 bus_space_write_4((sc)->gcs_bst, (sc)->gcs_bsh, (off), (val)) 186 187 #define ichwd_verbose_printf(dev, ...) \ 188 do { \ 189 if (bootverbose) \ 190 device_printf(dev, __VA_ARGS__);\ 191 } while (0) 192 193 /* 194 * Disable the watchdog timeout SMI handler. 195 * 196 * Apparently, some BIOSes install handlers that reset or disable the 197 * watchdog timer instead of resetting the system, so we disable the SMI 198 * (by clearing the SMI_TCO_EN bit of the SMI_EN register) to prevent this 199 * from happening. 200 */ 201 static __inline void 202 ichwd_smi_disable(struct ichwd_softc *sc) 203 { 204 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN); 205 } 206 207 /* 208 * Enable the watchdog timeout SMI handler. See above for details. 209 */ 210 static __inline void 211 ichwd_smi_enable(struct ichwd_softc *sc) 212 { 213 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN); 214 } 215 216 /* 217 * Reset the watchdog status bits. 218 */ 219 static __inline void 220 ichwd_sts_reset(struct ichwd_softc *sc) 221 { 222 /* 223 * The watchdog status bits are set to 1 by the hardware to 224 * indicate various conditions. They can be cleared by software 225 * by writing a 1, not a 0. 226 */ 227 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT); 228 /* 229 * According to Intel's docs, clearing SECOND_TO_STS and BOOT_STS must 230 * be done in two separate operations. 231 */ 232 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS); 233 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS); 234 } 235 236 /* 237 * Enable the watchdog timer by clearing the TCO_TMR_HALT bit in the 238 * TCO1_CNT register. This is complicated by the need to preserve bit 9 239 * of that same register, and the requirement that all other bits must be 240 * written back as zero. 241 */ 242 static __inline void 243 ichwd_tmr_enable(struct ichwd_softc *sc) 244 { 245 uint16_t cnt; 246 247 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 248 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT); 249 sc->active = 1; 250 ichwd_verbose_printf(sc->device, "timer enabled\n"); 251 } 252 253 /* 254 * Disable the watchdog timer. See above for details. 255 */ 256 static __inline void 257 ichwd_tmr_disable(struct ichwd_softc *sc) 258 { 259 uint16_t cnt; 260 261 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 262 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT); 263 sc->active = 0; 264 ichwd_verbose_printf(sc->device, "timer disabled\n"); 265 } 266 267 /* 268 * Reload the watchdog timer: writing anything to any of the lower five 269 * bits of the TCO_RLD register reloads the timer from the last value 270 * written to TCO_TMR. 271 */ 272 static __inline void 273 ichwd_tmr_reload(struct ichwd_softc *sc) 274 { 275 if (sc->ich_version <= 5) 276 ichwd_write_tco_1(sc, TCO_RLD, 1); 277 else 278 ichwd_write_tco_2(sc, TCO_RLD, 1); 279 280 ichwd_verbose_printf(sc->device, "timer reloaded\n"); 281 } 282 283 /* 284 * Set the initial timeout value. Note that this must always be followed 285 * by a reload. 286 */ 287 static __inline void 288 ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout) 289 { 290 291 if (timeout < TCO_RLD_TMR_MIN) 292 timeout = TCO_RLD_TMR_MIN; 293 294 if (sc->ich_version <= 5) { 295 uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1); 296 297 tmr_val8 &= (~TCO_RLD1_TMR_MAX & 0xff); 298 if (timeout > TCO_RLD1_TMR_MAX) 299 timeout = TCO_RLD1_TMR_MAX; 300 tmr_val8 |= timeout; 301 ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8); 302 } else { 303 uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2); 304 305 tmr_val16 &= (~TCO_RLD2_TMR_MAX & 0xffff); 306 if (timeout > TCO_RLD2_TMR_MAX) 307 timeout = TCO_RLD2_TMR_MAX; 308 tmr_val16 |= timeout; 309 ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16); 310 } 311 312 sc->timeout = timeout; 313 314 ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout); 315 } 316 317 static __inline int 318 ichwd_clear_noreboot(struct ichwd_softc *sc) 319 { 320 uint32_t status; 321 int rc = 0; 322 323 /* try to clear the NO_REBOOT bit */ 324 if (sc->ich_version <= 5) { 325 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 326 status &= ~ICH_GEN_STA_NO_REBOOT; 327 pci_write_config(sc->ich, ICH_GEN_STA, status, 1); 328 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 329 if (status & ICH_GEN_STA_NO_REBOOT) 330 rc = EIO; 331 } else { 332 status = ichwd_read_gcs_4(sc, 0); 333 status &= ~ICH_GCS_NO_REBOOT; 334 ichwd_write_gcs_4(sc, 0, status); 335 status = ichwd_read_gcs_4(sc, 0); 336 if (status & ICH_GCS_NO_REBOOT) 337 rc = EIO; 338 } 339 340 if (rc) 341 device_printf(sc->device, 342 "ICH WDT present but disabled in BIOS or hardware\n"); 343 344 return (rc); 345 } 346 347 /* 348 * Watchdog event handler - called by the framework to enable or disable 349 * the watchdog or change the initial timeout value. 350 */ 351 static void 352 ichwd_event(void *arg, unsigned int cmd, int *error) 353 { 354 struct ichwd_softc *sc = arg; 355 unsigned int timeout; 356 357 /* convert from power-of-two-ns to WDT ticks */ 358 cmd &= WD_INTERVAL; 359 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK; 360 if (cmd) { 361 if (timeout != sc->timeout) { 362 if (!sc->active) 363 ichwd_tmr_enable(sc); 364 ichwd_tmr_set(sc, timeout); 365 } 366 ichwd_tmr_reload(sc); 367 *error = 0; 368 } else { 369 if (sc->active) 370 ichwd_tmr_disable(sc); 371 } 372 } 373 374 static device_t 375 ichwd_find_ich_lpc_bridge(struct ichwd_device **id_p) 376 { 377 struct ichwd_device *id; 378 device_t ich = NULL; 379 380 /* look for an ICH LPC interface bridge */ 381 for (id = ichwd_devices; id->desc != NULL; ++id) 382 if ((ich = pci_find_device(VENDORID_INTEL, id->device)) != NULL) 383 break; 384 385 if (ich == NULL) 386 return (NULL); 387 388 ichwd_verbose_printf(ich, "found ICH%d or equivalent chipset: %s\n", 389 id->version, id->desc); 390 391 if (id_p) 392 *id_p = id; 393 394 return (ich); 395 } 396 397 /* 398 * Look for an ICH LPC interface bridge. If one is found, register an 399 * ichwd device. There can be only one. 400 */ 401 static void 402 ichwd_identify(driver_t *driver, device_t parent) 403 { 404 struct ichwd_device *id_p; 405 device_t ich = NULL; 406 device_t dev; 407 uint32_t rcba; 408 int rc; 409 410 ich = ichwd_find_ich_lpc_bridge(&id_p); 411 if (ich == NULL) 412 return; 413 414 /* good, add child to bus */ 415 if ((dev = device_find_child(parent, driver->name, 0)) == NULL) 416 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0); 417 418 if (dev == NULL) 419 return; 420 421 device_set_desc_copy(dev, id_p->desc); 422 423 if (id_p->version >= 6) { 424 /* get RCBA (root complex base address) */ 425 rcba = pci_read_config(ich, ICH_RCBA, 4); 426 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 427 (rcba & 0xffffc000) + ICH_GCS_OFFSET, ICH_GCS_SIZE); 428 if (rc) 429 ichwd_verbose_printf(dev, 430 "Can not set memory resource for RCBA\n"); 431 } 432 } 433 434 static int 435 ichwd_probe(device_t dev) 436 { 437 438 /* Do not claim some ISA PnP device by accident. */ 439 if (isa_get_logicalid(dev) != 0) 440 return (ENXIO); 441 return (0); 442 } 443 444 static int 445 ichwd_attach(device_t dev) 446 { 447 struct ichwd_softc *sc; 448 struct ichwd_device *id_p; 449 device_t ich; 450 unsigned int pmbase = 0; 451 452 sc = device_get_softc(dev); 453 sc->device = dev; 454 455 ich = ichwd_find_ich_lpc_bridge(&id_p); 456 if (ich == NULL) { 457 device_printf(sc->device, "Can not find ICH device.\n"); 458 goto fail; 459 } 460 sc->ich = ich; 461 sc->ich_version = id_p->version; 462 463 /* get ACPI base address */ 464 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK; 465 if (pmbase == 0) { 466 device_printf(dev, "ICH PMBASE register is empty\n"); 467 goto fail; 468 } 469 470 /* allocate I/O register space */ 471 sc->smi_rid = 0; 472 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 473 pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN, 474 RF_ACTIVE | RF_SHAREABLE); 475 if (sc->smi_res == NULL) { 476 device_printf(dev, "unable to reserve SMI registers\n"); 477 goto fail; 478 } 479 sc->smi_bst = rman_get_bustag(sc->smi_res); 480 sc->smi_bsh = rman_get_bushandle(sc->smi_res); 481 482 sc->tco_rid = 1; 483 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid, 484 pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN, 485 RF_ACTIVE | RF_SHAREABLE); 486 if (sc->tco_res == NULL) { 487 device_printf(dev, "unable to reserve TCO registers\n"); 488 goto fail; 489 } 490 sc->tco_bst = rman_get_bustag(sc->tco_res); 491 sc->tco_bsh = rman_get_bushandle(sc->tco_res); 492 493 sc->gcs_rid = 0; 494 if (sc->ich_version >= 6) { 495 sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY, 496 &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE); 497 if (sc->gcs_res == NULL) { 498 device_printf(dev, "unable to reserve GCS registers\n"); 499 goto fail; 500 } 501 sc->gcs_bst = rman_get_bustag(sc->gcs_res); 502 sc->gcs_bsh = rman_get_bushandle(sc->gcs_res); 503 } else { 504 sc->gcs_res = 0; 505 sc->gcs_bst = 0; 506 sc->gcs_bsh = 0; 507 } 508 509 if (ichwd_clear_noreboot(sc) != 0) 510 goto fail; 511 512 ichwd_verbose_printf(dev, "%s (ICH%d or equivalent)\n", 513 device_get_desc(dev), sc->ich_version); 514 515 /* 516 * Determine if we are coming up after a watchdog-induced reset. Some 517 * BIOSes may clear this bit at bootup, preventing us from reporting 518 * this case on such systems. We clear this bit in ichwd_sts_reset(). 519 */ 520 if ((ichwd_read_tco_2(sc, TCO2_STS) & TCO_SECOND_TO_STS) != 0) 521 device_printf(dev, 522 "resuming after hardware watchdog timeout\n"); 523 524 /* reset the watchdog status registers */ 525 ichwd_sts_reset(sc); 526 527 /* make sure the WDT starts out inactive */ 528 ichwd_tmr_disable(sc); 529 530 /* register the watchdog event handler */ 531 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0); 532 533 /* disable the SMI handler */ 534 ichwd_smi_disable(sc); 535 536 return (0); 537 fail: 538 sc = device_get_softc(dev); 539 if (sc->tco_res != NULL) 540 bus_release_resource(dev, SYS_RES_IOPORT, 541 sc->tco_rid, sc->tco_res); 542 if (sc->smi_res != NULL) 543 bus_release_resource(dev, SYS_RES_IOPORT, 544 sc->smi_rid, sc->smi_res); 545 if (sc->gcs_res != NULL) 546 bus_release_resource(ich, SYS_RES_MEMORY, 547 sc->gcs_rid, sc->gcs_res); 548 549 return (ENXIO); 550 } 551 552 static int 553 ichwd_detach(device_t dev) 554 { 555 struct ichwd_softc *sc; 556 device_t ich = NULL; 557 558 sc = device_get_softc(dev); 559 560 /* halt the watchdog timer */ 561 if (sc->active) 562 ichwd_tmr_disable(sc); 563 564 /* enable the SMI handler */ 565 ichwd_smi_enable(sc); 566 567 /* deregister event handler */ 568 if (sc->ev_tag != NULL) 569 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 570 sc->ev_tag = NULL; 571 572 /* reset the watchdog status registers */ 573 ichwd_sts_reset(sc); 574 575 /* deallocate I/O register space */ 576 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res); 577 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res); 578 579 /* deallocate memory resource */ 580 ich = ichwd_find_ich_lpc_bridge(NULL); 581 if (sc->gcs_res && ich) 582 bus_release_resource(ich, SYS_RES_MEMORY, sc->gcs_rid, sc->gcs_res); 583 584 return (0); 585 } 586 587 static device_method_t ichwd_methods[] = { 588 DEVMETHOD(device_identify, ichwd_identify), 589 DEVMETHOD(device_probe, ichwd_probe), 590 DEVMETHOD(device_attach, ichwd_attach), 591 DEVMETHOD(device_detach, ichwd_detach), 592 DEVMETHOD(device_shutdown, ichwd_detach), 593 {0,0} 594 }; 595 596 static driver_t ichwd_driver = { 597 "ichwd", 598 ichwd_methods, 599 sizeof(struct ichwd_softc), 600 }; 601 602 DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, NULL, NULL); 603