1 /*- 2 * ichsmb_reg.h 3 * 4 * Copyright (c) 2000 Whistle Communications, Inc. 5 * All rights reserved. 6 * 7 * Subject to the following obligations and disclaimer of warranty, use and 8 * redistribution of this software, in source or object code forms, with or 9 * without modifications are expressly permitted by Whistle Communications; 10 * provided, however, that: 11 * 1. Any and all reproductions of the source or object code must include the 12 * copyright notice above and the following disclaimer of warranties; and 13 * 2. No rights are granted, in any manner or form, to use Whistle 14 * Communications, Inc. trademarks, including the mark "WHISTLE 15 * COMMUNICATIONS" on advertising, endorsements, or otherwise except as 16 * such appears in the above copyright notice or in the software. 17 * 18 * THIS SOFTWARE IS BEING PROVIDED BY WHISTLE COMMUNICATIONS "AS IS", AND 19 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, WHISTLE COMMUNICATIONS MAKES NO 20 * REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, REGARDING THIS SOFTWARE, 21 * INCLUDING WITHOUT LIMITATION, ANY AND ALL IMPLIED WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. 23 * WHISTLE COMMUNICATIONS DOES NOT WARRANT, GUARANTEE, OR MAKE ANY 24 * REPRESENTATIONS REGARDING THE USE OF, OR THE RESULTS OF THE USE OF THIS 25 * SOFTWARE IN TERMS OF ITS CORRECTNESS, ACCURACY, RELIABILITY OR OTHERWISE. 26 * IN NO EVENT SHALL WHISTLE COMMUNICATIONS BE LIABLE FOR ANY DAMAGES 27 * RESULTING FROM OR ARISING OUT OF ANY USE OF THIS SOFTWARE, INCLUDING 28 * WITHOUT LIMITATION, ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 29 * PUNITIVE, OR CONSEQUENTIAL DAMAGES, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES, LOSS OF USE, DATA OR PROFITS, HOWEVER CAUSED AND UNDER ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 33 * THIS SOFTWARE, EVEN IF WHISTLE COMMUNICATIONS IS ADVISED OF THE POSSIBILITY 34 * OF SUCH DAMAGE. 35 * 36 * Author: Archie Cobbs <archie@freebsd.org> 37 */ 38 39 #ifndef _DEV_ICHSMB_ICHSMB_REG_H_ 40 #define _DEV_ICHSMB_ICHSMB_REG_H_ 41 42 /* 43 * Definitions for the SMBus controller logical device which is part of the 44 * Intel 81801AA (ICH) and 81801AB (ICH0) I/O controller hub chips. 45 */ 46 47 /* 48 * PCI configuration registers 49 */ 50 #define ICH_SMB_BASE 0x20 /* base address register */ 51 #define ICH_HOSTC 0x40 /* host config register */ 52 #define ICH_HOSTC_I2C_EN 0x04 /* enable i2c mode */ 53 #define ICH_HOSTC_SMB_SMI_EN 0x02 /* SMI# instead of irq */ 54 #define ICH_HOSTC_HST_EN 0x01 /* enable host cntrlr */ 55 56 /* 57 * I/O registers 58 */ 59 #define ICH_HST_STA 0x00 /* host status */ 60 #define ICH_HST_STA_BYTE_DONE_STS 0x80 /* byte send/rec'd */ 61 #define ICH_HST_STA_INUSE_STS 0x40 /* device access mutex */ 62 #define ICH_HST_STA_SMBALERT_STS 0x20 /* SMBALERT# signal */ 63 #define ICH_HST_STA_FAILED 0x10 /* failed bus transaction */ 64 #define ICH_HST_STA_BUS_ERR 0x08 /* transaction collision */ 65 #define ICH_HST_STA_DEV_ERR 0x04 /* misc. smb device error */ 66 #define ICH_HST_STA_INTR 0x02 /* command completed ok */ 67 #define ICH_HST_STA_HOST_BUSY 0x01 /* command is running */ 68 #define ICH_HST_CNT 0x02 /* host control */ 69 #define ICH_HST_CNT_START 0x40 /* start command */ 70 #define ICH_HST_CNT_LAST_BYTE 0x20 /* indicate last byte */ 71 #define ICH_HST_CNT_SMB_CMD_QUICK 0x00 /* command: quick */ 72 #define ICH_HST_CNT_SMB_CMD_BYTE 0x04 /* command: byte */ 73 #define ICH_HST_CNT_SMB_CMD_BYTE_DATA 0x08 /* command: byte data */ 74 #define ICH_HST_CNT_SMB_CMD_WORD_DATA 0x0c /* command: word data */ 75 #define ICH_HST_CNT_SMB_CMD_PROC_CALL 0x10 /* command: process call */ 76 #define ICH_HST_CNT_SMB_CMD_BLOCK 0x14 /* command: block */ 77 #define ICH_HST_CNT_SMB_CMD_I2C_READ 0x18 /* command: i2c read */ 78 #define ICH_HST_CNT_KILL 0x02 /* kill current transaction */ 79 #define ICH_HST_CNT_INTREN 0x01 /* enable interrupt */ 80 #define ICH_HST_CMD 0x03 /* host command */ 81 #define ICH_XMIT_SLVA 0x04 /* transmit slave address */ 82 #define ICH_XMIT_SLVA_READ 0x01 /* direction: read */ 83 #define ICH_XMIT_SLVA_WRITE 0x00 /* direction: write */ 84 #define ICH_D0 0x05 /* host data 0 */ 85 #define ICH_D1 0x06 /* host data 1 */ 86 #define ICH_BLOCK_DB 0x07 /* block data byte */ 87 88 #endif /* _DEV_ICHSMB_ICHSMB_REG_H_ */ 89 90