xref: /freebsd/sys/dev/ichsmb/ichsmb_pci.c (revision 6574b8ed19b093f0af09501d2c9676c28993cb97)
1 /*-
2  * ichsmb_pci.c
3  *
4  * Author: Archie Cobbs <archie@freebsd.org>
5  * Copyright (c) 2000 Whistle Communications, Inc.
6  * All rights reserved.
7  * Author: Archie Cobbs <archie@freebsd.org>
8  *
9  * Subject to the following obligations and disclaimer of warranty, use and
10  * redistribution of this software, in source or object code forms, with or
11  * without modifications are expressly permitted by Whistle Communications;
12  * provided, however, that:
13  * 1. Any and all reproductions of the source or object code must include the
14  *    copyright notice above and the following disclaimer of warranties; and
15  * 2. No rights are granted, in any manner or form, to use Whistle
16  *    Communications, Inc. trademarks, including the mark "WHISTLE
17  *    COMMUNICATIONS" on advertising, endorsements, or otherwise except as
18  *    such appears in the above copyright notice or in the software.
19  *
20  * THIS SOFTWARE IS BEING PROVIDED BY WHISTLE COMMUNICATIONS "AS IS", AND
21  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, WHISTLE COMMUNICATIONS MAKES NO
22  * REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, REGARDING THIS SOFTWARE,
23  * INCLUDING WITHOUT LIMITATION, ANY AND ALL IMPLIED WARRANTIES OF
24  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
25  * WHISTLE COMMUNICATIONS DOES NOT WARRANT, GUARANTEE, OR MAKE ANY
26  * REPRESENTATIONS REGARDING THE USE OF, OR THE RESULTS OF THE USE OF THIS
27  * SOFTWARE IN TERMS OF ITS CORRECTNESS, ACCURACY, RELIABILITY OR OTHERWISE.
28  * IN NO EVENT SHALL WHISTLE COMMUNICATIONS BE LIABLE FOR ANY DAMAGES
29  * RESULTING FROM OR ARISING OUT OF ANY USE OF THIS SOFTWARE, INCLUDING
30  * WITHOUT LIMITATION, ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
31  * PUNITIVE, OR CONSEQUENTIAL DAMAGES, PROCUREMENT OF SUBSTITUTE GOODS OR
32  * SERVICES, LOSS OF USE, DATA OR PROFITS, HOWEVER CAUSED AND UNDER ANY
33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
35  * THIS SOFTWARE, EVEN IF WHISTLE COMMUNICATIONS IS ADVISED OF THE POSSIBILITY
36  * OF SUCH DAMAGE.
37  */
38 
39 #include <sys/cdefs.h>
40 __FBSDID("$FreeBSD$");
41 
42 /*
43  * Support for the SMBus controller logical device which is part of the
44  * Intel 81801AA/AB/BA/CA/DC/EB (ICH/ICH[02345]) I/O controller hub chips.
45  */
46 
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/module.h>
51 #include <sys/errno.h>
52 #include <sys/lock.h>
53 #include <sys/mutex.h>
54 #include <sys/syslog.h>
55 #include <sys/bus.h>
56 
57 #include <machine/bus.h>
58 #include <sys/rman.h>
59 #include <machine/resource.h>
60 
61 #include <dev/pci/pcivar.h>
62 #include <dev/pci/pcireg.h>
63 
64 #include <dev/smbus/smbconf.h>
65 
66 #include <dev/ichsmb/ichsmb_var.h>
67 #include <dev/ichsmb/ichsmb_reg.h>
68 
69 /* PCI unique identifiers */
70 #define ID_82801AA			0x24138086
71 #define ID_82801AB			0x24238086
72 #define ID_82801BA			0x24438086
73 #define ID_82801CA			0x24838086
74 #define ID_82801DC			0x24C38086
75 #define ID_82801EB			0x24D38086
76 #define ID_82801FB			0x266A8086
77 #define ID_82801GB			0x27da8086
78 #define ID_82801H			0x283e8086
79 #define ID_82801I			0x29308086
80 #define ID_82801JI			0x3a308086
81 #define ID_PCH				0x3b308086
82 #define ID_6300ESB			0x25a48086
83 #define	ID_631xESB			0x269b8086
84 #define ID_DH89XXCC			0x23308086
85 #define ID_PATSBURG			0x1d228086
86 #define ID_CPT				0x1c228086
87 #define ID_PPT				0x1e228086
88 #define ID_AVOTON			0x1f3c8086
89 #define ID_COLETOCRK			0x23B08086
90 #define ID_LPT				0x8c228086
91 
92 #define PCIS_SERIALBUS_SMBUS_PROGIF	0x00
93 
94 /* Internal functions */
95 static int	ichsmb_pci_probe(device_t dev);
96 static int	ichsmb_pci_attach(device_t dev);
97 /*Use generic one for now*/
98 #if 0
99 static int	ichsmb_pci_detach(device_t dev);
100 #endif
101 
102 /* Device methods */
103 static device_method_t ichsmb_pci_methods[] = {
104 	/* Device interface */
105         DEVMETHOD(device_probe, ichsmb_pci_probe),
106         DEVMETHOD(device_attach, ichsmb_pci_attach),
107         DEVMETHOD(device_detach, ichsmb_detach),
108 
109 	/* SMBus methods */
110         DEVMETHOD(smbus_callback, ichsmb_callback),
111         DEVMETHOD(smbus_quick, ichsmb_quick),
112         DEVMETHOD(smbus_sendb, ichsmb_sendb),
113         DEVMETHOD(smbus_recvb, ichsmb_recvb),
114         DEVMETHOD(smbus_writeb, ichsmb_writeb),
115         DEVMETHOD(smbus_writew, ichsmb_writew),
116         DEVMETHOD(smbus_readb, ichsmb_readb),
117         DEVMETHOD(smbus_readw, ichsmb_readw),
118         DEVMETHOD(smbus_pcall, ichsmb_pcall),
119         DEVMETHOD(smbus_bwrite, ichsmb_bwrite),
120         DEVMETHOD(smbus_bread, ichsmb_bread),
121 
122 	DEVMETHOD_END
123 };
124 
125 static driver_t ichsmb_pci_driver = {
126 	"ichsmb",
127 	ichsmb_pci_methods,
128 	sizeof(struct ichsmb_softc)
129 };
130 
131 static devclass_t ichsmb_pci_devclass;
132 
133 DRIVER_MODULE(ichsmb, pci, ichsmb_pci_driver, ichsmb_pci_devclass, 0, 0);
134 
135 static int
136 ichsmb_pci_probe(device_t dev)
137 {
138 	/* Check PCI identifier */
139 	switch (pci_get_devid(dev)) {
140 	case ID_82801AA:
141 		device_set_desc(dev, "Intel 82801AA (ICH) SMBus controller");
142 		break;
143 	case ID_82801AB:
144 		device_set_desc(dev, "Intel 82801AB (ICH0) SMBus controller");
145 		break;
146 	case ID_82801BA:
147 		device_set_desc(dev, "Intel 82801BA (ICH2) SMBus controller");
148 		break;
149 	case ID_82801CA:
150 		device_set_desc(dev, "Intel 82801CA (ICH3) SMBus controller");
151 		break;
152 	case ID_82801DC:
153 		device_set_desc(dev, "Intel 82801DC (ICH4) SMBus controller");
154 		break;
155 	case ID_82801EB:
156 		device_set_desc(dev, "Intel 82801EB (ICH5) SMBus controller");
157 		break;
158 	case ID_82801FB:
159 		device_set_desc(dev, "Intel 82801FB (ICH6) SMBus controller");
160 		break;
161 	case ID_82801GB:
162 		device_set_desc(dev, "Intel 82801GB (ICH7) SMBus controller");
163 		break;
164 	case ID_82801H:
165 		device_set_desc(dev, "Intel 82801H (ICH8) SMBus controller");
166 		break;
167 	case ID_82801I:
168 		device_set_desc(dev, "Intel 82801I (ICH9) SMBus controller");
169 		break;
170 	case ID_82801JI:
171 		device_set_desc(dev, "Intel 82801JI (ICH10) SMBus controller");
172 		break;
173 	case ID_PCH:
174 		device_set_desc(dev, "Intel PCH SMBus controller");
175 		break;
176 	case ID_6300ESB:
177 		device_set_desc(dev, "Intel 6300ESB (ICH) SMBus controller");
178 		break;
179 	case ID_631xESB:
180 		device_set_desc(dev, "Intel 631xESB/6321ESB (ESB2) SMBus controller");
181 		break;
182 	case ID_DH89XXCC:
183 		device_set_desc(dev, "Intel DH89xxCC SMBus controller");
184 		break;
185 	case ID_PATSBURG:
186 		device_set_desc(dev, "Intel Patsburg SMBus controller");
187 		break;
188 	case ID_CPT:
189 		device_set_desc(dev, "Intel Cougar Point SMBus controller");
190 		break;
191 	case ID_PPT:
192 		device_set_desc(dev, "Intel Panther Point SMBus controller");
193 		break;
194 	case ID_AVOTON:
195 		device_set_desc(dev, "Intel Avoton SMBus controller");
196 		break;
197 	case ID_LPT:
198 		device_set_desc(dev, "Intel Lynx Point SMBus controller");
199 		break;
200 	case ID_COLETOCRK:
201 		device_set_desc(dev, "Intel Coleto Creek SMBus controller");
202 		break;
203 	default:
204 		return (ENXIO);
205 	}
206 
207 	/* Done */
208 	return (ichsmb_probe(dev));
209 }
210 
211 static int
212 ichsmb_pci_attach(device_t dev)
213 {
214 	const sc_p sc = device_get_softc(dev);
215 	int error;
216 
217 	/* Initialize private state */
218 	bzero(sc, sizeof(*sc));
219 	sc->ich_cmd = -1;
220 	sc->dev = dev;
221 
222 	/* Allocate an I/O range */
223 	sc->io_rid = ICH_SMB_BASE;
224 	sc->io_res = bus_alloc_resource(dev, SYS_RES_IOPORT,
225 	    &sc->io_rid, 0, ~0, 16, RF_ACTIVE);
226 	if (sc->io_res == NULL)
227 		sc->io_res = bus_alloc_resource(dev, SYS_RES_IOPORT,
228 		    &sc->io_rid, 0ul, ~0ul, 32, RF_ACTIVE);
229 	if (sc->io_res == NULL) {
230 		device_printf(dev, "can't map I/O\n");
231 		error = ENXIO;
232 		goto fail;
233 	}
234 
235 	/* Allocate interrupt */
236 	sc->irq_rid = 0;
237 	sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
238 	    &sc->irq_rid, RF_ACTIVE | RF_SHAREABLE);
239 	if (sc->irq_res == NULL) {
240 		device_printf(dev, "can't get IRQ\n");
241 		error = ENXIO;
242 		goto fail;
243 	}
244 
245 	/* Enable device */
246 	pci_write_config(dev, ICH_HOSTC, ICH_HOSTC_HST_EN, 1);
247 
248 	/* Done */
249 	error = ichsmb_attach(dev);
250 	if (error)
251 		goto fail;
252 	return (0);
253 
254 fail:
255 	/* Attach failed, release resources */
256 	ichsmb_release_resources(sc);
257 	return (error);
258 }
259 
260 
261 MODULE_DEPEND(ichsmb, pci, 1, 1, 1);
262 MODULE_DEPEND(ichsmb, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER);
263 MODULE_VERSION(ichsmb, 1);
264