1 2 /* 3 * ichsmb_pci.c 4 * 5 * Copyright (c) 2000 Whistle Communications, Inc. 6 * All rights reserved. 7 * 8 * Subject to the following obligations and disclaimer of warranty, use and 9 * redistribution of this software, in source or object code forms, with or 10 * without modifications are expressly permitted by Whistle Communications; 11 * provided, however, that: 12 * 1. Any and all reproductions of the source or object code must include the 13 * copyright notice above and the following disclaimer of warranties; and 14 * 2. No rights are granted, in any manner or form, to use Whistle 15 * Communications, Inc. trademarks, including the mark "WHISTLE 16 * COMMUNICATIONS" on advertising, endorsements, or otherwise except as 17 * such appears in the above copyright notice or in the software. 18 * 19 * THIS SOFTWARE IS BEING PROVIDED BY WHISTLE COMMUNICATIONS "AS IS", AND 20 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, WHISTLE COMMUNICATIONS MAKES NO 21 * REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, REGARDING THIS SOFTWARE, 22 * INCLUDING WITHOUT LIMITATION, ANY AND ALL IMPLIED WARRANTIES OF 23 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. 24 * WHISTLE COMMUNICATIONS DOES NOT WARRANT, GUARANTEE, OR MAKE ANY 25 * REPRESENTATIONS REGARDING THE USE OF, OR THE RESULTS OF THE USE OF THIS 26 * SOFTWARE IN TERMS OF ITS CORRECTNESS, ACCURACY, RELIABILITY OR OTHERWISE. 27 * IN NO EVENT SHALL WHISTLE COMMUNICATIONS BE LIABLE FOR ANY DAMAGES 28 * RESULTING FROM OR ARISING OUT OF ANY USE OF THIS SOFTWARE, INCLUDING 29 * WITHOUT LIMITATION, ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 30 * PUNITIVE, OR CONSEQUENTIAL DAMAGES, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES, LOSS OF USE, DATA OR PROFITS, HOWEVER CAUSED AND UNDER ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF WHISTLE COMMUNICATIONS IS ADVISED OF THE POSSIBILITY 35 * OF SUCH DAMAGE. 36 * 37 * Author: Archie Cobbs <archie@freebsd.org> 38 * 39 * $FreeBSD$ 40 */ 41 42 /* 43 * Support for the SMBus controller logical device which is part of the 44 * Intel 81801AA (ICH) and 81801AB (ICH0) I/O controller hub chips. 45 */ 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/lock.h> 52 #include <sys/mutex.h> 53 #include <sys/syslog.h> 54 #include <sys/bus.h> 55 56 #include <machine/bus.h> 57 #include <sys/rman.h> 58 #include <machine/resource.h> 59 60 #include <pci/pcivar.h> 61 #include <pci/pcireg.h> 62 63 #include <dev/smbus/smbconf.h> 64 65 #include <dev/ichsmb/ichsmb_var.h> 66 #include <dev/ichsmb/ichsmb_reg.h> 67 68 /* PCI unique identifiers */ 69 #define ID_81801AA 0x24138086 70 #define ID_81801AB 0x24238086 71 #define ID_82801BA 0x24438086 72 #define ID_82801CA 0x24838086 73 74 #define PCIS_SERIALBUS_SMBUS_PROGIF 0x00 75 76 /* Internal functions */ 77 static int ichsmb_pci_probe(device_t dev); 78 static int ichsmb_pci_attach(device_t dev); 79 80 /* Device methods */ 81 static device_method_t ichsmb_pci_methods[] = { 82 /* Device interface */ 83 DEVMETHOD(device_probe, ichsmb_pci_probe), 84 DEVMETHOD(device_attach, ichsmb_pci_attach), 85 86 /* Bus methods */ 87 DEVMETHOD(bus_print_child, bus_generic_print_child), 88 89 /* SMBus methods */ 90 DEVMETHOD(smbus_callback, ichsmb_callback), 91 DEVMETHOD(smbus_quick, ichsmb_quick), 92 DEVMETHOD(smbus_sendb, ichsmb_sendb), 93 DEVMETHOD(smbus_recvb, ichsmb_recvb), 94 DEVMETHOD(smbus_writeb, ichsmb_writeb), 95 DEVMETHOD(smbus_writew, ichsmb_writew), 96 DEVMETHOD(smbus_readb, ichsmb_readb), 97 DEVMETHOD(smbus_readw, ichsmb_readw), 98 DEVMETHOD(smbus_pcall, ichsmb_pcall), 99 DEVMETHOD(smbus_bwrite, ichsmb_bwrite), 100 DEVMETHOD(smbus_bread, ichsmb_bread), 101 { 0, 0 } 102 }; 103 104 static driver_t ichsmb_pci_driver = { 105 "ichsmb", 106 ichsmb_pci_methods, 107 sizeof(struct ichsmb_softc) 108 }; 109 110 static devclass_t ichsmb_pci_devclass; 111 112 DRIVER_MODULE(ichsmb, pci, ichsmb_pci_driver, ichsmb_pci_devclass, 0, 0); 113 114 static int 115 ichsmb_pci_probe(device_t dev) 116 { 117 /* Check PCI identifier */ 118 switch (pci_get_devid(dev)) { 119 case ID_81801AA: 120 device_set_desc(dev, "Intel 82801AA (ICH) SMBus controller"); 121 break; 122 case ID_81801AB: 123 device_set_desc(dev, "Intel 82801AB (ICH0) SMBus controller"); 124 break; 125 case ID_82801BA: 126 device_set_desc(dev, "Intel 82801BA (ICH2) SMBus controller"); 127 break; 128 case ID_82801CA: 129 device_set_desc(dev, "Intel 82801CA (ICH3) SMBus controller"); 130 break; 131 default: 132 if (pci_get_class(dev) == PCIC_SERIALBUS 133 && pci_get_subclass(dev) == PCIS_SERIALBUS_SMBUS 134 && pci_get_progif(dev) == PCIS_SERIALBUS_SMBUS_PROGIF) { 135 device_set_desc(dev, "SMBus controller"); 136 return (-2); /* XXX */ 137 } 138 return (ENXIO); 139 } 140 141 /* Done */ 142 return (ichsmb_probe(dev)); 143 } 144 145 static int 146 ichsmb_pci_attach(device_t dev) 147 { 148 const sc_p sc = device_get_softc(dev); 149 u_int32_t cmd; 150 int error; 151 152 /* Initialize private state */ 153 bzero(sc, sizeof(*sc)); 154 sc->ich_cmd = -1; 155 sc->dev = dev; 156 157 /* Allocate an I/O range */ 158 sc->io_rid = ICH_SMB_BASE; 159 sc->io_res = bus_alloc_resource(dev, SYS_RES_IOPORT, 160 &sc->io_rid, 0, ~0, 16, RF_ACTIVE); 161 if (sc->io_res == NULL) { 162 log(LOG_ERR, "%s: can't map I/O\n", device_get_nameunit(dev)); 163 error = ENXIO; 164 goto fail; 165 } 166 sc->io_bst = rman_get_bustag(sc->io_res); 167 sc->io_bsh = rman_get_bushandle(sc->io_res); 168 169 /* Allocate interrupt */ 170 sc->irq_rid = 0; 171 sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, 172 &sc->irq_rid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 173 if (sc->irq_res == NULL) { 174 log(LOG_ERR, "%s: can't get IRQ\n", device_get_nameunit(dev)); 175 error = ENXIO; 176 goto fail; 177 } 178 179 /* Set up interrupt handler */ 180 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC, 181 ichsmb_device_intr, sc, &sc->irq_handle); 182 if (error != 0) { 183 log(LOG_ERR, "%s: can't setup irq\n", device_get_nameunit(dev)); 184 goto fail; 185 } 186 187 /* Enable I/O mapping */ 188 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 189 cmd |= PCIM_CMD_PORTEN; 190 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 191 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 192 if ((cmd & PCIM_CMD_PORTEN) == 0) { 193 log(LOG_ERR, "%s: can't enable memory map\n", 194 device_get_nameunit(dev)); 195 error = ENXIO; 196 goto fail; 197 } 198 199 /* Enable device */ 200 pci_write_config(dev, ICH_HOSTC, ICH_HOSTC_HST_EN, 1); 201 202 /* Done */ 203 return (ichsmb_attach(dev)); 204 205 fail: 206 /* Attach failed, release resources */ 207 ichsmb_release_resources(sc); 208 return (error); 209 } 210 211