1 /*- 2 * ichsmb.c 3 * 4 * Author: Archie Cobbs <archie@freebsd.org> 5 * Copyright (c) 2000 Whistle Communications, Inc. 6 * All rights reserved. 7 * 8 * Subject to the following obligations and disclaimer of warranty, use and 9 * redistribution of this software, in source or object code forms, with or 10 * without modifications are expressly permitted by Whistle Communications; 11 * provided, however, that: 12 * 1. Any and all reproductions of the source or object code must include the 13 * copyright notice above and the following disclaimer of warranties; and 14 * 2. No rights are granted, in any manner or form, to use Whistle 15 * Communications, Inc. trademarks, including the mark "WHISTLE 16 * COMMUNICATIONS" on advertising, endorsements, or otherwise except as 17 * such appears in the above copyright notice or in the software. 18 * 19 * THIS SOFTWARE IS BEING PROVIDED BY WHISTLE COMMUNICATIONS "AS IS", AND 20 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, WHISTLE COMMUNICATIONS MAKES NO 21 * REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, REGARDING THIS SOFTWARE, 22 * INCLUDING WITHOUT LIMITATION, ANY AND ALL IMPLIED WARRANTIES OF 23 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. 24 * WHISTLE COMMUNICATIONS DOES NOT WARRANT, GUARANTEE, OR MAKE ANY 25 * REPRESENTATIONS REGARDING THE USE OF, OR THE RESULTS OF THE USE OF THIS 26 * SOFTWARE IN TERMS OF ITS CORRECTNESS, ACCURACY, RELIABILITY OR OTHERWISE. 27 * IN NO EVENT SHALL WHISTLE COMMUNICATIONS BE LIABLE FOR ANY DAMAGES 28 * RESULTING FROM OR ARISING OUT OF ANY USE OF THIS SOFTWARE, INCLUDING 29 * WITHOUT LIMITATION, ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 30 * PUNITIVE, OR CONSEQUENTIAL DAMAGES, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES, LOSS OF USE, DATA OR PROFITS, HOWEVER CAUSED AND UNDER ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF WHISTLE COMMUNICATIONS IS ADVISED OF THE POSSIBILITY 35 * OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __FBSDID("$FreeBSD$"); 40 41 /* 42 * Support for the SMBus controller logical device which is part of the 43 * Intel 81801AA (ICH) and 81801AB (ICH0) I/O controller hub chips. 44 * 45 * This driver assumes that the generic SMBus code will ensure that 46 * at most one process at a time calls into the SMBus methods below. 47 */ 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/errno.h> 53 #include <sys/lock.h> 54 #include <sys/module.h> 55 #include <sys/mutex.h> 56 #include <sys/syslog.h> 57 #include <sys/bus.h> 58 59 #include <machine/bus.h> 60 #include <sys/rman.h> 61 #include <machine/resource.h> 62 63 #include <dev/smbus/smbconf.h> 64 65 #include <dev/ichsmb/ichsmb_var.h> 66 #include <dev/ichsmb/ichsmb_reg.h> 67 68 /* 69 * Enable debugging by defining ICHSMB_DEBUG to a non-zero value. 70 */ 71 #define ICHSMB_DEBUG 0 72 #if ICHSMB_DEBUG != 0 && defined(__CC_SUPPORTS___FUNC__) 73 #define DBG(fmt, args...) \ 74 do { log(LOG_DEBUG, "%s: " fmt, __func__ , ## args); } while (0) 75 #else 76 #define DBG(fmt, args...) do { } while (0) 77 #endif 78 79 /* 80 * Our child device driver name 81 */ 82 #define DRIVER_SMBUS "smbus" 83 84 /* 85 * Internal functions 86 */ 87 static int ichsmb_wait(sc_p sc); 88 89 /******************************************************************** 90 BUS-INDEPENDENT BUS METHODS 91 ********************************************************************/ 92 93 /* 94 * Handle probe-time duties that are independent of the bus 95 * our device lives on. 96 */ 97 int 98 ichsmb_probe(device_t dev) 99 { 100 return (BUS_PROBE_DEFAULT); 101 } 102 103 /* 104 * Handle attach-time duties that are independent of the bus 105 * our device lives on. 106 */ 107 int 108 ichsmb_attach(device_t dev) 109 { 110 const sc_p sc = device_get_softc(dev); 111 int error; 112 113 /* Add child: an instance of the "smbus" device */ 114 if ((sc->smb = device_add_child(dev, DRIVER_SMBUS, -1)) == NULL) { 115 log(LOG_ERR, "%s: no \"%s\" child found\n", 116 device_get_nameunit(dev), DRIVER_SMBUS); 117 return (ENXIO); 118 } 119 120 /* Clear interrupt conditions */ 121 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_HST_STA, 0xff); 122 123 /* Add "smbus" child */ 124 if ((error = bus_generic_attach(dev)) != 0) { 125 log(LOG_ERR, "%s: failed to attach child: %d\n", 126 device_get_nameunit(dev), error); 127 return (ENXIO); 128 } 129 130 /* Create mutex */ 131 mtx_init(&sc->mutex, device_get_nameunit(dev), "ichsmb", MTX_DEF); 132 return (0); 133 } 134 135 /******************************************************************** 136 SMBUS METHODS 137 ********************************************************************/ 138 139 int 140 ichsmb_callback(device_t dev, int index, void *data) 141 { 142 int smb_error = 0; 143 144 DBG("index=%d how=%d\n", index, data ? *(int *)data : -1); 145 switch (index) { 146 case SMB_REQUEST_BUS: 147 break; 148 case SMB_RELEASE_BUS: 149 break; 150 default: 151 smb_error = SMB_EABORT; /* XXX */ 152 break; 153 } 154 DBG("smb_error=%d\n", smb_error); 155 return (smb_error); 156 } 157 158 int 159 ichsmb_quick(device_t dev, u_char slave, int how) 160 { 161 const sc_p sc = device_get_softc(dev); 162 int smb_error; 163 164 DBG("slave=0x%02x how=%d\n", slave, how); 165 KASSERT(sc->ich_cmd == -1, 166 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd)); 167 switch (how) { 168 case SMB_QREAD: 169 case SMB_QWRITE: 170 mtx_lock(&sc->mutex); 171 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_QUICK; 172 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_XMIT_SLVA, 173 (slave << 1) | (how == SMB_QREAD ? 174 ICH_XMIT_SLVA_READ : ICH_XMIT_SLVA_WRITE)); 175 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_HST_CNT, 176 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd); 177 smb_error = ichsmb_wait(sc); 178 mtx_unlock(&sc->mutex); 179 break; 180 default: 181 smb_error = SMB_ENOTSUPP; 182 } 183 DBG("smb_error=%d\n", smb_error); 184 return (smb_error); 185 } 186 187 int 188 ichsmb_sendb(device_t dev, u_char slave, char byte) 189 { 190 const sc_p sc = device_get_softc(dev); 191 int smb_error; 192 193 DBG("slave=0x%02x byte=0x%02x\n", slave, (u_char)byte); 194 KASSERT(sc->ich_cmd == -1, 195 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd)); 196 mtx_lock(&sc->mutex); 197 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_BYTE; 198 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_XMIT_SLVA, 199 (slave << 1) | ICH_XMIT_SLVA_WRITE); 200 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_HST_CMD, byte); 201 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_HST_CNT, 202 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd); 203 smb_error = ichsmb_wait(sc); 204 mtx_unlock(&sc->mutex); 205 DBG("smb_error=%d\n", smb_error); 206 return (smb_error); 207 } 208 209 int 210 ichsmb_recvb(device_t dev, u_char slave, char *byte) 211 { 212 const sc_p sc = device_get_softc(dev); 213 int smb_error; 214 215 DBG("slave=0x%02x\n", slave); 216 KASSERT(sc->ich_cmd == -1, 217 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd)); 218 mtx_lock(&sc->mutex); 219 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_BYTE; 220 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_XMIT_SLVA, 221 (slave << 1) | ICH_XMIT_SLVA_READ); 222 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_HST_CNT, 223 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd); 224 if ((smb_error = ichsmb_wait(sc)) == SMB_ENOERR) 225 *byte = bus_space_read_1(sc->io_bst, sc->io_bsh, ICH_D0); 226 mtx_unlock(&sc->mutex); 227 DBG("smb_error=%d byte=0x%02x\n", smb_error, (u_char)*byte); 228 return (smb_error); 229 } 230 231 int 232 ichsmb_writeb(device_t dev, u_char slave, char cmd, char byte) 233 { 234 const sc_p sc = device_get_softc(dev); 235 int smb_error; 236 237 DBG("slave=0x%02x cmd=0x%02x byte=0x%02x\n", 238 slave, (u_char)cmd, (u_char)byte); 239 KASSERT(sc->ich_cmd == -1, 240 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd)); 241 mtx_lock(&sc->mutex); 242 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_BYTE_DATA; 243 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_XMIT_SLVA, 244 (slave << 1) | ICH_XMIT_SLVA_WRITE); 245 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_HST_CMD, cmd); 246 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_D0, byte); 247 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_HST_CNT, 248 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd); 249 smb_error = ichsmb_wait(sc); 250 mtx_unlock(&sc->mutex); 251 DBG("smb_error=%d\n", smb_error); 252 return (smb_error); 253 } 254 255 int 256 ichsmb_writew(device_t dev, u_char slave, char cmd, short word) 257 { 258 const sc_p sc = device_get_softc(dev); 259 int smb_error; 260 261 DBG("slave=0x%02x cmd=0x%02x word=0x%04x\n", 262 slave, (u_char)cmd, (u_int16_t)word); 263 KASSERT(sc->ich_cmd == -1, 264 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd)); 265 mtx_lock(&sc->mutex); 266 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_WORD_DATA; 267 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_XMIT_SLVA, 268 (slave << 1) | ICH_XMIT_SLVA_WRITE); 269 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_HST_CMD, cmd); 270 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_D0, word & 0xff); 271 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_D1, word >> 8); 272 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_HST_CNT, 273 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd); 274 smb_error = ichsmb_wait(sc); 275 mtx_unlock(&sc->mutex); 276 DBG("smb_error=%d\n", smb_error); 277 return (smb_error); 278 } 279 280 int 281 ichsmb_readb(device_t dev, u_char slave, char cmd, char *byte) 282 { 283 const sc_p sc = device_get_softc(dev); 284 int smb_error; 285 286 DBG("slave=0x%02x cmd=0x%02x\n", slave, (u_char)cmd); 287 KASSERT(sc->ich_cmd == -1, 288 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd)); 289 mtx_lock(&sc->mutex); 290 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_BYTE_DATA; 291 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_XMIT_SLVA, 292 (slave << 1) | ICH_XMIT_SLVA_READ); 293 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_HST_CMD, cmd); 294 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_HST_CNT, 295 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd); 296 if ((smb_error = ichsmb_wait(sc)) == SMB_ENOERR) 297 *byte = bus_space_read_1(sc->io_bst, sc->io_bsh, ICH_D0); 298 mtx_unlock(&sc->mutex); 299 DBG("smb_error=%d byte=0x%02x\n", smb_error, (u_char)*byte); 300 return (smb_error); 301 } 302 303 int 304 ichsmb_readw(device_t dev, u_char slave, char cmd, short *word) 305 { 306 const sc_p sc = device_get_softc(dev); 307 int smb_error; 308 309 DBG("slave=0x%02x cmd=0x%02x\n", slave, (u_char)cmd); 310 KASSERT(sc->ich_cmd == -1, 311 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd)); 312 mtx_lock(&sc->mutex); 313 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_WORD_DATA; 314 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_XMIT_SLVA, 315 (slave << 1) | ICH_XMIT_SLVA_READ); 316 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_HST_CMD, cmd); 317 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_HST_CNT, 318 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd); 319 if ((smb_error = ichsmb_wait(sc)) == SMB_ENOERR) { 320 *word = (bus_space_read_1(sc->io_bst, 321 sc->io_bsh, ICH_D0) & 0xff) 322 | (bus_space_read_1(sc->io_bst, 323 sc->io_bsh, ICH_D1) << 8); 324 } 325 mtx_unlock(&sc->mutex); 326 DBG("smb_error=%d word=0x%04x\n", smb_error, (u_int16_t)*word); 327 return (smb_error); 328 } 329 330 int 331 ichsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata) 332 { 333 const sc_p sc = device_get_softc(dev); 334 int smb_error; 335 336 DBG("slave=0x%02x cmd=0x%02x sdata=0x%04x\n", 337 slave, (u_char)cmd, (u_int16_t)sdata); 338 KASSERT(sc->ich_cmd == -1, 339 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd)); 340 mtx_lock(&sc->mutex); 341 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_PROC_CALL; 342 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_XMIT_SLVA, 343 (slave << 1) | ICH_XMIT_SLVA_WRITE); 344 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_HST_CMD, cmd); 345 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_D0, sdata & 0xff); 346 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_D1, sdata >> 8); 347 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_HST_CNT, 348 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd); 349 if ((smb_error = ichsmb_wait(sc)) == SMB_ENOERR) { 350 *rdata = (bus_space_read_1(sc->io_bst, 351 sc->io_bsh, ICH_D0) & 0xff) 352 | (bus_space_read_1(sc->io_bst, 353 sc->io_bsh, ICH_D1) << 8); 354 } 355 mtx_unlock(&sc->mutex); 356 DBG("smb_error=%d rdata=0x%04x\n", smb_error, (u_int16_t)*rdata); 357 return (smb_error); 358 } 359 360 int 361 ichsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf) 362 { 363 const sc_p sc = device_get_softc(dev); 364 int smb_error; 365 366 DBG("slave=0x%02x cmd=0x%02x count=%d\n", slave, (u_char)cmd, count); 367 #if ICHSMB_DEBUG 368 #define DISP(ch) (((ch) < 0x20 || (ch) >= 0x7e) ? '.' : (ch)) 369 { 370 u_char *p; 371 372 for (p = (u_char *)buf; p - (u_char *)buf < 32; p += 8) { 373 DBG("%02x: %02x %02x %02x %02x %02x %02x %02x %02x" 374 " %c%c%c%c%c%c%c%c", (p - (u_char *)buf), 375 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], 376 DISP(p[0]), DISP(p[1]), DISP(p[2]), DISP(p[3]), 377 DISP(p[4]), DISP(p[5]), DISP(p[6]), DISP(p[7])); 378 } 379 } 380 #undef DISP 381 #endif 382 KASSERT(sc->ich_cmd == -1, 383 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd)); 384 if (count < 1 || count > 32) 385 return (SMB_EINVAL); 386 bcopy(buf, sc->block_data, count); 387 sc->block_count = count; 388 sc->block_index = 1; 389 sc->block_write = 1; 390 391 mtx_lock(&sc->mutex); 392 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_BLOCK; 393 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_XMIT_SLVA, 394 (slave << 1) | ICH_XMIT_SLVA_WRITE); 395 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_HST_CMD, cmd); 396 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_D0, count); 397 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_BLOCK_DB, buf[0]); 398 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_HST_CNT, 399 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd); 400 smb_error = ichsmb_wait(sc); 401 mtx_unlock(&sc->mutex); 402 DBG("smb_error=%d\n", smb_error); 403 return (smb_error); 404 } 405 406 int 407 ichsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf) 408 { 409 const sc_p sc = device_get_softc(dev); 410 int smb_error; 411 412 DBG("slave=0x%02x cmd=0x%02x count=%d\n", slave, (u_char)cmd, count); 413 KASSERT(sc->ich_cmd == -1, 414 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd)); 415 if (*count < 1 || *count > 32) 416 return (SMB_EINVAL); 417 bzero(sc->block_data, sizeof(sc->block_data)); 418 sc->block_count = 0; 419 sc->block_index = 0; 420 sc->block_write = 0; 421 422 mtx_lock(&sc->mutex); 423 sc->ich_cmd = ICH_HST_CNT_SMB_CMD_BLOCK; 424 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_XMIT_SLVA, 425 (slave << 1) | ICH_XMIT_SLVA_READ); 426 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_HST_CMD, cmd); 427 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_D0, *count); /* XXX? */ 428 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_HST_CNT, 429 ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd); 430 if ((smb_error = ichsmb_wait(sc)) == SMB_ENOERR) { 431 bcopy(sc->block_data, buf, min(sc->block_count, *count)); 432 *count = sc->block_count; 433 } 434 mtx_unlock(&sc->mutex); 435 DBG("smb_error=%d\n", smb_error); 436 #if ICHSMB_DEBUG 437 #define DISP(ch) (((ch) < 0x20 || (ch) >= 0x7e) ? '.' : (ch)) 438 { 439 u_char *p; 440 441 for (p = (u_char *)buf; p - (u_char *)buf < 32; p += 8) { 442 DBG("%02x: %02x %02x %02x %02x %02x %02x %02x %02x" 443 " %c%c%c%c%c%c%c%c", (p - (u_char *)buf), 444 p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], 445 DISP(p[0]), DISP(p[1]), DISP(p[2]), DISP(p[3]), 446 DISP(p[4]), DISP(p[5]), DISP(p[6]), DISP(p[7])); 447 } 448 } 449 #undef DISP 450 #endif 451 return (smb_error); 452 } 453 454 /******************************************************************** 455 OTHER FUNCTIONS 456 ********************************************************************/ 457 458 /* 459 * This table describes what interrupts we should ever expect to 460 * see after each ICH command, not including the SMBALERT interrupt. 461 */ 462 static const u_int8_t ichsmb_state_irqs[] = { 463 /* quick */ 464 (ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR), 465 /* byte */ 466 (ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR), 467 /* byte data */ 468 (ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR), 469 /* word data */ 470 (ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR), 471 /* process call */ 472 (ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR), 473 /* block */ 474 (ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR 475 | ICH_HST_STA_BYTE_DONE_STS), 476 /* i2c read (not used) */ 477 (ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR 478 | ICH_HST_STA_BYTE_DONE_STS) 479 }; 480 481 /* 482 * Interrupt handler. This handler is bus-independent. Note that our 483 * interrupt may be shared, so we must handle "false" interrupts. 484 */ 485 void 486 ichsmb_device_intr(void *cookie) 487 { 488 const sc_p sc = cookie; 489 const device_t dev = sc->dev; 490 const int maxloops = 16; 491 u_int8_t status; 492 u_int8_t ok_bits; 493 int cmd_index; 494 int count; 495 496 mtx_lock(&sc->mutex); 497 for (count = 0; count < maxloops; count++) { 498 499 /* Get and reset status bits */ 500 status = bus_space_read_1(sc->io_bst, sc->io_bsh, ICH_HST_STA); 501 #if ICHSMB_DEBUG 502 if ((status & ~(ICH_HST_STA_INUSE_STS | ICH_HST_STA_HOST_BUSY)) 503 || count > 0) { 504 DBG("%d stat=0x%02x\n", count, status); 505 } 506 #endif 507 status &= ~(ICH_HST_STA_INUSE_STS | ICH_HST_STA_HOST_BUSY); 508 if (status == 0) 509 break; 510 511 /* Check for unexpected interrupt */ 512 ok_bits = ICH_HST_STA_SMBALERT_STS; 513 cmd_index = sc->ich_cmd >> 2; 514 if (sc->ich_cmd != -1) { 515 KASSERT(cmd_index < sizeof(ichsmb_state_irqs), 516 ("%s: ich_cmd=%d", device_get_nameunit(dev), 517 sc->ich_cmd)); 518 ok_bits |= ichsmb_state_irqs[cmd_index]; 519 } 520 if ((status & ~ok_bits) != 0) { 521 log(LOG_ERR, "%s: irq 0x%02x during %d\n", 522 device_get_nameunit(dev), status, cmd_index); 523 bus_space_write_1(sc->io_bst, sc->io_bsh, 524 ICH_HST_STA, (status & ~ok_bits)); 525 continue; 526 } 527 528 /* Handle SMBALERT interrupt */ 529 if (status & ICH_HST_STA_SMBALERT_STS) { 530 static int smbalert_count = 16; 531 if (smbalert_count > 0) { 532 log(LOG_WARNING, "%s: SMBALERT# rec'd\n", 533 device_get_nameunit(dev)); 534 if (--smbalert_count == 0) { 535 log(LOG_WARNING, 536 "%s: not logging anymore\n", 537 device_get_nameunit(dev)); 538 } 539 } 540 } 541 542 /* Check for bus error */ 543 if (status & ICH_HST_STA_BUS_ERR) { 544 sc->smb_error = SMB_ECOLLI; /* XXX SMB_EBUSERR? */ 545 goto finished; 546 } 547 548 /* Check for device error */ 549 if (status & ICH_HST_STA_DEV_ERR) { 550 sc->smb_error = SMB_ENOACK; /* or SMB_ETIMEOUT? */ 551 goto finished; 552 } 553 554 /* Check for byte completion in block transfer */ 555 if (status & ICH_HST_STA_BYTE_DONE_STS) { 556 if (sc->block_write) { 557 if (sc->block_index < sc->block_count) { 558 559 /* Write next byte */ 560 bus_space_write_1(sc->io_bst, 561 sc->io_bsh, ICH_BLOCK_DB, 562 sc->block_data[sc->block_index++]); 563 } 564 } else { 565 566 /* First interrupt, get the count also */ 567 if (sc->block_index == 0) { 568 sc->block_count = bus_space_read_1( 569 sc->io_bst, sc->io_bsh, ICH_D0); 570 } 571 572 /* Get next byte, if any */ 573 if (sc->block_index < sc->block_count) { 574 575 /* Read next byte */ 576 sc->block_data[sc->block_index++] = 577 bus_space_read_1(sc->io_bst, 578 sc->io_bsh, ICH_BLOCK_DB); 579 580 /* Set "LAST_BYTE" bit before reading 581 the last byte of block data */ 582 if (sc->block_index 583 >= sc->block_count - 1) { 584 bus_space_write_1(sc->io_bst, 585 sc->io_bsh, ICH_HST_CNT, 586 ICH_HST_CNT_LAST_BYTE 587 | ICH_HST_CNT_INTREN 588 | sc->ich_cmd); 589 } 590 } 591 } 592 } 593 594 /* Check command completion */ 595 if (status & ICH_HST_STA_INTR) { 596 sc->smb_error = SMB_ENOERR; 597 finished: 598 sc->ich_cmd = -1; 599 bus_space_write_1(sc->io_bst, sc->io_bsh, 600 ICH_HST_STA, status); 601 wakeup(sc); 602 break; 603 } 604 605 /* Clear status bits and try again */ 606 bus_space_write_1(sc->io_bst, sc->io_bsh, ICH_HST_STA, status); 607 } 608 mtx_unlock(&sc->mutex); 609 610 /* Too many loops? */ 611 if (count == maxloops) { 612 log(LOG_ERR, "%s: interrupt loop, status=0x%02x\n", 613 device_get_nameunit(dev), 614 bus_space_read_1(sc->io_bst, sc->io_bsh, ICH_HST_STA)); 615 } 616 } 617 618 /* 619 * Wait for command completion. Assumes mutex is held. 620 * Returns an SMB_* error code. 621 */ 622 static int 623 ichsmb_wait(sc_p sc) 624 { 625 const device_t dev = sc->dev; 626 int error, smb_error; 627 628 KASSERT(sc->ich_cmd != -1, 629 ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd)); 630 mtx_assert(&sc->mutex, MA_OWNED); 631 error = msleep(sc, &sc->mutex, PZERO, "ichsmb", hz / 4); 632 DBG("msleep -> %d\n", error); 633 switch (error) { 634 case 0: 635 smb_error = sc->smb_error; 636 break; 637 case EWOULDBLOCK: 638 log(LOG_ERR, "%s: device timeout, status=0x%02x\n", 639 device_get_nameunit(dev), 640 bus_space_read_1(sc->io_bst, sc->io_bsh, ICH_HST_STA)); 641 sc->ich_cmd = -1; 642 smb_error = SMB_ETIMEOUT; 643 break; 644 default: 645 smb_error = SMB_EABORT; 646 break; 647 } 648 return (smb_error); 649 } 650 651 /* 652 * Release resources associated with device. 653 */ 654 void 655 ichsmb_release_resources(sc_p sc) 656 { 657 const device_t dev = sc->dev; 658 659 if (sc->irq_handle != NULL) { 660 bus_teardown_intr(dev, sc->irq_res, sc->irq_handle); 661 sc->irq_handle = NULL; 662 } 663 if (sc->irq_res != NULL) { 664 bus_release_resource(dev, 665 SYS_RES_IRQ, sc->irq_rid, sc->irq_res); 666 sc->irq_res = NULL; 667 } 668 if (sc->io_res != NULL) { 669 bus_release_resource(dev, 670 SYS_RES_IOPORT, sc->io_rid, sc->io_res); 671 sc->io_res = NULL; 672 } 673 } 674 675 int 676 ichsmb_detach(device_t dev) 677 { 678 const sc_p sc = device_get_softc(dev); 679 int error; 680 681 error = bus_generic_detach(dev); 682 if (error) 683 return (error); 684 device_delete_child(dev, sc->smb); 685 ichsmb_release_resources(sc); 686 mtx_destroy(&sc->mutex); 687 688 return 0; 689 } 690 691 DRIVER_MODULE(smbus, ichsmb, smbus_driver, smbus_devclass, 0, 0); 692