xref: /freebsd/sys/dev/ichsmb/ichsmb.c (revision 4c9a0adad18263ec8725d9bfc5f560c6ad1da8bd)
1 /*-
2  * ichsmb.c
3  *
4  * Author: Archie Cobbs <archie@freebsd.org>
5  * Copyright (c) 2000 Whistle Communications, Inc.
6  * All rights reserved.
7  *
8  * Subject to the following obligations and disclaimer of warranty, use and
9  * redistribution of this software, in source or object code forms, with or
10  * without modifications are expressly permitted by Whistle Communications;
11  * provided, however, that:
12  * 1. Any and all reproductions of the source or object code must include the
13  *    copyright notice above and the following disclaimer of warranties; and
14  * 2. No rights are granted, in any manner or form, to use Whistle
15  *    Communications, Inc. trademarks, including the mark "WHISTLE
16  *    COMMUNICATIONS" on advertising, endorsements, or otherwise except as
17  *    such appears in the above copyright notice or in the software.
18  *
19  * THIS SOFTWARE IS BEING PROVIDED BY WHISTLE COMMUNICATIONS "AS IS", AND
20  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, WHISTLE COMMUNICATIONS MAKES NO
21  * REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, REGARDING THIS SOFTWARE,
22  * INCLUDING WITHOUT LIMITATION, ANY AND ALL IMPLIED WARRANTIES OF
23  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
24  * WHISTLE COMMUNICATIONS DOES NOT WARRANT, GUARANTEE, OR MAKE ANY
25  * REPRESENTATIONS REGARDING THE USE OF, OR THE RESULTS OF THE USE OF THIS
26  * SOFTWARE IN TERMS OF ITS CORRECTNESS, ACCURACY, RELIABILITY OR OTHERWISE.
27  * IN NO EVENT SHALL WHISTLE COMMUNICATIONS BE LIABLE FOR ANY DAMAGES
28  * RESULTING FROM OR ARISING OUT OF ANY USE OF THIS SOFTWARE, INCLUDING
29  * WITHOUT LIMITATION, ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
30  * PUNITIVE, OR CONSEQUENTIAL DAMAGES, PROCUREMENT OF SUBSTITUTE GOODS OR
31  * SERVICES, LOSS OF USE, DATA OR PROFITS, HOWEVER CAUSED AND UNDER ANY
32  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
34  * THIS SOFTWARE, EVEN IF WHISTLE COMMUNICATIONS IS ADVISED OF THE POSSIBILITY
35  * OF SUCH DAMAGE.
36  */
37 
38 #include <sys/cdefs.h>
39 /*
40  * Support for the SMBus controller logical device which is part of the
41  * Intel 81801AA (ICH) and 81801AB (ICH0) I/O controller hub chips.
42  *
43  * This driver assumes that the generic SMBus code will ensure that
44  * at most one process at a time calls into the SMBus methods below.
45  */
46 
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/errno.h>
51 #include <sys/lock.h>
52 #include <sys/module.h>
53 #include <sys/mutex.h>
54 #include <sys/syslog.h>
55 #include <sys/bus.h>
56 
57 #include <machine/bus.h>
58 #include <sys/rman.h>
59 #include <machine/resource.h>
60 
61 #include <dev/smbus/smbconf.h>
62 
63 #include <dev/ichsmb/ichsmb_var.h>
64 #include <dev/ichsmb/ichsmb_reg.h>
65 
66 /*
67  * Enable debugging by defining ICHSMB_DEBUG to a non-zero value.
68  */
69 #define ICHSMB_DEBUG	0
70 #if ICHSMB_DEBUG != 0
71 #define DBG(fmt, args...)	\
72 	do { printf("%s: " fmt, __func__ , ## args); } while (0)
73 #else
74 #define DBG(fmt, args...)	do { } while (0)
75 #endif
76 
77 /*
78  * Our child device driver name
79  */
80 #define DRIVER_SMBUS	"smbus"
81 
82 /*
83  * Internal functions
84  */
85 static int ichsmb_wait(sc_p sc);
86 
87 /********************************************************************
88 		BUS-INDEPENDENT BUS METHODS
89 ********************************************************************/
90 
91 /*
92  * Handle probe-time duties that are independent of the bus
93  * our device lives on.
94  */
95 int
96 ichsmb_probe(device_t dev)
97 {
98 	return (BUS_PROBE_DEFAULT);
99 }
100 
101 /*
102  * Handle attach-time duties that are independent of the bus
103  * our device lives on.
104  */
105 int
106 ichsmb_attach(device_t dev)
107 {
108 	const sc_p sc = device_get_softc(dev);
109 	int error;
110 
111 	/* Create mutex */
112 	mtx_init(&sc->mutex, device_get_nameunit(dev), "ichsmb", MTX_DEF);
113 
114 	/* Add child: an instance of the "smbus" device */
115 	if ((sc->smb = device_add_child(dev, DRIVER_SMBUS, -1)) == NULL) {
116 		device_printf(dev, "no \"%s\" child found\n", DRIVER_SMBUS);
117 		error = ENXIO;
118 		goto fail;
119 	}
120 
121 	/* Clear interrupt conditions */
122 	bus_write_1(sc->io_res, ICH_HST_STA, 0xff);
123 
124 	/* Set up interrupt handler */
125 	error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
126 	    NULL, ichsmb_device_intr, sc, &sc->irq_handle);
127 	if (error != 0) {
128 		device_printf(dev, "can't setup irq\n");
129 		goto fail;
130 	}
131 
132 	/* Attach children when interrupts are available */
133 	return (bus_delayed_attach_children(dev));
134 fail:
135 	mtx_destroy(&sc->mutex);
136 	return (error);
137 }
138 
139 /********************************************************************
140 			SMBUS METHODS
141 ********************************************************************/
142 
143 int
144 ichsmb_callback(device_t dev, int index, void *data)
145 {
146 	int smb_error = 0;
147 
148 	DBG("index=%d how=%d\n", index, data ? *(int *)data : -1);
149 	switch (index) {
150 	case SMB_REQUEST_BUS:
151 		break;
152 	case SMB_RELEASE_BUS:
153 		break;
154 	default:
155 		smb_error = SMB_EABORT;	/* XXX */
156 		break;
157 	}
158 	DBG("smb_error=%d\n", smb_error);
159 	return (smb_error);
160 }
161 
162 int
163 ichsmb_quick(device_t dev, u_char slave, int how)
164 {
165 	const sc_p sc = device_get_softc(dev);
166 	int smb_error;
167 
168 	DBG("slave=0x%02x how=%d\n", slave, how);
169 	KASSERT(sc->ich_cmd == -1,
170 	    ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
171 	switch (how) {
172 	case SMB_QREAD:
173 	case SMB_QWRITE:
174 		mtx_lock(&sc->mutex);
175 		sc->ich_cmd = ICH_HST_CNT_SMB_CMD_QUICK;
176 		bus_write_1(sc->io_res, ICH_XMIT_SLVA,
177 		    slave | (how == SMB_QREAD ?
178 	    		ICH_XMIT_SLVA_READ : ICH_XMIT_SLVA_WRITE));
179 		bus_write_1(sc->io_res, ICH_HST_CNT,
180 		    ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
181 		smb_error = ichsmb_wait(sc);
182 		mtx_unlock(&sc->mutex);
183 		break;
184 	default:
185 		smb_error = SMB_ENOTSUPP;
186 	}
187 	DBG("smb_error=%d\n", smb_error);
188 	return (smb_error);
189 }
190 
191 int
192 ichsmb_sendb(device_t dev, u_char slave, char byte)
193 {
194 	const sc_p sc = device_get_softc(dev);
195 	int smb_error;
196 
197 	DBG("slave=0x%02x byte=0x%02x\n", slave, (u_char)byte);
198 	KASSERT(sc->ich_cmd == -1,
199 	    ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
200 	mtx_lock(&sc->mutex);
201 	sc->ich_cmd = ICH_HST_CNT_SMB_CMD_BYTE;
202 	bus_write_1(sc->io_res, ICH_XMIT_SLVA,
203 	    slave | ICH_XMIT_SLVA_WRITE);
204 	bus_write_1(sc->io_res, ICH_HST_CMD, byte);
205 	bus_write_1(sc->io_res, ICH_HST_CNT,
206 	    ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
207 	smb_error = ichsmb_wait(sc);
208 	mtx_unlock(&sc->mutex);
209 	DBG("smb_error=%d\n", smb_error);
210 	return (smb_error);
211 }
212 
213 int
214 ichsmb_recvb(device_t dev, u_char slave, char *byte)
215 {
216 	const sc_p sc = device_get_softc(dev);
217 	int smb_error;
218 
219 	DBG("slave=0x%02x\n", slave);
220 	KASSERT(sc->ich_cmd == -1,
221 	    ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
222 	mtx_lock(&sc->mutex);
223 	sc->ich_cmd = ICH_HST_CNT_SMB_CMD_BYTE;
224 	bus_write_1(sc->io_res, ICH_XMIT_SLVA,
225 	    slave | ICH_XMIT_SLVA_READ);
226 	bus_write_1(sc->io_res, ICH_HST_CNT,
227 	    ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
228 	if ((smb_error = ichsmb_wait(sc)) == SMB_ENOERR)
229 		*byte = bus_read_1(sc->io_res, ICH_D0);
230 	mtx_unlock(&sc->mutex);
231 	DBG("smb_error=%d byte=0x%02x\n", smb_error, (u_char)*byte);
232 	return (smb_error);
233 }
234 
235 int
236 ichsmb_writeb(device_t dev, u_char slave, char cmd, char byte)
237 {
238 	const sc_p sc = device_get_softc(dev);
239 	int smb_error;
240 
241 	DBG("slave=0x%02x cmd=0x%02x byte=0x%02x\n",
242 	    slave, (u_char)cmd, (u_char)byte);
243 	KASSERT(sc->ich_cmd == -1,
244 	    ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
245 	mtx_lock(&sc->mutex);
246 	sc->ich_cmd = ICH_HST_CNT_SMB_CMD_BYTE_DATA;
247 	bus_write_1(sc->io_res, ICH_XMIT_SLVA,
248 	    slave | ICH_XMIT_SLVA_WRITE);
249 	bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
250 	bus_write_1(sc->io_res, ICH_D0, byte);
251 	bus_write_1(sc->io_res, ICH_HST_CNT,
252 	    ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
253 	smb_error = ichsmb_wait(sc);
254 	mtx_unlock(&sc->mutex);
255 	DBG("smb_error=%d\n", smb_error);
256 	return (smb_error);
257 }
258 
259 int
260 ichsmb_writew(device_t dev, u_char slave, char cmd, short word)
261 {
262 	const sc_p sc = device_get_softc(dev);
263 	int smb_error;
264 
265 	DBG("slave=0x%02x cmd=0x%02x word=0x%04x\n",
266 	    slave, (u_char)cmd, (u_int16_t)word);
267 	KASSERT(sc->ich_cmd == -1,
268 	    ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
269 	mtx_lock(&sc->mutex);
270 	sc->ich_cmd = ICH_HST_CNT_SMB_CMD_WORD_DATA;
271 	bus_write_1(sc->io_res, ICH_XMIT_SLVA,
272 	    slave | ICH_XMIT_SLVA_WRITE);
273 	bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
274 	bus_write_1(sc->io_res, ICH_D0, word & 0xff);
275 	bus_write_1(sc->io_res, ICH_D1, word >> 8);
276 	bus_write_1(sc->io_res, ICH_HST_CNT,
277 	    ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
278 	smb_error = ichsmb_wait(sc);
279 	mtx_unlock(&sc->mutex);
280 	DBG("smb_error=%d\n", smb_error);
281 	return (smb_error);
282 }
283 
284 int
285 ichsmb_readb(device_t dev, u_char slave, char cmd, char *byte)
286 {
287 	const sc_p sc = device_get_softc(dev);
288 	int smb_error;
289 
290 	DBG("slave=0x%02x cmd=0x%02x\n", slave, (u_char)cmd);
291 	KASSERT(sc->ich_cmd == -1,
292 	    ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
293 	mtx_lock(&sc->mutex);
294 	sc->ich_cmd = ICH_HST_CNT_SMB_CMD_BYTE_DATA;
295 	bus_write_1(sc->io_res, ICH_XMIT_SLVA,
296 	    slave | ICH_XMIT_SLVA_READ);
297 	bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
298 	bus_write_1(sc->io_res, ICH_HST_CNT,
299 	    ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
300 	if ((smb_error = ichsmb_wait(sc)) == SMB_ENOERR)
301 		*byte = bus_read_1(sc->io_res, ICH_D0);
302 	mtx_unlock(&sc->mutex);
303 	DBG("smb_error=%d byte=0x%02x\n", smb_error, (u_char)*byte);
304 	return (smb_error);
305 }
306 
307 int
308 ichsmb_readw(device_t dev, u_char slave, char cmd, short *word)
309 {
310 	const sc_p sc = device_get_softc(dev);
311 	int smb_error;
312 
313 	DBG("slave=0x%02x cmd=0x%02x\n", slave, (u_char)cmd);
314 	KASSERT(sc->ich_cmd == -1,
315 	    ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
316 	mtx_lock(&sc->mutex);
317 	sc->ich_cmd = ICH_HST_CNT_SMB_CMD_WORD_DATA;
318 	bus_write_1(sc->io_res, ICH_XMIT_SLVA,
319 	    slave | ICH_XMIT_SLVA_READ);
320 	bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
321 	bus_write_1(sc->io_res, ICH_HST_CNT,
322 	    ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
323 	if ((smb_error = ichsmb_wait(sc)) == SMB_ENOERR) {
324 		*word = (bus_read_1(sc->io_res,
325 			ICH_D0) & 0xff)
326 		  | (bus_read_1(sc->io_res,
327 			ICH_D1) << 8);
328 	}
329 	mtx_unlock(&sc->mutex);
330 	DBG("smb_error=%d word=0x%04x\n", smb_error, (u_int16_t)*word);
331 	return (smb_error);
332 }
333 
334 int
335 ichsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata)
336 {
337 	const sc_p sc = device_get_softc(dev);
338 	int smb_error;
339 
340 	DBG("slave=0x%02x cmd=0x%02x sdata=0x%04x\n",
341 	    slave, (u_char)cmd, (u_int16_t)sdata);
342 	KASSERT(sc->ich_cmd == -1,
343 	    ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
344 	mtx_lock(&sc->mutex);
345 	sc->ich_cmd = ICH_HST_CNT_SMB_CMD_PROC_CALL;
346 	bus_write_1(sc->io_res, ICH_XMIT_SLVA,
347 	    slave | ICH_XMIT_SLVA_WRITE);
348 	bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
349 	bus_write_1(sc->io_res, ICH_D0, sdata & 0xff);
350 	bus_write_1(sc->io_res, ICH_D1, sdata >> 8);
351 	bus_write_1(sc->io_res, ICH_HST_CNT,
352 	    ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
353 	if ((smb_error = ichsmb_wait(sc)) == SMB_ENOERR) {
354 		*rdata = (bus_read_1(sc->io_res,
355 			ICH_D0) & 0xff)
356 		  | (bus_read_1(sc->io_res,
357 			ICH_D1) << 8);
358 	}
359 	mtx_unlock(&sc->mutex);
360 	DBG("smb_error=%d rdata=0x%04x\n", smb_error, (u_int16_t)*rdata);
361 	return (smb_error);
362 }
363 
364 int
365 ichsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf)
366 {
367 	const sc_p sc = device_get_softc(dev);
368 	int smb_error;
369 
370 	DBG("slave=0x%02x cmd=0x%02x count=%d\n", slave, (u_char)cmd, count);
371 #if ICHSMB_DEBUG
372 #define DISP(ch)	(((ch) < 0x20 || (ch) >= 0x7e) ? '.' : (ch))
373 	{
374 	    u_char *p;
375 
376 	    for (p = (u_char *)buf; p - (u_char *)buf < 32; p += 8) {
377 		DBG("%02x: %02x %02x %02x %02x %02x %02x %02x %02x"
378 		    "  %c%c%c%c%c%c%c%c", (p - (u_char *)buf),
379 		    p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],
380 		    DISP(p[0]), DISP(p[1]), DISP(p[2]), DISP(p[3]),
381 		    DISP(p[4]), DISP(p[5]), DISP(p[6]), DISP(p[7]));
382 	    }
383 	}
384 #undef DISP
385 #endif
386 	KASSERT(sc->ich_cmd == -1,
387 	    ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
388 	if (count < 1 || count > 32)
389 		return (SMB_EINVAL);
390 	bcopy(buf, sc->block_data, count);
391 	sc->block_count = count;
392 	sc->block_index = 1;
393 	sc->block_write = 1;
394 
395 	mtx_lock(&sc->mutex);
396 	sc->ich_cmd = ICH_HST_CNT_SMB_CMD_BLOCK;
397 	bus_write_1(sc->io_res, ICH_XMIT_SLVA,
398 	    slave | ICH_XMIT_SLVA_WRITE);
399 	bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
400 	bus_write_1(sc->io_res, ICH_D0, count);
401 	bus_write_1(sc->io_res, ICH_BLOCK_DB, buf[0]);
402 	bus_write_1(sc->io_res, ICH_HST_CNT,
403 	    ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
404 	smb_error = ichsmb_wait(sc);
405 	mtx_unlock(&sc->mutex);
406 	DBG("smb_error=%d\n", smb_error);
407 	return (smb_error);
408 }
409 
410 int
411 ichsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf)
412 {
413 	const sc_p sc = device_get_softc(dev);
414 	int smb_error;
415 
416 	DBG("slave=0x%02x cmd=0x%02x count=%d\n", slave, (u_char)cmd, count);
417 	KASSERT(sc->ich_cmd == -1,
418 	    ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
419 	if (*count < 1 || *count > 32)
420 		return (SMB_EINVAL);
421 	bzero(sc->block_data, sizeof(sc->block_data));
422 	sc->block_count = 0;
423 	sc->block_index = 0;
424 	sc->block_write = 0;
425 
426 	mtx_lock(&sc->mutex);
427 	sc->ich_cmd = ICH_HST_CNT_SMB_CMD_BLOCK;
428 	bus_write_1(sc->io_res, ICH_XMIT_SLVA,
429 	    slave | ICH_XMIT_SLVA_READ);
430 	bus_write_1(sc->io_res, ICH_HST_CMD, cmd);
431 	bus_write_1(sc->io_res, ICH_D0, *count); /* XXX? */
432 	bus_write_1(sc->io_res, ICH_HST_CNT,
433 	    ICH_HST_CNT_START | ICH_HST_CNT_INTREN | sc->ich_cmd);
434 	if ((smb_error = ichsmb_wait(sc)) == SMB_ENOERR) {
435 		bcopy(sc->block_data, buf, min(sc->block_count, *count));
436 		*count = sc->block_count;
437 	}
438 	mtx_unlock(&sc->mutex);
439 	DBG("smb_error=%d\n", smb_error);
440 #if ICHSMB_DEBUG
441 #define DISP(ch)	(((ch) < 0x20 || (ch) >= 0x7e) ? '.' : (ch))
442 	{
443 	    u_char *p;
444 
445 	    for (p = (u_char *)buf; p - (u_char *)buf < 32; p += 8) {
446 		DBG("%02x: %02x %02x %02x %02x %02x %02x %02x %02x"
447 		    "  %c%c%c%c%c%c%c%c", (p - (u_char *)buf),
448 		    p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],
449 		    DISP(p[0]), DISP(p[1]), DISP(p[2]), DISP(p[3]),
450 		    DISP(p[4]), DISP(p[5]), DISP(p[6]), DISP(p[7]));
451 	    }
452 	}
453 #undef DISP
454 #endif
455 	return (smb_error);
456 }
457 
458 /********************************************************************
459 			OTHER FUNCTIONS
460 ********************************************************************/
461 
462 /*
463  * This table describes what interrupts we should ever expect to
464  * see after each ICH command, not including the SMBALERT interrupt.
465  */
466 static const u_int8_t ichsmb_state_irqs[] = {
467 	/* quick */
468 	(ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR),
469 	/* byte */
470 	(ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR),
471 	/* byte data */
472 	(ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR),
473 	/* word data */
474 	(ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR),
475 	/* process call */
476 	(ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR),
477 	/* block */
478 	(ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR
479 	    | ICH_HST_STA_BYTE_DONE_STS),
480 	/* i2c read (not used) */
481 	(ICH_HST_STA_BUS_ERR | ICH_HST_STA_DEV_ERR | ICH_HST_STA_INTR
482 	    | ICH_HST_STA_BYTE_DONE_STS)
483 };
484 
485 /*
486  * Interrupt handler. This handler is bus-independent. Note that our
487  * interrupt may be shared, so we must handle "false" interrupts.
488  */
489 void
490 ichsmb_device_intr(void *cookie)
491 {
492 	const sc_p sc = cookie;
493 	const device_t dev = sc->dev;
494 	const int maxloops = 16;
495 	u_int8_t status;
496 	u_int8_t ok_bits;
497 	int cmd_index;
498         int count;
499 
500 	mtx_lock(&sc->mutex);
501 	for (count = 0; count < maxloops; count++) {
502 
503 		/* Get and reset status bits */
504 		status = bus_read_1(sc->io_res, ICH_HST_STA);
505 #if ICHSMB_DEBUG
506 		if ((status & ~(ICH_HST_STA_INUSE_STS | ICH_HST_STA_HOST_BUSY))
507 		    || count > 0) {
508 			DBG("%d stat=0x%02x\n", count, status);
509 		}
510 #endif
511 		status &= ~(ICH_HST_STA_INUSE_STS | ICH_HST_STA_HOST_BUSY |
512 		    ICH_HST_STA_SMBALERT_STS);
513 		if (status == 0)
514 			break;
515 
516 		/* Check for unexpected interrupt */
517 		ok_bits = ICH_HST_STA_SMBALERT_STS;
518 		cmd_index = sc->ich_cmd >> 2;
519 		if (sc->ich_cmd != -1) {
520 			KASSERT(cmd_index < sizeof(ichsmb_state_irqs),
521 			    ("%s: ich_cmd=%d", device_get_nameunit(dev),
522 			    sc->ich_cmd));
523 			ok_bits |= ichsmb_state_irqs[cmd_index];
524 		}
525 		if ((status & ~ok_bits) != 0) {
526 			device_printf(dev, "irq 0x%02x during %d\n", status,
527 			    cmd_index);
528 			bus_write_1(sc->io_res,
529 			    ICH_HST_STA, (status & ~ok_bits));
530 			continue;
531 		}
532 
533 		/* Check for bus error */
534 		if (status & ICH_HST_STA_BUS_ERR) {
535 			sc->smb_error = SMB_ECOLLI;	/* XXX SMB_EBUSERR? */
536 			goto finished;
537 		}
538 
539 		/* Check for device error */
540 		if (status & ICH_HST_STA_DEV_ERR) {
541 			sc->smb_error = SMB_ENOACK;	/* or SMB_ETIMEOUT? */
542 			goto finished;
543 		}
544 
545 		/* Check for byte completion in block transfer */
546 		if (status & ICH_HST_STA_BYTE_DONE_STS) {
547 			if (sc->block_write) {
548 				if (sc->block_index < sc->block_count) {
549 
550 					/* Write next byte */
551 					bus_write_1(sc->io_res,
552 					    ICH_BLOCK_DB,
553 					    sc->block_data[sc->block_index++]);
554 				}
555 			} else {
556 
557 				/* First interrupt, get the count also */
558 				if (sc->block_index == 0) {
559 					sc->block_count = bus_read_1(
560 					    sc->io_res, ICH_D0);
561 				}
562 
563 				/* Get next byte, if any */
564 				if (sc->block_index < sc->block_count) {
565 
566 					/* Read next byte */
567 					sc->block_data[sc->block_index++] =
568 					    bus_read_1(sc->io_res,
569 					      ICH_BLOCK_DB);
570 
571 					/* Set "LAST_BYTE" bit before reading
572 					   the last byte of block data */
573 					if (sc->block_index
574 					    >= sc->block_count - 1) {
575 						bus_write_1(sc->io_res,
576 						    ICH_HST_CNT,
577 						    ICH_HST_CNT_LAST_BYTE
578 							| ICH_HST_CNT_INTREN
579 							| sc->ich_cmd);
580 					}
581 				}
582 			}
583 		}
584 
585 		/* Check command completion */
586 		if (status & ICH_HST_STA_INTR) {
587 			sc->smb_error = SMB_ENOERR;
588 finished:
589 			sc->ich_cmd = -1;
590 			bus_write_1(sc->io_res,
591 			    ICH_HST_STA, status);
592 			wakeup(sc);
593 			break;
594 		}
595 
596 		/* Clear status bits and try again */
597 		bus_write_1(sc->io_res, ICH_HST_STA, status);
598 	}
599 	mtx_unlock(&sc->mutex);
600 
601 	/* Too many loops? */
602 	if (count == maxloops) {
603 		device_printf(dev, "interrupt loop, status=0x%02x\n",
604 		    bus_read_1(sc->io_res, ICH_HST_STA));
605 	}
606 }
607 
608 /*
609  * Wait for command completion. Assumes mutex is held.
610  * Returns an SMB_* error code.
611  */
612 static int
613 ichsmb_wait(sc_p sc)
614 {
615 	const device_t dev = sc->dev;
616 	int error, smb_error;
617 
618 	KASSERT(sc->ich_cmd != -1,
619 	    ("%s: ich_cmd=%d\n", __func__ , sc->ich_cmd));
620 	mtx_assert(&sc->mutex, MA_OWNED);
621 	error = msleep(sc, &sc->mutex, PZERO, "ichsmb", hz / 4);
622 	DBG("msleep -> %d\n", error);
623 	switch (error) {
624 	case 0:
625 		smb_error = sc->smb_error;
626 		break;
627 	case EWOULDBLOCK:
628 		device_printf(dev, "device timeout, status=0x%02x\n",
629 		    bus_read_1(sc->io_res, ICH_HST_STA));
630 		sc->ich_cmd = -1;
631 		smb_error = SMB_ETIMEOUT;
632 		break;
633 	default:
634 		smb_error = SMB_EABORT;
635 		break;
636 	}
637 	return (smb_error);
638 }
639 
640 /*
641  * Release resources associated with device.
642  */
643 void
644 ichsmb_release_resources(sc_p sc)
645 {
646 	const device_t dev = sc->dev;
647 
648 	if (sc->irq_handle != NULL) {
649 		bus_teardown_intr(dev, sc->irq_res, sc->irq_handle);
650 		sc->irq_handle = NULL;
651 	}
652 	if (sc->irq_res != NULL) {
653 		bus_release_resource(dev,
654 		    SYS_RES_IRQ, sc->irq_rid, sc->irq_res);
655 		sc->irq_res = NULL;
656 	}
657 	if (sc->io_res != NULL) {
658 		bus_release_resource(dev,
659 		    SYS_RES_IOPORT, sc->io_rid, sc->io_res);
660 		sc->io_res = NULL;
661 	}
662 }
663 
664 int
665 ichsmb_detach(device_t dev)
666 {
667 	const sc_p sc = device_get_softc(dev);
668 	int error;
669 
670 	error = bus_generic_detach(dev);
671 	if (error)
672 		return (error);
673 	device_delete_child(dev, sc->smb);
674 	ichsmb_release_resources(sc);
675 	mtx_destroy(&sc->mutex);
676 
677 	return 0;
678 }
679 
680 DRIVER_MODULE(smbus, ichsmb, smbus_driver, 0, 0);
681