1 /* 2 * Copyright (c) 2014 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Matthew Dillon <dillon@backplane.com> and was subsequently ported 6 * to FreeBSD by Michael Gmelin <freebsd@grem.de> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 /* 36 * Intel fourth generation mobile cpus integrated I2C device. 37 * 38 * Datasheet reference: Section 22. 39 * 40 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/4th-gen-core-family-mobile-i-o-datasheet.pdf 41 * 42 * This is a from-scratch driver under the BSD license using the Intel data 43 * sheet and the linux driver for reference. All code is freshly written 44 * without referencing the linux driver code. However, during testing 45 * I am also using the linux driver code as a reference to help resolve any 46 * issues that come. These will be specifically documented in the code. 47 * 48 * This controller is an I2C master only and cannot act as a slave. The IO 49 * voltage should be set by the BIOS. Standard (100Kb/s) and Fast (400Kb/s) 50 * and fast mode plus (1MB/s) is supported. High speed mode (3.4 MB/s) is NOT 51 * supported. 52 */ 53 54 #ifndef _ICHIIC_IG4_REG_H_ 55 #define _ICHIIC_IG4_REG_H_ 56 57 /* 58 * 22.2 MMIO registers can be accessed through BAR0 in PCI mode or through 59 * BAR1 when in ACPI mode. 60 * 61 * Register width is 32-bits 62 * 63 * 22.2 Default Values on device reset are 0 except as specified here: 64 * TAR_ADD 0x00000055 65 * SS_SCL_HCNT 0x00000264 66 * SS_SCL_LCNT 0x000002C2 67 * FS_SCL_HCNT 0x0000006E 68 * FS_SCL_LCNT 0x000000CF 69 * INTR_MASK 0x000008FF 70 * I2C_STA 0x00000006 71 * SDA_HOLD 0x00000001 72 * SDA_SETUP 0x00000064 73 * COMP_PARAM1 0x00FFFF6E 74 */ 75 76 #define IG4_REG_CTL 0x0000 /* RW Control Register */ 77 #define IG4_REG_TAR_ADD 0x0004 /* RW Target Address */ 78 #define IG4_REG_HS_MADDR 0x000C /* RW High Speed Master Mode Code Address*/ 79 #define IG4_REG_DATA_CMD 0x0010 /* RW Data Buffer and Command */ 80 #define IG4_REG_SS_SCL_HCNT 0x0014 /* RW Std Speed clock High Count */ 81 #define IG4_REG_SS_SCL_LCNT 0x0018 /* RW Std Speed clock Low Count */ 82 #define IG4_REG_FS_SCL_HCNT 0x001C /* RW Fast Speed clock High Count */ 83 #define IG4_REG_FS_SCL_LCNT 0x0020 /* RW Fast Speed clock Low Count */ 84 #define IG4_REG_INTR_STAT 0x002C /* RO Interrupt Status */ 85 #define IG4_REG_INTR_MASK 0x0030 /* RW Interrupt Mask */ 86 #define IG4_REG_RAW_INTR_STAT 0x0034 /* RO Raw Interrupt Status */ 87 #define IG4_REG_RX_TL 0x0038 /* RW Receive FIFO Threshold */ 88 #define IG4_REG_TX_TL 0x003C /* RW Transmit FIFO Threshold */ 89 #define IG4_REG_CLR_INTR 0x0040 /* RO Clear Interrupt */ 90 #define IG4_REG_CLR_RX_UNDER 0x0044 /* RO Clear RX_Under Interrupt */ 91 #define IG4_REG_CLR_RX_OVER 0x0048 /* RO Clear RX_Over Interrupt */ 92 #define IG4_REG_CLR_TX_OVER 0x004C /* RO Clear TX_Over Interrupt */ 93 #define IG4_REG_CLR_RD_REQ 0x0050 /* RO Clear RD_Req Interrupt */ 94 #define IG4_REG_CLR_TX_ABORT 0x0054 /* RO Clear TX_Abort Interrupt */ 95 #define IG4_REG_CLR_RX_DONE 0x0058 /* RO Clear RX_Done Interrupt */ 96 #define IG4_REG_CLR_ACTIVITY 0x005C /* RO Clear Activity Interrupt */ 97 #define IG4_REG_CLR_STOP_DET 0x0060 /* RO Clear STOP Detection Int */ 98 #define IG4_REG_CLR_START_DET 0x0064 /* RO Clear START Detection Int */ 99 #define IG4_REG_CLR_GEN_CALL 0x0068 /* RO Clear General Call Interrupt */ 100 #define IG4_REG_I2C_EN 0x006C /* RW I2C Enable */ 101 #define IG4_REG_I2C_STA 0x0070 /* RO I2C Status */ 102 #define IG4_REG_TXFLR 0x0074 /* RO Transmit FIFO Level */ 103 #define IG4_REG_RXFLR 0x0078 /* RO Receive FIFO Level */ 104 #define IG4_REG_SDA_HOLD 0x007C /* RW SDA Hold Time Length */ 105 #define IG4_REG_TX_ABRT_SOURCE 0x0080 /* RO Transmit Abort Source */ 106 #define IG4_REG_SLV_DATA_NACK 0x0084 /* RW General Slave Data NACK */ 107 #define IG4_REG_DMA_CTRL 0x0088 /* RW DMA Control */ 108 #define IG4_REG_DMA_TDLR 0x008C /* RW DMA Transmit Data Level */ 109 #define IG4_REG_DMA_RDLR 0x0090 /* RW DMA Receive Data Level */ 110 #define IG4_REG_SDA_SETUP 0x0094 /* RW SDA Setup */ 111 #define IG4_REG_ACK_GENERAL_CALL 0x0098 /* RW I2C ACK General Call */ 112 #define IG4_REG_ENABLE_STATUS 0x009C /* RO Enable Status */ 113 /* Available at least on Atom SoCs, Haswell mobile and some Skylakes. */ 114 #define IG4_REG_COMP_PARAM1 0x00F4 /* RO Component Parameter */ 115 #define IG4_REG_COMP_VER 0x00F8 /* RO Component Version */ 116 /* Available at least on Atom SoCs */ 117 #define IG4_REG_COMP_TYPE 0x00FC /* RO Probe width/endian? (linux) */ 118 /* 0x200-0x2FF - Additional registers available on Skylake-U/Y and others */ 119 #define IG4_REG_RESETS_SKL 0x0204 /* RW Reset Register */ 120 #define IG4_REG_ACTIVE_LTR_VALUE 0x0210 /* RW Active LTR Value */ 121 #define IG4_REG_IDLE_LTR_VALUE 0x0214 /* RW Idle LTR Value */ 122 #define IG4_REG_TX_ACK_COUNT 0x0218 /* RO TX ACK Count */ 123 #define IG4_REG_RX_BYTE_COUNT 0x021C /* RO RX ACK Count */ 124 #define IG4_REG_DEVIDLE_CTRL 0x024C /* RW Device Control */ 125 /* Available at least on Atom SoCs */ 126 #define IG4_REG_CLK_PARMS 0x0800 /* RW Clock Parameters */ 127 #define IG4_CLK_PARMS_EN 0x00000001 /* functional clock ungated */ 128 /* Available at least on Atom SoCs and Haswell mobile */ 129 #define IG4_REG_RESETS_HSW 0x0804 /* RW Reset Register */ 130 #define IG4_REG_GENERAL 0x0808 /* RW General Register */ 131 /* These LTR config registers are at least available on Haswell mobile. */ 132 #define IG4_REG_SW_LTR_VALUE 0x0810 /* RW SW LTR Value */ 133 #define IG4_REG_AUTO_LTR_VALUE 0x0814 /* RW Auto LTR Value */ 134 135 /* 136 * CTL - Control Register 22.2.1 137 * Default Value: 0x0000007F. 138 * 139 * RESTARTEN - RW Restart Enable 140 * 10BIT - RW Controller operates in 10-bit mode, else 7-bit 141 * 142 * NOTE: When restart is disabled the controller is incapable of 143 * performing the following functions: 144 * 145 * Sending a START Byte 146 * Performing any high-speed mode op 147 * Performing direction changes in combined format mode 148 * Performing a read operation with a 10-bit address 149 * 150 * Attempting to perform the above operations will result in the 151 * TX_ABORT bit being set in RAW_INTR_STAT. 152 */ 153 #define IG4_CTL_SLAVE_DISABLE 0x0040 /* snarfed from linux */ 154 #define IG4_CTL_RESTARTEN 0x0020 /* Allow Restart when master */ 155 #define IG4_CTL_10BIT 0x0010 /* ctlr accepts 10-bit addresses */ 156 #define IG4_CTL_SPEED_MASK 0x0006 /* speed at which the I2C operates */ 157 #define IG4_CTL_MASTER 0x0001 /* snarfed from linux */ 158 159 #define IG4_CTL_SPEED_HIGH 0x0006 /* snarfed from linux */ 160 #define IG4_CTL_SPEED_FAST 0x0004 /* snarfed from linux */ 161 #define IG4_CTL_SPEED_STD 0x0002 /* snarfed from linux */ 162 163 /* 164 * TAR_ADD - Target Address Register 22.2.2 165 * Default Value: 0x00000055F 166 * 167 * 10BIT - RW controller starts its transfers in 10-bit 168 * address mode, else 7-bit. 169 * 170 * SPECIAL - RW Indicates whether software performs a General Call 171 * or START BYTE command. 172 * 173 * 0 Ignore GC_OR_START and use TAR address. 174 * 175 * 1 Perform special I2C Command based on GC_OR_START. 176 * 177 * GC_OR_START - RW (only if SPECIAL is set) 178 * 179 * 0 General Call Address. After issuing a General Call, 180 * only writes may be performed. Attempting to issue 181 * a read command results in IX_ABRT in RAW_INTR_STAT. 182 * The controller remains in General Call mode until 183 * bit 11 (SPECIAL) is cleared. 184 * 185 * 1 START BYTE. 186 * 187 * 188 * IC_TAR - RW when transmitting a general call, these bits are 189 * ignored. To generate a START BYTE, the address 190 * needs to be written into these bits once. 191 * 192 * This register should only be updated when the IIC is disabled (I2C_ENABLE=0) 193 */ 194 #define IG4_TAR_10BIT 0x1000 /* start xfer in 10-bit mode */ 195 #define IG4_TAR_SPECIAL 0x0800 /* Perform special command */ 196 #define IG4_TAR_GC_OR_START 0x0400 /* General Call or Start */ 197 #define IG4_TAR_ADDR_MASK 0x03FF /* Target address */ 198 199 /* 200 * TAR_DATA_CMD - Data Buffer and Command Register 22.2.3 201 * 202 * RESTART - RW This bit controls whether a forced RESTART is 203 * issued before the byte is sent or received. 204 * 205 * 0 If not set a RESTART is only issued if the transfer 206 * direction is changing from the previous command. 207 * 208 * 1 A RESTART is issued before the byte is sent or 209 * received, regardless of whether or not the transfer 210 * direction is changing from the previous command. 211 * 212 * STOP - RW This bit controls whether a STOP is issued after 213 * the byte is sent or received. 214 * 215 * 0 STOP is not issued after this byte, regardless 216 * of whether or not the Tx FIFO is empty. 217 * 218 * 1 STOP is issued after this byte, regardless of 219 * whether or not the Tx FIFO is empty. If the 220 * Tx FIFO is not empty the master immediately tries 221 * to start a new transfer by issuing a START and 222 * arbitrating for the bus. 223 * 224 * i.e. the STOP is issued along with this byte, 225 * within the write stream. 226 * 227 * COMMAND - RW Control whether a read or write is performed. 228 * 229 * 0 WRITE 230 * 231 * 1 READ 232 * 233 * DATA (7:0) - RW Contains the data to be transmitted or received 234 * on the I2C bus. 235 * 236 * NOTE: Writing to this register causes a START + slave + RW to be 237 * issued if the direction has changed or the last data byte was 238 * sent with a STOP. 239 * 240 * NOTE: We control termination? so this register must be written 241 * for each byte we wish to receive. We can then drain the 242 * receive FIFO. 243 */ 244 245 #define IG4_DATA_RESTART 0x0400 /* Force RESTART */ 246 #define IG4_DATA_STOP 0x0200 /* Force STOP[+START] */ 247 #define IG4_DATA_COMMAND_RD 0x0100 /* bus direction 0=write 1=read */ 248 #define IG4_DATA_MASK 0x00FF 249 250 /* 251 * SS_SCL_HCNT - Standard Speed Clock High Count Register 22.2.4 252 * SS_SCL_LCNT - Standard Speed Clock Low Count Register 22.2.5 253 * FS_SCL_HCNT - Fast Speed Clock High Count Register 22.2.6 254 * FS_SCL_LCNT - Fast Speed Clock Low Count Register 22.2.7 255 * 256 * COUNT (15:0) - Set the period count to a value between 6 and 257 * 65525. 258 */ 259 #define IG4_SCL_CLOCK_MASK 0xFFFFU /* count bits in register */ 260 261 /* 262 * INTR_STAT - (RO) Interrupt Status Register 22.2.8 263 * INTR_MASK - (RW) Interrupt Mask Register 22.2.9 264 * RAW_INTR_STAT- (RO) Raw Interrupt Status Register 22.2.10 265 * 266 * GEN_CALL Set only when a general call (broadcast) address 267 * is received and acknowleged, stays set until 268 * cleared by reading CLR_GEN_CALL. 269 * 270 * START_DET Set when a START or RESTART condition has occurred 271 * on the interface. 272 * 273 * STOP_DET Set when a STOP condition has occurred on the 274 * interface. 275 * 276 * ACTIVITY Set by any activity on the interface. Cleared 277 * by reading CLR_ACTIVITY or CLR_INTR. 278 * 279 * TX_ABRT Indicates the controller as a transmitter is 280 * unable to complete the intended action. When set, 281 * the controller will hold the TX FIFO in a reset 282 * state (flushed) until CLR_TX_ABORT is read to 283 * clear the condition. Once cleared, the TX FIFO 284 * will be available again. 285 * 286 * TX_EMPTY Indicates that the transmitter is at or below 287 * the specified TX_TL threshold. Automatically 288 * cleared by HW when the buffer level goes above 289 * the threshold. 290 * 291 * TX_OVER Indicates that the processor attempted to write 292 * to the TX FIFO while the TX FIFO was full. Cleared 293 * by reading CLR_TX_OVER. 294 * 295 * RX_FULL Indicates that the receive FIFO has reached or 296 * exceeded the specified RX_TL threshold. Cleared 297 * by HW when the cpu drains the FIFO to below the 298 * threshold. 299 * 300 * RX_OVER Indicates that the receive FIFO was unable to 301 * accept new data and data was lost. Cleared by 302 * reading CLR_RX_OVER. 303 * 304 * RX_UNDER Indicates that the cpu attempted to read data 305 * from the receive buffer while the RX FIFO was 306 * empty. Cleared by reading CLR_RX_UNDER. 307 * 308 * NOTES ON RAW_INTR_STAT: 309 * 310 * This register can be used to monitor the GEN_CALL, START_DET, 311 * STOP_DET, ACTIVITY, TX_ABRT, TX_EMPTY, TX_OVER, RX_FULL, RX_OVER, 312 * and RX_UNDER bits. The documentation is a bit unclear but presumably 313 * this is the unlatched version. 314 * 315 * Code should test FIFO conditions using the I2C_STA (status) register, 316 * not the interrupt status registers. 317 */ 318 319 #define IG4_INTR_GEN_CALL 0x0800 320 #define IG4_INTR_START_DET 0x0400 321 #define IG4_INTR_STOP_DET 0x0200 322 #define IG4_INTR_ACTIVITY 0x0100 323 #define IG4_INTR_TX_ABRT 0x0040 324 #define IG4_INTR_TX_EMPTY 0x0010 325 #define IG4_INTR_TX_OVER 0x0008 326 #define IG4_INTR_RX_FULL 0x0004 327 #define IG4_INTR_RX_OVER 0x0002 328 #define IG4_INTR_RX_UNDER 0x0001 329 330 #define IG4_INTR_ERR_MASK (IG4_INTR_TX_ABRT | IG4_INTR_TX_OVER | \ 331 IG4_INTR_RX_OVER | IG4_INTR_RX_UNDER) 332 333 /* 334 * RX_TL - (RW) Receive FIFO Threshold Register 22.2.11 335 * TX_TL - (RW) Transmit FIFO Threshold Register 22.2.12 336 * 337 * Specify the receive and transmit FIFO threshold register. The 338 * FIFOs have 16 elements. The valid range is 0-15. Setting a 339 * value greater than 15 causes the actual value to be the maximum 340 * depth of the FIFO. 341 * 342 * Generally speaking since everything is messaged, we can use a 343 * mid-level setting for both parameters and (e.g.) fully drain the 344 * receive FIFO on the STOP_DET condition to handle loose ends. 345 */ 346 #define IG4_FIFO_MASK 0x00FF 347 #define IG4_FIFO_LIMIT 16 348 349 /* 350 * CLR_INTR - (RO) Clear Interrupt Register 22.2.13 351 * CLR_RX_UNDER - (RO) Clear Interrupt Register (specific) 22.2.14 352 * CLR_RX_OVER - (RO) Clear Interrupt Register (specific) 22.2.15 353 * CLR_TX_OVER - (RO) Clear Interrupt Register (specific) 22.2.16 354 * CLR_TX_ABORT - (RO) Clear Interrupt Register (specific) 22.2.17 355 * CLR_ACTIVITY - (RO) Clear Interrupt Register (specific) 22.2.18 356 * CLR_STOP_DET - (RO) Clear Interrupt Register (specific) 22.2.19 357 * CLR_START_DET- (RO) Clear Interrupt Register (specific) 22.2.20 358 * CLR_GEN_CALL - (RO) Clear Interrupt Register (specific) 22.2.21 359 * 360 * CLR_* specific operations clear the appropriate bit in the 361 * RAW_INTR_STAT register. Intel does not really document whether 362 * these operations clear the normal interrupt status register. 363 * 364 * CLR_INTR clears bits in the normal interrupt status register and 365 * presumably also the raw(?) register? Intel is again unclear. 366 * 367 * NOTE: CLR_INTR only clears software-clearable interrupts. Hardware 368 * clearable interrupts are controlled entirely by the hardware. 369 * CLR_INTR also clears the TX_ABRT_SOURCE register. 370 * 371 * NOTE: CLR_TX_ABORT also clears the TX_ABRT_SOURCE register and releases 372 * the TX FIFO from its flushed/reset state, allowing more writes 373 * to the TX FIFO. 374 * 375 * NOTE: CLR_ACTIVITY has no effect if the I2C bus is still active. 376 * Intel documents that the bit is automatically cleared when 377 * there is no further activity on the bus. 378 */ 379 #define IG4_CLR_BIT 0x0001 /* Reflects source */ 380 381 /* 382 * I2C_EN - (RW) I2C Enable Register 22.2.22 383 * 384 * ABORT Software can abort an I2C transfer by setting this 385 * bit. In response, the controller issues the STOP 386 * condition over the I2C bus, followed by TX FIFO flush. 387 * Hardware will clear the bit once the STOP has 388 * been detected. This bit can only be set while the 389 * I2C interface is enabled. 390 * 391 * I2C_ENABLE Enable the controller, else disable it. 392 * (Use I2C_ENABLE_STATUS to poll enable status 393 * & wait for changes) 394 */ 395 #define IG4_I2C_ABORT 0x0002 396 #define IG4_I2C_ENABLE 0x0001 397 398 /* 399 * I2C_STA - (RO) I2C Status Register 22.2.23 400 */ 401 #define IG4_STATUS_ACTIVITY 0x0020 /* Controller is active */ 402 #define IG4_STATUS_RX_FULL 0x0010 /* RX FIFO completely full */ 403 #define IG4_STATUS_RX_NOTEMPTY 0x0008 /* RX FIFO not empty */ 404 #define IG4_STATUS_TX_EMPTY 0x0004 /* TX FIFO completely empty */ 405 #define IG4_STATUS_TX_NOTFULL 0x0002 /* TX FIFO not full */ 406 #define IG4_STATUS_I2C_ACTIVE 0x0001 /* I2C bus is active */ 407 408 /* 409 * TXFLR - (RO) Transmit FIFO Level Register 22.2.24 410 * RXFLR - (RO) Receive FIFO Level Register 22.2.25 411 * 412 * Read the number of entries currently in the Transmit or Receive 413 * FIFOs. Note that for some reason the mask is 9 bits instead of 414 * the 8 bits the fill level controls. 415 */ 416 #define IG4_FIFOLVL_MASK 0x01FF 417 418 /* 419 * SDA_HOLD - (RW) SDA Hold Time Length Register 22.2.26 420 * 421 * Set the SDA hold time length register in I2C clocks. 422 */ 423 #define IG4_SDA_TX_HOLD_MASK 0x0000FFFF 424 425 /* 426 * TX_ABRT_SOURCE- (RO) Transmit Abort Source Register 22.2.27 427 * 428 * Indicates the cause of a transmit abort. This can indicate a 429 * software programming error or a device expected address width 430 * mismatch or other issues. The NORESTART conditions and GENCALL_NOACK 431 * can only occur if a programming error was made in the driver software. 432 * 433 * In particular, it should be possible to detect whether any devices 434 * are on the bus by observing the GENCALL_READ status, and it might 435 * be possible to detect ADDR7 vs ADDR10 mismatches. 436 */ 437 #define IG4_ABRTSRC_TRANSFER 0x00010000 /* Abort initiated by user */ 438 #define IG4_ABRTSRC_ARBLOST 0x00001000 /* Arbitration lost */ 439 #define IG4_ABRTSRC_NORESTART_10 0x00000400 /* RESTART disabled */ 440 #define IG4_ABRTSRC_NORESTART_START 0x00000200 /* RESTART disabled */ 441 #define IG4_ABRTSRC_ACKED_START 0x00000080 /* Improper acked START */ 442 #define IG4_ABRTSRC_GENCALL_READ 0x00000020 /* Improper GENCALL */ 443 #define IG4_ABRTSRC_GENCALL_NOACK 0x00000010 /* Nobody acked GENCALL */ 444 #define IG4_ABRTSRC_TXNOACK_DATA 0x00000008 /* data phase no ACK */ 445 #define IG4_ABRTSRC_TXNOACK_ADDR10_2 0x00000004 /* addr10/1 phase no ACK */ 446 #define IG4_ABRTSRC_TXNOACK_ADDR10_1 0x00000002 /* addr10/2 phase no ACK */ 447 #define IG4_ABRTSRC_TXNOACK_ADDR7 0x00000001 /* addr7 phase no ACK */ 448 449 /* 450 * SLV_DATA_NACK - (RW) Generate Slave DATA NACK Register 22.2.28 451 * 452 * When the controller is a receiver a NACK can be generated on 453 * receipt of data. 454 * 455 * NACK_GENERATE Set to 0 for normal NACK/ACK generation. 456 * Set to 1 to generate a NACK after next data 457 * byte received. 458 * 459 */ 460 #define IG4_NACK_GENERATE 0x0001 461 462 /* 463 * DMA_CTRL - (RW) DMA Control Register 22.2.29 464 * 465 * Enables DMA on the transmit and/or receive DMA channel. 466 */ 467 #define IG4_TX_DMA_ENABLE 0x0002 468 #define IG4_RX_DMA_ENABLE 0x0001 469 470 /* 471 * DMA_TDLR - (RW) DMA Transmit Data Level Register 22.2.30 472 * DMA_RDLR - (RW) DMA Receive Data Level Register 22.2.31 473 * 474 * Similar to RX_TL and TX_TL but controls when a DMA burst occurs 475 * to empty or fill the FIFOs. Use the same IG4_FIFO_MASK and 476 * IG4_FIFO_LIMIT defines for RX_RL and TX_TL. 477 */ 478 /* empty */ 479 480 /* 481 * SDA_SETUP - (RW) SDA Setup Time Length Register 22.2.32 482 * 483 * Set the SDA setup time length register in I2C clocks. 484 * The register must be programmed with a value >=2. 485 * (Defaults to 0x64). 486 */ 487 #define IG4_SDA_SETUP_MASK 0x00FF 488 489 /* 490 * ACK_GEN_CALL - (RW) ACK General Call Register 22.2.33 491 * 492 * Control whether the controller responds with a ACK or NACK when 493 * it receives an I2C General Call address. 494 * 495 * If set to 0 a NACK is generated and a General Call interrupt is 496 * NOT generated. Otherwise an ACK + interrupt is generated. 497 */ 498 #define IG4_ACKGC_ACK 0x0001 499 500 /* 501 * ENABLE_STATUS - (RO) Enable Status Registger 22.2.34 502 * 503 * DATA_LOST - Indicates that a slave receiver operation has 504 * been aborted with at least one data byte received 505 * from a transfer due to the I2C controller being 506 * disabled (IG4_I2C_ENABLE -> 0) 507 * 508 * ENABLED - Intel documentation is lacking but I assume this 509 * is a reflection of the IG4_I2C_ENABLE bit in the 510 * I2C_EN register. 511 * 512 */ 513 #define IG4_ENASTAT_DATA_LOST 0x0004 514 #define IG4_ENASTAT_ENABLED 0x0001 515 516 /* 517 * COMP_PARAM1 - (RO) Component Parameter Register 22.2.35 518 * Default Value 0x00FFFF6E 519 * 520 * VALID - Intel documentation is unclear but I believe this 521 * must be read as a 1 to indicate that the rest of 522 * the bits in the register are valid. 523 * 524 * HASDMA - Indicates that the chip is DMA-capable. Presumably 525 * in certain virtualization cases the chip might be 526 * set to not be DMA-capable. 527 * 528 * INTR_IO - Indicates that all interrupts are combined to 529 * generate one interrupt. If not set, interrupts 530 * are individual (more virtualization stuff?) 531 * 532 * HCCNT_RO - Indicates that the clock timing registers are 533 * RW. If not set, the registers are RO. 534 * (more virtualization stuff). 535 * 536 * MAXSPEED - Indicates the maximum speed supported. 537 * 538 * DATAW - Indicates the internal bus width in bits. 539 */ 540 #define IG4_PARAM1_TXFIFO_DEPTH(v) ((((v) >> 16) & 0xFF) + 1) 541 #define IG4_PARAM1_RXFIFO_DEPTH(v) ((((v) >> 8) & 0xFF) + 1) 542 #define IG4_PARAM1_CONFIG_VALID 0x00000080 543 #define IG4_PARAM1_CONFIG_HASDMA 0x00000040 544 #define IG4_PARAM1_CONFIG_INTR_IO 0x00000020 545 #define IG4_PARAM1_CONFIG_HCCNT_RO 0x00000010 546 #define IG4_PARAM1_CONFIG_MAXSPEED_MASK 0x0000000C 547 #define IG4_PARAM1_CONFIG_DATAW_MASK 0x00000003 548 549 #define IG4_CONFIG_MAXSPEED_RESERVED00 0x00000000 550 #define IG4_CONFIG_MAXSPEED_STANDARD 0x00000004 551 #define IG4_CONFIG_MAXSPEED_FAST 0x00000008 552 #define IG4_CONFIG_MAXSPEED_HIGH 0x0000000C 553 554 #define IG4_CONFIG_DATAW_8 0x00000000 555 #define IG4_CONFIG_DATAW_16 0x00000001 556 #define IG4_CONFIG_DATAW_32 0x00000002 557 #define IG4_CONFIG_DATAW_RESERVED11 0x00000003 558 559 /* 560 * COMP_VER - (RO) Component Version Register 22.2.36 561 * 562 * Contains the chip version number. All 32 bits. 563 */ 564 #define IG4_COMP_MIN_VER 0x3131352A 565 566 /* 567 * COMP_TYPE - (RO) (linux) Endian and bus width probe 568 * 569 * Read32 from this register and test against IG4_COMP_TYPE 570 * to determine the bus width. e.g. 01404457 = endian-reversed, 571 * and 00000140 or 00004457 means internal 16-bit bus (?). 572 * 573 * This register is not in the intel documentation, I pulled it 574 * from the linux driver i2c-designware-core.c. 575 */ 576 #define IG4_COMP_TYPE 0x44570140 577 578 /* 579 * RESETS - (RW) Resets Register 22.2.37 580 * 581 * Used to reset the I2C host controller by SW. There is no timing 582 * requirement, software can assert and de-assert in back-to-back 583 * transactions. 584 * 585 * 00 I2C host controller is NOT in reset. 586 * 01 (reserved) 587 * 10 (reserved) 588 * 11 I2C host controller is in reset. 589 */ 590 #define IG4_RESETS_ASSERT_HSW 0x0003 591 #define IG4_RESETS_DEASSERT_HSW 0x0000 592 593 /* Skylake-U/Y and Kaby Lake-U/Y have the reset bits inverted */ 594 #define IG4_RESETS_DEASSERT_SKL 0x0003 595 #define IG4_RESETS_ASSERT_SKL 0x0000 596 597 /* Newer versions of the I2C controller allow to check whether 598 * the above ASSERT/DEASSERT is necessary by querying the DEVIDLE_CONTROL 599 * register. 600 * 601 * the RESTORE_REQUIRED bit can be cleared by writing 1 602 * the DEVICE_IDLE status can be set to put the controller in an idle state 603 * 604 */ 605 #define IG4_RESTORE_REQUIRED 0x0008 606 #define IG4_DEVICE_IDLE 0x0004 607 608 /* 609 * GENERAL - (RW) General Reigster 22.2.38 610 * 611 * IOVOLT 0=1.8V 1=3.3V 612 * 613 * LTR 0=Auto 1=SW 614 * 615 * In Auto mode the BIOS will write to the host controller's 616 * AUTO LTR Value register (offset 0x0814) with the active 617 * state LTR value, and will write to the SW LTR Value register 618 * (offset 0x0810) with the idle state LTR value. 619 * 620 * In SW mode the SW will write to the host controller SW LTR 621 * value (offset 0x0810). It is the SW responsibility to update 622 * the LTR with the appropriate value. 623 */ 624 #define IG4_GENERAL_IOVOLT3_3 0x0008 625 #define IG4_GENERAL_SWMODE 0x0004 626 627 /* 628 * SW_LTR_VALUE - (RW) SW LTR Value Register 22.2.39 629 * AUTO_LTR_VALUE - (RW) SW LTR Value Register 22.2.40 630 * 631 * Default value is 0x00000800 which means the best possible 632 * service/response time. 633 * 634 * It isn't quite clear how the snooping works. There are two scale 635 * bits for both sets but two of the four codes are reserved. The 636 * *SNOOP_VALUE() is specified as a 10-bit latency value. If 0, it 637 * indicates that the device cannot tolerate any delay and needs the 638 * best possible service/response time. 639 * 640 * I think this is for snooping (testing) the I2C bus. The lowest 641 * delay (0) probably runs the controller polling at a high, power hungry 642 * rate. But I dunno. 643 */ 644 #define IG4_SWLTR_NSNOOP_REQ 0x80000000 /* (ro) */ 645 #define IG4_SWLTR_NSNOOP_SCALE_MASK 0x1C000000 /* (ro) */ 646 #define IG4_SWLTR_NSNOOP_SCALE_1US 0x08000000 /* (ro) */ 647 #define IG4_SWLTR_NSNOOP_SCALE_32US 0x0C000000 /* (ro) */ 648 #define IG4_SWLTR_NSNOOP_VALUE_DECODE(v) (((v) >> 16) & 0x3F) 649 #define IG4_SWLTR_NSNOOP_VALUE_ENCODE(v) (((v) & 0x3F) << 16) 650 651 #define IG4_SWLTR_SNOOP_REQ 0x00008000 /* (rw) */ 652 #define IG4_SWLTR_SNOOP_SCALE_MASK 0x00001C00 /* (rw) */ 653 #define IG4_SWLTR_SNOOP_SCALE_1US 0x00000800 /* (rw) */ 654 #define IG4_SWLTR_SNOOP_SCALE_32US 0x00000C00 /* (rw) */ 655 #define IG4_SWLTR_SNOOP_VALUE_DECODE(v) ((v) & 0x3F) 656 #define IG4_SWLTR_SNOOP_VALUE_ENCODE(v) ((v) & 0x3F) 657 658 #endif /* _ICHIIC_IG4_REG_H_ */ 659