1 /* 2 * Copyright (c) 2014 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Matthew Dillon <dillon@backplane.com> and was subsequently ported 6 * to FreeBSD by Michael Gmelin <freebsd@grem.de> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 /* 40 * Intel fourth generation mobile cpus integrated I2C device. 41 * 42 * See ig4_reg.h for datasheet reference and notes. 43 */ 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/module.h> 49 #include <sys/errno.h> 50 #include <sys/lock.h> 51 #include <sys/mutex.h> 52 #include <sys/sx.h> 53 #include <sys/syslog.h> 54 #include <sys/bus.h> 55 56 #include <machine/bus.h> 57 #include <sys/rman.h> 58 #include <machine/resource.h> 59 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pcireg.h> 62 #include <dev/iicbus/iiconf.h> 63 64 #include <dev/ichiic/ig4_reg.h> 65 #include <dev/ichiic/ig4_var.h> 66 67 static int ig4iic_pci_detach(device_t dev); 68 69 #define PCI_CHIP_LYNXPT_LP_I2C_1 0x9c618086 70 #define PCI_CHIP_LYNXPT_LP_I2C_2 0x9c628086 71 #define PCI_CHIP_BRASWELL_I2C_1 0x22c18086 72 #define PCI_CHIP_BRASWELL_I2C_2 0x22c28086 73 #define PCI_CHIP_BRASWELL_I2C_3 0x22c38086 74 #define PCI_CHIP_BRASWELL_I2C_5 0x22c58086 75 #define PCI_CHIP_BRASWELL_I2C_6 0x22c68086 76 #define PCI_CHIP_BRASWELL_I2C_7 0x22c78086 77 #define PCI_CHIP_SKYLAKE_I2C_0 0x9d608086 78 #define PCI_CHIP_SKYLAKE_I2C_1 0x9d618086 79 #define PCI_CHIP_SKYLAKE_I2C_2 0x9d628086 80 #define PCI_CHIP_SKYLAKE_I2C_3 0x9d638086 81 #define PCI_CHIP_SKYLAKE_I2C_4 0x9d648086 82 #define PCI_CHIP_SKYLAKE_I2C_5 0x9d658086 83 #define PCI_CHIP_KABYLAKE_I2C_0 0xa1608086 84 #define PCI_CHIP_KABYLAKE_I2C_1 0xa1618086 85 #define PCI_CHIP_APL_I2C_0 0x5aac8086 86 #define PCI_CHIP_APL_I2C_1 0x5aae8086 87 #define PCI_CHIP_APL_I2C_2 0x5ab08086 88 #define PCI_CHIP_APL_I2C_3 0x5ab28086 89 #define PCI_CHIP_APL_I2C_4 0x5ab48086 90 #define PCI_CHIP_APL_I2C_5 0x5ab68086 91 #define PCI_CHIP_APL_I2C_6 0x5ab88086 92 #define PCI_CHIP_APL_I2C_7 0x5aba8086 93 #define PCI_CHIP_CANNONLAKE_LP_I2C_0 0x9dc58086 94 #define PCI_CHIP_CANNONLAKE_LP_I2C_1 0x9dc68086 95 #define PCI_CHIP_CANNONLAKE_LP_I2C_2 0x9de88086 96 #define PCI_CHIP_CANNONLAKE_LP_I2C_3 0x9de98086 97 #define PCI_CHIP_CANNONLAKE_LP_I2C_4 0x9dea8086 98 #define PCI_CHIP_CANNONLAKE_LP_I2C_5 0x9deb8086 99 #define PCI_CHIP_CANNONLAKE_H_I2C_0 0xa3688086 100 #define PCI_CHIP_CANNONLAKE_H_I2C_1 0xa3698086 101 #define PCI_CHIP_CANNONLAKE_H_I2C_2 0xa36a8086 102 #define PCI_CHIP_CANNONLAKE_H_I2C_3 0xa36b8086 103 104 struct ig4iic_pci_device { 105 uint32_t devid; 106 const char *desc; 107 enum ig4_vers version; 108 }; 109 110 static struct ig4iic_pci_device ig4iic_pci_devices[] = { 111 { PCI_CHIP_LYNXPT_LP_I2C_1, "Intel Lynx Point-LP I2C Controller-1", IG4_HASWELL}, 112 { PCI_CHIP_LYNXPT_LP_I2C_2, "Intel Lynx Point-LP I2C Controller-2", IG4_HASWELL}, 113 { PCI_CHIP_BRASWELL_I2C_1, "Intel Braswell Serial I/O I2C Port 1", IG4_ATOM}, 114 { PCI_CHIP_BRASWELL_I2C_2, "Intel Braswell Serial I/O I2C Port 2", IG4_ATOM}, 115 { PCI_CHIP_BRASWELL_I2C_3, "Intel Braswell Serial I/O I2C Port 3", IG4_ATOM}, 116 { PCI_CHIP_BRASWELL_I2C_5, "Intel Braswell Serial I/O I2C Port 5", IG4_ATOM}, 117 { PCI_CHIP_BRASWELL_I2C_6, "Intel Braswell Serial I/O I2C Port 6", IG4_ATOM}, 118 { PCI_CHIP_BRASWELL_I2C_7, "Intel Braswell Serial I/O I2C Port 7", IG4_ATOM}, 119 { PCI_CHIP_SKYLAKE_I2C_0, "Intel Sunrise Point-LP I2C Controller-0", IG4_SKYLAKE}, 120 { PCI_CHIP_SKYLAKE_I2C_1, "Intel Sunrise Point-LP I2C Controller-1", IG4_SKYLAKE}, 121 { PCI_CHIP_SKYLAKE_I2C_2, "Intel Sunrise Point-LP I2C Controller-2", IG4_SKYLAKE}, 122 { PCI_CHIP_SKYLAKE_I2C_3, "Intel Sunrise Point-LP I2C Controller-3", IG4_SKYLAKE}, 123 { PCI_CHIP_SKYLAKE_I2C_4, "Intel Sunrise Point-LP I2C Controller-4", IG4_SKYLAKE}, 124 { PCI_CHIP_SKYLAKE_I2C_5, "Intel Sunrise Point-LP I2C Controller-5", IG4_SKYLAKE}, 125 { PCI_CHIP_KABYLAKE_I2C_0, "Intel Sunrise Point-H I2C Controller-0", IG4_SKYLAKE}, 126 { PCI_CHIP_KABYLAKE_I2C_1, "Intel Sunrise Point-H I2C Controller-1", IG4_SKYLAKE}, 127 { PCI_CHIP_APL_I2C_0, "Intel Apollo Lake I2C Controller-0", IG4_APL}, 128 { PCI_CHIP_APL_I2C_1, "Intel Apollo Lake I2C Controller-1", IG4_APL}, 129 { PCI_CHIP_APL_I2C_2, "Intel Apollo Lake I2C Controller-2", IG4_APL}, 130 { PCI_CHIP_APL_I2C_3, "Intel Apollo Lake I2C Controller-3", IG4_APL}, 131 { PCI_CHIP_APL_I2C_4, "Intel Apollo Lake I2C Controller-4", IG4_APL}, 132 { PCI_CHIP_APL_I2C_5, "Intel Apollo Lake I2C Controller-5", IG4_APL}, 133 { PCI_CHIP_APL_I2C_6, "Intel Apollo Lake I2C Controller-6", IG4_APL}, 134 { PCI_CHIP_APL_I2C_7, "Intel Apollo Lake I2C Controller-7", IG4_APL}, 135 { PCI_CHIP_CANNONLAKE_LP_I2C_0, "Intel Cannon Lake-LP I2C Controller-0", IG4_CANNONLAKE}, 136 { PCI_CHIP_CANNONLAKE_LP_I2C_1, "Intel Cannon Lake-LP I2C Controller-1", IG4_CANNONLAKE}, 137 { PCI_CHIP_CANNONLAKE_LP_I2C_2, "Intel Cannon Lake-LP I2C Controller-2", IG4_CANNONLAKE}, 138 { PCI_CHIP_CANNONLAKE_LP_I2C_3, "Intel Cannon Lake-LP I2C Controller-3", IG4_CANNONLAKE}, 139 { PCI_CHIP_CANNONLAKE_LP_I2C_4, "Intel Cannon Lake-LP I2C Controller-4", IG4_CANNONLAKE}, 140 { PCI_CHIP_CANNONLAKE_LP_I2C_5, "Intel Cannon Lake-LP I2C Controller-5", IG4_CANNONLAKE}, 141 { PCI_CHIP_CANNONLAKE_H_I2C_0, "Intel Cannon Lake-H I2C Controller-0", IG4_CANNONLAKE}, 142 { PCI_CHIP_CANNONLAKE_H_I2C_1, "Intel Cannon Lake-H I2C Controller-1", IG4_CANNONLAKE}, 143 { PCI_CHIP_CANNONLAKE_H_I2C_2, "Intel Cannon Lake-H I2C Controller-2", IG4_CANNONLAKE}, 144 { PCI_CHIP_CANNONLAKE_H_I2C_3, "Intel Cannon Lake-H I2C Controller-3", IG4_CANNONLAKE}, 145 }; 146 147 static int 148 ig4iic_pci_probe(device_t dev) 149 { 150 ig4iic_softc_t *sc = device_get_softc(dev); 151 uint32_t devid; 152 int i; 153 154 devid = pci_get_devid(dev); 155 for (i = 0; i < nitems(ig4iic_pci_devices); i++) { 156 if (ig4iic_pci_devices[i].devid == devid) { 157 device_set_desc(dev, ig4iic_pci_devices[i].desc); 158 sc->version = ig4iic_pci_devices[i].version; 159 return (BUS_PROBE_DEFAULT); 160 } 161 } 162 return (ENXIO); 163 } 164 165 static int 166 ig4iic_pci_attach(device_t dev) 167 { 168 ig4iic_softc_t *sc = device_get_softc(dev); 169 int error; 170 171 sc->dev = dev; 172 sc->regs_rid = PCIR_BAR(0); 173 sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 174 &sc->regs_rid, RF_ACTIVE); 175 if (sc->regs_res == NULL) { 176 device_printf(dev, "unable to map registers\n"); 177 ig4iic_pci_detach(dev); 178 return (ENXIO); 179 } 180 sc->intr_rid = 0; 181 if (pci_alloc_msi(dev, &sc->intr_rid)) { 182 device_printf(dev, "Using MSI\n"); 183 } 184 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 185 &sc->intr_rid, RF_SHAREABLE | RF_ACTIVE); 186 if (sc->intr_res == NULL) { 187 device_printf(dev, "unable to map interrupt\n"); 188 ig4iic_pci_detach(dev); 189 return (ENXIO); 190 } 191 sc->platform_attached = 1; 192 193 error = ig4iic_attach(sc); 194 if (error) 195 ig4iic_pci_detach(dev); 196 197 return (error); 198 } 199 200 static int 201 ig4iic_pci_detach(device_t dev) 202 { 203 ig4iic_softc_t *sc = device_get_softc(dev); 204 int error; 205 206 if (sc->platform_attached) { 207 error = ig4iic_detach(sc); 208 if (error) 209 return (error); 210 sc->platform_attached = 0; 211 } 212 213 if (sc->intr_res) { 214 bus_release_resource(dev, SYS_RES_IRQ, 215 sc->intr_rid, sc->intr_res); 216 sc->intr_res = NULL; 217 } 218 if (sc->intr_rid != 0) 219 pci_release_msi(dev); 220 if (sc->regs_res) { 221 bus_release_resource(dev, SYS_RES_MEMORY, 222 sc->regs_rid, sc->regs_res); 223 sc->regs_res = NULL; 224 } 225 226 return (0); 227 } 228 229 static int 230 ig4iic_pci_suspend(device_t dev) 231 { 232 ig4iic_softc_t *sc = device_get_softc(dev); 233 234 return (ig4iic_suspend(sc)); 235 } 236 237 static int 238 ig4iic_pci_resume(device_t dev) 239 { 240 ig4iic_softc_t *sc = device_get_softc(dev); 241 242 return (ig4iic_resume(sc)); 243 } 244 245 static device_method_t ig4iic_pci_methods[] = { 246 /* Device interface */ 247 DEVMETHOD(device_probe, ig4iic_pci_probe), 248 DEVMETHOD(device_attach, ig4iic_pci_attach), 249 DEVMETHOD(device_detach, ig4iic_pci_detach), 250 DEVMETHOD(device_suspend, ig4iic_pci_suspend), 251 DEVMETHOD(device_resume, ig4iic_pci_resume), 252 253 /* Bus interface */ 254 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 255 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 256 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 257 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 258 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 259 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 260 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 261 262 /* iicbus interface */ 263 DEVMETHOD(iicbus_transfer, ig4iic_transfer), 264 DEVMETHOD(iicbus_reset, ig4iic_reset), 265 DEVMETHOD(iicbus_callback, ig4iic_callback), 266 267 DEVMETHOD_END 268 }; 269 270 static driver_t ig4iic_pci_driver = { 271 "ig4iic", 272 ig4iic_pci_methods, 273 sizeof(struct ig4iic_softc) 274 }; 275 276 DRIVER_MODULE_ORDERED(ig4iic, pci, ig4iic_pci_driver, ig4iic_devclass, 0, 0, 277 SI_ORDER_ANY); 278 MODULE_DEPEND(ig4iic, pci, 1, 1, 1); 279 MODULE_PNP_INFO("W32:vendor/device", pci, ig4iic, ig4iic_pci_devices, 280 nitems(ig4iic_pci_devices)); 281