xref: /freebsd/sys/dev/ichiic/ig4_pci.c (revision d4eeb02986980bf33dd56c41ceb9fc5f180c0d47)
1 /*
2  * Copyright (c) 2014 The DragonFly Project.  All rights reserved.
3  *
4  * This code is derived from software contributed to The DragonFly Project
5  * by Matthew Dillon <dillon@backplane.com> and was subsequently ported
6  * to FreeBSD by Michael Gmelin <freebsd@grem.de>
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  *
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in
16  *    the documentation and/or other materials provided with the
17  *    distribution.
18  * 3. Neither the name of The DragonFly Project nor the names of its
19  *    contributors may be used to endorse or promote products derived
20  *    from this software without specific, prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
25  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
26  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
28  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
32  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33  * SUCH DAMAGE.
34  */
35 
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
38 
39 /*
40  * Intel fourth generation mobile cpus integrated I2C device.
41  *
42  * See ig4_reg.h for datasheet reference and notes.
43  */
44 
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/kernel.h>
48 #include <sys/module.h>
49 #include <sys/errno.h>
50 #include <sys/lock.h>
51 #include <sys/mutex.h>
52 #include <sys/sx.h>
53 #include <sys/syslog.h>
54 #include <sys/bus.h>
55 
56 #include <machine/bus.h>
57 #include <sys/rman.h>
58 #include <machine/resource.h>
59 
60 #include <dev/pci/pcivar.h>
61 #include <dev/pci/pcireg.h>
62 #include <dev/iicbus/iiconf.h>
63 
64 #include <dev/ichiic/ig4_reg.h>
65 #include <dev/ichiic/ig4_var.h>
66 
67 static int ig4iic_pci_detach(device_t dev);
68 
69 #define PCI_CHIP_BAYTRAIL_I2C_1 	0x0f418086
70 #define PCI_CHIP_BAYTRAIL_I2C_2 	0x0f428086
71 #define PCI_CHIP_BAYTRAIL_I2C_3 	0x0f438086
72 #define PCI_CHIP_BAYTRAIL_I2C_4 	0x0f448086
73 #define PCI_CHIP_BAYTRAIL_I2C_5 	0x0f458086
74 #define PCI_CHIP_BAYTRAIL_I2C_6 	0x0f468086
75 #define PCI_CHIP_BAYTRAIL_I2C_7 	0x0f478086
76 #define PCI_CHIP_LYNXPT_LP_I2C_1	0x9c618086
77 #define PCI_CHIP_LYNXPT_LP_I2C_2	0x9c628086
78 #define PCI_CHIP_BRASWELL_I2C_1 	0x22c18086
79 #define PCI_CHIP_BRASWELL_I2C_2 	0x22c28086
80 #define PCI_CHIP_BRASWELL_I2C_3 	0x22c38086
81 #define PCI_CHIP_BRASWELL_I2C_5 	0x22c58086
82 #define PCI_CHIP_BRASWELL_I2C_6 	0x22c68086
83 #define PCI_CHIP_BRASWELL_I2C_7 	0x22c78086
84 #define PCI_CHIP_SKYLAKE_I2C_0		0x9d608086
85 #define PCI_CHIP_SKYLAKE_I2C_1		0x9d618086
86 #define PCI_CHIP_SKYLAKE_I2C_2		0x9d628086
87 #define PCI_CHIP_SKYLAKE_I2C_3		0x9d638086
88 #define PCI_CHIP_SKYLAKE_I2C_4		0x9d648086
89 #define PCI_CHIP_SKYLAKE_I2C_5		0x9d658086
90 #define PCI_CHIP_KABYLAKE_I2C_0		0xa1608086
91 #define PCI_CHIP_KABYLAKE_I2C_1		0xa1618086
92 #define PCI_CHIP_APL_I2C_0		0x5aac8086
93 #define PCI_CHIP_APL_I2C_1		0x5aae8086
94 #define PCI_CHIP_APL_I2C_2		0x5ab08086
95 #define PCI_CHIP_APL_I2C_3		0x5ab28086
96 #define PCI_CHIP_APL_I2C_4		0x5ab48086
97 #define PCI_CHIP_APL_I2C_5		0x5ab68086
98 #define PCI_CHIP_APL_I2C_6		0x5ab88086
99 #define PCI_CHIP_APL_I2C_7		0x5aba8086
100 #define PCI_CHIP_CANNONLAKE_LP_I2C_0	0x9dc58086
101 #define PCI_CHIP_CANNONLAKE_LP_I2C_1	0x9dc68086
102 #define PCI_CHIP_CANNONLAKE_LP_I2C_2	0x9de88086
103 #define PCI_CHIP_CANNONLAKE_LP_I2C_3	0x9de98086
104 #define PCI_CHIP_CANNONLAKE_LP_I2C_4	0x9dea8086
105 #define PCI_CHIP_CANNONLAKE_LP_I2C_5	0x9deb8086
106 #define PCI_CHIP_CANNONLAKE_H_I2C_0	0xa3688086
107 #define PCI_CHIP_CANNONLAKE_H_I2C_1	0xa3698086
108 #define PCI_CHIP_CANNONLAKE_H_I2C_2	0xa36a8086
109 #define PCI_CHIP_CANNONLAKE_H_I2C_3	0xa36b8086
110 #define PCI_CHIP_COMETLAKE_LP_I2C_0	0x02e88086
111 #define PCI_CHIP_COMETLAKE_LP_I2C_1	0x02e98086
112 #define PCI_CHIP_COMETLAKE_LP_I2C_2	0x02ea8086
113 #define PCI_CHIP_COMETLAKE_LP_I2C_3	0x02eb8086
114 #define PCI_CHIP_COMETLAKE_LP_I2C_4	0x02c58086
115 #define PCI_CHIP_COMETLAKE_LP_I2C_5	0x02c68086
116 #define PCI_CHIP_COMETLAKE_H_I2C_0	0x06e88086
117 #define PCI_CHIP_COMETLAKE_H_I2C_1	0x06e98086
118 #define PCI_CHIP_COMETLAKE_H_I2C_2	0x06ea8086
119 #define PCI_CHIP_COMETLAKE_H_I2C_3	0x06eb8086
120 #define PCI_CHIP_COMETLAKE_V_I2C_0	0xa3e08086
121 #define PCI_CHIP_COMETLAKE_V_I2C_1	0xa3e18086
122 #define PCI_CHIP_COMETLAKE_V_I2C_2	0xa3e28086
123 #define PCI_CHIP_COMETLAKE_V_I2C_3	0xa3e38086
124 #define PCI_CHIP_TIGERLAKE_H_I2C_0	0x43d88086
125 #define PCI_CHIP_TIGERLAKE_H_I2C_1	0x43e88086
126 #define PCI_CHIP_TIGERLAKE_H_I2C_2	0x43e98086
127 #define PCI_CHIP_TIGERLAKE_H_I2C_3	0x43ea8086
128 #define PCI_CHIP_TIGERLAKE_H_I2C_4	0x43eb8086
129 #define PCI_CHIP_TIGERLAKE_H_I2C_5	0x43ad8086
130 #define PCI_CHIP_TIGERLAKE_H_I2C_6	0x43ae8086
131 #define PCI_CHIP_TIGERLAKE_LP_I2C_0	0xa0c58086
132 #define PCI_CHIP_TIGERLAKE_LP_I2C_1	0xa0c68086
133 #define PCI_CHIP_TIGERLAKE_LP_I2C_2	0xa0d88086
134 #define PCI_CHIP_TIGERLAKE_LP_I2C_3	0xa0d98086
135 #define PCI_CHIP_TIGERLAKE_LP_I2C_4	0xa0e88086
136 #define PCI_CHIP_TIGERLAKE_LP_I2C_5	0xa0e98086
137 #define PCI_CHIP_TIGERLAKE_LP_I2C_6	0xa0ea8086
138 #define PCI_CHIP_TIGERLAKE_LP_I2C_7	0xa0eb8086
139 #define PCI_CHIP_GEMINILAKE_I2C_0	0x31ac8086
140 #define PCI_CHIP_GEMINILAKE_I2C_1	0x31ae8086
141 #define PCI_CHIP_GEMINILAKE_I2C_2	0x31b08086
142 #define PCI_CHIP_GEMINILAKE_I2C_3	0x31b28086
143 #define PCI_CHIP_GEMINILAKE_I2C_4	0x31b48086
144 #define PCI_CHIP_GEMINILAKE_I2C_5	0x31b68086
145 #define PCI_CHIP_GEMINILAKE_I2C_6	0x31b88086
146 #define PCI_CHIP_GEMINILAKE_I2C_7	0x31ba8086
147 #define PCI_CHIP_ALDERLAKE_P_I2C_0	0x51e88086
148 #define PCI_CHIP_ALDERLAKE_P_I2C_1	0x51e98086
149 #define PCI_CHIP_ALDERLAKE_P_I2C_2	0x51ea8086
150 #define PCI_CHIP_ALDERLAKE_P_I2C_3	0x51eb8086
151 #define PCI_CHIP_ALDERLAKE_P_I2C_4	0x51c58086
152 #define PCI_CHIP_ALDERLAKE_P_I2C_5	0x51c68086
153 #define PCI_CHIP_ALDERLAKE_P_I2C_6	0x51d88086
154 #define PCI_CHIP_ALDERLAKE_P_I2C_7	0x51d98086
155 #define PCI_CHIP_ALDERLAKE_S_I2C_0	0x7acc8086
156 #define PCI_CHIP_ALDERLAKE_S_I2C_1	0x7acd8086
157 #define PCI_CHIP_ALDERLAKE_S_I2C_2	0x7ace8086
158 #define PCI_CHIP_ALDERLAKE_S_I2C_3	0x7acf8086
159 #define PCI_CHIP_ALDERLAKE_S_I2C_4	0x7afc8086
160 #define PCI_CHIP_ALDERLAKE_S_I2C_5	0x7afd8086
161 #define PCI_CHIP_ALDERLAKE_M_I2C_0	0x54e88086
162 #define PCI_CHIP_ALDERLAKE_M_I2C_1	0x54e98086
163 #define PCI_CHIP_ALDERLAKE_M_I2C_2	0x54ea8086
164 #define PCI_CHIP_ALDERLAKE_M_I2C_3	0x54eb8086
165 #define PCI_CHIP_ALDERLAKE_M_I2C_4	0x54c58086
166 #define PCI_CHIP_ALDERLAKE_M_I2C_5	0x54c68086
167 
168 struct ig4iic_pci_device {
169 	uint32_t	devid;
170 	const char	*desc;
171 	enum ig4_vers	version;
172 };
173 
174 static struct ig4iic_pci_device ig4iic_pci_devices[] = {
175 	{ PCI_CHIP_BAYTRAIL_I2C_1, "Intel BayTrail Serial I/O I2C Port 1", IG4_ATOM},
176 	{ PCI_CHIP_BAYTRAIL_I2C_2, "Intel BayTrail Serial I/O I2C Port 2", IG4_ATOM},
177 	{ PCI_CHIP_BAYTRAIL_I2C_3, "Intel BayTrail Serial I/O I2C Port 3", IG4_ATOM},
178 	{ PCI_CHIP_BAYTRAIL_I2C_4, "Intel BayTrail Serial I/O I2C Port 4", IG4_ATOM},
179 	{ PCI_CHIP_BAYTRAIL_I2C_5, "Intel BayTrail Serial I/O I2C Port 5", IG4_ATOM},
180 	{ PCI_CHIP_BAYTRAIL_I2C_6, "Intel BayTrail Serial I/O I2C Port 6", IG4_ATOM},
181 	{ PCI_CHIP_BAYTRAIL_I2C_7, "Intel BayTrail Serial I/O I2C Port 7", IG4_ATOM},
182 	{ PCI_CHIP_LYNXPT_LP_I2C_1, "Intel Lynx Point-LP I2C Controller-1", IG4_HASWELL},
183 	{ PCI_CHIP_LYNXPT_LP_I2C_2, "Intel Lynx Point-LP I2C Controller-2", IG4_HASWELL},
184 	{ PCI_CHIP_BRASWELL_I2C_1, "Intel Braswell Serial I/O I2C Port 1", IG4_ATOM},
185 	{ PCI_CHIP_BRASWELL_I2C_2, "Intel Braswell Serial I/O I2C Port 2", IG4_ATOM},
186 	{ PCI_CHIP_BRASWELL_I2C_3, "Intel Braswell Serial I/O I2C Port 3", IG4_ATOM},
187 	{ PCI_CHIP_BRASWELL_I2C_5, "Intel Braswell Serial I/O I2C Port 5", IG4_ATOM},
188 	{ PCI_CHIP_BRASWELL_I2C_6, "Intel Braswell Serial I/O I2C Port 6", IG4_ATOM},
189 	{ PCI_CHIP_BRASWELL_I2C_7, "Intel Braswell Serial I/O I2C Port 7", IG4_ATOM},
190 	{ PCI_CHIP_SKYLAKE_I2C_0, "Intel Sunrise Point-LP I2C Controller-0", IG4_SKYLAKE},
191 	{ PCI_CHIP_SKYLAKE_I2C_1, "Intel Sunrise Point-LP I2C Controller-1", IG4_SKYLAKE},
192 	{ PCI_CHIP_SKYLAKE_I2C_2, "Intel Sunrise Point-LP I2C Controller-2", IG4_SKYLAKE},
193 	{ PCI_CHIP_SKYLAKE_I2C_3, "Intel Sunrise Point-LP I2C Controller-3", IG4_SKYLAKE},
194 	{ PCI_CHIP_SKYLAKE_I2C_4, "Intel Sunrise Point-LP I2C Controller-4", IG4_SKYLAKE},
195 	{ PCI_CHIP_SKYLAKE_I2C_5, "Intel Sunrise Point-LP I2C Controller-5", IG4_SKYLAKE},
196 	{ PCI_CHIP_KABYLAKE_I2C_0, "Intel Sunrise Point-H I2C Controller-0", IG4_SKYLAKE},
197 	{ PCI_CHIP_KABYLAKE_I2C_1, "Intel Sunrise Point-H I2C Controller-1", IG4_SKYLAKE},
198 	{ PCI_CHIP_APL_I2C_0, "Intel Apollo Lake I2C Controller-0", IG4_APL},
199 	{ PCI_CHIP_APL_I2C_1, "Intel Apollo Lake I2C Controller-1", IG4_APL},
200 	{ PCI_CHIP_APL_I2C_2, "Intel Apollo Lake I2C Controller-2", IG4_APL},
201 	{ PCI_CHIP_APL_I2C_3, "Intel Apollo Lake I2C Controller-3", IG4_APL},
202 	{ PCI_CHIP_APL_I2C_4, "Intel Apollo Lake I2C Controller-4", IG4_APL},
203 	{ PCI_CHIP_APL_I2C_5, "Intel Apollo Lake I2C Controller-5", IG4_APL},
204 	{ PCI_CHIP_APL_I2C_6, "Intel Apollo Lake I2C Controller-6", IG4_APL},
205 	{ PCI_CHIP_APL_I2C_7, "Intel Apollo Lake I2C Controller-7", IG4_APL},
206 	{ PCI_CHIP_CANNONLAKE_LP_I2C_0, "Intel Cannon Lake-LP I2C Controller-0", IG4_CANNONLAKE},
207 	{ PCI_CHIP_CANNONLAKE_LP_I2C_1, "Intel Cannon Lake-LP I2C Controller-1", IG4_CANNONLAKE},
208 	{ PCI_CHIP_CANNONLAKE_LP_I2C_2, "Intel Cannon Lake-LP I2C Controller-2", IG4_CANNONLAKE},
209 	{ PCI_CHIP_CANNONLAKE_LP_I2C_3, "Intel Cannon Lake-LP I2C Controller-3", IG4_CANNONLAKE},
210 	{ PCI_CHIP_CANNONLAKE_LP_I2C_4, "Intel Cannon Lake-LP I2C Controller-4", IG4_CANNONLAKE},
211 	{ PCI_CHIP_CANNONLAKE_LP_I2C_5, "Intel Cannon Lake-LP I2C Controller-5", IG4_CANNONLAKE},
212 	{ PCI_CHIP_CANNONLAKE_H_I2C_0, "Intel Cannon Lake-H I2C Controller-0", IG4_CANNONLAKE},
213 	{ PCI_CHIP_CANNONLAKE_H_I2C_1, "Intel Cannon Lake-H I2C Controller-1", IG4_CANNONLAKE},
214 	{ PCI_CHIP_CANNONLAKE_H_I2C_2, "Intel Cannon Lake-H I2C Controller-2", IG4_CANNONLAKE},
215 	{ PCI_CHIP_CANNONLAKE_H_I2C_3, "Intel Cannon Lake-H I2C Controller-3", IG4_CANNONLAKE},
216 	{ PCI_CHIP_COMETLAKE_LP_I2C_0, "Intel Comet Lake-LP I2C Controller-0", IG4_CANNONLAKE},
217 	{ PCI_CHIP_COMETLAKE_LP_I2C_1, "Intel Comet Lake-LP I2C Controller-1", IG4_CANNONLAKE},
218 	{ PCI_CHIP_COMETLAKE_LP_I2C_2, "Intel Comet Lake-LP I2C Controller-2", IG4_CANNONLAKE},
219 	{ PCI_CHIP_COMETLAKE_LP_I2C_3, "Intel Comet Lake-LP I2C Controller-3", IG4_CANNONLAKE},
220 	{ PCI_CHIP_COMETLAKE_LP_I2C_4, "Intel Comet Lake-LP I2C Controller-4", IG4_CANNONLAKE},
221 	{ PCI_CHIP_COMETLAKE_LP_I2C_5, "Intel Comet Lake-LP I2C Controller-5", IG4_CANNONLAKE},
222 	{ PCI_CHIP_COMETLAKE_H_I2C_0, "Intel Comet Lake-H I2C Controller-0", IG4_CANNONLAKE},
223 	{ PCI_CHIP_COMETLAKE_H_I2C_1, "Intel Comet Lake-H I2C Controller-1", IG4_CANNONLAKE},
224 	{ PCI_CHIP_COMETLAKE_H_I2C_2, "Intel Comet Lake-H I2C Controller-2", IG4_CANNONLAKE},
225 	{ PCI_CHIP_COMETLAKE_H_I2C_3, "Intel Comet Lake-H I2C Controller-3", IG4_CANNONLAKE},
226 	{ PCI_CHIP_COMETLAKE_V_I2C_0, "Intel Comet Lake-V I2C Controller-0", IG4_CANNONLAKE},
227 	{ PCI_CHIP_COMETLAKE_V_I2C_1, "Intel Comet Lake-V I2C Controller-1", IG4_CANNONLAKE},
228 	{ PCI_CHIP_COMETLAKE_V_I2C_2, "Intel Comet Lake-V I2C Controller-2", IG4_CANNONLAKE},
229 	{ PCI_CHIP_COMETLAKE_V_I2C_3, "Intel Comet Lake-V I2C Controller-3", IG4_CANNONLAKE},
230 	{ PCI_CHIP_TIGERLAKE_H_I2C_0, "Intel Tiger Lake-H I2C Controller-0", IG4_TIGERLAKE},
231 	{ PCI_CHIP_TIGERLAKE_H_I2C_1, "Intel Tiger Lake-H I2C Controller-1", IG4_TIGERLAKE},
232 	{ PCI_CHIP_TIGERLAKE_H_I2C_2, "Intel Tiger Lake-H I2C Controller-2", IG4_TIGERLAKE},
233 	{ PCI_CHIP_TIGERLAKE_H_I2C_3, "Intel Tiger Lake-H I2C Controller-3", IG4_TIGERLAKE},
234 	{ PCI_CHIP_TIGERLAKE_H_I2C_4, "Intel Tiger Lake-H I2C Controller-4", IG4_TIGERLAKE},
235 	{ PCI_CHIP_TIGERLAKE_H_I2C_5, "Intel Tiger Lake-H I2C Controller-5", IG4_TIGERLAKE},
236 	{ PCI_CHIP_TIGERLAKE_H_I2C_6, "Intel Tiger Lake-H I2C Controller-6", IG4_TIGERLAKE},
237 	{ PCI_CHIP_TIGERLAKE_LP_I2C_0, "Intel Tiger Lake-LP I2C Controller-0", IG4_SKYLAKE},
238 	{ PCI_CHIP_TIGERLAKE_LP_I2C_1, "Intel Tiger Lake-LP I2C Controller-1", IG4_SKYLAKE},
239 	{ PCI_CHIP_TIGERLAKE_LP_I2C_2, "Intel Tiger Lake-LP I2C Controller-2", IG4_SKYLAKE},
240 	{ PCI_CHIP_TIGERLAKE_LP_I2C_3, "Intel Tiger Lake-LP I2C Controller-3", IG4_SKYLAKE},
241 	{ PCI_CHIP_TIGERLAKE_LP_I2C_4, "Intel Tiger Lake-LP I2C Controller-4", IG4_SKYLAKE},
242 	{ PCI_CHIP_TIGERLAKE_LP_I2C_5, "Intel Tiger Lake-LP I2C Controller-5", IG4_SKYLAKE},
243 	{ PCI_CHIP_TIGERLAKE_LP_I2C_6, "Intel Tiger Lake-LP I2C Controller-6", IG4_SKYLAKE},
244 	{ PCI_CHIP_TIGERLAKE_LP_I2C_7, "Intel Tiger Lake-LP I2C Controller-7", IG4_SKYLAKE},
245 	{ PCI_CHIP_GEMINILAKE_I2C_0, "Intel Gemini Lake I2C Controller-0", IG4_GEMINILAKE},
246 	{ PCI_CHIP_GEMINILAKE_I2C_1, "Intel Gemini Lake I2C Controller-1", IG4_GEMINILAKE},
247 	{ PCI_CHIP_GEMINILAKE_I2C_2, "Intel Gemini Lake I2C Controller-2", IG4_GEMINILAKE},
248 	{ PCI_CHIP_GEMINILAKE_I2C_3, "Intel Gemini Lake I2C Controller-3", IG4_GEMINILAKE},
249 	{ PCI_CHIP_GEMINILAKE_I2C_4, "Intel Gemini Lake I2C Controller-4", IG4_GEMINILAKE},
250 	{ PCI_CHIP_GEMINILAKE_I2C_5, "Intel Gemini Lake I2C Controller-5", IG4_GEMINILAKE},
251 	{ PCI_CHIP_GEMINILAKE_I2C_6, "Intel Gemini Lake I2C Controller-6", IG4_GEMINILAKE},
252 	{ PCI_CHIP_GEMINILAKE_I2C_7, "Intel Gemini Lake I2C Controller-7", IG4_GEMINILAKE},
253 	{ PCI_CHIP_ALDERLAKE_P_I2C_0, "Intel Alder Lake-P I2C Controller-0", IG4_TIGERLAKE},
254 	{ PCI_CHIP_ALDERLAKE_P_I2C_1, "Intel Alder Lake-P I2C Controller-1", IG4_TIGERLAKE},
255 	{ PCI_CHIP_ALDERLAKE_P_I2C_2, "Intel Alder Lake-P I2C Controller-2", IG4_TIGERLAKE},
256 	{ PCI_CHIP_ALDERLAKE_P_I2C_3, "Intel Alder Lake-P I2C Controller-3", IG4_TIGERLAKE},
257 	{ PCI_CHIP_ALDERLAKE_P_I2C_4, "Intel Alder Lake-P I2C Controller-4", IG4_TIGERLAKE},
258 	{ PCI_CHIP_ALDERLAKE_P_I2C_5, "Intel Alder Lake-P I2C Controller-5", IG4_TIGERLAKE},
259 	{ PCI_CHIP_ALDERLAKE_P_I2C_6, "Intel Alder Lake-P I2C Controller-6", IG4_TIGERLAKE},
260 	{ PCI_CHIP_ALDERLAKE_P_I2C_7, "Intel Alder Lake-P I2C Controller-7", IG4_TIGERLAKE},
261 	{ PCI_CHIP_ALDERLAKE_S_I2C_0, "Intel Alder Lake-S I2C Controller-0", IG4_TIGERLAKE},
262 	{ PCI_CHIP_ALDERLAKE_S_I2C_1, "Intel Alder Lake-S I2C Controller-1", IG4_TIGERLAKE},
263 	{ PCI_CHIP_ALDERLAKE_S_I2C_2, "Intel Alder Lake-S I2C Controller-2", IG4_TIGERLAKE},
264 	{ PCI_CHIP_ALDERLAKE_S_I2C_3, "Intel Alder Lake-S I2C Controller-3", IG4_TIGERLAKE},
265 	{ PCI_CHIP_ALDERLAKE_S_I2C_4, "Intel Alder Lake-S I2C Controller-4", IG4_TIGERLAKE},
266 	{ PCI_CHIP_ALDERLAKE_S_I2C_5, "Intel Alder Lake-S I2C Controller-5", IG4_TIGERLAKE},
267 	{ PCI_CHIP_ALDERLAKE_M_I2C_0, "Intel Alder Lake-M I2C Controller-0", IG4_TIGERLAKE},
268 	{ PCI_CHIP_ALDERLAKE_M_I2C_1, "Intel Alder Lake-M I2C Controller-1", IG4_TIGERLAKE},
269 	{ PCI_CHIP_ALDERLAKE_M_I2C_2, "Intel Alder Lake-M I2C Controller-2", IG4_TIGERLAKE},
270 	{ PCI_CHIP_ALDERLAKE_M_I2C_3, "Intel Alder Lake-M I2C Controller-3", IG4_TIGERLAKE},
271 	{ PCI_CHIP_ALDERLAKE_M_I2C_4, "Intel Alder Lake-M I2C Controller-4", IG4_TIGERLAKE},
272 	{ PCI_CHIP_ALDERLAKE_M_I2C_5, "Intel Alder Lake-M I2C Controller-5", IG4_TIGERLAKE},
273 };
274 
275 static int
276 ig4iic_pci_probe(device_t dev)
277 {
278 	ig4iic_softc_t *sc = device_get_softc(dev);
279 	uint32_t devid;
280 	int i;
281 
282 	devid = pci_get_devid(dev);
283 	for (i = 0; i < nitems(ig4iic_pci_devices); i++) {
284 		if (ig4iic_pci_devices[i].devid == devid) {
285 			device_set_desc(dev, ig4iic_pci_devices[i].desc);
286 			sc->version = ig4iic_pci_devices[i].version;
287 			return (BUS_PROBE_DEFAULT);
288 		}
289 	}
290 	return (ENXIO);
291 }
292 
293 static int
294 ig4iic_pci_attach(device_t dev)
295 {
296 	ig4iic_softc_t *sc = device_get_softc(dev);
297 	int error;
298 
299 	sc->dev = dev;
300 	sc->regs_rid = PCIR_BAR(0);
301 	sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
302 					  &sc->regs_rid, RF_ACTIVE);
303 	if (sc->regs_res == NULL) {
304 		device_printf(dev, "unable to map registers\n");
305 		ig4iic_pci_detach(dev);
306 		return (ENXIO);
307 	}
308 	sc->intr_rid = 0;
309 	if (pci_alloc_msi(dev, &sc->intr_rid)) {
310 		device_printf(dev, "Using MSI\n");
311 	}
312 	sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
313 					  &sc->intr_rid, RF_SHAREABLE | RF_ACTIVE);
314 	if (sc->intr_res == NULL) {
315 		device_printf(dev, "unable to map interrupt\n");
316 		ig4iic_pci_detach(dev);
317 		return (ENXIO);
318 	}
319 	sc->platform_attached = 1;
320 
321 	error = ig4iic_attach(sc);
322 	if (error)
323 		ig4iic_pci_detach(dev);
324 
325 	return (error);
326 }
327 
328 static int
329 ig4iic_pci_detach(device_t dev)
330 {
331 	ig4iic_softc_t *sc = device_get_softc(dev);
332 	int error;
333 
334 	if (sc->platform_attached) {
335 		error = ig4iic_detach(sc);
336 		if (error)
337 			return (error);
338 		sc->platform_attached = 0;
339 	}
340 
341 	if (sc->intr_res) {
342 		bus_release_resource(dev, SYS_RES_IRQ,
343 				     sc->intr_rid, sc->intr_res);
344 		sc->intr_res = NULL;
345 	}
346 	if (sc->intr_rid != 0)
347 		pci_release_msi(dev);
348 	if (sc->regs_res) {
349 		bus_release_resource(dev, SYS_RES_MEMORY,
350 				     sc->regs_rid, sc->regs_res);
351 		sc->regs_res = NULL;
352 	}
353 
354 	return (0);
355 }
356 
357 static int
358 ig4iic_pci_suspend(device_t dev)
359 {
360 	ig4iic_softc_t *sc = device_get_softc(dev);
361 
362 	return (ig4iic_suspend(sc));
363 }
364 
365 static int
366 ig4iic_pci_resume(device_t dev)
367 {
368 	ig4iic_softc_t *sc  = device_get_softc(dev);
369 
370 	return (ig4iic_resume(sc));
371 }
372 
373 static device_method_t ig4iic_pci_methods[] = {
374 	/* Device interface */
375 	DEVMETHOD(device_probe, ig4iic_pci_probe),
376 	DEVMETHOD(device_attach, ig4iic_pci_attach),
377 	DEVMETHOD(device_detach, ig4iic_pci_detach),
378 	DEVMETHOD(device_suspend, ig4iic_pci_suspend),
379 	DEVMETHOD(device_resume, ig4iic_pci_resume),
380 
381 	/* Bus interface */
382 	DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
383 	DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
384 	DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
385 	DEVMETHOD(bus_release_resource, bus_generic_release_resource),
386 	DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
387 	DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
388 	DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
389 
390 	/* iicbus interface */
391 	DEVMETHOD(iicbus_transfer, ig4iic_transfer),
392 	DEVMETHOD(iicbus_reset, ig4iic_reset),
393 	DEVMETHOD(iicbus_callback, ig4iic_callback),
394 
395 	DEVMETHOD_END
396 };
397 
398 static driver_t ig4iic_pci_driver = {
399 	"ig4iic",
400 	ig4iic_pci_methods,
401 	sizeof(struct ig4iic_softc)
402 };
403 
404 DRIVER_MODULE_ORDERED(ig4iic, pci, ig4iic_pci_driver, 0, 0, SI_ORDER_ANY);
405 MODULE_DEPEND(ig4iic, pci, 1, 1, 1);
406 MODULE_PNP_INFO("W32:vendor/device", pci, ig4iic, ig4iic_pci_devices,
407     nitems(ig4iic_pci_devices));
408