1 /* 2 * Copyright (c) 2014 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Matthew Dillon <dillon@backplane.com> and was subsequently ported 6 * to FreeBSD by Michael Gmelin <freebsd@grem.de> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 /* 40 * Intel fourth generation mobile cpus integrated I2C device. 41 * 42 * See ig4_reg.h for datasheet reference and notes. 43 */ 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/module.h> 49 #include <sys/errno.h> 50 #include <sys/lock.h> 51 #include <sys/mutex.h> 52 #include <sys/sx.h> 53 #include <sys/syslog.h> 54 #include <sys/bus.h> 55 56 #include <machine/bus.h> 57 #include <sys/rman.h> 58 #include <machine/resource.h> 59 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pcireg.h> 62 #include <dev/iicbus/iiconf.h> 63 64 #include <dev/ichiic/ig4_reg.h> 65 #include <dev/ichiic/ig4_var.h> 66 67 static int ig4iic_pci_detach(device_t dev); 68 69 #define PCI_CHIP_BAYTRAIL_I2C_1 0x0f418086 70 #define PCI_CHIP_BAYTRAIL_I2C_2 0x0f428086 71 #define PCI_CHIP_BAYTRAIL_I2C_3 0x0f438086 72 #define PCI_CHIP_BAYTRAIL_I2C_4 0x0f448086 73 #define PCI_CHIP_BAYTRAIL_I2C_5 0x0f458086 74 #define PCI_CHIP_BAYTRAIL_I2C_6 0x0f468086 75 #define PCI_CHIP_BAYTRAIL_I2C_7 0x0f478086 76 #define PCI_CHIP_LYNXPT_LP_I2C_1 0x9c618086 77 #define PCI_CHIP_LYNXPT_LP_I2C_2 0x9c628086 78 #define PCI_CHIP_BRASWELL_I2C_1 0x22c18086 79 #define PCI_CHIP_BRASWELL_I2C_2 0x22c28086 80 #define PCI_CHIP_BRASWELL_I2C_3 0x22c38086 81 #define PCI_CHIP_BRASWELL_I2C_5 0x22c58086 82 #define PCI_CHIP_BRASWELL_I2C_6 0x22c68086 83 #define PCI_CHIP_BRASWELL_I2C_7 0x22c78086 84 #define PCI_CHIP_SKYLAKE_I2C_0 0x9d608086 85 #define PCI_CHIP_SKYLAKE_I2C_1 0x9d618086 86 #define PCI_CHIP_SKYLAKE_I2C_2 0x9d628086 87 #define PCI_CHIP_SKYLAKE_I2C_3 0x9d638086 88 #define PCI_CHIP_SKYLAKE_I2C_4 0x9d648086 89 #define PCI_CHIP_SKYLAKE_I2C_5 0x9d658086 90 #define PCI_CHIP_KABYLAKE_I2C_0 0xa1608086 91 #define PCI_CHIP_KABYLAKE_I2C_1 0xa1618086 92 #define PCI_CHIP_APL_I2C_0 0x5aac8086 93 #define PCI_CHIP_APL_I2C_1 0x5aae8086 94 #define PCI_CHIP_APL_I2C_2 0x5ab08086 95 #define PCI_CHIP_APL_I2C_3 0x5ab28086 96 #define PCI_CHIP_APL_I2C_4 0x5ab48086 97 #define PCI_CHIP_APL_I2C_5 0x5ab68086 98 #define PCI_CHIP_APL_I2C_6 0x5ab88086 99 #define PCI_CHIP_APL_I2C_7 0x5aba8086 100 #define PCI_CHIP_CANNONLAKE_LP_I2C_0 0x9dc58086 101 #define PCI_CHIP_CANNONLAKE_LP_I2C_1 0x9dc68086 102 #define PCI_CHIP_CANNONLAKE_LP_I2C_2 0x9de88086 103 #define PCI_CHIP_CANNONLAKE_LP_I2C_3 0x9de98086 104 #define PCI_CHIP_CANNONLAKE_LP_I2C_4 0x9dea8086 105 #define PCI_CHIP_CANNONLAKE_LP_I2C_5 0x9deb8086 106 #define PCI_CHIP_CANNONLAKE_H_I2C_0 0xa3688086 107 #define PCI_CHIP_CANNONLAKE_H_I2C_1 0xa3698086 108 #define PCI_CHIP_CANNONLAKE_H_I2C_2 0xa36a8086 109 #define PCI_CHIP_CANNONLAKE_H_I2C_3 0xa36b8086 110 #define PCI_CHIP_COMETLAKE_LP_I2C_0 0x02e88086 111 #define PCI_CHIP_COMETLAKE_LP_I2C_1 0x02e98086 112 #define PCI_CHIP_COMETLAKE_LP_I2C_2 0x02ea8086 113 #define PCI_CHIP_COMETLAKE_LP_I2C_3 0x02eb8086 114 #define PCI_CHIP_COMETLAKE_LP_I2C_4 0x02c58086 115 #define PCI_CHIP_COMETLAKE_LP_I2C_5 0x02c68086 116 #define PCI_CHIP_COMETLAKE_H_I2C_0 0x06e88086 117 #define PCI_CHIP_COMETLAKE_H_I2C_1 0x06e98086 118 #define PCI_CHIP_COMETLAKE_H_I2C_2 0x06ea8086 119 #define PCI_CHIP_COMETLAKE_H_I2C_3 0x06eb8086 120 #define PCI_CHIP_COMETLAKE_V_I2C_0 0xa3e08086 121 #define PCI_CHIP_COMETLAKE_V_I2C_1 0xa3e18086 122 #define PCI_CHIP_COMETLAKE_V_I2C_2 0xa3e28086 123 #define PCI_CHIP_COMETLAKE_V_I2C_3 0xa3e38086 124 125 struct ig4iic_pci_device { 126 uint32_t devid; 127 const char *desc; 128 enum ig4_vers version; 129 }; 130 131 static struct ig4iic_pci_device ig4iic_pci_devices[] = { 132 { PCI_CHIP_BAYTRAIL_I2C_1, "Intel BayTrail Serial I/O I2C Port 1", IG4_ATOM}, 133 { PCI_CHIP_BAYTRAIL_I2C_2, "Intel BayTrail Serial I/O I2C Port 2", IG4_ATOM}, 134 { PCI_CHIP_BAYTRAIL_I2C_3, "Intel BayTrail Serial I/O I2C Port 3", IG4_ATOM}, 135 { PCI_CHIP_BAYTRAIL_I2C_4, "Intel BayTrail Serial I/O I2C Port 4", IG4_ATOM}, 136 { PCI_CHIP_BAYTRAIL_I2C_5, "Intel BayTrail Serial I/O I2C Port 5", IG4_ATOM}, 137 { PCI_CHIP_BAYTRAIL_I2C_6, "Intel BayTrail Serial I/O I2C Port 6", IG4_ATOM}, 138 { PCI_CHIP_BAYTRAIL_I2C_7, "Intel BayTrail Serial I/O I2C Port 7", IG4_ATOM}, 139 { PCI_CHIP_LYNXPT_LP_I2C_1, "Intel Lynx Point-LP I2C Controller-1", IG4_HASWELL}, 140 { PCI_CHIP_LYNXPT_LP_I2C_2, "Intel Lynx Point-LP I2C Controller-2", IG4_HASWELL}, 141 { PCI_CHIP_BRASWELL_I2C_1, "Intel Braswell Serial I/O I2C Port 1", IG4_ATOM}, 142 { PCI_CHIP_BRASWELL_I2C_2, "Intel Braswell Serial I/O I2C Port 2", IG4_ATOM}, 143 { PCI_CHIP_BRASWELL_I2C_3, "Intel Braswell Serial I/O I2C Port 3", IG4_ATOM}, 144 { PCI_CHIP_BRASWELL_I2C_5, "Intel Braswell Serial I/O I2C Port 5", IG4_ATOM}, 145 { PCI_CHIP_BRASWELL_I2C_6, "Intel Braswell Serial I/O I2C Port 6", IG4_ATOM}, 146 { PCI_CHIP_BRASWELL_I2C_7, "Intel Braswell Serial I/O I2C Port 7", IG4_ATOM}, 147 { PCI_CHIP_SKYLAKE_I2C_0, "Intel Sunrise Point-LP I2C Controller-0", IG4_SKYLAKE}, 148 { PCI_CHIP_SKYLAKE_I2C_1, "Intel Sunrise Point-LP I2C Controller-1", IG4_SKYLAKE}, 149 { PCI_CHIP_SKYLAKE_I2C_2, "Intel Sunrise Point-LP I2C Controller-2", IG4_SKYLAKE}, 150 { PCI_CHIP_SKYLAKE_I2C_3, "Intel Sunrise Point-LP I2C Controller-3", IG4_SKYLAKE}, 151 { PCI_CHIP_SKYLAKE_I2C_4, "Intel Sunrise Point-LP I2C Controller-4", IG4_SKYLAKE}, 152 { PCI_CHIP_SKYLAKE_I2C_5, "Intel Sunrise Point-LP I2C Controller-5", IG4_SKYLAKE}, 153 { PCI_CHIP_KABYLAKE_I2C_0, "Intel Sunrise Point-H I2C Controller-0", IG4_SKYLAKE}, 154 { PCI_CHIP_KABYLAKE_I2C_1, "Intel Sunrise Point-H I2C Controller-1", IG4_SKYLAKE}, 155 { PCI_CHIP_APL_I2C_0, "Intel Apollo Lake I2C Controller-0", IG4_APL}, 156 { PCI_CHIP_APL_I2C_1, "Intel Apollo Lake I2C Controller-1", IG4_APL}, 157 { PCI_CHIP_APL_I2C_2, "Intel Apollo Lake I2C Controller-2", IG4_APL}, 158 { PCI_CHIP_APL_I2C_3, "Intel Apollo Lake I2C Controller-3", IG4_APL}, 159 { PCI_CHIP_APL_I2C_4, "Intel Apollo Lake I2C Controller-4", IG4_APL}, 160 { PCI_CHIP_APL_I2C_5, "Intel Apollo Lake I2C Controller-5", IG4_APL}, 161 { PCI_CHIP_APL_I2C_6, "Intel Apollo Lake I2C Controller-6", IG4_APL}, 162 { PCI_CHIP_APL_I2C_7, "Intel Apollo Lake I2C Controller-7", IG4_APL}, 163 { PCI_CHIP_CANNONLAKE_LP_I2C_0, "Intel Cannon Lake-LP I2C Controller-0", IG4_CANNONLAKE}, 164 { PCI_CHIP_CANNONLAKE_LP_I2C_1, "Intel Cannon Lake-LP I2C Controller-1", IG4_CANNONLAKE}, 165 { PCI_CHIP_CANNONLAKE_LP_I2C_2, "Intel Cannon Lake-LP I2C Controller-2", IG4_CANNONLAKE}, 166 { PCI_CHIP_CANNONLAKE_LP_I2C_3, "Intel Cannon Lake-LP I2C Controller-3", IG4_CANNONLAKE}, 167 { PCI_CHIP_CANNONLAKE_LP_I2C_4, "Intel Cannon Lake-LP I2C Controller-4", IG4_CANNONLAKE}, 168 { PCI_CHIP_CANNONLAKE_LP_I2C_5, "Intel Cannon Lake-LP I2C Controller-5", IG4_CANNONLAKE}, 169 { PCI_CHIP_CANNONLAKE_H_I2C_0, "Intel Cannon Lake-H I2C Controller-0", IG4_CANNONLAKE}, 170 { PCI_CHIP_CANNONLAKE_H_I2C_1, "Intel Cannon Lake-H I2C Controller-1", IG4_CANNONLAKE}, 171 { PCI_CHIP_CANNONLAKE_H_I2C_2, "Intel Cannon Lake-H I2C Controller-2", IG4_CANNONLAKE}, 172 { PCI_CHIP_CANNONLAKE_H_I2C_3, "Intel Cannon Lake-H I2C Controller-3", IG4_CANNONLAKE}, 173 { PCI_CHIP_COMETLAKE_LP_I2C_0, "Intel Comet Lake-LP I2C Controller-0", IG4_CANNONLAKE}, 174 { PCI_CHIP_COMETLAKE_LP_I2C_1, "Intel Comet Lake-LP I2C Controller-1", IG4_CANNONLAKE}, 175 { PCI_CHIP_COMETLAKE_LP_I2C_2, "Intel Comet Lake-LP I2C Controller-2", IG4_CANNONLAKE}, 176 { PCI_CHIP_COMETLAKE_LP_I2C_3, "Intel Comet Lake-LP I2C Controller-3", IG4_CANNONLAKE}, 177 { PCI_CHIP_COMETLAKE_LP_I2C_4, "Intel Comet Lake-LP I2C Controller-4", IG4_CANNONLAKE}, 178 { PCI_CHIP_COMETLAKE_LP_I2C_5, "Intel Comet Lake-LP I2C Controller-5", IG4_CANNONLAKE}, 179 { PCI_CHIP_COMETLAKE_H_I2C_0, "Intel Comet Lake-H I2C Controller-0", IG4_CANNONLAKE}, 180 { PCI_CHIP_COMETLAKE_H_I2C_1, "Intel Comet Lake-H I2C Controller-1", IG4_CANNONLAKE}, 181 { PCI_CHIP_COMETLAKE_H_I2C_2, "Intel Comet Lake-H I2C Controller-2", IG4_CANNONLAKE}, 182 { PCI_CHIP_COMETLAKE_H_I2C_3, "Intel Comet Lake-H I2C Controller-3", IG4_CANNONLAKE}, 183 { PCI_CHIP_COMETLAKE_V_I2C_0, "Intel Comet Lake-V I2C Controller-0", IG4_CANNONLAKE}, 184 { PCI_CHIP_COMETLAKE_V_I2C_1, "Intel Comet Lake-V I2C Controller-1", IG4_CANNONLAKE}, 185 { PCI_CHIP_COMETLAKE_V_I2C_2, "Intel Comet Lake-V I2C Controller-2", IG4_CANNONLAKE}, 186 { PCI_CHIP_COMETLAKE_V_I2C_3, "Intel Comet Lake-V I2C Controller-3", IG4_CANNONLAKE}, 187 }; 188 189 static int 190 ig4iic_pci_probe(device_t dev) 191 { 192 ig4iic_softc_t *sc = device_get_softc(dev); 193 uint32_t devid; 194 int i; 195 196 devid = pci_get_devid(dev); 197 for (i = 0; i < nitems(ig4iic_pci_devices); i++) { 198 if (ig4iic_pci_devices[i].devid == devid) { 199 device_set_desc(dev, ig4iic_pci_devices[i].desc); 200 sc->version = ig4iic_pci_devices[i].version; 201 return (BUS_PROBE_DEFAULT); 202 } 203 } 204 return (ENXIO); 205 } 206 207 static int 208 ig4iic_pci_attach(device_t dev) 209 { 210 ig4iic_softc_t *sc = device_get_softc(dev); 211 int error; 212 213 sc->dev = dev; 214 sc->regs_rid = PCIR_BAR(0); 215 sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 216 &sc->regs_rid, RF_ACTIVE); 217 if (sc->regs_res == NULL) { 218 device_printf(dev, "unable to map registers\n"); 219 ig4iic_pci_detach(dev); 220 return (ENXIO); 221 } 222 sc->intr_rid = 0; 223 if (pci_alloc_msi(dev, &sc->intr_rid)) { 224 device_printf(dev, "Using MSI\n"); 225 } 226 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 227 &sc->intr_rid, RF_SHAREABLE | RF_ACTIVE); 228 if (sc->intr_res == NULL) { 229 device_printf(dev, "unable to map interrupt\n"); 230 ig4iic_pci_detach(dev); 231 return (ENXIO); 232 } 233 sc->platform_attached = 1; 234 235 error = ig4iic_attach(sc); 236 if (error) 237 ig4iic_pci_detach(dev); 238 239 return (error); 240 } 241 242 static int 243 ig4iic_pci_detach(device_t dev) 244 { 245 ig4iic_softc_t *sc = device_get_softc(dev); 246 int error; 247 248 if (sc->platform_attached) { 249 error = ig4iic_detach(sc); 250 if (error) 251 return (error); 252 sc->platform_attached = 0; 253 } 254 255 if (sc->intr_res) { 256 bus_release_resource(dev, SYS_RES_IRQ, 257 sc->intr_rid, sc->intr_res); 258 sc->intr_res = NULL; 259 } 260 if (sc->intr_rid != 0) 261 pci_release_msi(dev); 262 if (sc->regs_res) { 263 bus_release_resource(dev, SYS_RES_MEMORY, 264 sc->regs_rid, sc->regs_res); 265 sc->regs_res = NULL; 266 } 267 268 return (0); 269 } 270 271 static int 272 ig4iic_pci_suspend(device_t dev) 273 { 274 ig4iic_softc_t *sc = device_get_softc(dev); 275 276 return (ig4iic_suspend(sc)); 277 } 278 279 static int 280 ig4iic_pci_resume(device_t dev) 281 { 282 ig4iic_softc_t *sc = device_get_softc(dev); 283 284 return (ig4iic_resume(sc)); 285 } 286 287 static device_method_t ig4iic_pci_methods[] = { 288 /* Device interface */ 289 DEVMETHOD(device_probe, ig4iic_pci_probe), 290 DEVMETHOD(device_attach, ig4iic_pci_attach), 291 DEVMETHOD(device_detach, ig4iic_pci_detach), 292 DEVMETHOD(device_suspend, ig4iic_pci_suspend), 293 DEVMETHOD(device_resume, ig4iic_pci_resume), 294 295 /* Bus interface */ 296 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 297 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 298 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 299 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 300 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 301 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 302 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 303 304 /* iicbus interface */ 305 DEVMETHOD(iicbus_transfer, ig4iic_transfer), 306 DEVMETHOD(iicbus_reset, ig4iic_reset), 307 DEVMETHOD(iicbus_callback, ig4iic_callback), 308 309 DEVMETHOD_END 310 }; 311 312 static driver_t ig4iic_pci_driver = { 313 "ig4iic", 314 ig4iic_pci_methods, 315 sizeof(struct ig4iic_softc) 316 }; 317 318 DRIVER_MODULE_ORDERED(ig4iic, pci, ig4iic_pci_driver, ig4iic_devclass, 0, 0, 319 SI_ORDER_ANY); 320 MODULE_DEPEND(ig4iic, pci, 1, 1, 1); 321 MODULE_PNP_INFO("W32:vendor/device", pci, ig4iic, ig4iic_pci_devices, 322 nitems(ig4iic_pci_devices)); 323