1 /* 2 * Copyright (c) 2014 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Matthew Dillon <dillon@backplane.com> and was subsequently ported 6 * to FreeBSD by Michael Gmelin <freebsd@grem.de> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 /* 40 * Intel fourth generation mobile cpus integrated I2C device. 41 * 42 * See ig4_reg.h for datasheet reference and notes. 43 */ 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/module.h> 49 #include <sys/errno.h> 50 #include <sys/lock.h> 51 #include <sys/mutex.h> 52 #include <sys/sx.h> 53 #include <sys/syslog.h> 54 #include <sys/bus.h> 55 56 #include <machine/bus.h> 57 #include <sys/rman.h> 58 #include <machine/resource.h> 59 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pcireg.h> 62 #include <dev/iicbus/iiconf.h> 63 64 #include <dev/ichiic/ig4_reg.h> 65 #include <dev/ichiic/ig4_var.h> 66 67 static int ig4iic_pci_detach(device_t dev); 68 69 #define PCI_CHIP_LYNXPT_LP_I2C_1 0x9c618086 70 #define PCI_CHIP_LYNXPT_LP_I2C_2 0x9c628086 71 #define PCI_CHIP_BRASWELL_I2C_1 0x22c18086 72 #define PCI_CHIP_BRASWELL_I2C_2 0x22c28086 73 #define PCI_CHIP_BRASWELL_I2C_3 0x22c38086 74 #define PCI_CHIP_BRASWELL_I2C_5 0x22c58086 75 #define PCI_CHIP_BRASWELL_I2C_6 0x22c68086 76 #define PCI_CHIP_BRASWELL_I2C_7 0x22c78086 77 #define PCI_CHIP_SKYLAKE_I2C_0 0x9d608086 78 #define PCI_CHIP_SKYLAKE_I2C_1 0x9d618086 79 #define PCI_CHIP_SKYLAKE_I2C_2 0x9d628086 80 #define PCI_CHIP_SKYLAKE_I2C_3 0x9d638086 81 #define PCI_CHIP_SKYLAKE_I2C_4 0x9d648086 82 #define PCI_CHIP_SKYLAKE_I2C_5 0x9d658086 83 #define PCI_CHIP_KABYLAKE_I2C_0 0xa1608086 84 #define PCI_CHIP_KABYLAKE_I2C_1 0xa1618086 85 #define PCI_CHIP_APL_I2C_0 0x5aac8086 86 #define PCI_CHIP_APL_I2C_1 0x5aae8086 87 #define PCI_CHIP_APL_I2C_2 0x5ab08086 88 #define PCI_CHIP_APL_I2C_3 0x5ab28086 89 #define PCI_CHIP_APL_I2C_4 0x5ab48086 90 #define PCI_CHIP_APL_I2C_5 0x5ab68086 91 #define PCI_CHIP_APL_I2C_6 0x5ab88086 92 #define PCI_CHIP_APL_I2C_7 0x5aba8086 93 94 struct ig4iic_pci_device { 95 uint32_t devid; 96 const char *desc; 97 enum ig4_vers version; 98 }; 99 100 static struct ig4iic_pci_device ig4iic_pci_devices[] = { 101 { PCI_CHIP_LYNXPT_LP_I2C_1, "Intel Lynx Point-LP I2C Controller-1", IG4_HASWELL}, 102 { PCI_CHIP_LYNXPT_LP_I2C_2, "Intel Lynx Point-LP I2C Controller-2", IG4_HASWELL}, 103 { PCI_CHIP_BRASWELL_I2C_1, "Intel Braswell Serial I/O I2C Port 1", IG4_ATOM}, 104 { PCI_CHIP_BRASWELL_I2C_2, "Intel Braswell Serial I/O I2C Port 2", IG4_ATOM}, 105 { PCI_CHIP_BRASWELL_I2C_3, "Intel Braswell Serial I/O I2C Port 3", IG4_ATOM}, 106 { PCI_CHIP_BRASWELL_I2C_5, "Intel Braswell Serial I/O I2C Port 5", IG4_ATOM}, 107 { PCI_CHIP_BRASWELL_I2C_6, "Intel Braswell Serial I/O I2C Port 6", IG4_ATOM}, 108 { PCI_CHIP_BRASWELL_I2C_7, "Intel Braswell Serial I/O I2C Port 7", IG4_ATOM}, 109 { PCI_CHIP_SKYLAKE_I2C_0, "Intel Sunrise Point-LP I2C Controller-0", IG4_SKYLAKE}, 110 { PCI_CHIP_SKYLAKE_I2C_1, "Intel Sunrise Point-LP I2C Controller-1", IG4_SKYLAKE}, 111 { PCI_CHIP_SKYLAKE_I2C_2, "Intel Sunrise Point-LP I2C Controller-2", IG4_SKYLAKE}, 112 { PCI_CHIP_SKYLAKE_I2C_3, "Intel Sunrise Point-LP I2C Controller-3", IG4_SKYLAKE}, 113 { PCI_CHIP_SKYLAKE_I2C_4, "Intel Sunrise Point-LP I2C Controller-4", IG4_SKYLAKE}, 114 { PCI_CHIP_SKYLAKE_I2C_5, "Intel Sunrise Point-LP I2C Controller-5", IG4_SKYLAKE}, 115 { PCI_CHIP_KABYLAKE_I2C_0, "Intel Sunrise Point-H I2C Controller-0", IG4_SKYLAKE}, 116 { PCI_CHIP_KABYLAKE_I2C_1, "Intel Sunrise Point-H I2C Controller-1", IG4_SKYLAKE}, 117 { PCI_CHIP_APL_I2C_0, "Intel Apollo Lake I2C Controller-0", IG4_APL}, 118 { PCI_CHIP_APL_I2C_1, "Intel Apollo Lake I2C Controller-1", IG4_APL}, 119 { PCI_CHIP_APL_I2C_2, "Intel Apollo Lake I2C Controller-2", IG4_APL}, 120 { PCI_CHIP_APL_I2C_3, "Intel Apollo Lake I2C Controller-3", IG4_APL}, 121 { PCI_CHIP_APL_I2C_4, "Intel Apollo Lake I2C Controller-4", IG4_APL}, 122 { PCI_CHIP_APL_I2C_5, "Intel Apollo Lake I2C Controller-5", IG4_APL}, 123 { PCI_CHIP_APL_I2C_6, "Intel Apollo Lake I2C Controller-6", IG4_APL}, 124 { PCI_CHIP_APL_I2C_7, "Intel Apollo Lake I2C Controller-7", IG4_APL} 125 }; 126 127 static int 128 ig4iic_pci_probe(device_t dev) 129 { 130 ig4iic_softc_t *sc = device_get_softc(dev); 131 uint32_t devid; 132 int i; 133 134 devid = pci_get_devid(dev); 135 for (i = 0; i < nitems(ig4iic_pci_devices); i++) { 136 if (ig4iic_pci_devices[i].devid == devid) { 137 device_set_desc(dev, ig4iic_pci_devices[i].desc); 138 sc->version = ig4iic_pci_devices[i].version; 139 return (BUS_PROBE_DEFAULT); 140 } 141 } 142 return (ENXIO); 143 } 144 145 static int 146 ig4iic_pci_attach(device_t dev) 147 { 148 ig4iic_softc_t *sc = device_get_softc(dev); 149 int error; 150 151 sc->dev = dev; 152 sc->regs_rid = PCIR_BAR(0); 153 sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 154 &sc->regs_rid, RF_ACTIVE); 155 if (sc->regs_res == NULL) { 156 device_printf(dev, "unable to map registers\n"); 157 ig4iic_pci_detach(dev); 158 return (ENXIO); 159 } 160 sc->intr_rid = 0; 161 if (pci_alloc_msi(dev, &sc->intr_rid)) { 162 device_printf(dev, "Using MSI\n"); 163 } 164 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 165 &sc->intr_rid, RF_SHAREABLE | RF_ACTIVE); 166 if (sc->intr_res == NULL) { 167 device_printf(dev, "unable to map interrupt\n"); 168 ig4iic_pci_detach(dev); 169 return (ENXIO); 170 } 171 sc->platform_attached = 1; 172 173 error = ig4iic_attach(sc); 174 if (error) 175 ig4iic_pci_detach(dev); 176 177 return (error); 178 } 179 180 static int 181 ig4iic_pci_detach(device_t dev) 182 { 183 ig4iic_softc_t *sc = device_get_softc(dev); 184 int error; 185 186 if (sc->platform_attached) { 187 error = ig4iic_detach(sc); 188 if (error) 189 return (error); 190 sc->platform_attached = 0; 191 } 192 193 if (sc->intr_res) { 194 bus_release_resource(dev, SYS_RES_IRQ, 195 sc->intr_rid, sc->intr_res); 196 sc->intr_res = NULL; 197 } 198 if (sc->intr_rid != 0) 199 pci_release_msi(dev); 200 if (sc->regs_res) { 201 bus_release_resource(dev, SYS_RES_MEMORY, 202 sc->regs_rid, sc->regs_res); 203 sc->regs_res = NULL; 204 } 205 206 return (0); 207 } 208 209 static device_method_t ig4iic_pci_methods[] = { 210 /* Device interface */ 211 DEVMETHOD(device_probe, ig4iic_pci_probe), 212 DEVMETHOD(device_attach, ig4iic_pci_attach), 213 DEVMETHOD(device_detach, ig4iic_pci_detach), 214 215 DEVMETHOD(iicbus_transfer, ig4iic_transfer), 216 DEVMETHOD(iicbus_reset, ig4iic_reset), 217 DEVMETHOD(iicbus_callback, iicbus_null_callback), 218 219 DEVMETHOD_END 220 }; 221 222 static driver_t ig4iic_pci_driver = { 223 "ig4iic_pci", 224 ig4iic_pci_methods, 225 sizeof(struct ig4iic_softc) 226 }; 227 228 static devclass_t ig4iic_pci_devclass; 229 230 DRIVER_MODULE_ORDERED(ig4iic_pci, pci, ig4iic_pci_driver, ig4iic_pci_devclass, 0, 0, 231 SI_ORDER_ANY); 232 MODULE_DEPEND(ig4iic_pci, pci, 1, 1, 1); 233 MODULE_DEPEND(ig4iic_pci, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER); 234 MODULE_VERSION(ig4iic_pci, 1); 235 MODULE_PNP_INFO("W32:vendor/device", pci, ig4iic_pci, ig4iic_pci_devices, 236 nitems(ig4iic_pci_devices)); 237