1 /* 2 * Copyright (c) 2014 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Matthew Dillon <dillon@backplane.com> and was subsequently ported 6 * to FreeBSD by Michael Gmelin <freebsd@grem.de> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 /* 40 * Intel fourth generation mobile cpus integrated I2C device, smbus driver. 41 * 42 * See ig4_reg.h for datasheet reference and notes. 43 */ 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/module.h> 49 #include <sys/errno.h> 50 #include <sys/lock.h> 51 #include <sys/mutex.h> 52 #include <sys/syslog.h> 53 #include <sys/bus.h> 54 55 #include <machine/bus.h> 56 #include <sys/rman.h> 57 #include <machine/resource.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/smbus/smbconf.h> 62 63 #include "smbus_if.h" 64 65 #include <dev/ichiic/ig4_reg.h> 66 #include <dev/ichiic/ig4_var.h> 67 68 static int ig4iic_pci_detach(device_t dev); 69 70 #define PCI_CHIP_LYNXPT_LP_I2C_1 0x9c618086 71 #define PCI_CHIP_LYNXPT_LP_I2C_2 0x9c628086 72 73 static int 74 ig4iic_pci_probe(device_t dev) 75 { 76 switch(pci_get_devid(dev)) { 77 case PCI_CHIP_LYNXPT_LP_I2C_1: 78 device_set_desc(dev, "Intel Lynx Point-LP I2C Controller-1"); 79 break; 80 case PCI_CHIP_LYNXPT_LP_I2C_2: 81 device_set_desc(dev, "Intel Lynx Point-LP I2C Controller-2"); 82 break; 83 default: 84 return (ENXIO); 85 } 86 return (BUS_PROBE_DEFAULT); 87 } 88 89 static int 90 ig4iic_pci_attach(device_t dev) 91 { 92 ig4iic_softc_t *sc = device_get_softc(dev); 93 int error; 94 95 bzero(sc, sizeof(*sc)); 96 97 mtx_init(&sc->mutex, device_get_nameunit(dev), "ig4iic", MTX_DEF); 98 99 sc->dev = dev; 100 sc->regs_rid = PCIR_BAR(0); 101 sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 102 &sc->regs_rid, RF_ACTIVE); 103 if (sc->regs_res == NULL) { 104 device_printf(dev, "unable to map registers\n"); 105 ig4iic_pci_detach(dev); 106 return (ENXIO); 107 } 108 sc->intr_rid = 0; 109 if (pci_alloc_msi(dev, &sc->intr_rid)) { 110 device_printf(dev, "Using MSI\n"); 111 } 112 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 113 &sc->intr_rid, RF_SHAREABLE | RF_ACTIVE); 114 if (sc->intr_res == NULL) { 115 device_printf(dev, "unable to map interrupt\n"); 116 ig4iic_pci_detach(dev); 117 return (ENXIO); 118 } 119 sc->pci_attached = 1; 120 121 error = ig4iic_attach(sc); 122 if (error) 123 ig4iic_pci_detach(dev); 124 125 return (error); 126 } 127 128 static int 129 ig4iic_pci_detach(device_t dev) 130 { 131 ig4iic_softc_t *sc = device_get_softc(dev); 132 int error; 133 134 if (sc->pci_attached) { 135 error = ig4iic_detach(sc); 136 if (error) 137 return (error); 138 sc->pci_attached = 0; 139 } 140 141 if (sc->intr_res) { 142 bus_release_resource(dev, SYS_RES_IRQ, 143 sc->intr_rid, sc->intr_res); 144 sc->intr_res = NULL; 145 } 146 if (sc->intr_rid != 0) 147 pci_release_msi(dev); 148 if (sc->regs_res) { 149 bus_release_resource(dev, SYS_RES_MEMORY, 150 sc->regs_rid, sc->regs_res); 151 sc->regs_res = NULL; 152 } 153 mtx_destroy(&sc->mutex); 154 155 return (0); 156 } 157 158 static device_method_t ig4iic_pci_methods[] = { 159 /* Device interface */ 160 DEVMETHOD(device_probe, ig4iic_pci_probe), 161 DEVMETHOD(device_attach, ig4iic_pci_attach), 162 DEVMETHOD(device_detach, ig4iic_pci_detach), 163 164 /* SMBus methods from ig4_smb.c */ 165 DEVMETHOD(smbus_callback, ig4iic_smb_callback), 166 DEVMETHOD(smbus_quick, ig4iic_smb_quick), 167 DEVMETHOD(smbus_sendb, ig4iic_smb_sendb), 168 DEVMETHOD(smbus_recvb, ig4iic_smb_recvb), 169 DEVMETHOD(smbus_writeb, ig4iic_smb_writeb), 170 DEVMETHOD(smbus_writew, ig4iic_smb_writew), 171 DEVMETHOD(smbus_readb, ig4iic_smb_readb), 172 DEVMETHOD(smbus_readw, ig4iic_smb_readw), 173 DEVMETHOD(smbus_pcall, ig4iic_smb_pcall), 174 DEVMETHOD(smbus_bwrite, ig4iic_smb_bwrite), 175 DEVMETHOD(smbus_bread, ig4iic_smb_bread), 176 DEVMETHOD(smbus_trans, ig4iic_smb_trans), 177 178 DEVMETHOD_END 179 }; 180 181 static driver_t ig4iic_pci_driver = { 182 "ig4iic", 183 ig4iic_pci_methods, 184 sizeof(struct ig4iic_softc) 185 }; 186 187 static devclass_t ig4iic_pci_devclass; 188 189 DRIVER_MODULE(ig4iic, pci, ig4iic_pci_driver, ig4iic_pci_devclass, 0, 0); 190 MODULE_DEPEND(ig4iic, pci, 1, 1, 1); 191 MODULE_DEPEND(ig4iic, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER); 192 MODULE_VERSION(ig4iic, 1); 193