1 /* 2 * Copyright (c) 2014 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Matthew Dillon <dillon@backplane.com> and was subsequently ported 6 * to FreeBSD by Michael Gmelin <freebsd@grem.de> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 /* 40 * Intel fourth generation mobile cpus integrated I2C device, smbus driver. 41 * 42 * See ig4_reg.h for datasheet reference and notes. 43 */ 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/module.h> 49 #include <sys/errno.h> 50 #include <sys/lock.h> 51 #include <sys/mutex.h> 52 #include <sys/sx.h> 53 #include <sys/syslog.h> 54 #include <sys/bus.h> 55 56 #include <machine/bus.h> 57 #include <sys/rman.h> 58 #include <machine/resource.h> 59 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pcireg.h> 62 #include <dev/smbus/smbconf.h> 63 #include <dev/iicbus/iiconf.h> 64 65 #include "smbus_if.h" 66 67 #include <dev/ichiic/ig4_reg.h> 68 #include <dev/ichiic/ig4_var.h> 69 70 static int ig4iic_pci_detach(device_t dev); 71 72 #define PCI_CHIP_LYNXPT_LP_I2C_1 0x9c618086 73 #define PCI_CHIP_LYNXPT_LP_I2C_2 0x9c628086 74 75 static int 76 ig4iic_pci_probe(device_t dev) 77 { 78 switch(pci_get_devid(dev)) { 79 case PCI_CHIP_LYNXPT_LP_I2C_1: 80 device_set_desc(dev, "Intel Lynx Point-LP I2C Controller-1"); 81 break; 82 case PCI_CHIP_LYNXPT_LP_I2C_2: 83 device_set_desc(dev, "Intel Lynx Point-LP I2C Controller-2"); 84 break; 85 default: 86 return (ENXIO); 87 } 88 return (BUS_PROBE_DEFAULT); 89 } 90 91 static int 92 ig4iic_pci_attach(device_t dev) 93 { 94 ig4iic_softc_t *sc = device_get_softc(dev); 95 int error; 96 97 bzero(sc, sizeof(*sc)); 98 99 mtx_init(&sc->io_lock, "IG4 I/O lock", NULL, MTX_DEF); 100 sx_init(&sc->call_lock, "IG4 call lock"); 101 102 sc->dev = dev; 103 sc->regs_rid = PCIR_BAR(0); 104 sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 105 &sc->regs_rid, RF_ACTIVE); 106 if (sc->regs_res == NULL) { 107 device_printf(dev, "unable to map registers\n"); 108 ig4iic_pci_detach(dev); 109 return (ENXIO); 110 } 111 sc->intr_rid = 0; 112 if (pci_alloc_msi(dev, &sc->intr_rid)) { 113 device_printf(dev, "Using MSI\n"); 114 } 115 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 116 &sc->intr_rid, RF_SHAREABLE | RF_ACTIVE); 117 if (sc->intr_res == NULL) { 118 device_printf(dev, "unable to map interrupt\n"); 119 ig4iic_pci_detach(dev); 120 return (ENXIO); 121 } 122 sc->pci_attached = 1; 123 124 error = ig4iic_attach(sc); 125 if (error) 126 ig4iic_pci_detach(dev); 127 128 return (error); 129 } 130 131 static int 132 ig4iic_pci_detach(device_t dev) 133 { 134 ig4iic_softc_t *sc = device_get_softc(dev); 135 int error; 136 137 if (sc->pci_attached) { 138 error = ig4iic_detach(sc); 139 if (error) 140 return (error); 141 sc->pci_attached = 0; 142 } 143 144 if (sc->intr_res) { 145 bus_release_resource(dev, SYS_RES_IRQ, 146 sc->intr_rid, sc->intr_res); 147 sc->intr_res = NULL; 148 } 149 if (sc->intr_rid != 0) 150 pci_release_msi(dev); 151 if (sc->regs_res) { 152 bus_release_resource(dev, SYS_RES_MEMORY, 153 sc->regs_rid, sc->regs_res); 154 sc->regs_res = NULL; 155 } 156 if (mtx_initialized(&sc->io_lock)) { 157 mtx_destroy(&sc->io_lock); 158 sx_destroy(&sc->call_lock); 159 } 160 161 return (0); 162 } 163 164 static device_method_t ig4iic_pci_methods[] = { 165 /* Device interface */ 166 DEVMETHOD(device_probe, ig4iic_pci_probe), 167 DEVMETHOD(device_attach, ig4iic_pci_attach), 168 DEVMETHOD(device_detach, ig4iic_pci_detach), 169 170 /* SMBus methods from ig4_smb.c */ 171 DEVMETHOD(smbus_callback, ig4iic_smb_callback), 172 DEVMETHOD(smbus_quick, ig4iic_smb_quick), 173 DEVMETHOD(smbus_sendb, ig4iic_smb_sendb), 174 DEVMETHOD(smbus_recvb, ig4iic_smb_recvb), 175 DEVMETHOD(smbus_writeb, ig4iic_smb_writeb), 176 DEVMETHOD(smbus_writew, ig4iic_smb_writew), 177 DEVMETHOD(smbus_readb, ig4iic_smb_readb), 178 DEVMETHOD(smbus_readw, ig4iic_smb_readw), 179 DEVMETHOD(smbus_pcall, ig4iic_smb_pcall), 180 DEVMETHOD(smbus_bwrite, ig4iic_smb_bwrite), 181 DEVMETHOD(smbus_bread, ig4iic_smb_bread), 182 DEVMETHOD(smbus_trans, ig4iic_smb_trans), 183 184 DEVMETHOD(iicbus_transfer, ig4iic_transfer), 185 DEVMETHOD(iicbus_reset, ig4iic_reset), 186 DEVMETHOD(iicbus_callback, iicbus_null_callback), 187 188 DEVMETHOD_END 189 }; 190 191 static driver_t ig4iic_pci_driver = { 192 "ig4iic", 193 ig4iic_pci_methods, 194 sizeof(struct ig4iic_softc) 195 }; 196 197 static devclass_t ig4iic_pci_devclass; 198 199 DRIVER_MODULE_ORDERED(ig4iic, pci, ig4iic_pci_driver, ig4iic_pci_devclass, 0, 0, 200 SI_ORDER_ANY); 201 MODULE_DEPEND(ig4iic, pci, 1, 1, 1); 202 MODULE_DEPEND(ig4iic, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER); 203 MODULE_DEPEND(ig4iic, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER); 204 MODULE_VERSION(ig4iic, 1); 205