171d51719SMichael Gmelin /* 271d51719SMichael Gmelin * Copyright (c) 2014 The DragonFly Project. All rights reserved. 371d51719SMichael Gmelin * 471d51719SMichael Gmelin * This code is derived from software contributed to The DragonFly Project 571d51719SMichael Gmelin * by Matthew Dillon <dillon@backplane.com> and was subsequently ported 671d51719SMichael Gmelin * to FreeBSD by Michael Gmelin <freebsd@grem.de> 771d51719SMichael Gmelin * 871d51719SMichael Gmelin * Redistribution and use in source and binary forms, with or without 971d51719SMichael Gmelin * modification, are permitted provided that the following conditions 1071d51719SMichael Gmelin * are met: 1171d51719SMichael Gmelin * 1271d51719SMichael Gmelin * 1. Redistributions of source code must retain the above copyright 1371d51719SMichael Gmelin * notice, this list of conditions and the following disclaimer. 1471d51719SMichael Gmelin * 2. Redistributions in binary form must reproduce the above copyright 1571d51719SMichael Gmelin * notice, this list of conditions and the following disclaimer in 1671d51719SMichael Gmelin * the documentation and/or other materials provided with the 1771d51719SMichael Gmelin * distribution. 1871d51719SMichael Gmelin * 3. Neither the name of The DragonFly Project nor the names of its 1971d51719SMichael Gmelin * contributors may be used to endorse or promote products derived 2071d51719SMichael Gmelin * from this software without specific, prior written permission. 2171d51719SMichael Gmelin * 2271d51719SMichael Gmelin * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2371d51719SMichael Gmelin * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2471d51719SMichael Gmelin * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 2571d51719SMichael Gmelin * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 2671d51719SMichael Gmelin * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 2771d51719SMichael Gmelin * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 2871d51719SMichael Gmelin * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 2971d51719SMichael Gmelin * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 3071d51719SMichael Gmelin * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 3171d51719SMichael Gmelin * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 3271d51719SMichael Gmelin * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3371d51719SMichael Gmelin * SUCH DAMAGE. 3471d51719SMichael Gmelin */ 3571d51719SMichael Gmelin 3671d51719SMichael Gmelin #include <sys/cdefs.h> 3771d51719SMichael Gmelin /* 38e3d25549SAndriy Gapon * Intel fourth generation mobile cpus integrated I2C device. 3971d51719SMichael Gmelin * 4071d51719SMichael Gmelin * See ig4_reg.h for datasheet reference and notes. 4171d51719SMichael Gmelin */ 4271d51719SMichael Gmelin 4371d51719SMichael Gmelin #include <sys/param.h> 4471d51719SMichael Gmelin #include <sys/systm.h> 4571d51719SMichael Gmelin #include <sys/kernel.h> 4671d51719SMichael Gmelin #include <sys/module.h> 4771d51719SMichael Gmelin #include <sys/errno.h> 4871d51719SMichael Gmelin #include <sys/lock.h> 4971d51719SMichael Gmelin #include <sys/mutex.h> 504cd6abddSMichael Gmelin #include <sys/sx.h> 5171d51719SMichael Gmelin #include <sys/syslog.h> 5271d51719SMichael Gmelin #include <sys/bus.h> 5371d51719SMichael Gmelin 5471d51719SMichael Gmelin #include <machine/bus.h> 5571d51719SMichael Gmelin #include <sys/rman.h> 5671d51719SMichael Gmelin #include <machine/resource.h> 5771d51719SMichael Gmelin 5871d51719SMichael Gmelin #include <dev/pci/pcivar.h> 5971d51719SMichael Gmelin #include <dev/pci/pcireg.h> 60448897d3SAndriy Gapon #include <dev/iicbus/iiconf.h> 6171d51719SMichael Gmelin 6271d51719SMichael Gmelin #include <dev/ichiic/ig4_reg.h> 6371d51719SMichael Gmelin #include <dev/ichiic/ig4_var.h> 6471d51719SMichael Gmelin 6571d51719SMichael Gmelin static int ig4iic_pci_detach(device_t dev); 6671d51719SMichael Gmelin 676f6e2de0SVladimir Kondratyev #define PCI_CHIP_BAYTRAIL_I2C_1 0x0f418086 686f6e2de0SVladimir Kondratyev #define PCI_CHIP_BAYTRAIL_I2C_2 0x0f428086 696f6e2de0SVladimir Kondratyev #define PCI_CHIP_BAYTRAIL_I2C_3 0x0f438086 706f6e2de0SVladimir Kondratyev #define PCI_CHIP_BAYTRAIL_I2C_4 0x0f448086 716f6e2de0SVladimir Kondratyev #define PCI_CHIP_BAYTRAIL_I2C_5 0x0f458086 726f6e2de0SVladimir Kondratyev #define PCI_CHIP_BAYTRAIL_I2C_6 0x0f468086 736f6e2de0SVladimir Kondratyev #define PCI_CHIP_BAYTRAIL_I2C_7 0x0f478086 7471d51719SMichael Gmelin #define PCI_CHIP_LYNXPT_LP_I2C_1 0x9c618086 7571d51719SMichael Gmelin #define PCI_CHIP_LYNXPT_LP_I2C_2 0x9c628086 7600eb880dSConrad Meyer #define PCI_CHIP_BRASWELL_I2C_1 0x22c18086 7700eb880dSConrad Meyer #define PCI_CHIP_BRASWELL_I2C_2 0x22c28086 7800eb880dSConrad Meyer #define PCI_CHIP_BRASWELL_I2C_3 0x22c38086 7900eb880dSConrad Meyer #define PCI_CHIP_BRASWELL_I2C_5 0x22c58086 8000eb880dSConrad Meyer #define PCI_CHIP_BRASWELL_I2C_6 0x22c68086 8100eb880dSConrad Meyer #define PCI_CHIP_BRASWELL_I2C_7 0x22c78086 82b3e8ee5dSOleksandr Tymoshenko #define PCI_CHIP_SKYLAKE_I2C_0 0x9d608086 83b3e8ee5dSOleksandr Tymoshenko #define PCI_CHIP_SKYLAKE_I2C_1 0x9d618086 84b3e8ee5dSOleksandr Tymoshenko #define PCI_CHIP_SKYLAKE_I2C_2 0x9d628086 85b3e8ee5dSOleksandr Tymoshenko #define PCI_CHIP_SKYLAKE_I2C_3 0x9d638086 86b3e8ee5dSOleksandr Tymoshenko #define PCI_CHIP_SKYLAKE_I2C_4 0x9d648086 87b3e8ee5dSOleksandr Tymoshenko #define PCI_CHIP_SKYLAKE_I2C_5 0x9d658086 886fb3c894SOleksandr Tymoshenko #define PCI_CHIP_KABYLAKE_I2C_0 0xa1608086 896fb3c894SOleksandr Tymoshenko #define PCI_CHIP_KABYLAKE_I2C_1 0xa1618086 90e6f7f1bcSOleksandr Tymoshenko #define PCI_CHIP_APL_I2C_0 0x5aac8086 91e6f7f1bcSOleksandr Tymoshenko #define PCI_CHIP_APL_I2C_1 0x5aae8086 92e6f7f1bcSOleksandr Tymoshenko #define PCI_CHIP_APL_I2C_2 0x5ab08086 93e6f7f1bcSOleksandr Tymoshenko #define PCI_CHIP_APL_I2C_3 0x5ab28086 94e6f7f1bcSOleksandr Tymoshenko #define PCI_CHIP_APL_I2C_4 0x5ab48086 95e6f7f1bcSOleksandr Tymoshenko #define PCI_CHIP_APL_I2C_5 0x5ab68086 96e6f7f1bcSOleksandr Tymoshenko #define PCI_CHIP_APL_I2C_6 0x5ab88086 97e6f7f1bcSOleksandr Tymoshenko #define PCI_CHIP_APL_I2C_7 0x5aba8086 9881e81838SVladimir Kondratyev #define PCI_CHIP_CANNONLAKE_LP_I2C_0 0x9dc58086 9981e81838SVladimir Kondratyev #define PCI_CHIP_CANNONLAKE_LP_I2C_1 0x9dc68086 10081e81838SVladimir Kondratyev #define PCI_CHIP_CANNONLAKE_LP_I2C_2 0x9de88086 10181e81838SVladimir Kondratyev #define PCI_CHIP_CANNONLAKE_LP_I2C_3 0x9de98086 10281e81838SVladimir Kondratyev #define PCI_CHIP_CANNONLAKE_LP_I2C_4 0x9dea8086 10381e81838SVladimir Kondratyev #define PCI_CHIP_CANNONLAKE_LP_I2C_5 0x9deb8086 10481e81838SVladimir Kondratyev #define PCI_CHIP_CANNONLAKE_H_I2C_0 0xa3688086 10581e81838SVladimir Kondratyev #define PCI_CHIP_CANNONLAKE_H_I2C_1 0xa3698086 10681e81838SVladimir Kondratyev #define PCI_CHIP_CANNONLAKE_H_I2C_2 0xa36a8086 10781e81838SVladimir Kondratyev #define PCI_CHIP_CANNONLAKE_H_I2C_3 0xa36b8086 108f19aed35SVladimir Kondratyev #define PCI_CHIP_COMETLAKE_LP_I2C_0 0x02e88086 109f19aed35SVladimir Kondratyev #define PCI_CHIP_COMETLAKE_LP_I2C_1 0x02e98086 110f19aed35SVladimir Kondratyev #define PCI_CHIP_COMETLAKE_LP_I2C_2 0x02ea8086 111f19aed35SVladimir Kondratyev #define PCI_CHIP_COMETLAKE_LP_I2C_3 0x02eb8086 112f19aed35SVladimir Kondratyev #define PCI_CHIP_COMETLAKE_LP_I2C_4 0x02c58086 113f19aed35SVladimir Kondratyev #define PCI_CHIP_COMETLAKE_LP_I2C_5 0x02c68086 114f19aed35SVladimir Kondratyev #define PCI_CHIP_COMETLAKE_H_I2C_0 0x06e88086 115f19aed35SVladimir Kondratyev #define PCI_CHIP_COMETLAKE_H_I2C_1 0x06e98086 116f19aed35SVladimir Kondratyev #define PCI_CHIP_COMETLAKE_H_I2C_2 0x06ea8086 117f19aed35SVladimir Kondratyev #define PCI_CHIP_COMETLAKE_H_I2C_3 0x06eb8086 118f19aed35SVladimir Kondratyev #define PCI_CHIP_COMETLAKE_V_I2C_0 0xa3e08086 119f19aed35SVladimir Kondratyev #define PCI_CHIP_COMETLAKE_V_I2C_1 0xa3e18086 120f19aed35SVladimir Kondratyev #define PCI_CHIP_COMETLAKE_V_I2C_2 0xa3e28086 121f19aed35SVladimir Kondratyev #define PCI_CHIP_COMETLAKE_V_I2C_3 0xa3e38086 122789ffce3SVladimir Kondratyev #define PCI_CHIP_ICELAKE_LP_I2C_0 0x34e88086 123789ffce3SVladimir Kondratyev #define PCI_CHIP_ICELAKE_LP_I2C_1 0x34e98086 124789ffce3SVladimir Kondratyev #define PCI_CHIP_ICELAKE_LP_I2C_2 0x34ea8086 125789ffce3SVladimir Kondratyev #define PCI_CHIP_ICELAKE_LP_I2C_3 0x34eb8086 126789ffce3SVladimir Kondratyev #define PCI_CHIP_ICELAKE_LP_I2C_4 0x34c58086 127789ffce3SVladimir Kondratyev #define PCI_CHIP_ICELAKE_LP_I2C_5 0x34c68086 1286c6fd2b4SVladimir Kondratyev #define PCI_CHIP_TIGERLAKE_H_I2C_0 0x43d88086 1296c6fd2b4SVladimir Kondratyev #define PCI_CHIP_TIGERLAKE_H_I2C_1 0x43e88086 1306c6fd2b4SVladimir Kondratyev #define PCI_CHIP_TIGERLAKE_H_I2C_2 0x43e98086 1316c6fd2b4SVladimir Kondratyev #define PCI_CHIP_TIGERLAKE_H_I2C_3 0x43ea8086 1326c6fd2b4SVladimir Kondratyev #define PCI_CHIP_TIGERLAKE_H_I2C_4 0x43eb8086 1336c6fd2b4SVladimir Kondratyev #define PCI_CHIP_TIGERLAKE_H_I2C_5 0x43ad8086 1346c6fd2b4SVladimir Kondratyev #define PCI_CHIP_TIGERLAKE_H_I2C_6 0x43ae8086 1356c6fd2b4SVladimir Kondratyev #define PCI_CHIP_TIGERLAKE_LP_I2C_0 0xa0c58086 1366c6fd2b4SVladimir Kondratyev #define PCI_CHIP_TIGERLAKE_LP_I2C_1 0xa0c68086 1376c6fd2b4SVladimir Kondratyev #define PCI_CHIP_TIGERLAKE_LP_I2C_2 0xa0d88086 1386c6fd2b4SVladimir Kondratyev #define PCI_CHIP_TIGERLAKE_LP_I2C_3 0xa0d98086 1396c6fd2b4SVladimir Kondratyev #define PCI_CHIP_TIGERLAKE_LP_I2C_4 0xa0e88086 1406c6fd2b4SVladimir Kondratyev #define PCI_CHIP_TIGERLAKE_LP_I2C_5 0xa0e98086 1416c6fd2b4SVladimir Kondratyev #define PCI_CHIP_TIGERLAKE_LP_I2C_6 0xa0ea8086 1426c6fd2b4SVladimir Kondratyev #define PCI_CHIP_TIGERLAKE_LP_I2C_7 0xa0eb8086 143bbacb7ceSVladimir Kondratyev #define PCI_CHIP_GEMINILAKE_I2C_0 0x31ac8086 144bbacb7ceSVladimir Kondratyev #define PCI_CHIP_GEMINILAKE_I2C_1 0x31ae8086 145bbacb7ceSVladimir Kondratyev #define PCI_CHIP_GEMINILAKE_I2C_2 0x31b08086 146bbacb7ceSVladimir Kondratyev #define PCI_CHIP_GEMINILAKE_I2C_3 0x31b28086 147bbacb7ceSVladimir Kondratyev #define PCI_CHIP_GEMINILAKE_I2C_4 0x31b48086 148bbacb7ceSVladimir Kondratyev #define PCI_CHIP_GEMINILAKE_I2C_5 0x31b68086 149bbacb7ceSVladimir Kondratyev #define PCI_CHIP_GEMINILAKE_I2C_6 0x31b88086 150bbacb7ceSVladimir Kondratyev #define PCI_CHIP_GEMINILAKE_I2C_7 0x31ba8086 151e8e8d229SAlexander Motin #define PCI_CHIP_ALDERLAKE_P_I2C_0 0x51e88086 152e8e8d229SAlexander Motin #define PCI_CHIP_ALDERLAKE_P_I2C_1 0x51e98086 153e8e8d229SAlexander Motin #define PCI_CHIP_ALDERLAKE_P_I2C_2 0x51ea8086 154e8e8d229SAlexander Motin #define PCI_CHIP_ALDERLAKE_P_I2C_3 0x51eb8086 155e8e8d229SAlexander Motin #define PCI_CHIP_ALDERLAKE_P_I2C_4 0x51c58086 156e8e8d229SAlexander Motin #define PCI_CHIP_ALDERLAKE_P_I2C_5 0x51c68086 157e8e8d229SAlexander Motin #define PCI_CHIP_ALDERLAKE_P_I2C_6 0x51d88086 158e8e8d229SAlexander Motin #define PCI_CHIP_ALDERLAKE_P_I2C_7 0x51d98086 159e8e8d229SAlexander Motin #define PCI_CHIP_ALDERLAKE_S_I2C_0 0x7acc8086 160e8e8d229SAlexander Motin #define PCI_CHIP_ALDERLAKE_S_I2C_1 0x7acd8086 161e8e8d229SAlexander Motin #define PCI_CHIP_ALDERLAKE_S_I2C_2 0x7ace8086 162e8e8d229SAlexander Motin #define PCI_CHIP_ALDERLAKE_S_I2C_3 0x7acf8086 163e8e8d229SAlexander Motin #define PCI_CHIP_ALDERLAKE_S_I2C_4 0x7afc8086 164e8e8d229SAlexander Motin #define PCI_CHIP_ALDERLAKE_S_I2C_5 0x7afd8086 165e8e8d229SAlexander Motin #define PCI_CHIP_ALDERLAKE_M_I2C_0 0x54e88086 166e8e8d229SAlexander Motin #define PCI_CHIP_ALDERLAKE_M_I2C_1 0x54e98086 167e8e8d229SAlexander Motin #define PCI_CHIP_ALDERLAKE_M_I2C_2 0x54ea8086 168e8e8d229SAlexander Motin #define PCI_CHIP_ALDERLAKE_M_I2C_3 0x54eb8086 169e8e8d229SAlexander Motin #define PCI_CHIP_ALDERLAKE_M_I2C_4 0x54c58086 170e8e8d229SAlexander Motin #define PCI_CHIP_ALDERLAKE_M_I2C_5 0x54c68086 171*d3b05d0eSSHENG-YI HONG #define PCI_CHIP_METEORLAKE_M_I2C_0 0x7e788086 172*d3b05d0eSSHENG-YI HONG #define PCI_CHIP_METEORLAKE_M_I2C_1 0x7e798086 173*d3b05d0eSSHENG-YI HONG #define PCI_CHIP_METEORLAKE_M_I2C_2 0x7e508086 174*d3b05d0eSSHENG-YI HONG #define PCI_CHIP_METEORLAKE_M_I2C_3 0x7e518086 175e6f7f1bcSOleksandr Tymoshenko 176e6f7f1bcSOleksandr Tymoshenko struct ig4iic_pci_device { 177e6f7f1bcSOleksandr Tymoshenko uint32_t devid; 178e6f7f1bcSOleksandr Tymoshenko const char *desc; 179e6f7f1bcSOleksandr Tymoshenko enum ig4_vers version; 180e6f7f1bcSOleksandr Tymoshenko }; 181e6f7f1bcSOleksandr Tymoshenko 182e6f7f1bcSOleksandr Tymoshenko static struct ig4iic_pci_device ig4iic_pci_devices[] = { 1836f6e2de0SVladimir Kondratyev { PCI_CHIP_BAYTRAIL_I2C_1, "Intel BayTrail Serial I/O I2C Port 1", IG4_ATOM}, 1846f6e2de0SVladimir Kondratyev { PCI_CHIP_BAYTRAIL_I2C_2, "Intel BayTrail Serial I/O I2C Port 2", IG4_ATOM}, 1856f6e2de0SVladimir Kondratyev { PCI_CHIP_BAYTRAIL_I2C_3, "Intel BayTrail Serial I/O I2C Port 3", IG4_ATOM}, 1866f6e2de0SVladimir Kondratyev { PCI_CHIP_BAYTRAIL_I2C_4, "Intel BayTrail Serial I/O I2C Port 4", IG4_ATOM}, 1876f6e2de0SVladimir Kondratyev { PCI_CHIP_BAYTRAIL_I2C_5, "Intel BayTrail Serial I/O I2C Port 5", IG4_ATOM}, 1886f6e2de0SVladimir Kondratyev { PCI_CHIP_BAYTRAIL_I2C_6, "Intel BayTrail Serial I/O I2C Port 6", IG4_ATOM}, 1896f6e2de0SVladimir Kondratyev { PCI_CHIP_BAYTRAIL_I2C_7, "Intel BayTrail Serial I/O I2C Port 7", IG4_ATOM}, 190e6f7f1bcSOleksandr Tymoshenko { PCI_CHIP_LYNXPT_LP_I2C_1, "Intel Lynx Point-LP I2C Controller-1", IG4_HASWELL}, 191e6f7f1bcSOleksandr Tymoshenko { PCI_CHIP_LYNXPT_LP_I2C_2, "Intel Lynx Point-LP I2C Controller-2", IG4_HASWELL}, 192e6f7f1bcSOleksandr Tymoshenko { PCI_CHIP_BRASWELL_I2C_1, "Intel Braswell Serial I/O I2C Port 1", IG4_ATOM}, 193e6f7f1bcSOleksandr Tymoshenko { PCI_CHIP_BRASWELL_I2C_2, "Intel Braswell Serial I/O I2C Port 2", IG4_ATOM}, 194e6f7f1bcSOleksandr Tymoshenko { PCI_CHIP_BRASWELL_I2C_3, "Intel Braswell Serial I/O I2C Port 3", IG4_ATOM}, 195e6f7f1bcSOleksandr Tymoshenko { PCI_CHIP_BRASWELL_I2C_5, "Intel Braswell Serial I/O I2C Port 5", IG4_ATOM}, 196e6f7f1bcSOleksandr Tymoshenko { PCI_CHIP_BRASWELL_I2C_6, "Intel Braswell Serial I/O I2C Port 6", IG4_ATOM}, 197e6f7f1bcSOleksandr Tymoshenko { PCI_CHIP_BRASWELL_I2C_7, "Intel Braswell Serial I/O I2C Port 7", IG4_ATOM}, 198e6f7f1bcSOleksandr Tymoshenko { PCI_CHIP_SKYLAKE_I2C_0, "Intel Sunrise Point-LP I2C Controller-0", IG4_SKYLAKE}, 199e6f7f1bcSOleksandr Tymoshenko { PCI_CHIP_SKYLAKE_I2C_1, "Intel Sunrise Point-LP I2C Controller-1", IG4_SKYLAKE}, 200e6f7f1bcSOleksandr Tymoshenko { PCI_CHIP_SKYLAKE_I2C_2, "Intel Sunrise Point-LP I2C Controller-2", IG4_SKYLAKE}, 201e6f7f1bcSOleksandr Tymoshenko { PCI_CHIP_SKYLAKE_I2C_3, "Intel Sunrise Point-LP I2C Controller-3", IG4_SKYLAKE}, 202e6f7f1bcSOleksandr Tymoshenko { PCI_CHIP_SKYLAKE_I2C_4, "Intel Sunrise Point-LP I2C Controller-4", IG4_SKYLAKE}, 203e6f7f1bcSOleksandr Tymoshenko { PCI_CHIP_SKYLAKE_I2C_5, "Intel Sunrise Point-LP I2C Controller-5", IG4_SKYLAKE}, 204234afdb9SOleksandr Tymoshenko { PCI_CHIP_KABYLAKE_I2C_0, "Intel Sunrise Point-H I2C Controller-0", IG4_SKYLAKE}, 205234afdb9SOleksandr Tymoshenko { PCI_CHIP_KABYLAKE_I2C_1, "Intel Sunrise Point-H I2C Controller-1", IG4_SKYLAKE}, 2060a043c12SOleksandr Tymoshenko { PCI_CHIP_APL_I2C_0, "Intel Apollo Lake I2C Controller-0", IG4_APL}, 2070a043c12SOleksandr Tymoshenko { PCI_CHIP_APL_I2C_1, "Intel Apollo Lake I2C Controller-1", IG4_APL}, 2080a043c12SOleksandr Tymoshenko { PCI_CHIP_APL_I2C_2, "Intel Apollo Lake I2C Controller-2", IG4_APL}, 2090a043c12SOleksandr Tymoshenko { PCI_CHIP_APL_I2C_3, "Intel Apollo Lake I2C Controller-3", IG4_APL}, 2100a043c12SOleksandr Tymoshenko { PCI_CHIP_APL_I2C_4, "Intel Apollo Lake I2C Controller-4", IG4_APL}, 2110a043c12SOleksandr Tymoshenko { PCI_CHIP_APL_I2C_5, "Intel Apollo Lake I2C Controller-5", IG4_APL}, 2120a043c12SOleksandr Tymoshenko { PCI_CHIP_APL_I2C_6, "Intel Apollo Lake I2C Controller-6", IG4_APL}, 21381e81838SVladimir Kondratyev { PCI_CHIP_APL_I2C_7, "Intel Apollo Lake I2C Controller-7", IG4_APL}, 21481e81838SVladimir Kondratyev { PCI_CHIP_CANNONLAKE_LP_I2C_0, "Intel Cannon Lake-LP I2C Controller-0", IG4_CANNONLAKE}, 21581e81838SVladimir Kondratyev { PCI_CHIP_CANNONLAKE_LP_I2C_1, "Intel Cannon Lake-LP I2C Controller-1", IG4_CANNONLAKE}, 21681e81838SVladimir Kondratyev { PCI_CHIP_CANNONLAKE_LP_I2C_2, "Intel Cannon Lake-LP I2C Controller-2", IG4_CANNONLAKE}, 21781e81838SVladimir Kondratyev { PCI_CHIP_CANNONLAKE_LP_I2C_3, "Intel Cannon Lake-LP I2C Controller-3", IG4_CANNONLAKE}, 21881e81838SVladimir Kondratyev { PCI_CHIP_CANNONLAKE_LP_I2C_4, "Intel Cannon Lake-LP I2C Controller-4", IG4_CANNONLAKE}, 21981e81838SVladimir Kondratyev { PCI_CHIP_CANNONLAKE_LP_I2C_5, "Intel Cannon Lake-LP I2C Controller-5", IG4_CANNONLAKE}, 22081e81838SVladimir Kondratyev { PCI_CHIP_CANNONLAKE_H_I2C_0, "Intel Cannon Lake-H I2C Controller-0", IG4_CANNONLAKE}, 22181e81838SVladimir Kondratyev { PCI_CHIP_CANNONLAKE_H_I2C_1, "Intel Cannon Lake-H I2C Controller-1", IG4_CANNONLAKE}, 22281e81838SVladimir Kondratyev { PCI_CHIP_CANNONLAKE_H_I2C_2, "Intel Cannon Lake-H I2C Controller-2", IG4_CANNONLAKE}, 22381e81838SVladimir Kondratyev { PCI_CHIP_CANNONLAKE_H_I2C_3, "Intel Cannon Lake-H I2C Controller-3", IG4_CANNONLAKE}, 224f19aed35SVladimir Kondratyev { PCI_CHIP_COMETLAKE_LP_I2C_0, "Intel Comet Lake-LP I2C Controller-0", IG4_CANNONLAKE}, 225f19aed35SVladimir Kondratyev { PCI_CHIP_COMETLAKE_LP_I2C_1, "Intel Comet Lake-LP I2C Controller-1", IG4_CANNONLAKE}, 226f19aed35SVladimir Kondratyev { PCI_CHIP_COMETLAKE_LP_I2C_2, "Intel Comet Lake-LP I2C Controller-2", IG4_CANNONLAKE}, 227f19aed35SVladimir Kondratyev { PCI_CHIP_COMETLAKE_LP_I2C_3, "Intel Comet Lake-LP I2C Controller-3", IG4_CANNONLAKE}, 228f19aed35SVladimir Kondratyev { PCI_CHIP_COMETLAKE_LP_I2C_4, "Intel Comet Lake-LP I2C Controller-4", IG4_CANNONLAKE}, 229f19aed35SVladimir Kondratyev { PCI_CHIP_COMETLAKE_LP_I2C_5, "Intel Comet Lake-LP I2C Controller-5", IG4_CANNONLAKE}, 230f19aed35SVladimir Kondratyev { PCI_CHIP_COMETLAKE_H_I2C_0, "Intel Comet Lake-H I2C Controller-0", IG4_CANNONLAKE}, 231f19aed35SVladimir Kondratyev { PCI_CHIP_COMETLAKE_H_I2C_1, "Intel Comet Lake-H I2C Controller-1", IG4_CANNONLAKE}, 232f19aed35SVladimir Kondratyev { PCI_CHIP_COMETLAKE_H_I2C_2, "Intel Comet Lake-H I2C Controller-2", IG4_CANNONLAKE}, 233f19aed35SVladimir Kondratyev { PCI_CHIP_COMETLAKE_H_I2C_3, "Intel Comet Lake-H I2C Controller-3", IG4_CANNONLAKE}, 234f19aed35SVladimir Kondratyev { PCI_CHIP_COMETLAKE_V_I2C_0, "Intel Comet Lake-V I2C Controller-0", IG4_CANNONLAKE}, 235f19aed35SVladimir Kondratyev { PCI_CHIP_COMETLAKE_V_I2C_1, "Intel Comet Lake-V I2C Controller-1", IG4_CANNONLAKE}, 236f19aed35SVladimir Kondratyev { PCI_CHIP_COMETLAKE_V_I2C_2, "Intel Comet Lake-V I2C Controller-2", IG4_CANNONLAKE}, 237f19aed35SVladimir Kondratyev { PCI_CHIP_COMETLAKE_V_I2C_3, "Intel Comet Lake-V I2C Controller-3", IG4_CANNONLAKE}, 238789ffce3SVladimir Kondratyev { PCI_CHIP_ICELAKE_LP_I2C_0, "Intel Ice Lake-LP I2C Controller-0", IG4_TIGERLAKE}, 239789ffce3SVladimir Kondratyev { PCI_CHIP_ICELAKE_LP_I2C_1, "Intel Ice Lake-LP I2C Controller-1", IG4_TIGERLAKE}, 240789ffce3SVladimir Kondratyev { PCI_CHIP_ICELAKE_LP_I2C_2, "Intel Ice Lake-LP I2C Controller-2", IG4_TIGERLAKE}, 241789ffce3SVladimir Kondratyev { PCI_CHIP_ICELAKE_LP_I2C_3, "Intel Ice Lake-LP I2C Controller-3", IG4_TIGERLAKE}, 242789ffce3SVladimir Kondratyev { PCI_CHIP_ICELAKE_LP_I2C_4, "Intel Ice Lake-LP I2C Controller-4", IG4_TIGERLAKE}, 243789ffce3SVladimir Kondratyev { PCI_CHIP_ICELAKE_LP_I2C_5, "Intel Ice Lake-LP I2C Controller-5", IG4_TIGERLAKE}, 2446c6fd2b4SVladimir Kondratyev { PCI_CHIP_TIGERLAKE_H_I2C_0, "Intel Tiger Lake-H I2C Controller-0", IG4_TIGERLAKE}, 2456c6fd2b4SVladimir Kondratyev { PCI_CHIP_TIGERLAKE_H_I2C_1, "Intel Tiger Lake-H I2C Controller-1", IG4_TIGERLAKE}, 2466c6fd2b4SVladimir Kondratyev { PCI_CHIP_TIGERLAKE_H_I2C_2, "Intel Tiger Lake-H I2C Controller-2", IG4_TIGERLAKE}, 2476c6fd2b4SVladimir Kondratyev { PCI_CHIP_TIGERLAKE_H_I2C_3, "Intel Tiger Lake-H I2C Controller-3", IG4_TIGERLAKE}, 2486c6fd2b4SVladimir Kondratyev { PCI_CHIP_TIGERLAKE_H_I2C_4, "Intel Tiger Lake-H I2C Controller-4", IG4_TIGERLAKE}, 2496c6fd2b4SVladimir Kondratyev { PCI_CHIP_TIGERLAKE_H_I2C_5, "Intel Tiger Lake-H I2C Controller-5", IG4_TIGERLAKE}, 2506c6fd2b4SVladimir Kondratyev { PCI_CHIP_TIGERLAKE_H_I2C_6, "Intel Tiger Lake-H I2C Controller-6", IG4_TIGERLAKE}, 2516c6fd2b4SVladimir Kondratyev { PCI_CHIP_TIGERLAKE_LP_I2C_0, "Intel Tiger Lake-LP I2C Controller-0", IG4_SKYLAKE}, 2526c6fd2b4SVladimir Kondratyev { PCI_CHIP_TIGERLAKE_LP_I2C_1, "Intel Tiger Lake-LP I2C Controller-1", IG4_SKYLAKE}, 2536c6fd2b4SVladimir Kondratyev { PCI_CHIP_TIGERLAKE_LP_I2C_2, "Intel Tiger Lake-LP I2C Controller-2", IG4_SKYLAKE}, 2546c6fd2b4SVladimir Kondratyev { PCI_CHIP_TIGERLAKE_LP_I2C_3, "Intel Tiger Lake-LP I2C Controller-3", IG4_SKYLAKE}, 2556c6fd2b4SVladimir Kondratyev { PCI_CHIP_TIGERLAKE_LP_I2C_4, "Intel Tiger Lake-LP I2C Controller-4", IG4_SKYLAKE}, 2566c6fd2b4SVladimir Kondratyev { PCI_CHIP_TIGERLAKE_LP_I2C_5, "Intel Tiger Lake-LP I2C Controller-5", IG4_SKYLAKE}, 2576c6fd2b4SVladimir Kondratyev { PCI_CHIP_TIGERLAKE_LP_I2C_6, "Intel Tiger Lake-LP I2C Controller-6", IG4_SKYLAKE}, 2586c6fd2b4SVladimir Kondratyev { PCI_CHIP_TIGERLAKE_LP_I2C_7, "Intel Tiger Lake-LP I2C Controller-7", IG4_SKYLAKE}, 259bbacb7ceSVladimir Kondratyev { PCI_CHIP_GEMINILAKE_I2C_0, "Intel Gemini Lake I2C Controller-0", IG4_GEMINILAKE}, 260bbacb7ceSVladimir Kondratyev { PCI_CHIP_GEMINILAKE_I2C_1, "Intel Gemini Lake I2C Controller-1", IG4_GEMINILAKE}, 261bbacb7ceSVladimir Kondratyev { PCI_CHIP_GEMINILAKE_I2C_2, "Intel Gemini Lake I2C Controller-2", IG4_GEMINILAKE}, 262bbacb7ceSVladimir Kondratyev { PCI_CHIP_GEMINILAKE_I2C_3, "Intel Gemini Lake I2C Controller-3", IG4_GEMINILAKE}, 263bbacb7ceSVladimir Kondratyev { PCI_CHIP_GEMINILAKE_I2C_4, "Intel Gemini Lake I2C Controller-4", IG4_GEMINILAKE}, 264bbacb7ceSVladimir Kondratyev { PCI_CHIP_GEMINILAKE_I2C_5, "Intel Gemini Lake I2C Controller-5", IG4_GEMINILAKE}, 265bbacb7ceSVladimir Kondratyev { PCI_CHIP_GEMINILAKE_I2C_6, "Intel Gemini Lake I2C Controller-6", IG4_GEMINILAKE}, 266bbacb7ceSVladimir Kondratyev { PCI_CHIP_GEMINILAKE_I2C_7, "Intel Gemini Lake I2C Controller-7", IG4_GEMINILAKE}, 267e8e8d229SAlexander Motin { PCI_CHIP_ALDERLAKE_P_I2C_0, "Intel Alder Lake-P I2C Controller-0", IG4_TIGERLAKE}, 268e8e8d229SAlexander Motin { PCI_CHIP_ALDERLAKE_P_I2C_1, "Intel Alder Lake-P I2C Controller-1", IG4_TIGERLAKE}, 269e8e8d229SAlexander Motin { PCI_CHIP_ALDERLAKE_P_I2C_2, "Intel Alder Lake-P I2C Controller-2", IG4_TIGERLAKE}, 270e8e8d229SAlexander Motin { PCI_CHIP_ALDERLAKE_P_I2C_3, "Intel Alder Lake-P I2C Controller-3", IG4_TIGERLAKE}, 271e8e8d229SAlexander Motin { PCI_CHIP_ALDERLAKE_P_I2C_4, "Intel Alder Lake-P I2C Controller-4", IG4_TIGERLAKE}, 272e8e8d229SAlexander Motin { PCI_CHIP_ALDERLAKE_P_I2C_5, "Intel Alder Lake-P I2C Controller-5", IG4_TIGERLAKE}, 273e8e8d229SAlexander Motin { PCI_CHIP_ALDERLAKE_P_I2C_6, "Intel Alder Lake-P I2C Controller-6", IG4_TIGERLAKE}, 274e8e8d229SAlexander Motin { PCI_CHIP_ALDERLAKE_P_I2C_7, "Intel Alder Lake-P I2C Controller-7", IG4_TIGERLAKE}, 275e8e8d229SAlexander Motin { PCI_CHIP_ALDERLAKE_S_I2C_0, "Intel Alder Lake-S I2C Controller-0", IG4_TIGERLAKE}, 276e8e8d229SAlexander Motin { PCI_CHIP_ALDERLAKE_S_I2C_1, "Intel Alder Lake-S I2C Controller-1", IG4_TIGERLAKE}, 277e8e8d229SAlexander Motin { PCI_CHIP_ALDERLAKE_S_I2C_2, "Intel Alder Lake-S I2C Controller-2", IG4_TIGERLAKE}, 278e8e8d229SAlexander Motin { PCI_CHIP_ALDERLAKE_S_I2C_3, "Intel Alder Lake-S I2C Controller-3", IG4_TIGERLAKE}, 279e8e8d229SAlexander Motin { PCI_CHIP_ALDERLAKE_S_I2C_4, "Intel Alder Lake-S I2C Controller-4", IG4_TIGERLAKE}, 280e8e8d229SAlexander Motin { PCI_CHIP_ALDERLAKE_S_I2C_5, "Intel Alder Lake-S I2C Controller-5", IG4_TIGERLAKE}, 281e8e8d229SAlexander Motin { PCI_CHIP_ALDERLAKE_M_I2C_0, "Intel Alder Lake-M I2C Controller-0", IG4_TIGERLAKE}, 282e8e8d229SAlexander Motin { PCI_CHIP_ALDERLAKE_M_I2C_1, "Intel Alder Lake-M I2C Controller-1", IG4_TIGERLAKE}, 283e8e8d229SAlexander Motin { PCI_CHIP_ALDERLAKE_M_I2C_2, "Intel Alder Lake-M I2C Controller-2", IG4_TIGERLAKE}, 284e8e8d229SAlexander Motin { PCI_CHIP_ALDERLAKE_M_I2C_3, "Intel Alder Lake-M I2C Controller-3", IG4_TIGERLAKE}, 285e8e8d229SAlexander Motin { PCI_CHIP_ALDERLAKE_M_I2C_4, "Intel Alder Lake-M I2C Controller-4", IG4_TIGERLAKE}, 286e8e8d229SAlexander Motin { PCI_CHIP_ALDERLAKE_M_I2C_5, "Intel Alder Lake-M I2C Controller-5", IG4_TIGERLAKE}, 287*d3b05d0eSSHENG-YI HONG { PCI_CHIP_METEORLAKE_M_I2C_0, "Intel Meteor Lake-M I2C Controller-0", IG4_TIGERLAKE}, 288*d3b05d0eSSHENG-YI HONG { PCI_CHIP_METEORLAKE_M_I2C_1, "Intel Meteor Lake-M I2C Controller-1", IG4_TIGERLAKE}, 289*d3b05d0eSSHENG-YI HONG { PCI_CHIP_METEORLAKE_M_I2C_2, "Intel Meteor Lake-M I2C Controller-2", IG4_TIGERLAKE}, 290*d3b05d0eSSHENG-YI HONG { PCI_CHIP_METEORLAKE_M_I2C_3, "Intel Meteor Lake-M I2C Controller-3", IG4_TIGERLAKE}, 291e6f7f1bcSOleksandr Tymoshenko }; 29271d51719SMichael Gmelin 29371d51719SMichael Gmelin static int 29471d51719SMichael Gmelin ig4iic_pci_probe(device_t dev) 29571d51719SMichael Gmelin { 296b3e8ee5dSOleksandr Tymoshenko ig4iic_softc_t *sc = device_get_softc(dev); 297e6f7f1bcSOleksandr Tymoshenko uint32_t devid; 298e6f7f1bcSOleksandr Tymoshenko int i; 299b3e8ee5dSOleksandr Tymoshenko 300e6f7f1bcSOleksandr Tymoshenko devid = pci_get_devid(dev); 30100b5108bSOleksandr Tymoshenko for (i = 0; i < nitems(ig4iic_pci_devices); i++) { 302e6f7f1bcSOleksandr Tymoshenko if (ig4iic_pci_devices[i].devid == devid) { 303e6f7f1bcSOleksandr Tymoshenko device_set_desc(dev, ig4iic_pci_devices[i].desc); 304e6f7f1bcSOleksandr Tymoshenko sc->version = ig4iic_pci_devices[i].version; 30571d51719SMichael Gmelin return (BUS_PROBE_DEFAULT); 30671d51719SMichael Gmelin } 307e6f7f1bcSOleksandr Tymoshenko } 308e6f7f1bcSOleksandr Tymoshenko return (ENXIO); 309e6f7f1bcSOleksandr Tymoshenko } 31071d51719SMichael Gmelin 31171d51719SMichael Gmelin static int 31271d51719SMichael Gmelin ig4iic_pci_attach(device_t dev) 31371d51719SMichael Gmelin { 31471d51719SMichael Gmelin ig4iic_softc_t *sc = device_get_softc(dev); 31571d51719SMichael Gmelin int error; 31671d51719SMichael Gmelin 31771d51719SMichael Gmelin sc->dev = dev; 31871d51719SMichael Gmelin sc->regs_rid = PCIR_BAR(0); 31971d51719SMichael Gmelin sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 32071d51719SMichael Gmelin &sc->regs_rid, RF_ACTIVE); 32171d51719SMichael Gmelin if (sc->regs_res == NULL) { 32271d51719SMichael Gmelin device_printf(dev, "unable to map registers\n"); 32371d51719SMichael Gmelin ig4iic_pci_detach(dev); 32471d51719SMichael Gmelin return (ENXIO); 32571d51719SMichael Gmelin } 32671d51719SMichael Gmelin sc->intr_rid = 0; 32771d51719SMichael Gmelin if (pci_alloc_msi(dev, &sc->intr_rid)) { 32871d51719SMichael Gmelin device_printf(dev, "Using MSI\n"); 32971d51719SMichael Gmelin } 33071d51719SMichael Gmelin sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 33171d51719SMichael Gmelin &sc->intr_rid, RF_SHAREABLE | RF_ACTIVE); 33271d51719SMichael Gmelin if (sc->intr_res == NULL) { 33371d51719SMichael Gmelin device_printf(dev, "unable to map interrupt\n"); 33471d51719SMichael Gmelin ig4iic_pci_detach(dev); 33571d51719SMichael Gmelin return (ENXIO); 33671d51719SMichael Gmelin } 33787f55ab0SDimitry Andric sc->platform_attached = true; 33871d51719SMichael Gmelin 33971d51719SMichael Gmelin error = ig4iic_attach(sc); 34071d51719SMichael Gmelin if (error) 34171d51719SMichael Gmelin ig4iic_pci_detach(dev); 34271d51719SMichael Gmelin 34371d51719SMichael Gmelin return (error); 34471d51719SMichael Gmelin } 34571d51719SMichael Gmelin 34671d51719SMichael Gmelin static int 34771d51719SMichael Gmelin ig4iic_pci_detach(device_t dev) 34871d51719SMichael Gmelin { 34971d51719SMichael Gmelin ig4iic_softc_t *sc = device_get_softc(dev); 35071d51719SMichael Gmelin int error; 35171d51719SMichael Gmelin 3525c5bcb1dSOleksandr Tymoshenko if (sc->platform_attached) { 35371d51719SMichael Gmelin error = ig4iic_detach(sc); 35471d51719SMichael Gmelin if (error) 35571d51719SMichael Gmelin return (error); 35687f55ab0SDimitry Andric sc->platform_attached = false; 35771d51719SMichael Gmelin } 35871d51719SMichael Gmelin 35971d51719SMichael Gmelin if (sc->intr_res) { 36071d51719SMichael Gmelin bus_release_resource(dev, SYS_RES_IRQ, 36171d51719SMichael Gmelin sc->intr_rid, sc->intr_res); 36271d51719SMichael Gmelin sc->intr_res = NULL; 36371d51719SMichael Gmelin } 36471d51719SMichael Gmelin if (sc->intr_rid != 0) 36571d51719SMichael Gmelin pci_release_msi(dev); 36671d51719SMichael Gmelin if (sc->regs_res) { 36771d51719SMichael Gmelin bus_release_resource(dev, SYS_RES_MEMORY, 36871d51719SMichael Gmelin sc->regs_rid, sc->regs_res); 36971d51719SMichael Gmelin sc->regs_res = NULL; 37071d51719SMichael Gmelin } 37171d51719SMichael Gmelin 37271d51719SMichael Gmelin return (0); 37371d51719SMichael Gmelin } 37471d51719SMichael Gmelin 375db7caa2eSVladimir Kondratyev static int 376db7caa2eSVladimir Kondratyev ig4iic_pci_suspend(device_t dev) 377db7caa2eSVladimir Kondratyev { 378db7caa2eSVladimir Kondratyev ig4iic_softc_t *sc = device_get_softc(dev); 379db7caa2eSVladimir Kondratyev 380db7caa2eSVladimir Kondratyev return (ig4iic_suspend(sc)); 381db7caa2eSVladimir Kondratyev } 382db7caa2eSVladimir Kondratyev 383db7caa2eSVladimir Kondratyev static int 384db7caa2eSVladimir Kondratyev ig4iic_pci_resume(device_t dev) 385db7caa2eSVladimir Kondratyev { 386db7caa2eSVladimir Kondratyev ig4iic_softc_t *sc = device_get_softc(dev); 387db7caa2eSVladimir Kondratyev 388db7caa2eSVladimir Kondratyev return (ig4iic_resume(sc)); 389db7caa2eSVladimir Kondratyev } 390db7caa2eSVladimir Kondratyev 39171d51719SMichael Gmelin static device_method_t ig4iic_pci_methods[] = { 39271d51719SMichael Gmelin /* Device interface */ 39371d51719SMichael Gmelin DEVMETHOD(device_probe, ig4iic_pci_probe), 39471d51719SMichael Gmelin DEVMETHOD(device_attach, ig4iic_pci_attach), 39571d51719SMichael Gmelin DEVMETHOD(device_detach, ig4iic_pci_detach), 396db7caa2eSVladimir Kondratyev DEVMETHOD(device_suspend, ig4iic_pci_suspend), 397db7caa2eSVladimir Kondratyev DEVMETHOD(device_resume, ig4iic_pci_resume), 39871d51719SMichael Gmelin 399fceaa2ecSVladimir Kondratyev /* Bus interface */ 400fceaa2ecSVladimir Kondratyev DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 401fceaa2ecSVladimir Kondratyev DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 402fceaa2ecSVladimir Kondratyev DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 403fceaa2ecSVladimir Kondratyev DEVMETHOD(bus_release_resource, bus_generic_release_resource), 404fceaa2ecSVladimir Kondratyev DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 405fceaa2ecSVladimir Kondratyev DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 406fceaa2ecSVladimir Kondratyev DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 407fceaa2ecSVladimir Kondratyev 408fceaa2ecSVladimir Kondratyev /* iicbus interface */ 409448897d3SAndriy Gapon DEVMETHOD(iicbus_transfer, ig4iic_transfer), 410448897d3SAndriy Gapon DEVMETHOD(iicbus_reset, ig4iic_reset), 41141b24e09SVladimir Kondratyev DEVMETHOD(iicbus_callback, ig4iic_callback), 412448897d3SAndriy Gapon 41371d51719SMichael Gmelin DEVMETHOD_END 41471d51719SMichael Gmelin }; 41571d51719SMichael Gmelin 41671d51719SMichael Gmelin static driver_t ig4iic_pci_driver = { 417984ed3e4SVladimir Kondratyev "ig4iic", 41871d51719SMichael Gmelin ig4iic_pci_methods, 41971d51719SMichael Gmelin sizeof(struct ig4iic_softc) 42071d51719SMichael Gmelin }; 42171d51719SMichael Gmelin 4224e9e71fdSJohn Baldwin DRIVER_MODULE_ORDERED(ig4iic, pci, ig4iic_pci_driver, 0, 0, SI_ORDER_ANY); 423984ed3e4SVladimir Kondratyev MODULE_DEPEND(ig4iic, pci, 1, 1, 1); 424984ed3e4SVladimir Kondratyev MODULE_PNP_INFO("W32:vendor/device", pci, ig4iic, ig4iic_pci_devices, 425e710f8caSMark Johnston nitems(ig4iic_pci_devices)); 426