1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2023, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _ICE_SCHED_H_ 33 #define _ICE_SCHED_H_ 34 35 #include "ice_common.h" 36 37 #define ICE_SCHED_5_LAYERS 5 38 #define ICE_SCHED_9_LAYERS 9 39 40 #define ICE_QGRP_LAYER_OFFSET 2 41 #define ICE_VSI_LAYER_OFFSET 4 42 #define ICE_AGG_LAYER_OFFSET 6 43 #define ICE_SCHED_INVAL_LAYER_NUM 0xFF 44 /* Burst size is a 12 bits register that is configured while creating the RL 45 * profile(s). MSB is a granularity bit and tells the granularity type 46 * 0 - LSB bits are in 64 bytes granularity 47 * 1 - LSB bits are in 1K bytes granularity 48 */ 49 #define ICE_64_BYTE_GRANULARITY 0 50 #define ICE_KBYTE_GRANULARITY BIT(11) 51 #define ICE_MIN_BURST_SIZE_ALLOWED 64 /* In Bytes */ 52 #define ICE_MAX_BURST_SIZE_ALLOWED \ 53 ((BIT(11) - 1) * 1024) /* In Bytes */ 54 #define ICE_MAX_BURST_SIZE_64_BYTE_GRANULARITY \ 55 ((BIT(11) - 1) * 64) /* In Bytes */ 56 #define ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY ICE_MAX_BURST_SIZE_ALLOWED 57 58 #define ICE_RL_PROF_ACCURACY_BYTES 128 59 #define ICE_RL_PROF_MULTIPLIER 10000 60 #define ICE_RL_PROF_TS_MULTIPLIER 32 61 #define ICE_RL_PROF_FRACTION 512 62 63 #define ICE_PSM_CLK_367MHZ_IN_HZ 367647059 64 #define ICE_PSM_CLK_416MHZ_IN_HZ 416666667 65 #define ICE_PSM_CLK_446MHZ_IN_HZ 446428571 66 #define ICE_PSM_CLK_390MHZ_IN_HZ 390625000 67 68 struct rl_profile_params { 69 u32 bw; /* in Kbps */ 70 u16 rl_multiplier; 71 u16 wake_up_calc; 72 u16 rl_encode; 73 }; 74 75 /* BW rate limit profile parameters list entry along 76 * with bandwidth maintained per layer in port info 77 */ 78 struct ice_aqc_rl_profile_info { 79 struct ice_aqc_rl_profile_elem profile; 80 struct LIST_ENTRY_TYPE list_entry; 81 u32 bw; /* requested */ 82 u16 prof_id_ref; /* profile ID to node association ref count */ 83 }; 84 85 struct ice_sched_agg_vsi_info { 86 struct LIST_ENTRY_TYPE list_entry; 87 ice_declare_bitmap(tc_bitmap, ICE_MAX_TRAFFIC_CLASS); 88 u16 vsi_handle; 89 /* save aggregator VSI TC bitmap */ 90 ice_declare_bitmap(replay_tc_bitmap, ICE_MAX_TRAFFIC_CLASS); 91 }; 92 93 struct ice_sched_agg_info { 94 struct LIST_HEAD_TYPE agg_vsi_list; 95 struct LIST_ENTRY_TYPE list_entry; 96 ice_declare_bitmap(tc_bitmap, ICE_MAX_TRAFFIC_CLASS); 97 u32 agg_id; 98 enum ice_agg_type agg_type; 99 /* bw_t_info saves aggregator BW information */ 100 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS]; 101 /* save aggregator TC bitmap */ 102 ice_declare_bitmap(replay_tc_bitmap, ICE_MAX_TRAFFIC_CLASS); 103 }; 104 105 /* FW AQ command calls */ 106 enum ice_status 107 ice_aq_query_rl_profile(struct ice_hw *hw, u16 num_profiles, 108 struct ice_aqc_rl_profile_elem *buf, u16 buf_size, 109 struct ice_sq_cd *cd); 110 enum ice_status 111 ice_aq_cfg_node_attr(struct ice_hw *hw, u16 num_nodes, 112 struct ice_aqc_node_attr_elem *buf, u16 buf_size, 113 struct ice_sq_cd *cd); 114 enum ice_status 115 ice_aq_cfg_l2_node_cgd(struct ice_hw *hw, u16 num_nodes, 116 struct ice_aqc_cfg_l2_node_cgd_elem *buf, u16 buf_size, 117 struct ice_sq_cd *cd); 118 enum ice_status 119 ice_aq_move_sched_elems(struct ice_hw *hw, u16 grps_req, 120 struct ice_aqc_move_elem *buf, u16 buf_size, 121 u16 *grps_movd, struct ice_sq_cd *cd); 122 enum ice_status 123 ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req, 124 struct ice_aqc_txsched_elem_data *buf, u16 buf_size, 125 u16 *elems_ret, struct ice_sq_cd *cd); 126 enum ice_status ice_sched_init_port(struct ice_port_info *pi); 127 enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw); 128 void ice_sched_get_psm_clk_freq(struct ice_hw *hw); 129 130 /* Functions to cleanup scheduler SW DB */ 131 void ice_sched_clear_port(struct ice_port_info *pi); 132 void ice_sched_cleanup_all(struct ice_hw *hw); 133 void ice_sched_clear_agg(struct ice_hw *hw); 134 135 /* Get a scheduling node from SW DB for given TEID */ 136 struct ice_sched_node *ice_sched_get_node(struct ice_port_info *pi, u32 teid); 137 struct ice_sched_node * 138 ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid); 139 /* Add a scheduling node into SW DB for given info */ 140 enum ice_status 141 ice_sched_add_node(struct ice_port_info *pi, u8 layer, 142 struct ice_aqc_txsched_elem_data *info); 143 void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node); 144 struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc); 145 struct ice_sched_node * 146 ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 147 u8 owner); 148 enum ice_status 149 ice_sched_cfg_vsi(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 maxqs, 150 u8 owner, bool enable); 151 enum ice_status ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle); 152 enum ice_status ice_rm_vsi_rdma_cfg(struct ice_port_info *pi, u16 vsi_handle); 153 struct ice_sched_node * 154 ice_sched_get_vsi_node(struct ice_port_info *pi, struct ice_sched_node *tc_node, 155 u16 vsi_handle); 156 bool ice_sched_is_tree_balanced(struct ice_hw *hw, struct ice_sched_node *node); 157 enum ice_status 158 ice_aq_query_node_to_root(struct ice_hw *hw, u32 node_teid, 159 struct ice_aqc_txsched_elem_data *buf, u16 buf_size, 160 struct ice_sq_cd *cd); 161 162 /* Tx scheduler rate limiter functions */ 163 enum ice_status 164 ice_cfg_agg(struct ice_port_info *pi, u32 agg_id, 165 enum ice_agg_type agg_type, u8 tc_bitmap); 166 enum ice_status 167 ice_move_vsi_to_agg(struct ice_port_info *pi, u32 agg_id, u16 vsi_handle, 168 u8 tc_bitmap); 169 enum ice_status ice_rm_agg_cfg(struct ice_port_info *pi, u32 agg_id); 170 enum ice_status 171 ice_cfg_q_bw_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 172 u16 q_handle, enum ice_rl_type rl_type, u32 bw); 173 enum ice_status 174 ice_cfg_q_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 175 u16 q_handle, enum ice_rl_type rl_type); 176 enum ice_status 177 ice_cfg_tc_node_bw_lmt(struct ice_port_info *pi, u8 tc, 178 enum ice_rl_type rl_type, u32 bw); 179 enum ice_status 180 ice_cfg_tc_node_bw_dflt_lmt(struct ice_port_info *pi, u8 tc, 181 enum ice_rl_type rl_type); 182 enum ice_status 183 ice_cfg_vsi_bw_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 184 enum ice_rl_type rl_type, u32 bw); 185 enum ice_status 186 ice_cfg_vsi_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 187 enum ice_rl_type rl_type); 188 enum ice_status 189 ice_cfg_agg_bw_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc, 190 enum ice_rl_type rl_type, u32 bw); 191 enum ice_status 192 ice_cfg_agg_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc, 193 enum ice_rl_type rl_type); 194 enum ice_status 195 ice_cfg_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle, u32 min_bw, 196 u32 max_bw, u32 shared_bw); 197 enum ice_status 198 ice_cfg_vsi_bw_no_shared_lmt(struct ice_port_info *pi, u16 vsi_handle); 199 enum ice_status 200 ice_cfg_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 min_bw, 201 u32 max_bw, u32 shared_bw); 202 enum ice_status 203 ice_cfg_agg_bw_no_shared_lmt(struct ice_port_info *pi, u32 agg_id); 204 enum ice_status 205 ice_cfg_agg_bw_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc, 206 u32 min_bw, u32 max_bw, u32 shared_bw); 207 enum ice_status 208 ice_cfg_agg_bw_no_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, 209 u8 tc); 210 enum ice_status 211 ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 num_qs, u32 *q_ids, 212 u8 *q_prio); 213 enum ice_status 214 ice_cfg_vsi_bw_alloc(struct ice_port_info *pi, u16 vsi_handle, u8 ena_tcmap, 215 enum ice_rl_type rl_type, u8 *bw_alloc); 216 enum ice_status 217 ice_cfg_agg_vsi_priority_per_tc(struct ice_port_info *pi, u32 agg_id, 218 u16 num_vsis, u16 *vsi_handle_arr, 219 u8 *node_prio, u8 tc); 220 enum ice_status 221 ice_cfg_agg_bw_alloc(struct ice_port_info *pi, u32 agg_id, u8 ena_tcmap, 222 enum ice_rl_type rl_type, u8 *bw_alloc); 223 bool 224 ice_sched_find_node_in_subtree(struct ice_hw *hw, struct ice_sched_node *base, 225 struct ice_sched_node *node); 226 enum ice_status 227 ice_sched_set_agg_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle); 228 enum ice_status 229 ice_sched_set_node_bw_lmt_per_tc(struct ice_port_info *pi, u32 id, 230 enum ice_agg_type agg_type, u8 tc, 231 enum ice_rl_type rl_type, u32 bw); 232 enum ice_status 233 ice_sched_set_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle, 234 u32 min_bw, u32 max_bw, u32 shared_bw); 235 enum ice_status 236 ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 min_bw, 237 u32 max_bw, u32 shared_bw); 238 enum ice_status 239 ice_sched_set_agg_bw_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, 240 u8 tc, u32 min_bw, u32 max_bw, 241 u32 shared_bw); 242 enum ice_status 243 ice_sched_cfg_sibl_node_prio(struct ice_port_info *pi, 244 struct ice_sched_node *node, u8 priority); 245 enum ice_status 246 ice_cfg_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc, 247 enum ice_rl_type rl_type, u8 bw_alloc); 248 enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes); 249 void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw); 250 void ice_sched_replay_agg(struct ice_hw *hw); 251 enum ice_status ice_sched_replay_tc_node_bw(struct ice_port_info *pi); 252 enum ice_status ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle); 253 enum ice_status ice_sched_replay_root_node_bw(struct ice_port_info *pi); 254 enum ice_status 255 ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx); 256 257 #endif /* _ICE_SCHED_H_ */ 258