1*71d10453SEric Joyner /* SPDX-License-Identifier: BSD-3-Clause */ 2*71d10453SEric Joyner /* Copyright (c) 2020, Intel Corporation 3*71d10453SEric Joyner * All rights reserved. 4*71d10453SEric Joyner * 5*71d10453SEric Joyner * Redistribution and use in source and binary forms, with or without 6*71d10453SEric Joyner * modification, are permitted provided that the following conditions are met: 7*71d10453SEric Joyner * 8*71d10453SEric Joyner * 1. Redistributions of source code must retain the above copyright notice, 9*71d10453SEric Joyner * this list of conditions and the following disclaimer. 10*71d10453SEric Joyner * 11*71d10453SEric Joyner * 2. Redistributions in binary form must reproduce the above copyright 12*71d10453SEric Joyner * notice, this list of conditions and the following disclaimer in the 13*71d10453SEric Joyner * documentation and/or other materials provided with the distribution. 14*71d10453SEric Joyner * 15*71d10453SEric Joyner * 3. Neither the name of the Intel Corporation nor the names of its 16*71d10453SEric Joyner * contributors may be used to endorse or promote products derived from 17*71d10453SEric Joyner * this software without specific prior written permission. 18*71d10453SEric Joyner * 19*71d10453SEric Joyner * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20*71d10453SEric Joyner * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21*71d10453SEric Joyner * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22*71d10453SEric Joyner * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23*71d10453SEric Joyner * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24*71d10453SEric Joyner * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25*71d10453SEric Joyner * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26*71d10453SEric Joyner * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27*71d10453SEric Joyner * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28*71d10453SEric Joyner * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29*71d10453SEric Joyner * POSSIBILITY OF SUCH DAMAGE. 30*71d10453SEric Joyner */ 31*71d10453SEric Joyner /*$FreeBSD$*/ 32*71d10453SEric Joyner 33*71d10453SEric Joyner #ifndef _ICE_SCHED_H_ 34*71d10453SEric Joyner #define _ICE_SCHED_H_ 35*71d10453SEric Joyner 36*71d10453SEric Joyner #include "ice_common.h" 37*71d10453SEric Joyner 38*71d10453SEric Joyner #define ICE_QGRP_LAYER_OFFSET 2 39*71d10453SEric Joyner #define ICE_VSI_LAYER_OFFSET 4 40*71d10453SEric Joyner #define ICE_AGG_LAYER_OFFSET 6 41*71d10453SEric Joyner #define ICE_SCHED_INVAL_LAYER_NUM 0xFF 42*71d10453SEric Joyner /* Burst size is a 12 bits register that is configured while creating the RL 43*71d10453SEric Joyner * profile(s). MSB is a granularity bit and tells the granularity type 44*71d10453SEric Joyner * 0 - LSB bits are in 64 bytes granularity 45*71d10453SEric Joyner * 1 - LSB bits are in 1K bytes granularity 46*71d10453SEric Joyner */ 47*71d10453SEric Joyner #define ICE_64_BYTE_GRANULARITY 0 48*71d10453SEric Joyner #define ICE_KBYTE_GRANULARITY BIT(11) 49*71d10453SEric Joyner #define ICE_MIN_BURST_SIZE_ALLOWED 64 /* In Bytes */ 50*71d10453SEric Joyner #define ICE_MAX_BURST_SIZE_ALLOWED \ 51*71d10453SEric Joyner ((BIT(11) - 1) * 1024) /* In Bytes */ 52*71d10453SEric Joyner #define ICE_MAX_BURST_SIZE_64_BYTE_GRANULARITY \ 53*71d10453SEric Joyner ((BIT(11) - 1) * 64) /* In Bytes */ 54*71d10453SEric Joyner #define ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY ICE_MAX_BURST_SIZE_ALLOWED 55*71d10453SEric Joyner 56*71d10453SEric Joyner #define ICE_RL_PROF_ACCURACY_BYTES 128 57*71d10453SEric Joyner #define ICE_RL_PROF_MULTIPLIER 10000 58*71d10453SEric Joyner #define ICE_RL_PROF_TS_MULTIPLIER 32 59*71d10453SEric Joyner #define ICE_RL_PROF_FRACTION 512 60*71d10453SEric Joyner 61*71d10453SEric Joyner #define ICE_PSM_CLK_367MHZ_IN_HZ 367647059 62*71d10453SEric Joyner #define ICE_PSM_CLK_416MHZ_IN_HZ 416666667 63*71d10453SEric Joyner #define ICE_PSM_CLK_446MHZ_IN_HZ 446428571 64*71d10453SEric Joyner #define ICE_PSM_CLK_390MHZ_IN_HZ 390625000 65*71d10453SEric Joyner 66*71d10453SEric Joyner struct rl_profile_params { 67*71d10453SEric Joyner u32 bw; /* in Kbps */ 68*71d10453SEric Joyner u16 rl_multiplier; 69*71d10453SEric Joyner u16 wake_up_calc; 70*71d10453SEric Joyner u16 rl_encode; 71*71d10453SEric Joyner }; 72*71d10453SEric Joyner 73*71d10453SEric Joyner /* BW rate limit profile parameters list entry along 74*71d10453SEric Joyner * with bandwidth maintained per layer in port info 75*71d10453SEric Joyner */ 76*71d10453SEric Joyner struct ice_aqc_rl_profile_info { 77*71d10453SEric Joyner struct ice_aqc_rl_profile_elem profile; 78*71d10453SEric Joyner struct LIST_ENTRY_TYPE list_entry; 79*71d10453SEric Joyner u32 bw; /* requested */ 80*71d10453SEric Joyner u16 prof_id_ref; /* profile ID to node association ref count */ 81*71d10453SEric Joyner }; 82*71d10453SEric Joyner 83*71d10453SEric Joyner struct ice_sched_agg_vsi_info { 84*71d10453SEric Joyner struct LIST_ENTRY_TYPE list_entry; 85*71d10453SEric Joyner ice_declare_bitmap(tc_bitmap, ICE_MAX_TRAFFIC_CLASS); 86*71d10453SEric Joyner u16 vsi_handle; 87*71d10453SEric Joyner /* save aggregator VSI TC bitmap */ 88*71d10453SEric Joyner ice_declare_bitmap(replay_tc_bitmap, ICE_MAX_TRAFFIC_CLASS); 89*71d10453SEric Joyner }; 90*71d10453SEric Joyner 91*71d10453SEric Joyner struct ice_sched_agg_info { 92*71d10453SEric Joyner struct LIST_HEAD_TYPE agg_vsi_list; 93*71d10453SEric Joyner struct LIST_ENTRY_TYPE list_entry; 94*71d10453SEric Joyner ice_declare_bitmap(tc_bitmap, ICE_MAX_TRAFFIC_CLASS); 95*71d10453SEric Joyner u32 agg_id; 96*71d10453SEric Joyner enum ice_agg_type agg_type; 97*71d10453SEric Joyner /* bw_t_info saves aggregator BW information */ 98*71d10453SEric Joyner struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS]; 99*71d10453SEric Joyner /* save aggregator TC bitmap */ 100*71d10453SEric Joyner ice_declare_bitmap(replay_tc_bitmap, ICE_MAX_TRAFFIC_CLASS); 101*71d10453SEric Joyner }; 102*71d10453SEric Joyner 103*71d10453SEric Joyner /* FW AQ command calls */ 104*71d10453SEric Joyner enum ice_status 105*71d10453SEric Joyner ice_aq_query_rl_profile(struct ice_hw *hw, u16 num_profiles, 106*71d10453SEric Joyner struct ice_aqc_rl_profile_generic_elem *buf, 107*71d10453SEric Joyner u16 buf_size, struct ice_sq_cd *cd); 108*71d10453SEric Joyner enum ice_status 109*71d10453SEric Joyner ice_aq_cfg_l2_node_cgd(struct ice_hw *hw, u16 num_nodes, 110*71d10453SEric Joyner struct ice_aqc_cfg_l2_node_cgd_data *buf, u16 buf_size, 111*71d10453SEric Joyner struct ice_sq_cd *cd); 112*71d10453SEric Joyner enum ice_status 113*71d10453SEric Joyner ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req, 114*71d10453SEric Joyner struct ice_aqc_get_elem *buf, u16 buf_size, 115*71d10453SEric Joyner u16 *elems_ret, struct ice_sq_cd *cd); 116*71d10453SEric Joyner enum ice_status ice_sched_init_port(struct ice_port_info *pi); 117*71d10453SEric Joyner enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw); 118*71d10453SEric Joyner void ice_sched_get_psm_clk_freq(struct ice_hw *hw); 119*71d10453SEric Joyner 120*71d10453SEric Joyner /* Functions to cleanup scheduler SW DB */ 121*71d10453SEric Joyner void ice_sched_clear_port(struct ice_port_info *pi); 122*71d10453SEric Joyner void ice_sched_cleanup_all(struct ice_hw *hw); 123*71d10453SEric Joyner void ice_sched_clear_agg(struct ice_hw *hw); 124*71d10453SEric Joyner 125*71d10453SEric Joyner /* Get a scheduling node from SW DB for given TEID */ 126*71d10453SEric Joyner struct ice_sched_node *ice_sched_get_node(struct ice_port_info *pi, u32 teid); 127*71d10453SEric Joyner struct ice_sched_node * 128*71d10453SEric Joyner ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid); 129*71d10453SEric Joyner /* Add a scheduling node into SW DB for given info */ 130*71d10453SEric Joyner enum ice_status 131*71d10453SEric Joyner ice_sched_add_node(struct ice_port_info *pi, u8 layer, 132*71d10453SEric Joyner struct ice_aqc_txsched_elem_data *info); 133*71d10453SEric Joyner void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node); 134*71d10453SEric Joyner struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc); 135*71d10453SEric Joyner struct ice_sched_node * 136*71d10453SEric Joyner ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 137*71d10453SEric Joyner u8 owner); 138*71d10453SEric Joyner enum ice_status 139*71d10453SEric Joyner ice_sched_cfg_vsi(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 maxqs, 140*71d10453SEric Joyner u8 owner, bool enable); 141*71d10453SEric Joyner enum ice_status ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle); 142*71d10453SEric Joyner struct ice_sched_node * 143*71d10453SEric Joyner ice_sched_get_vsi_node(struct ice_port_info *pi, struct ice_sched_node *tc_node, 144*71d10453SEric Joyner u16 vsi_handle); 145*71d10453SEric Joyner bool ice_sched_is_tree_balanced(struct ice_hw *hw, struct ice_sched_node *node); 146*71d10453SEric Joyner enum ice_status 147*71d10453SEric Joyner ice_aq_query_node_to_root(struct ice_hw *hw, u32 node_teid, 148*71d10453SEric Joyner struct ice_aqc_get_elem *buf, u16 buf_size, 149*71d10453SEric Joyner struct ice_sq_cd *cd); 150*71d10453SEric Joyner 151*71d10453SEric Joyner /* Tx scheduler rate limiter functions */ 152*71d10453SEric Joyner enum ice_status 153*71d10453SEric Joyner ice_cfg_agg(struct ice_port_info *pi, u32 agg_id, 154*71d10453SEric Joyner enum ice_agg_type agg_type, u8 tc_bitmap); 155*71d10453SEric Joyner enum ice_status 156*71d10453SEric Joyner ice_move_vsi_to_agg(struct ice_port_info *pi, u32 agg_id, u16 vsi_handle, 157*71d10453SEric Joyner u8 tc_bitmap); 158*71d10453SEric Joyner enum ice_status ice_rm_agg_cfg(struct ice_port_info *pi, u32 agg_id); 159*71d10453SEric Joyner enum ice_status 160*71d10453SEric Joyner ice_cfg_q_bw_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 161*71d10453SEric Joyner u16 q_handle, enum ice_rl_type rl_type, u32 bw); 162*71d10453SEric Joyner enum ice_status 163*71d10453SEric Joyner ice_cfg_q_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 164*71d10453SEric Joyner u16 q_handle, enum ice_rl_type rl_type); 165*71d10453SEric Joyner enum ice_status 166*71d10453SEric Joyner ice_cfg_tc_node_bw_lmt(struct ice_port_info *pi, u8 tc, 167*71d10453SEric Joyner enum ice_rl_type rl_type, u32 bw); 168*71d10453SEric Joyner enum ice_status 169*71d10453SEric Joyner ice_cfg_tc_node_bw_dflt_lmt(struct ice_port_info *pi, u8 tc, 170*71d10453SEric Joyner enum ice_rl_type rl_type); 171*71d10453SEric Joyner enum ice_status 172*71d10453SEric Joyner ice_cfg_vsi_bw_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 173*71d10453SEric Joyner enum ice_rl_type rl_type, u32 bw); 174*71d10453SEric Joyner enum ice_status 175*71d10453SEric Joyner ice_cfg_vsi_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 176*71d10453SEric Joyner enum ice_rl_type rl_type); 177*71d10453SEric Joyner enum ice_status 178*71d10453SEric Joyner ice_cfg_agg_bw_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc, 179*71d10453SEric Joyner enum ice_rl_type rl_type, u32 bw); 180*71d10453SEric Joyner enum ice_status 181*71d10453SEric Joyner ice_cfg_agg_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc, 182*71d10453SEric Joyner enum ice_rl_type rl_type); 183*71d10453SEric Joyner enum ice_status 184*71d10453SEric Joyner ice_cfg_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle, u32 bw); 185*71d10453SEric Joyner enum ice_status 186*71d10453SEric Joyner ice_cfg_vsi_bw_no_shared_lmt(struct ice_port_info *pi, u16 vsi_handle); 187*71d10453SEric Joyner enum ice_status 188*71d10453SEric Joyner ice_cfg_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw); 189*71d10453SEric Joyner enum ice_status 190*71d10453SEric Joyner ice_cfg_agg_bw_no_shared_lmt(struct ice_port_info *pi, u32 agg_id); 191*71d10453SEric Joyner enum ice_status 192*71d10453SEric Joyner ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 num_qs, u32 *q_ids, 193*71d10453SEric Joyner u8 *q_prio); 194*71d10453SEric Joyner enum ice_status 195*71d10453SEric Joyner ice_cfg_vsi_bw_alloc(struct ice_port_info *pi, u16 vsi_handle, u8 ena_tcmap, 196*71d10453SEric Joyner enum ice_rl_type rl_type, u8 *bw_alloc); 197*71d10453SEric Joyner enum ice_status 198*71d10453SEric Joyner ice_cfg_agg_vsi_priority_per_tc(struct ice_port_info *pi, u32 agg_id, 199*71d10453SEric Joyner u16 num_vsis, u16 *vsi_handle_arr, 200*71d10453SEric Joyner u8 *node_prio, u8 tc); 201*71d10453SEric Joyner enum ice_status 202*71d10453SEric Joyner ice_cfg_agg_bw_alloc(struct ice_port_info *pi, u32 agg_id, u8 ena_tcmap, 203*71d10453SEric Joyner enum ice_rl_type rl_type, u8 *bw_alloc); 204*71d10453SEric Joyner bool 205*71d10453SEric Joyner ice_sched_find_node_in_subtree(struct ice_hw *hw, struct ice_sched_node *base, 206*71d10453SEric Joyner struct ice_sched_node *node); 207*71d10453SEric Joyner enum ice_status 208*71d10453SEric Joyner ice_sched_set_agg_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle); 209*71d10453SEric Joyner enum ice_status 210*71d10453SEric Joyner ice_sched_set_node_bw_lmt_per_tc(struct ice_port_info *pi, u32 id, 211*71d10453SEric Joyner enum ice_agg_type agg_type, u8 tc, 212*71d10453SEric Joyner enum ice_rl_type rl_type, u32 bw); 213*71d10453SEric Joyner enum ice_status 214*71d10453SEric Joyner ice_sched_set_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle, 215*71d10453SEric Joyner u32 bw); 216*71d10453SEric Joyner enum ice_status 217*71d10453SEric Joyner ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 bw); 218*71d10453SEric Joyner enum ice_status 219*71d10453SEric Joyner ice_sched_cfg_sibl_node_prio(struct ice_port_info *pi, 220*71d10453SEric Joyner struct ice_sched_node *node, u8 priority); 221*71d10453SEric Joyner enum ice_status 222*71d10453SEric Joyner ice_cfg_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc, 223*71d10453SEric Joyner enum ice_rl_type rl_type, u8 bw_alloc); 224*71d10453SEric Joyner enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes); 225*71d10453SEric Joyner #endif /* _ICE_SCHED_H_ */ 226