1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2023, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*$FreeBSD$*/ 32 33 #include "ice_sched.h" 34 35 /** 36 * ice_sched_add_root_node - Insert the Tx scheduler root node in SW DB 37 * @pi: port information structure 38 * @info: Scheduler element information from firmware 39 * 40 * This function inserts the root node of the scheduling tree topology 41 * to the SW DB. 42 */ 43 static enum ice_status 44 ice_sched_add_root_node(struct ice_port_info *pi, 45 struct ice_aqc_txsched_elem_data *info) 46 { 47 struct ice_sched_node *root; 48 struct ice_hw *hw; 49 50 if (!pi) 51 return ICE_ERR_PARAM; 52 53 hw = pi->hw; 54 55 root = (struct ice_sched_node *)ice_malloc(hw, sizeof(*root)); 56 if (!root) 57 return ICE_ERR_NO_MEMORY; 58 59 /* coverity[suspicious_sizeof] */ 60 root->children = (struct ice_sched_node **) 61 ice_calloc(hw, hw->max_children[0], sizeof(*root)); 62 if (!root->children) { 63 ice_free(hw, root); 64 return ICE_ERR_NO_MEMORY; 65 } 66 67 ice_memcpy(&root->info, info, sizeof(*info), ICE_DMA_TO_NONDMA); 68 pi->root = root; 69 return ICE_SUCCESS; 70 } 71 72 /** 73 * ice_sched_find_node_by_teid - Find the Tx scheduler node in SW DB 74 * @start_node: pointer to the starting ice_sched_node struct in a sub-tree 75 * @teid: node TEID to search 76 * 77 * This function searches for a node matching the TEID in the scheduling tree 78 * from the SW DB. The search is recursive and is restricted by the number of 79 * layers it has searched through; stopping at the max supported layer. 80 * 81 * This function needs to be called when holding the port_info->sched_lock 82 */ 83 struct ice_sched_node * 84 ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid) 85 { 86 u16 i; 87 88 /* The TEID is same as that of the start_node */ 89 if (ICE_TXSCHED_GET_NODE_TEID(start_node) == teid) 90 return start_node; 91 92 /* The node has no children or is at the max layer */ 93 if (!start_node->num_children || 94 start_node->tx_sched_layer >= ICE_AQC_TOPO_MAX_LEVEL_NUM || 95 start_node->info.data.elem_type == ICE_AQC_ELEM_TYPE_LEAF) 96 return NULL; 97 98 /* Check if TEID matches to any of the children nodes */ 99 for (i = 0; i < start_node->num_children; i++) 100 if (ICE_TXSCHED_GET_NODE_TEID(start_node->children[i]) == teid) 101 return start_node->children[i]; 102 103 /* Search within each child's sub-tree */ 104 for (i = 0; i < start_node->num_children; i++) { 105 struct ice_sched_node *tmp; 106 107 tmp = ice_sched_find_node_by_teid(start_node->children[i], 108 teid); 109 if (tmp) 110 return tmp; 111 } 112 113 return NULL; 114 } 115 116 /** 117 * ice_aqc_send_sched_elem_cmd - send scheduling elements cmd 118 * @hw: pointer to the HW struct 119 * @cmd_opc: cmd opcode 120 * @elems_req: number of elements to request 121 * @buf: pointer to buffer 122 * @buf_size: buffer size in bytes 123 * @elems_resp: returns total number of elements response 124 * @cd: pointer to command details structure or NULL 125 * 126 * This function sends a scheduling elements cmd (cmd_opc) 127 */ 128 static enum ice_status 129 ice_aqc_send_sched_elem_cmd(struct ice_hw *hw, enum ice_adminq_opc cmd_opc, 130 u16 elems_req, void *buf, u16 buf_size, 131 u16 *elems_resp, struct ice_sq_cd *cd) 132 { 133 struct ice_aqc_sched_elem_cmd *cmd; 134 struct ice_aq_desc desc; 135 enum ice_status status; 136 137 cmd = &desc.params.sched_elem_cmd; 138 ice_fill_dflt_direct_cmd_desc(&desc, cmd_opc); 139 cmd->num_elem_req = CPU_TO_LE16(elems_req); 140 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 141 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 142 if (!status && elems_resp) 143 *elems_resp = LE16_TO_CPU(cmd->num_elem_resp); 144 145 return status; 146 } 147 148 /** 149 * ice_aq_query_sched_elems - query scheduler elements 150 * @hw: pointer to the HW struct 151 * @elems_req: number of elements to query 152 * @buf: pointer to buffer 153 * @buf_size: buffer size in bytes 154 * @elems_ret: returns total number of elements returned 155 * @cd: pointer to command details structure or NULL 156 * 157 * Query scheduling elements (0x0404) 158 */ 159 enum ice_status 160 ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req, 161 struct ice_aqc_txsched_elem_data *buf, u16 buf_size, 162 u16 *elems_ret, struct ice_sq_cd *cd) 163 { 164 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_get_sched_elems, 165 elems_req, (void *)buf, buf_size, 166 elems_ret, cd); 167 } 168 169 /** 170 * ice_sched_add_node - Insert the Tx scheduler node in SW DB 171 * @pi: port information structure 172 * @layer: Scheduler layer of the node 173 * @info: Scheduler element information from firmware 174 * 175 * This function inserts a scheduler node to the SW DB. 176 */ 177 enum ice_status 178 ice_sched_add_node(struct ice_port_info *pi, u8 layer, 179 struct ice_aqc_txsched_elem_data *info) 180 { 181 struct ice_aqc_txsched_elem_data elem; 182 struct ice_sched_node *parent; 183 struct ice_sched_node *node; 184 enum ice_status status; 185 struct ice_hw *hw; 186 187 if (!pi) 188 return ICE_ERR_PARAM; 189 190 hw = pi->hw; 191 192 /* A valid parent node should be there */ 193 parent = ice_sched_find_node_by_teid(pi->root, 194 LE32_TO_CPU(info->parent_teid)); 195 if (!parent) { 196 ice_debug(hw, ICE_DBG_SCHED, "Parent Node not found for parent_teid=0x%x\n", 197 LE32_TO_CPU(info->parent_teid)); 198 return ICE_ERR_PARAM; 199 } 200 201 /* query the current node information from FW before adding it 202 * to the SW DB 203 */ 204 status = ice_sched_query_elem(hw, LE32_TO_CPU(info->node_teid), &elem); 205 if (status) 206 return status; 207 node = (struct ice_sched_node *)ice_malloc(hw, sizeof(*node)); 208 if (!node) 209 return ICE_ERR_NO_MEMORY; 210 if (hw->max_children[layer]) { 211 /* coverity[suspicious_sizeof] */ 212 node->children = (struct ice_sched_node **) 213 ice_calloc(hw, hw->max_children[layer], sizeof(*node)); 214 if (!node->children) { 215 ice_free(hw, node); 216 return ICE_ERR_NO_MEMORY; 217 } 218 } 219 220 node->in_use = true; 221 node->parent = parent; 222 node->tx_sched_layer = layer; 223 parent->children[parent->num_children++] = node; 224 node->info = elem; 225 return ICE_SUCCESS; 226 } 227 228 /** 229 * ice_aq_delete_sched_elems - delete scheduler elements 230 * @hw: pointer to the HW struct 231 * @grps_req: number of groups to delete 232 * @buf: pointer to buffer 233 * @buf_size: buffer size in bytes 234 * @grps_del: returns total number of elements deleted 235 * @cd: pointer to command details structure or NULL 236 * 237 * Delete scheduling elements (0x040F) 238 */ 239 static enum ice_status 240 ice_aq_delete_sched_elems(struct ice_hw *hw, u16 grps_req, 241 struct ice_aqc_delete_elem *buf, u16 buf_size, 242 u16 *grps_del, struct ice_sq_cd *cd) 243 { 244 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_delete_sched_elems, 245 grps_req, (void *)buf, buf_size, 246 grps_del, cd); 247 } 248 249 /** 250 * ice_sched_remove_elems - remove nodes from HW 251 * @hw: pointer to the HW struct 252 * @parent: pointer to the parent node 253 * @num_nodes: number of nodes 254 * @node_teids: array of node teids to be deleted 255 * 256 * This function remove nodes from HW 257 */ 258 static enum ice_status 259 ice_sched_remove_elems(struct ice_hw *hw, struct ice_sched_node *parent, 260 u16 num_nodes, u32 *node_teids) 261 { 262 struct ice_aqc_delete_elem *buf; 263 u16 i, num_groups_removed = 0; 264 enum ice_status status; 265 u16 buf_size; 266 267 buf_size = ice_struct_size(buf, teid, num_nodes); 268 buf = (struct ice_aqc_delete_elem *)ice_malloc(hw, buf_size); 269 if (!buf) 270 return ICE_ERR_NO_MEMORY; 271 272 buf->hdr.parent_teid = parent->info.node_teid; 273 buf->hdr.num_elems = CPU_TO_LE16(num_nodes); 274 for (i = 0; i < num_nodes; i++) 275 buf->teid[i] = CPU_TO_LE32(node_teids[i]); 276 277 status = ice_aq_delete_sched_elems(hw, 1, buf, buf_size, 278 &num_groups_removed, NULL); 279 if (status != ICE_SUCCESS || num_groups_removed != 1) 280 ice_debug(hw, ICE_DBG_SCHED, "remove node failed FW error %d\n", 281 hw->adminq.sq_last_status); 282 283 ice_free(hw, buf); 284 return status; 285 } 286 287 /** 288 * ice_sched_get_first_node - get the first node of the given layer 289 * @pi: port information structure 290 * @parent: pointer the base node of the subtree 291 * @layer: layer number 292 * 293 * This function retrieves the first node of the given layer from the subtree 294 */ 295 static struct ice_sched_node * 296 ice_sched_get_first_node(struct ice_port_info *pi, 297 struct ice_sched_node *parent, u8 layer) 298 { 299 return pi->sib_head[parent->tc_num][layer]; 300 } 301 302 /** 303 * ice_sched_get_tc_node - get pointer to TC node 304 * @pi: port information structure 305 * @tc: TC number 306 * 307 * This function returns the TC node pointer 308 */ 309 struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc) 310 { 311 u8 i; 312 313 if (!pi || !pi->root) 314 return NULL; 315 for (i = 0; i < pi->root->num_children; i++) 316 if (pi->root->children[i]->tc_num == tc) 317 return pi->root->children[i]; 318 return NULL; 319 } 320 321 /** 322 * ice_free_sched_node - Free a Tx scheduler node from SW DB 323 * @pi: port information structure 324 * @node: pointer to the ice_sched_node struct 325 * 326 * This function frees up a node from SW DB as well as from HW 327 * 328 * This function needs to be called with the port_info->sched_lock held 329 */ 330 void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node) 331 { 332 struct ice_sched_node *parent; 333 struct ice_hw *hw = pi->hw; 334 u8 i, j; 335 336 /* Free the children before freeing up the parent node 337 * The parent array is updated below and that shifts the nodes 338 * in the array. So always pick the first child if num children > 0 339 */ 340 while (node->num_children) 341 ice_free_sched_node(pi, node->children[0]); 342 343 /* Leaf, TC and root nodes can't be deleted by SW */ 344 if (node->tx_sched_layer >= hw->sw_entry_point_layer && 345 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_TC && 346 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_ROOT_PORT && 347 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_LEAF) { 348 u32 teid = LE32_TO_CPU(node->info.node_teid); 349 350 ice_sched_remove_elems(hw, node->parent, 1, &teid); 351 } 352 parent = node->parent; 353 /* root has no parent */ 354 if (parent) { 355 struct ice_sched_node *p; 356 357 /* update the parent */ 358 for (i = 0; i < parent->num_children; i++) 359 if (parent->children[i] == node) { 360 for (j = i + 1; j < parent->num_children; j++) 361 parent->children[j - 1] = 362 parent->children[j]; 363 parent->num_children--; 364 break; 365 } 366 367 p = ice_sched_get_first_node(pi, node, node->tx_sched_layer); 368 while (p) { 369 if (p->sibling == node) { 370 p->sibling = node->sibling; 371 break; 372 } 373 p = p->sibling; 374 } 375 376 /* update the sibling head if head is getting removed */ 377 if (pi->sib_head[node->tc_num][node->tx_sched_layer] == node) 378 pi->sib_head[node->tc_num][node->tx_sched_layer] = 379 node->sibling; 380 } 381 382 /* leaf nodes have no children */ 383 if (node->children) 384 ice_free(hw, node->children); 385 ice_free(hw, node); 386 } 387 388 /** 389 * ice_aq_get_dflt_topo - gets default scheduler topology 390 * @hw: pointer to the HW struct 391 * @lport: logical port number 392 * @buf: pointer to buffer 393 * @buf_size: buffer size in bytes 394 * @num_branches: returns total number of queue to port branches 395 * @cd: pointer to command details structure or NULL 396 * 397 * Get default scheduler topology (0x400) 398 */ 399 static enum ice_status 400 ice_aq_get_dflt_topo(struct ice_hw *hw, u8 lport, 401 struct ice_aqc_get_topo_elem *buf, u16 buf_size, 402 u8 *num_branches, struct ice_sq_cd *cd) 403 { 404 struct ice_aqc_get_topo *cmd; 405 struct ice_aq_desc desc; 406 enum ice_status status; 407 408 cmd = &desc.params.get_topo; 409 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_dflt_topo); 410 cmd->port_num = lport; 411 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 412 if (!status && num_branches) 413 *num_branches = cmd->num_branches; 414 415 return status; 416 } 417 418 /** 419 * ice_aq_add_sched_elems - adds scheduling element 420 * @hw: pointer to the HW struct 421 * @grps_req: the number of groups that are requested to be added 422 * @buf: pointer to buffer 423 * @buf_size: buffer size in bytes 424 * @grps_added: returns total number of groups added 425 * @cd: pointer to command details structure or NULL 426 * 427 * Add scheduling elements (0x0401) 428 */ 429 static enum ice_status 430 ice_aq_add_sched_elems(struct ice_hw *hw, u16 grps_req, 431 struct ice_aqc_add_elem *buf, u16 buf_size, 432 u16 *grps_added, struct ice_sq_cd *cd) 433 { 434 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_add_sched_elems, 435 grps_req, (void *)buf, buf_size, 436 grps_added, cd); 437 } 438 439 /** 440 * ice_aq_cfg_sched_elems - configures scheduler elements 441 * @hw: pointer to the HW struct 442 * @elems_req: number of elements to configure 443 * @buf: pointer to buffer 444 * @buf_size: buffer size in bytes 445 * @elems_cfgd: returns total number of elements configured 446 * @cd: pointer to command details structure or NULL 447 * 448 * Configure scheduling elements (0x0403) 449 */ 450 static enum ice_status 451 ice_aq_cfg_sched_elems(struct ice_hw *hw, u16 elems_req, 452 struct ice_aqc_txsched_elem_data *buf, u16 buf_size, 453 u16 *elems_cfgd, struct ice_sq_cd *cd) 454 { 455 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_cfg_sched_elems, 456 elems_req, (void *)buf, buf_size, 457 elems_cfgd, cd); 458 } 459 460 /** 461 * ice_aq_move_sched_elems - move scheduler elements 462 * @hw: pointer to the HW struct 463 * @grps_req: number of groups to move 464 * @buf: pointer to buffer 465 * @buf_size: buffer size in bytes 466 * @grps_movd: returns total number of groups moved 467 * @cd: pointer to command details structure or NULL 468 * 469 * Move scheduling elements (0x0408) 470 */ 471 enum ice_status 472 ice_aq_move_sched_elems(struct ice_hw *hw, u16 grps_req, 473 struct ice_aqc_move_elem *buf, u16 buf_size, 474 u16 *grps_movd, struct ice_sq_cd *cd) 475 { 476 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_move_sched_elems, 477 grps_req, (void *)buf, buf_size, 478 grps_movd, cd); 479 } 480 481 /** 482 * ice_aq_suspend_sched_elems - suspend scheduler elements 483 * @hw: pointer to the HW struct 484 * @elems_req: number of elements to suspend 485 * @buf: pointer to buffer 486 * @buf_size: buffer size in bytes 487 * @elems_ret: returns total number of elements suspended 488 * @cd: pointer to command details structure or NULL 489 * 490 * Suspend scheduling elements (0x0409) 491 */ 492 static enum ice_status 493 ice_aq_suspend_sched_elems(struct ice_hw *hw, u16 elems_req, __le32 *buf, 494 u16 buf_size, u16 *elems_ret, struct ice_sq_cd *cd) 495 { 496 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_suspend_sched_elems, 497 elems_req, (void *)buf, buf_size, 498 elems_ret, cd); 499 } 500 501 /** 502 * ice_aq_resume_sched_elems - resume scheduler elements 503 * @hw: pointer to the HW struct 504 * @elems_req: number of elements to resume 505 * @buf: pointer to buffer 506 * @buf_size: buffer size in bytes 507 * @elems_ret: returns total number of elements resumed 508 * @cd: pointer to command details structure or NULL 509 * 510 * resume scheduling elements (0x040A) 511 */ 512 static enum ice_status 513 ice_aq_resume_sched_elems(struct ice_hw *hw, u16 elems_req, __le32 *buf, 514 u16 buf_size, u16 *elems_ret, struct ice_sq_cd *cd) 515 { 516 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_resume_sched_elems, 517 elems_req, (void *)buf, buf_size, 518 elems_ret, cd); 519 } 520 521 /** 522 * ice_aq_query_sched_res - query scheduler resource 523 * @hw: pointer to the HW struct 524 * @buf_size: buffer size in bytes 525 * @buf: pointer to buffer 526 * @cd: pointer to command details structure or NULL 527 * 528 * Query scheduler resource allocation (0x0412) 529 */ 530 static enum ice_status 531 ice_aq_query_sched_res(struct ice_hw *hw, u16 buf_size, 532 struct ice_aqc_query_txsched_res_resp *buf, 533 struct ice_sq_cd *cd) 534 { 535 struct ice_aq_desc desc; 536 537 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_query_sched_res); 538 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 539 } 540 541 /** 542 * ice_sched_suspend_resume_elems - suspend or resume HW nodes 543 * @hw: pointer to the HW struct 544 * @num_nodes: number of nodes 545 * @node_teids: array of node teids to be suspended or resumed 546 * @suspend: true means suspend / false means resume 547 * 548 * This function suspends or resumes HW nodes 549 */ 550 static enum ice_status 551 ice_sched_suspend_resume_elems(struct ice_hw *hw, u8 num_nodes, u32 *node_teids, 552 bool suspend) 553 { 554 u16 i, buf_size, num_elem_ret = 0; 555 enum ice_status status; 556 __le32 *buf; 557 558 buf_size = sizeof(*buf) * num_nodes; 559 buf = (__le32 *)ice_malloc(hw, buf_size); 560 if (!buf) 561 return ICE_ERR_NO_MEMORY; 562 563 for (i = 0; i < num_nodes; i++) 564 buf[i] = CPU_TO_LE32(node_teids[i]); 565 566 if (suspend) 567 status = ice_aq_suspend_sched_elems(hw, num_nodes, buf, 568 buf_size, &num_elem_ret, 569 NULL); 570 else 571 status = ice_aq_resume_sched_elems(hw, num_nodes, buf, 572 buf_size, &num_elem_ret, 573 NULL); 574 if (status != ICE_SUCCESS || num_elem_ret != num_nodes) 575 ice_debug(hw, ICE_DBG_SCHED, "suspend/resume failed\n"); 576 577 ice_free(hw, buf); 578 return status; 579 } 580 581 /** 582 * ice_alloc_lan_q_ctx - allocate LAN queue contexts for the given VSI and TC 583 * @hw: pointer to the HW struct 584 * @vsi_handle: VSI handle 585 * @tc: TC number 586 * @new_numqs: number of queues 587 */ 588 static enum ice_status 589 ice_alloc_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 new_numqs) 590 { 591 struct ice_vsi_ctx *vsi_ctx; 592 struct ice_q_ctx *q_ctx; 593 594 vsi_ctx = ice_get_vsi_ctx(hw, vsi_handle); 595 if (!vsi_ctx) 596 return ICE_ERR_PARAM; 597 /* allocate LAN queue contexts */ 598 if (!vsi_ctx->lan_q_ctx[tc]) { 599 vsi_ctx->lan_q_ctx[tc] = (struct ice_q_ctx *) 600 ice_calloc(hw, new_numqs, sizeof(*q_ctx)); 601 if (!vsi_ctx->lan_q_ctx[tc]) 602 return ICE_ERR_NO_MEMORY; 603 vsi_ctx->num_lan_q_entries[tc] = new_numqs; 604 return ICE_SUCCESS; 605 } 606 /* num queues are increased, update the queue contexts */ 607 if (new_numqs > vsi_ctx->num_lan_q_entries[tc]) { 608 u16 prev_num = vsi_ctx->num_lan_q_entries[tc]; 609 610 q_ctx = (struct ice_q_ctx *) 611 ice_calloc(hw, new_numqs, sizeof(*q_ctx)); 612 if (!q_ctx) 613 return ICE_ERR_NO_MEMORY; 614 ice_memcpy(q_ctx, vsi_ctx->lan_q_ctx[tc], 615 prev_num * sizeof(*q_ctx), ICE_DMA_TO_NONDMA); 616 ice_free(hw, vsi_ctx->lan_q_ctx[tc]); 617 vsi_ctx->lan_q_ctx[tc] = q_ctx; 618 vsi_ctx->num_lan_q_entries[tc] = new_numqs; 619 } 620 return ICE_SUCCESS; 621 } 622 623 /** 624 * ice_alloc_rdma_q_ctx - allocate RDMA queue contexts for the given VSI and TC 625 * @hw: pointer to the HW struct 626 * @vsi_handle: VSI handle 627 * @tc: TC number 628 * @new_numqs: number of queues 629 */ 630 static enum ice_status 631 ice_alloc_rdma_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 new_numqs) 632 { 633 struct ice_vsi_ctx *vsi_ctx; 634 struct ice_q_ctx *q_ctx; 635 636 vsi_ctx = ice_get_vsi_ctx(hw, vsi_handle); 637 if (!vsi_ctx) 638 return ICE_ERR_PARAM; 639 /* allocate RDMA queue contexts */ 640 if (!vsi_ctx->rdma_q_ctx[tc]) { 641 vsi_ctx->rdma_q_ctx[tc] = (struct ice_q_ctx *) 642 ice_calloc(hw, new_numqs, sizeof(*q_ctx)); 643 if (!vsi_ctx->rdma_q_ctx[tc]) 644 return ICE_ERR_NO_MEMORY; 645 vsi_ctx->num_rdma_q_entries[tc] = new_numqs; 646 return ICE_SUCCESS; 647 } 648 /* num queues are increased, update the queue contexts */ 649 if (new_numqs > vsi_ctx->num_rdma_q_entries[tc]) { 650 u16 prev_num = vsi_ctx->num_rdma_q_entries[tc]; 651 652 q_ctx = (struct ice_q_ctx *) 653 ice_calloc(hw, new_numqs, sizeof(*q_ctx)); 654 if (!q_ctx) 655 return ICE_ERR_NO_MEMORY; 656 ice_memcpy(q_ctx, vsi_ctx->rdma_q_ctx[tc], 657 prev_num * sizeof(*q_ctx), ICE_DMA_TO_NONDMA); 658 ice_free(hw, vsi_ctx->rdma_q_ctx[tc]); 659 vsi_ctx->rdma_q_ctx[tc] = q_ctx; 660 vsi_ctx->num_rdma_q_entries[tc] = new_numqs; 661 } 662 return ICE_SUCCESS; 663 } 664 665 /** 666 * ice_aq_rl_profile - performs a rate limiting task 667 * @hw: pointer to the HW struct 668 * @opcode: opcode for add, query, or remove profile(s) 669 * @num_profiles: the number of profiles 670 * @buf: pointer to buffer 671 * @buf_size: buffer size in bytes 672 * @num_processed: number of processed add or remove profile(s) to return 673 * @cd: pointer to command details structure 674 * 675 * RL profile function to add, query, or remove profile(s) 676 */ 677 static enum ice_status 678 ice_aq_rl_profile(struct ice_hw *hw, enum ice_adminq_opc opcode, 679 u16 num_profiles, struct ice_aqc_rl_profile_elem *buf, 680 u16 buf_size, u16 *num_processed, struct ice_sq_cd *cd) 681 { 682 struct ice_aqc_rl_profile *cmd; 683 struct ice_aq_desc desc; 684 enum ice_status status; 685 686 cmd = &desc.params.rl_profile; 687 688 ice_fill_dflt_direct_cmd_desc(&desc, opcode); 689 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 690 cmd->num_profiles = CPU_TO_LE16(num_profiles); 691 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 692 if (!status && num_processed) 693 *num_processed = LE16_TO_CPU(cmd->num_processed); 694 return status; 695 } 696 697 /** 698 * ice_aq_add_rl_profile - adds rate limiting profile(s) 699 * @hw: pointer to the HW struct 700 * @num_profiles: the number of profile(s) to be add 701 * @buf: pointer to buffer 702 * @buf_size: buffer size in bytes 703 * @num_profiles_added: total number of profiles added to return 704 * @cd: pointer to command details structure 705 * 706 * Add RL profile (0x0410) 707 */ 708 static enum ice_status 709 ice_aq_add_rl_profile(struct ice_hw *hw, u16 num_profiles, 710 struct ice_aqc_rl_profile_elem *buf, u16 buf_size, 711 u16 *num_profiles_added, struct ice_sq_cd *cd) 712 { 713 return ice_aq_rl_profile(hw, ice_aqc_opc_add_rl_profiles, num_profiles, 714 buf, buf_size, num_profiles_added, cd); 715 } 716 717 /** 718 * ice_aq_query_rl_profile - query rate limiting profile(s) 719 * @hw: pointer to the HW struct 720 * @num_profiles: the number of profile(s) to query 721 * @buf: pointer to buffer 722 * @buf_size: buffer size in bytes 723 * @cd: pointer to command details structure 724 * 725 * Query RL profile (0x0411) 726 */ 727 enum ice_status 728 ice_aq_query_rl_profile(struct ice_hw *hw, u16 num_profiles, 729 struct ice_aqc_rl_profile_elem *buf, u16 buf_size, 730 struct ice_sq_cd *cd) 731 { 732 return ice_aq_rl_profile(hw, ice_aqc_opc_query_rl_profiles, 733 num_profiles, buf, buf_size, NULL, cd); 734 } 735 736 /** 737 * ice_aq_remove_rl_profile - removes RL profile(s) 738 * @hw: pointer to the HW struct 739 * @num_profiles: the number of profile(s) to remove 740 * @buf: pointer to buffer 741 * @buf_size: buffer size in bytes 742 * @num_profiles_removed: total number of profiles removed to return 743 * @cd: pointer to command details structure or NULL 744 * 745 * Remove RL profile (0x0415) 746 */ 747 static enum ice_status 748 ice_aq_remove_rl_profile(struct ice_hw *hw, u16 num_profiles, 749 struct ice_aqc_rl_profile_elem *buf, u16 buf_size, 750 u16 *num_profiles_removed, struct ice_sq_cd *cd) 751 { 752 return ice_aq_rl_profile(hw, ice_aqc_opc_remove_rl_profiles, 753 num_profiles, buf, buf_size, 754 num_profiles_removed, cd); 755 } 756 757 /** 758 * ice_sched_del_rl_profile - remove RL profile 759 * @hw: pointer to the HW struct 760 * @rl_info: rate limit profile information 761 * 762 * If the profile ID is not referenced anymore, it removes profile ID with 763 * its associated parameters from HW DB,and locally. The caller needs to 764 * hold scheduler lock. 765 */ 766 static enum ice_status 767 ice_sched_del_rl_profile(struct ice_hw *hw, 768 struct ice_aqc_rl_profile_info *rl_info) 769 { 770 struct ice_aqc_rl_profile_elem *buf; 771 u16 num_profiles_removed; 772 enum ice_status status; 773 u16 num_profiles = 1; 774 775 if (rl_info->prof_id_ref != 0) 776 return ICE_ERR_IN_USE; 777 778 /* Safe to remove profile ID */ 779 buf = &rl_info->profile; 780 status = ice_aq_remove_rl_profile(hw, num_profiles, buf, sizeof(*buf), 781 &num_profiles_removed, NULL); 782 if (status || num_profiles_removed != num_profiles) 783 return ICE_ERR_CFG; 784 785 /* Delete stale entry now */ 786 LIST_DEL(&rl_info->list_entry); 787 ice_free(hw, rl_info); 788 return status; 789 } 790 791 /** 792 * ice_sched_clear_rl_prof - clears RL prof entries 793 * @pi: port information structure 794 * 795 * This function removes all RL profile from HW as well as from SW DB. 796 */ 797 static void ice_sched_clear_rl_prof(struct ice_port_info *pi) 798 { 799 u16 ln; 800 struct ice_hw *hw = pi->hw; 801 802 for (ln = 0; ln < hw->num_tx_sched_layers; ln++) { 803 struct ice_aqc_rl_profile_info *rl_prof_elem; 804 struct ice_aqc_rl_profile_info *rl_prof_tmp; 805 806 LIST_FOR_EACH_ENTRY_SAFE(rl_prof_elem, rl_prof_tmp, 807 &hw->rl_prof_list[ln], 808 ice_aqc_rl_profile_info, list_entry) { 809 enum ice_status status; 810 811 rl_prof_elem->prof_id_ref = 0; 812 status = ice_sched_del_rl_profile(hw, rl_prof_elem); 813 if (status) { 814 ice_debug(hw, ICE_DBG_SCHED, "Remove rl profile failed\n"); 815 /* On error, free mem required */ 816 LIST_DEL(&rl_prof_elem->list_entry); 817 ice_free(hw, rl_prof_elem); 818 } 819 } 820 } 821 } 822 823 /** 824 * ice_sched_clear_agg - clears the aggregator related information 825 * @hw: pointer to the hardware structure 826 * 827 * This function removes aggregator list and free up aggregator related memory 828 * previously allocated. 829 */ 830 void ice_sched_clear_agg(struct ice_hw *hw) 831 { 832 struct ice_sched_agg_info *agg_info; 833 struct ice_sched_agg_info *atmp; 834 835 LIST_FOR_EACH_ENTRY_SAFE(agg_info, atmp, &hw->agg_list, 836 ice_sched_agg_info, 837 list_entry) { 838 struct ice_sched_agg_vsi_info *agg_vsi_info; 839 struct ice_sched_agg_vsi_info *vtmp; 840 841 LIST_FOR_EACH_ENTRY_SAFE(agg_vsi_info, vtmp, 842 &agg_info->agg_vsi_list, 843 ice_sched_agg_vsi_info, list_entry) { 844 LIST_DEL(&agg_vsi_info->list_entry); 845 ice_free(hw, agg_vsi_info); 846 } 847 LIST_DEL(&agg_info->list_entry); 848 ice_free(hw, agg_info); 849 } 850 } 851 852 /** 853 * ice_sched_clear_tx_topo - clears the scheduler tree nodes 854 * @pi: port information structure 855 * 856 * This function removes all the nodes from HW as well as from SW DB. 857 */ 858 static void ice_sched_clear_tx_topo(struct ice_port_info *pi) 859 { 860 if (!pi) 861 return; 862 /* remove RL profiles related lists */ 863 ice_sched_clear_rl_prof(pi); 864 if (pi->root) { 865 ice_free_sched_node(pi, pi->root); 866 pi->root = NULL; 867 } 868 } 869 870 /** 871 * ice_sched_clear_port - clear the scheduler elements from SW DB for a port 872 * @pi: port information structure 873 * 874 * Cleanup scheduling elements from SW DB 875 */ 876 void ice_sched_clear_port(struct ice_port_info *pi) 877 { 878 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 879 return; 880 881 pi->port_state = ICE_SCHED_PORT_STATE_INIT; 882 ice_acquire_lock(&pi->sched_lock); 883 ice_sched_clear_tx_topo(pi); 884 ice_release_lock(&pi->sched_lock); 885 ice_destroy_lock(&pi->sched_lock); 886 } 887 888 /** 889 * ice_sched_cleanup_all - cleanup scheduler elements from SW DB for all ports 890 * @hw: pointer to the HW struct 891 * 892 * Cleanup scheduling elements from SW DB for all the ports 893 */ 894 void ice_sched_cleanup_all(struct ice_hw *hw) 895 { 896 if (!hw) 897 return; 898 899 if (hw->layer_info) { 900 ice_free(hw, hw->layer_info); 901 hw->layer_info = NULL; 902 } 903 904 ice_sched_clear_port(hw->port_info); 905 906 hw->num_tx_sched_layers = 0; 907 hw->num_tx_sched_phys_layers = 0; 908 hw->flattened_layers = 0; 909 hw->max_cgds = 0; 910 } 911 912 /** 913 * ice_aq_cfg_node_attr - configure nodes' per-cone flattening attributes 914 * @hw: pointer to the HW struct 915 * @num_nodes: the number of nodes whose attributes to configure 916 * @buf: pointer to buffer 917 * @buf_size: buffer size in bytes 918 * @cd: pointer to command details structure or NULL 919 * 920 * Configure Node Attributes (0x0417) 921 */ 922 enum ice_status 923 ice_aq_cfg_node_attr(struct ice_hw *hw, u16 num_nodes, 924 struct ice_aqc_node_attr_elem *buf, u16 buf_size, 925 struct ice_sq_cd *cd) 926 { 927 struct ice_aqc_node_attr *cmd; 928 struct ice_aq_desc desc; 929 930 cmd = &desc.params.node_attr; 931 ice_fill_dflt_direct_cmd_desc(&desc, 932 ice_aqc_opc_cfg_node_attr); 933 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 934 935 cmd->num_entries = CPU_TO_LE16(num_nodes); 936 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 937 } 938 939 /** 940 * ice_aq_cfg_l2_node_cgd - configures L2 node to CGD mapping 941 * @hw: pointer to the HW struct 942 * @num_l2_nodes: the number of L2 nodes whose CGDs to configure 943 * @buf: pointer to buffer 944 * @buf_size: buffer size in bytes 945 * @cd: pointer to command details structure or NULL 946 * 947 * Configure L2 Node CGD (0x0414) 948 */ 949 enum ice_status 950 ice_aq_cfg_l2_node_cgd(struct ice_hw *hw, u16 num_l2_nodes, 951 struct ice_aqc_cfg_l2_node_cgd_elem *buf, 952 u16 buf_size, struct ice_sq_cd *cd) 953 { 954 struct ice_aqc_cfg_l2_node_cgd *cmd; 955 struct ice_aq_desc desc; 956 957 cmd = &desc.params.cfg_l2_node_cgd; 958 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_l2_node_cgd); 959 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 960 961 cmd->num_l2_nodes = CPU_TO_LE16(num_l2_nodes); 962 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 963 } 964 965 /** 966 * ice_sched_add_elems - add nodes to HW and SW DB 967 * @pi: port information structure 968 * @tc_node: pointer to the branch node 969 * @parent: pointer to the parent node 970 * @layer: layer number to add nodes 971 * @num_nodes: number of nodes 972 * @num_nodes_added: pointer to num nodes added 973 * @first_node_teid: if new nodes are added then return the TEID of first node 974 * 975 * This function add nodes to HW as well as to SW DB for a given layer 976 */ 977 static enum ice_status 978 ice_sched_add_elems(struct ice_port_info *pi, struct ice_sched_node *tc_node, 979 struct ice_sched_node *parent, u8 layer, u16 num_nodes, 980 u16 *num_nodes_added, u32 *first_node_teid) 981 { 982 struct ice_sched_node *prev, *new_node; 983 struct ice_aqc_add_elem *buf; 984 u16 i, num_groups_added = 0; 985 enum ice_status status = ICE_SUCCESS; 986 struct ice_hw *hw = pi->hw; 987 u16 buf_size; 988 u32 teid; 989 990 buf_size = ice_struct_size(buf, generic, num_nodes); 991 buf = (struct ice_aqc_add_elem *)ice_malloc(hw, buf_size); 992 if (!buf) 993 return ICE_ERR_NO_MEMORY; 994 995 buf->hdr.parent_teid = parent->info.node_teid; 996 buf->hdr.num_elems = CPU_TO_LE16(num_nodes); 997 for (i = 0; i < num_nodes; i++) { 998 buf->generic[i].parent_teid = parent->info.node_teid; 999 buf->generic[i].data.elem_type = ICE_AQC_ELEM_TYPE_SE_GENERIC; 1000 buf->generic[i].data.valid_sections = 1001 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 1002 ICE_AQC_ELEM_VALID_EIR; 1003 buf->generic[i].data.generic = 0; 1004 buf->generic[i].data.cir_bw.bw_profile_idx = 1005 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); 1006 buf->generic[i].data.cir_bw.bw_alloc = 1007 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); 1008 buf->generic[i].data.eir_bw.bw_profile_idx = 1009 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); 1010 buf->generic[i].data.eir_bw.bw_alloc = 1011 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); 1012 } 1013 1014 status = ice_aq_add_sched_elems(hw, 1, buf, buf_size, 1015 &num_groups_added, NULL); 1016 if (status != ICE_SUCCESS || num_groups_added != 1) { 1017 ice_debug(hw, ICE_DBG_SCHED, "add node failed FW Error %d\n", 1018 hw->adminq.sq_last_status); 1019 ice_free(hw, buf); 1020 return ICE_ERR_CFG; 1021 } 1022 1023 *num_nodes_added = num_nodes; 1024 /* add nodes to the SW DB */ 1025 for (i = 0; i < num_nodes; i++) { 1026 status = ice_sched_add_node(pi, layer, &buf->generic[i]); 1027 if (status != ICE_SUCCESS) { 1028 ice_debug(hw, ICE_DBG_SCHED, "add nodes in SW DB failed status =%d\n", 1029 status); 1030 break; 1031 } 1032 1033 teid = LE32_TO_CPU(buf->generic[i].node_teid); 1034 new_node = ice_sched_find_node_by_teid(parent, teid); 1035 if (!new_node) { 1036 ice_debug(hw, ICE_DBG_SCHED, "Node is missing for teid =%d\n", teid); 1037 break; 1038 } 1039 1040 new_node->sibling = NULL; 1041 new_node->tc_num = tc_node->tc_num; 1042 1043 /* add it to previous node sibling pointer */ 1044 /* Note: siblings are not linked across branches */ 1045 prev = ice_sched_get_first_node(pi, tc_node, layer); 1046 if (prev && prev != new_node) { 1047 while (prev->sibling) 1048 prev = prev->sibling; 1049 prev->sibling = new_node; 1050 } 1051 1052 /* initialize the sibling head */ 1053 if (!pi->sib_head[tc_node->tc_num][layer]) 1054 pi->sib_head[tc_node->tc_num][layer] = new_node; 1055 1056 if (i == 0) 1057 *first_node_teid = teid; 1058 } 1059 1060 ice_free(hw, buf); 1061 return status; 1062 } 1063 1064 /** 1065 * ice_sched_add_nodes_to_hw_layer - Add nodes to hw layer 1066 * @pi: port information structure 1067 * @tc_node: pointer to TC node 1068 * @parent: pointer to parent node 1069 * @layer: layer number to add nodes 1070 * @num_nodes: number of nodes to be added 1071 * @first_node_teid: pointer to the first node TEID 1072 * @num_nodes_added: pointer to number of nodes added 1073 * 1074 * Add nodes into specific hw layer. 1075 */ 1076 static enum ice_status 1077 ice_sched_add_nodes_to_hw_layer(struct ice_port_info *pi, 1078 struct ice_sched_node *tc_node, 1079 struct ice_sched_node *parent, u8 layer, 1080 u16 num_nodes, u32 *first_node_teid, 1081 u16 *num_nodes_added) 1082 { 1083 u16 max_child_nodes; 1084 1085 *num_nodes_added = 0; 1086 1087 if (!num_nodes) 1088 return ICE_SUCCESS; 1089 1090 if (!parent || layer < pi->hw->sw_entry_point_layer) 1091 return ICE_ERR_PARAM; 1092 1093 /* max children per node per layer */ 1094 max_child_nodes = pi->hw->max_children[parent->tx_sched_layer]; 1095 1096 /* current number of children + required nodes exceed max children */ 1097 if ((parent->num_children + num_nodes) > max_child_nodes) { 1098 /* Fail if the parent is a TC node */ 1099 if (parent == tc_node) 1100 return ICE_ERR_CFG; 1101 return ICE_ERR_MAX_LIMIT; 1102 } 1103 1104 return ice_sched_add_elems(pi, tc_node, parent, layer, num_nodes, 1105 num_nodes_added, first_node_teid); 1106 } 1107 1108 /** 1109 * ice_sched_add_nodes_to_layer - Add nodes to a given layer 1110 * @pi: port information structure 1111 * @tc_node: pointer to TC node 1112 * @parent: pointer to parent node 1113 * @layer: layer number to add nodes 1114 * @num_nodes: number of nodes to be added 1115 * @first_node_teid: pointer to the first node TEID 1116 * @num_nodes_added: pointer to number of nodes added 1117 * 1118 * This function add nodes to a given layer. 1119 */ 1120 static enum ice_status 1121 ice_sched_add_nodes_to_layer(struct ice_port_info *pi, 1122 struct ice_sched_node *tc_node, 1123 struct ice_sched_node *parent, u8 layer, 1124 u16 num_nodes, u32 *first_node_teid, 1125 u16 *num_nodes_added) 1126 { 1127 u32 *first_teid_ptr = first_node_teid; 1128 u16 new_num_nodes = num_nodes; 1129 enum ice_status status = ICE_SUCCESS; 1130 1131 *num_nodes_added = 0; 1132 while (*num_nodes_added < num_nodes) { 1133 u16 max_child_nodes, num_added = 0; 1134 u32 temp; 1135 1136 status = ice_sched_add_nodes_to_hw_layer(pi, tc_node, parent, 1137 layer, new_num_nodes, 1138 first_teid_ptr, 1139 &num_added); 1140 if (status == ICE_SUCCESS) 1141 *num_nodes_added += num_added; 1142 /* added more nodes than requested ? */ 1143 if (*num_nodes_added > num_nodes) { 1144 ice_debug(pi->hw, ICE_DBG_SCHED, "added extra nodes %d %d\n", num_nodes, 1145 *num_nodes_added); 1146 status = ICE_ERR_CFG; 1147 break; 1148 } 1149 /* break if all the nodes are added successfully */ 1150 if (status == ICE_SUCCESS && (*num_nodes_added == num_nodes)) 1151 break; 1152 /* break if the error is not max limit */ 1153 if (status != ICE_SUCCESS && status != ICE_ERR_MAX_LIMIT) 1154 break; 1155 /* Exceeded the max children */ 1156 max_child_nodes = pi->hw->max_children[parent->tx_sched_layer]; 1157 /* utilize all the spaces if the parent is not full */ 1158 if (parent->num_children < max_child_nodes) { 1159 new_num_nodes = max_child_nodes - parent->num_children; 1160 } else { 1161 /* This parent is full, try the next sibling */ 1162 parent = parent->sibling; 1163 /* Don't modify the first node TEID memory if the 1164 * first node was added already in the above call. 1165 * Instead send some temp memory for all other 1166 * recursive calls. 1167 */ 1168 if (num_added) 1169 first_teid_ptr = &temp; 1170 1171 new_num_nodes = num_nodes - *num_nodes_added; 1172 } 1173 } 1174 return status; 1175 } 1176 1177 /** 1178 * ice_sched_get_qgrp_layer - get the current queue group layer number 1179 * @hw: pointer to the HW struct 1180 * 1181 * This function returns the current queue group layer number 1182 */ 1183 static u8 ice_sched_get_qgrp_layer(struct ice_hw *hw) 1184 { 1185 /* It's always total layers - 1, the array is 0 relative so -2 */ 1186 return hw->num_tx_sched_layers - ICE_QGRP_LAYER_OFFSET; 1187 } 1188 1189 /** 1190 * ice_sched_get_vsi_layer - get the current VSI layer number 1191 * @hw: pointer to the HW struct 1192 * 1193 * This function returns the current VSI layer number 1194 */ 1195 static u8 ice_sched_get_vsi_layer(struct ice_hw *hw) 1196 { 1197 /* Num Layers VSI layer 1198 * 9 6 1199 * 7 4 1200 * 5 or less sw_entry_point_layer 1201 */ 1202 /* calculate the VSI layer based on number of layers. */ 1203 if (hw->num_tx_sched_layers == ICE_SCHED_9_LAYERS) 1204 return hw->num_tx_sched_layers - ICE_VSI_LAYER_OFFSET; 1205 else if (hw->num_tx_sched_layers == ICE_SCHED_5_LAYERS) 1206 /* qgroup and VSI layers are same */ 1207 return hw->num_tx_sched_layers - ICE_QGRP_LAYER_OFFSET; 1208 return hw->sw_entry_point_layer; 1209 } 1210 1211 /** 1212 * ice_sched_get_agg_layer - get the current aggregator layer number 1213 * @hw: pointer to the HW struct 1214 * 1215 * This function returns the current aggregator layer number 1216 */ 1217 static u8 ice_sched_get_agg_layer(struct ice_hw *hw) 1218 { 1219 /* Num Layers aggregator layer 1220 * 9 4 1221 * 7 or less sw_entry_point_layer 1222 */ 1223 /* calculate the aggregator layer based on number of layers. */ 1224 if (hw->num_tx_sched_layers == ICE_SCHED_9_LAYERS) 1225 return hw->num_tx_sched_layers - ICE_AGG_LAYER_OFFSET; 1226 return hw->sw_entry_point_layer; 1227 } 1228 1229 /** 1230 * ice_rm_dflt_leaf_node - remove the default leaf node in the tree 1231 * @pi: port information structure 1232 * 1233 * This function removes the leaf node that was created by the FW 1234 * during initialization 1235 */ 1236 static void ice_rm_dflt_leaf_node(struct ice_port_info *pi) 1237 { 1238 struct ice_sched_node *node; 1239 1240 node = pi->root; 1241 while (node) { 1242 if (!node->num_children) 1243 break; 1244 node = node->children[0]; 1245 } 1246 if (node && node->info.data.elem_type == ICE_AQC_ELEM_TYPE_LEAF) { 1247 u32 teid = LE32_TO_CPU(node->info.node_teid); 1248 enum ice_status status; 1249 1250 /* remove the default leaf node */ 1251 status = ice_sched_remove_elems(pi->hw, node->parent, 1, &teid); 1252 if (!status) 1253 ice_free_sched_node(pi, node); 1254 } 1255 } 1256 1257 /** 1258 * ice_sched_rm_dflt_nodes - free the default nodes in the tree 1259 * @pi: port information structure 1260 * 1261 * This function frees all the nodes except root and TC that were created by 1262 * the FW during initialization 1263 */ 1264 static void ice_sched_rm_dflt_nodes(struct ice_port_info *pi) 1265 { 1266 struct ice_sched_node *node; 1267 1268 ice_rm_dflt_leaf_node(pi); 1269 1270 /* remove the default nodes except TC and root nodes */ 1271 node = pi->root; 1272 while (node) { 1273 if (node->tx_sched_layer >= pi->hw->sw_entry_point_layer && 1274 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_TC && 1275 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_ROOT_PORT) { 1276 ice_free_sched_node(pi, node); 1277 break; 1278 } 1279 1280 if (!node->num_children) 1281 break; 1282 node = node->children[0]; 1283 } 1284 } 1285 1286 /** 1287 * ice_sched_init_port - Initialize scheduler by querying information from FW 1288 * @pi: port info structure for the tree to cleanup 1289 * 1290 * This function is the initial call to find the total number of Tx scheduler 1291 * resources, default topology created by firmware and storing the information 1292 * in SW DB. 1293 */ 1294 enum ice_status ice_sched_init_port(struct ice_port_info *pi) 1295 { 1296 struct ice_aqc_get_topo_elem *buf; 1297 enum ice_status status; 1298 struct ice_hw *hw; 1299 u8 num_branches; 1300 u16 num_elems; 1301 u8 i, j; 1302 1303 if (!pi) 1304 return ICE_ERR_PARAM; 1305 hw = pi->hw; 1306 1307 /* Query the Default Topology from FW */ 1308 buf = (struct ice_aqc_get_topo_elem *)ice_malloc(hw, 1309 ICE_AQ_MAX_BUF_LEN); 1310 if (!buf) 1311 return ICE_ERR_NO_MEMORY; 1312 1313 /* Query default scheduling tree topology */ 1314 status = ice_aq_get_dflt_topo(hw, pi->lport, buf, ICE_AQ_MAX_BUF_LEN, 1315 &num_branches, NULL); 1316 if (status) 1317 goto err_init_port; 1318 1319 /* num_branches should be between 1-8 */ 1320 if (num_branches < 1 || num_branches > ICE_TXSCHED_MAX_BRANCHES) { 1321 ice_debug(hw, ICE_DBG_SCHED, "num_branches unexpected %d\n", 1322 num_branches); 1323 status = ICE_ERR_PARAM; 1324 goto err_init_port; 1325 } 1326 1327 /* get the number of elements on the default/first branch */ 1328 num_elems = LE16_TO_CPU(buf[0].hdr.num_elems); 1329 1330 /* num_elems should always be between 1-9 */ 1331 if (num_elems < 1 || num_elems > ICE_AQC_TOPO_MAX_LEVEL_NUM) { 1332 ice_debug(hw, ICE_DBG_SCHED, "num_elems unexpected %d\n", 1333 num_elems); 1334 status = ICE_ERR_PARAM; 1335 goto err_init_port; 1336 } 1337 1338 /* If the last node is a leaf node then the index of the queue group 1339 * layer is two less than the number of elements. 1340 */ 1341 if (num_elems > 2 && buf[0].generic[num_elems - 1].data.elem_type == 1342 ICE_AQC_ELEM_TYPE_LEAF) 1343 pi->last_node_teid = 1344 LE32_TO_CPU(buf[0].generic[num_elems - 2].node_teid); 1345 else 1346 pi->last_node_teid = 1347 LE32_TO_CPU(buf[0].generic[num_elems - 1].node_teid); 1348 1349 /* Insert the Tx Sched root node */ 1350 status = ice_sched_add_root_node(pi, &buf[0].generic[0]); 1351 if (status) 1352 goto err_init_port; 1353 1354 /* Parse the default tree and cache the information */ 1355 for (i = 0; i < num_branches; i++) { 1356 num_elems = LE16_TO_CPU(buf[i].hdr.num_elems); 1357 1358 /* Skip root element as already inserted */ 1359 for (j = 1; j < num_elems; j++) { 1360 /* update the sw entry point */ 1361 if (buf[0].generic[j].data.elem_type == 1362 ICE_AQC_ELEM_TYPE_ENTRY_POINT) 1363 hw->sw_entry_point_layer = j; 1364 1365 status = ice_sched_add_node(pi, j, &buf[i].generic[j]); 1366 if (status) 1367 goto err_init_port; 1368 } 1369 } 1370 1371 /* Remove the default nodes. */ 1372 if (pi->root) 1373 ice_sched_rm_dflt_nodes(pi); 1374 1375 /* initialize the port for handling the scheduler tree */ 1376 pi->port_state = ICE_SCHED_PORT_STATE_READY; 1377 ice_init_lock(&pi->sched_lock); 1378 for (i = 0; i < ICE_AQC_TOPO_MAX_LEVEL_NUM; i++) 1379 INIT_LIST_HEAD(&hw->rl_prof_list[i]); 1380 1381 err_init_port: 1382 if (status && pi->root) { 1383 ice_free_sched_node(pi, pi->root); 1384 pi->root = NULL; 1385 } 1386 1387 ice_free(hw, buf); 1388 return status; 1389 } 1390 1391 /** 1392 * ice_sched_get_node - Get the struct ice_sched_node for given TEID 1393 * @pi: port information structure 1394 * @teid: Scheduler node TEID 1395 * 1396 * This function retrieves the ice_sched_node struct for given TEID from 1397 * the SW DB and returns it to the caller. 1398 */ 1399 struct ice_sched_node *ice_sched_get_node(struct ice_port_info *pi, u32 teid) 1400 { 1401 struct ice_sched_node *node; 1402 1403 if (!pi) 1404 return NULL; 1405 1406 /* Find the node starting from root */ 1407 ice_acquire_lock(&pi->sched_lock); 1408 node = ice_sched_find_node_by_teid(pi->root, teid); 1409 ice_release_lock(&pi->sched_lock); 1410 1411 if (!node) 1412 ice_debug(pi->hw, ICE_DBG_SCHED, "Node not found for teid=0x%x\n", teid); 1413 1414 return node; 1415 } 1416 1417 /** 1418 * ice_sched_query_res_alloc - query the FW for num of logical sched layers 1419 * @hw: pointer to the HW struct 1420 * 1421 * query FW for allocated scheduler resources and store in HW struct 1422 */ 1423 enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw) 1424 { 1425 struct ice_aqc_query_txsched_res_resp *buf; 1426 enum ice_status status = ICE_SUCCESS; 1427 __le16 max_sibl; 1428 u8 i; 1429 1430 if (hw->layer_info) 1431 return status; 1432 1433 buf = (struct ice_aqc_query_txsched_res_resp *) 1434 ice_malloc(hw, sizeof(*buf)); 1435 if (!buf) 1436 return ICE_ERR_NO_MEMORY; 1437 1438 status = ice_aq_query_sched_res(hw, sizeof(*buf), buf, NULL); 1439 if (status) 1440 goto sched_query_out; 1441 1442 hw->num_tx_sched_layers = 1443 (u8)LE16_TO_CPU(buf->sched_props.logical_levels); 1444 hw->num_tx_sched_phys_layers = 1445 (u8)LE16_TO_CPU(buf->sched_props.phys_levels); 1446 hw->flattened_layers = buf->sched_props.flattening_bitmap; 1447 hw->max_cgds = buf->sched_props.max_pf_cgds; 1448 1449 /* max sibling group size of current layer refers to the max children 1450 * of the below layer node. 1451 * layer 1 node max children will be layer 2 max sibling group size 1452 * layer 2 node max children will be layer 3 max sibling group size 1453 * and so on. This array will be populated from root (index 0) to 1454 * qgroup layer 7. Leaf node has no children. 1455 */ 1456 for (i = 0; i < hw->num_tx_sched_layers - 1; i++) { 1457 max_sibl = buf->layer_props[i + 1].max_sibl_grp_sz; 1458 hw->max_children[i] = LE16_TO_CPU(max_sibl); 1459 } 1460 1461 hw->layer_info = (struct ice_aqc_layer_props *) 1462 ice_memdup(hw, buf->layer_props, 1463 (hw->num_tx_sched_layers * 1464 sizeof(*hw->layer_info)), 1465 ICE_NONDMA_TO_NONDMA); 1466 if (!hw->layer_info) { 1467 status = ICE_ERR_NO_MEMORY; 1468 goto sched_query_out; 1469 } 1470 1471 sched_query_out: 1472 ice_free(hw, buf); 1473 return status; 1474 } 1475 1476 /** 1477 * ice_sched_get_psm_clk_freq - determine the PSM clock frequency 1478 * @hw: pointer to the HW struct 1479 * 1480 * Determine the PSM clock frequency and store in HW struct 1481 */ 1482 void ice_sched_get_psm_clk_freq(struct ice_hw *hw) 1483 { 1484 u32 val, clk_src; 1485 1486 val = rd32(hw, GLGEN_CLKSTAT_SRC); 1487 clk_src = (val & GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M) >> 1488 GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_S; 1489 1490 #define PSM_CLK_SRC_367_MHZ 0x0 1491 #define PSM_CLK_SRC_416_MHZ 0x1 1492 #define PSM_CLK_SRC_446_MHZ 0x2 1493 #define PSM_CLK_SRC_390_MHZ 0x3 1494 1495 switch (clk_src) { 1496 case PSM_CLK_SRC_367_MHZ: 1497 hw->psm_clk_freq = ICE_PSM_CLK_367MHZ_IN_HZ; 1498 break; 1499 case PSM_CLK_SRC_416_MHZ: 1500 hw->psm_clk_freq = ICE_PSM_CLK_416MHZ_IN_HZ; 1501 break; 1502 case PSM_CLK_SRC_446_MHZ: 1503 hw->psm_clk_freq = ICE_PSM_CLK_446MHZ_IN_HZ; 1504 break; 1505 case PSM_CLK_SRC_390_MHZ: 1506 hw->psm_clk_freq = ICE_PSM_CLK_390MHZ_IN_HZ; 1507 break; 1508 default: 1509 ice_debug(hw, ICE_DBG_SCHED, "PSM clk_src unexpected %u\n", 1510 clk_src); 1511 /* fall back to a safe default */ 1512 hw->psm_clk_freq = ICE_PSM_CLK_446MHZ_IN_HZ; 1513 } 1514 } 1515 1516 /** 1517 * ice_sched_find_node_in_subtree - Find node in part of base node subtree 1518 * @hw: pointer to the HW struct 1519 * @base: pointer to the base node 1520 * @node: pointer to the node to search 1521 * 1522 * This function checks whether a given node is part of the base node 1523 * subtree or not 1524 */ 1525 bool 1526 ice_sched_find_node_in_subtree(struct ice_hw *hw, struct ice_sched_node *base, 1527 struct ice_sched_node *node) 1528 { 1529 u8 i; 1530 1531 for (i = 0; i < base->num_children; i++) { 1532 struct ice_sched_node *child = base->children[i]; 1533 1534 if (node == child) 1535 return true; 1536 1537 if (child->tx_sched_layer > node->tx_sched_layer) 1538 return false; 1539 1540 /* this recursion is intentional, and wouldn't 1541 * go more than 8 calls 1542 */ 1543 if (ice_sched_find_node_in_subtree(hw, child, node)) 1544 return true; 1545 } 1546 return false; 1547 } 1548 1549 /** 1550 * ice_sched_get_free_qgrp - Scan all queue group siblings and find a free node 1551 * @pi: port information structure 1552 * @vsi_node: software VSI handle 1553 * @qgrp_node: first queue group node identified for scanning 1554 * @owner: LAN or RDMA 1555 * 1556 * This function retrieves a free LAN or RDMA queue group node by scanning 1557 * qgrp_node and its siblings for the queue group with the fewest number 1558 * of queues currently assigned. 1559 */ 1560 static struct ice_sched_node * 1561 ice_sched_get_free_qgrp(struct ice_port_info *pi, 1562 struct ice_sched_node *vsi_node, 1563 struct ice_sched_node *qgrp_node, u8 owner) 1564 { 1565 struct ice_sched_node *min_qgrp; 1566 u8 min_children; 1567 1568 if (!qgrp_node) 1569 return qgrp_node; 1570 min_children = qgrp_node->num_children; 1571 if (!min_children) 1572 return qgrp_node; 1573 min_qgrp = qgrp_node; 1574 /* scan all queue groups until find a node which has less than the 1575 * minimum number of children. This way all queue group nodes get 1576 * equal number of shares and active. The bandwidth will be equally 1577 * distributed across all queues. 1578 */ 1579 while (qgrp_node) { 1580 /* make sure the qgroup node is part of the VSI subtree */ 1581 if (ice_sched_find_node_in_subtree(pi->hw, vsi_node, qgrp_node)) 1582 if (qgrp_node->num_children < min_children && 1583 qgrp_node->owner == owner) { 1584 /* replace the new min queue group node */ 1585 min_qgrp = qgrp_node; 1586 min_children = min_qgrp->num_children; 1587 /* break if it has no children, */ 1588 if (!min_children) 1589 break; 1590 } 1591 qgrp_node = qgrp_node->sibling; 1592 } 1593 return min_qgrp; 1594 } 1595 1596 /** 1597 * ice_sched_get_free_qparent - Get a free LAN or RDMA queue group node 1598 * @pi: port information structure 1599 * @vsi_handle: software VSI handle 1600 * @tc: branch number 1601 * @owner: LAN or RDMA 1602 * 1603 * This function retrieves a free LAN or RDMA queue group node 1604 */ 1605 struct ice_sched_node * 1606 ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 1607 u8 owner) 1608 { 1609 struct ice_sched_node *vsi_node, *qgrp_node; 1610 struct ice_vsi_ctx *vsi_ctx; 1611 u8 qgrp_layer, vsi_layer; 1612 u16 max_children; 1613 1614 qgrp_layer = ice_sched_get_qgrp_layer(pi->hw); 1615 vsi_layer = ice_sched_get_vsi_layer(pi->hw); 1616 max_children = pi->hw->max_children[qgrp_layer]; 1617 1618 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 1619 if (!vsi_ctx) 1620 return NULL; 1621 vsi_node = vsi_ctx->sched.vsi_node[tc]; 1622 /* validate invalid VSI ID */ 1623 if (!vsi_node) 1624 return NULL; 1625 1626 /* If the queue group and vsi layer are same then queues 1627 * are all attached directly to VSI 1628 */ 1629 if (qgrp_layer == vsi_layer) 1630 return vsi_node; 1631 1632 /* get the first queue group node from VSI sub-tree */ 1633 qgrp_node = ice_sched_get_first_node(pi, vsi_node, qgrp_layer); 1634 while (qgrp_node) { 1635 /* make sure the qgroup node is part of the VSI subtree */ 1636 if (ice_sched_find_node_in_subtree(pi->hw, vsi_node, qgrp_node)) 1637 if (qgrp_node->num_children < max_children && 1638 qgrp_node->owner == owner) 1639 break; 1640 qgrp_node = qgrp_node->sibling; 1641 } 1642 1643 /* Select the best queue group */ 1644 return ice_sched_get_free_qgrp(pi, vsi_node, qgrp_node, owner); 1645 } 1646 1647 /** 1648 * ice_sched_get_vsi_node - Get a VSI node based on VSI ID 1649 * @pi: pointer to the port information structure 1650 * @tc_node: pointer to the TC node 1651 * @vsi_handle: software VSI handle 1652 * 1653 * This function retrieves a VSI node for a given VSI ID from a given 1654 * TC branch 1655 */ 1656 struct ice_sched_node * 1657 ice_sched_get_vsi_node(struct ice_port_info *pi, struct ice_sched_node *tc_node, 1658 u16 vsi_handle) 1659 { 1660 struct ice_sched_node *node; 1661 u8 vsi_layer; 1662 1663 vsi_layer = ice_sched_get_vsi_layer(pi->hw); 1664 node = ice_sched_get_first_node(pi, tc_node, vsi_layer); 1665 1666 /* Check whether it already exists */ 1667 while (node) { 1668 if (node->vsi_handle == vsi_handle) 1669 return node; 1670 node = node->sibling; 1671 } 1672 1673 return node; 1674 } 1675 1676 /** 1677 * ice_sched_get_agg_node - Get an aggregator node based on aggregator ID 1678 * @pi: pointer to the port information structure 1679 * @tc_node: pointer to the TC node 1680 * @agg_id: aggregator ID 1681 * 1682 * This function retrieves an aggregator node for a given aggregator ID from 1683 * a given TC branch 1684 */ 1685 static struct ice_sched_node * 1686 ice_sched_get_agg_node(struct ice_port_info *pi, struct ice_sched_node *tc_node, 1687 u32 agg_id) 1688 { 1689 struct ice_sched_node *node; 1690 struct ice_hw *hw = pi->hw; 1691 u8 agg_layer; 1692 1693 if (!hw) 1694 return NULL; 1695 agg_layer = ice_sched_get_agg_layer(hw); 1696 node = ice_sched_get_first_node(pi, tc_node, agg_layer); 1697 1698 /* Check whether it already exists */ 1699 while (node) { 1700 if (node->agg_id == agg_id) 1701 return node; 1702 node = node->sibling; 1703 } 1704 1705 return node; 1706 } 1707 1708 /** 1709 * ice_sched_check_node - Compare node parameters between SW DB and HW DB 1710 * @hw: pointer to the HW struct 1711 * @node: pointer to the ice_sched_node struct 1712 * 1713 * This function queries and compares the HW element with SW DB node parameters 1714 */ 1715 static bool ice_sched_check_node(struct ice_hw *hw, struct ice_sched_node *node) 1716 { 1717 struct ice_aqc_txsched_elem_data buf; 1718 enum ice_status status; 1719 u32 node_teid; 1720 1721 node_teid = LE32_TO_CPU(node->info.node_teid); 1722 status = ice_sched_query_elem(hw, node_teid, &buf); 1723 if (status != ICE_SUCCESS) 1724 return false; 1725 1726 if (memcmp(&buf, &node->info, sizeof(buf))) { 1727 ice_debug(hw, ICE_DBG_SCHED, "Node mismatch for teid=0x%x\n", 1728 node_teid); 1729 return false; 1730 } 1731 1732 return true; 1733 } 1734 1735 /** 1736 * ice_sched_calc_vsi_child_nodes - calculate number of VSI child nodes 1737 * @hw: pointer to the HW struct 1738 * @num_qs: number of queues 1739 * @num_nodes: num nodes array 1740 * 1741 * This function calculates the number of VSI child nodes based on the 1742 * number of queues. 1743 */ 1744 static void 1745 ice_sched_calc_vsi_child_nodes(struct ice_hw *hw, u16 num_qs, u16 *num_nodes) 1746 { 1747 u16 num = num_qs; 1748 u8 i, qgl, vsil; 1749 1750 qgl = ice_sched_get_qgrp_layer(hw); 1751 vsil = ice_sched_get_vsi_layer(hw); 1752 1753 /* calculate num nodes from queue group to VSI layer */ 1754 for (i = qgl; i > vsil; i--) { 1755 /* round to the next integer if there is a remainder */ 1756 num = DIVIDE_AND_ROUND_UP(num, hw->max_children[i]); 1757 1758 /* need at least one node */ 1759 num_nodes[i] = num ? num : 1; 1760 } 1761 } 1762 1763 /** 1764 * ice_sched_add_vsi_child_nodes - add VSI child nodes to tree 1765 * @pi: port information structure 1766 * @vsi_handle: software VSI handle 1767 * @tc_node: pointer to the TC node 1768 * @num_nodes: pointer to the num nodes that needs to be added per layer 1769 * @owner: node owner (LAN or RDMA) 1770 * 1771 * This function adds the VSI child nodes to tree. It gets called for 1772 * LAN and RDMA separately. 1773 */ 1774 static enum ice_status 1775 ice_sched_add_vsi_child_nodes(struct ice_port_info *pi, u16 vsi_handle, 1776 struct ice_sched_node *tc_node, u16 *num_nodes, 1777 u8 owner) 1778 { 1779 struct ice_sched_node *parent, *node; 1780 struct ice_hw *hw = pi->hw; 1781 u32 first_node_teid; 1782 u16 num_added = 0; 1783 u8 i, qgl, vsil; 1784 1785 qgl = ice_sched_get_qgrp_layer(hw); 1786 vsil = ice_sched_get_vsi_layer(hw); 1787 parent = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 1788 for (i = vsil + 1; i <= qgl; i++) { 1789 enum ice_status status; 1790 1791 if (!parent) 1792 return ICE_ERR_CFG; 1793 1794 status = ice_sched_add_nodes_to_layer(pi, tc_node, parent, i, 1795 num_nodes[i], 1796 &first_node_teid, 1797 &num_added); 1798 if (status != ICE_SUCCESS || num_nodes[i] != num_added) 1799 return ICE_ERR_CFG; 1800 1801 /* The newly added node can be a new parent for the next 1802 * layer nodes 1803 */ 1804 if (num_added) { 1805 parent = ice_sched_find_node_by_teid(tc_node, 1806 first_node_teid); 1807 node = parent; 1808 while (node) { 1809 node->owner = owner; 1810 node = node->sibling; 1811 } 1812 } else { 1813 parent = parent->children[0]; 1814 } 1815 } 1816 1817 return ICE_SUCCESS; 1818 } 1819 1820 /** 1821 * ice_sched_calc_vsi_support_nodes - calculate number of VSI support nodes 1822 * @pi: pointer to the port info structure 1823 * @tc_node: pointer to TC node 1824 * @num_nodes: pointer to num nodes array 1825 * 1826 * This function calculates the number of supported nodes needed to add this 1827 * VSI into Tx tree including the VSI, parent and intermediate nodes in below 1828 * layers 1829 */ 1830 static void 1831 ice_sched_calc_vsi_support_nodes(struct ice_port_info *pi, 1832 struct ice_sched_node *tc_node, u16 *num_nodes) 1833 { 1834 struct ice_sched_node *node; 1835 u8 vsil; 1836 int i; 1837 1838 vsil = ice_sched_get_vsi_layer(pi->hw); 1839 for (i = vsil; i >= pi->hw->sw_entry_point_layer; i--) 1840 /* Add intermediate nodes if TC has no children and 1841 * need at least one node for VSI 1842 */ 1843 if (!tc_node->num_children || i == vsil) { 1844 num_nodes[i]++; 1845 } else { 1846 /* If intermediate nodes are reached max children 1847 * then add a new one. 1848 */ 1849 node = ice_sched_get_first_node(pi, tc_node, (u8)i); 1850 /* scan all the siblings */ 1851 while (node) { 1852 if (node->num_children < 1853 pi->hw->max_children[i]) 1854 break; 1855 node = node->sibling; 1856 } 1857 1858 /* tree has one intermediate node to add this new VSI. 1859 * So no need to calculate supported nodes for below 1860 * layers. 1861 */ 1862 if (node) 1863 break; 1864 /* all the nodes are full, allocate a new one */ 1865 num_nodes[i]++; 1866 } 1867 } 1868 1869 /** 1870 * ice_sched_add_vsi_support_nodes - add VSI supported nodes into Tx tree 1871 * @pi: port information structure 1872 * @vsi_handle: software VSI handle 1873 * @tc_node: pointer to TC node 1874 * @num_nodes: pointer to num nodes array 1875 * 1876 * This function adds the VSI supported nodes into Tx tree including the 1877 * VSI, its parent and intermediate nodes in below layers 1878 */ 1879 static enum ice_status 1880 ice_sched_add_vsi_support_nodes(struct ice_port_info *pi, u16 vsi_handle, 1881 struct ice_sched_node *tc_node, u16 *num_nodes) 1882 { 1883 struct ice_sched_node *parent = tc_node; 1884 u32 first_node_teid; 1885 u16 num_added = 0; 1886 u8 i, vsil; 1887 1888 if (!pi) 1889 return ICE_ERR_PARAM; 1890 1891 vsil = ice_sched_get_vsi_layer(pi->hw); 1892 for (i = pi->hw->sw_entry_point_layer; i <= vsil; i++) { 1893 enum ice_status status; 1894 1895 status = ice_sched_add_nodes_to_layer(pi, tc_node, parent, 1896 i, num_nodes[i], 1897 &first_node_teid, 1898 &num_added); 1899 if (status != ICE_SUCCESS || num_nodes[i] != num_added) 1900 return ICE_ERR_CFG; 1901 1902 /* The newly added node can be a new parent for the next 1903 * layer nodes 1904 */ 1905 if (num_added) 1906 parent = ice_sched_find_node_by_teid(tc_node, 1907 first_node_teid); 1908 else 1909 parent = parent->children[0]; 1910 1911 if (!parent) 1912 return ICE_ERR_CFG; 1913 1914 if (i == vsil) 1915 parent->vsi_handle = vsi_handle; 1916 } 1917 1918 return ICE_SUCCESS; 1919 } 1920 1921 /** 1922 * ice_sched_add_vsi_to_topo - add a new VSI into tree 1923 * @pi: port information structure 1924 * @vsi_handle: software VSI handle 1925 * @tc: TC number 1926 * 1927 * This function adds a new VSI into scheduler tree 1928 */ 1929 static enum ice_status 1930 ice_sched_add_vsi_to_topo(struct ice_port_info *pi, u16 vsi_handle, u8 tc) 1931 { 1932 u16 num_nodes[ICE_AQC_TOPO_MAX_LEVEL_NUM] = { 0 }; 1933 struct ice_sched_node *tc_node; 1934 1935 tc_node = ice_sched_get_tc_node(pi, tc); 1936 if (!tc_node) 1937 return ICE_ERR_PARAM; 1938 1939 /* calculate number of supported nodes needed for this VSI */ 1940 ice_sched_calc_vsi_support_nodes(pi, tc_node, num_nodes); 1941 1942 /* add VSI supported nodes to TC subtree */ 1943 return ice_sched_add_vsi_support_nodes(pi, vsi_handle, tc_node, 1944 num_nodes); 1945 } 1946 1947 /** 1948 * ice_sched_update_vsi_child_nodes - update VSI child nodes 1949 * @pi: port information structure 1950 * @vsi_handle: software VSI handle 1951 * @tc: TC number 1952 * @new_numqs: new number of max queues 1953 * @owner: owner of this subtree 1954 * 1955 * This function updates the VSI child nodes based on the number of queues 1956 */ 1957 static enum ice_status 1958 ice_sched_update_vsi_child_nodes(struct ice_port_info *pi, u16 vsi_handle, 1959 u8 tc, u16 new_numqs, u8 owner) 1960 { 1961 u16 new_num_nodes[ICE_AQC_TOPO_MAX_LEVEL_NUM] = { 0 }; 1962 struct ice_sched_node *vsi_node; 1963 struct ice_sched_node *tc_node; 1964 struct ice_vsi_ctx *vsi_ctx; 1965 enum ice_status status = ICE_SUCCESS; 1966 struct ice_hw *hw = pi->hw; 1967 u16 prev_numqs; 1968 1969 tc_node = ice_sched_get_tc_node(pi, tc); 1970 if (!tc_node) 1971 return ICE_ERR_CFG; 1972 1973 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 1974 if (!vsi_node) 1975 return ICE_ERR_CFG; 1976 1977 vsi_ctx = ice_get_vsi_ctx(hw, vsi_handle); 1978 if (!vsi_ctx) 1979 return ICE_ERR_PARAM; 1980 1981 if (owner == ICE_SCHED_NODE_OWNER_LAN) 1982 prev_numqs = vsi_ctx->sched.max_lanq[tc]; 1983 else 1984 prev_numqs = vsi_ctx->sched.max_rdmaq[tc]; 1985 /* num queues are not changed or less than the previous number */ 1986 if (new_numqs <= prev_numqs) 1987 return status; 1988 if (owner == ICE_SCHED_NODE_OWNER_LAN) { 1989 status = ice_alloc_lan_q_ctx(hw, vsi_handle, tc, new_numqs); 1990 if (status) 1991 return status; 1992 } else { 1993 status = ice_alloc_rdma_q_ctx(hw, vsi_handle, tc, new_numqs); 1994 if (status) 1995 return status; 1996 } 1997 1998 if (new_numqs) 1999 ice_sched_calc_vsi_child_nodes(hw, new_numqs, new_num_nodes); 2000 /* Keep the max number of queue configuration all the time. Update the 2001 * tree only if number of queues > previous number of queues. This may 2002 * leave some extra nodes in the tree if number of queues < previous 2003 * number but that wouldn't harm anything. Removing those extra nodes 2004 * may complicate the code if those nodes are part of SRL or 2005 * individually rate limited. 2006 */ 2007 status = ice_sched_add_vsi_child_nodes(pi, vsi_handle, tc_node, 2008 new_num_nodes, owner); 2009 if (status) 2010 return status; 2011 if (owner == ICE_SCHED_NODE_OWNER_LAN) 2012 vsi_ctx->sched.max_lanq[tc] = new_numqs; 2013 else 2014 vsi_ctx->sched.max_rdmaq[tc] = new_numqs; 2015 2016 return ICE_SUCCESS; 2017 } 2018 2019 /** 2020 * ice_sched_cfg_vsi - configure the new/existing VSI 2021 * @pi: port information structure 2022 * @vsi_handle: software VSI handle 2023 * @tc: TC number 2024 * @maxqs: max number of queues 2025 * @owner: LAN or RDMA 2026 * @enable: TC enabled or disabled 2027 * 2028 * This function adds/updates VSI nodes based on the number of queues. If TC is 2029 * enabled and VSI is in suspended state then resume the VSI back. If TC is 2030 * disabled then suspend the VSI if it is not already. 2031 */ 2032 enum ice_status 2033 ice_sched_cfg_vsi(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 maxqs, 2034 u8 owner, bool enable) 2035 { 2036 struct ice_sched_node *vsi_node, *tc_node; 2037 struct ice_vsi_ctx *vsi_ctx; 2038 enum ice_status status = ICE_SUCCESS; 2039 struct ice_hw *hw = pi->hw; 2040 2041 ice_debug(pi->hw, ICE_DBG_SCHED, "add/config VSI %d\n", vsi_handle); 2042 tc_node = ice_sched_get_tc_node(pi, tc); 2043 if (!tc_node) 2044 return ICE_ERR_PARAM; 2045 vsi_ctx = ice_get_vsi_ctx(hw, vsi_handle); 2046 if (!vsi_ctx) 2047 return ICE_ERR_PARAM; 2048 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 2049 2050 /* suspend the VSI if TC is not enabled */ 2051 if (!enable) { 2052 if (vsi_node && vsi_node->in_use) { 2053 u32 teid = LE32_TO_CPU(vsi_node->info.node_teid); 2054 2055 status = ice_sched_suspend_resume_elems(hw, 1, &teid, 2056 true); 2057 if (!status) 2058 vsi_node->in_use = false; 2059 } 2060 return status; 2061 } 2062 2063 /* TC is enabled, if it is a new VSI then add it to the tree */ 2064 if (!vsi_node) { 2065 status = ice_sched_add_vsi_to_topo(pi, vsi_handle, tc); 2066 if (status) 2067 return status; 2068 2069 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 2070 if (!vsi_node) 2071 return ICE_ERR_CFG; 2072 2073 vsi_ctx->sched.vsi_node[tc] = vsi_node; 2074 vsi_node->in_use = true; 2075 /* invalidate the max queues whenever VSI gets added first time 2076 * into the scheduler tree (boot or after reset). We need to 2077 * recreate the child nodes all the time in these cases. 2078 */ 2079 vsi_ctx->sched.max_lanq[tc] = 0; 2080 vsi_ctx->sched.max_rdmaq[tc] = 0; 2081 } 2082 2083 /* update the VSI child nodes */ 2084 status = ice_sched_update_vsi_child_nodes(pi, vsi_handle, tc, maxqs, 2085 owner); 2086 if (status) 2087 return status; 2088 2089 /* TC is enabled, resume the VSI if it is in the suspend state */ 2090 if (!vsi_node->in_use) { 2091 u32 teid = LE32_TO_CPU(vsi_node->info.node_teid); 2092 2093 status = ice_sched_suspend_resume_elems(hw, 1, &teid, false); 2094 if (!status) 2095 vsi_node->in_use = true; 2096 } 2097 2098 return status; 2099 } 2100 2101 /** 2102 * ice_sched_rm_agg_vsi_info - remove aggregator related VSI info entry 2103 * @pi: port information structure 2104 * @vsi_handle: software VSI handle 2105 * 2106 * This function removes single aggregator VSI info entry from 2107 * aggregator list. 2108 */ 2109 static void ice_sched_rm_agg_vsi_info(struct ice_port_info *pi, u16 vsi_handle) 2110 { 2111 struct ice_sched_agg_info *agg_info; 2112 struct ice_sched_agg_info *atmp; 2113 2114 LIST_FOR_EACH_ENTRY_SAFE(agg_info, atmp, &pi->hw->agg_list, 2115 ice_sched_agg_info, 2116 list_entry) { 2117 struct ice_sched_agg_vsi_info *agg_vsi_info; 2118 struct ice_sched_agg_vsi_info *vtmp; 2119 2120 LIST_FOR_EACH_ENTRY_SAFE(agg_vsi_info, vtmp, 2121 &agg_info->agg_vsi_list, 2122 ice_sched_agg_vsi_info, list_entry) 2123 if (agg_vsi_info->vsi_handle == vsi_handle) { 2124 LIST_DEL(&agg_vsi_info->list_entry); 2125 ice_free(pi->hw, agg_vsi_info); 2126 return; 2127 } 2128 } 2129 } 2130 2131 /** 2132 * ice_sched_is_leaf_node_present - check for a leaf node in the sub-tree 2133 * @node: pointer to the sub-tree node 2134 * 2135 * This function checks for a leaf node presence in a given sub-tree node. 2136 */ 2137 static bool ice_sched_is_leaf_node_present(struct ice_sched_node *node) 2138 { 2139 u8 i; 2140 2141 for (i = 0; i < node->num_children; i++) 2142 if (ice_sched_is_leaf_node_present(node->children[i])) 2143 return true; 2144 /* check for a leaf node */ 2145 return (node->info.data.elem_type == ICE_AQC_ELEM_TYPE_LEAF); 2146 } 2147 2148 /** 2149 * ice_sched_rm_vsi_cfg - remove the VSI and its children nodes 2150 * @pi: port information structure 2151 * @vsi_handle: software VSI handle 2152 * @owner: LAN or RDMA 2153 * 2154 * This function removes the VSI and its LAN or RDMA children nodes from the 2155 * scheduler tree. 2156 */ 2157 static enum ice_status 2158 ice_sched_rm_vsi_cfg(struct ice_port_info *pi, u16 vsi_handle, u8 owner) 2159 { 2160 enum ice_status status = ICE_ERR_PARAM; 2161 struct ice_vsi_ctx *vsi_ctx; 2162 u8 i; 2163 2164 ice_debug(pi->hw, ICE_DBG_SCHED, "removing VSI %d\n", vsi_handle); 2165 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 2166 return status; 2167 ice_acquire_lock(&pi->sched_lock); 2168 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 2169 if (!vsi_ctx) 2170 goto exit_sched_rm_vsi_cfg; 2171 2172 ice_for_each_traffic_class(i) { 2173 struct ice_sched_node *vsi_node, *tc_node; 2174 u8 j = 0; 2175 2176 tc_node = ice_sched_get_tc_node(pi, i); 2177 if (!tc_node) 2178 continue; 2179 2180 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 2181 if (!vsi_node) 2182 continue; 2183 2184 if (ice_sched_is_leaf_node_present(vsi_node)) { 2185 ice_debug(pi->hw, ICE_DBG_SCHED, "VSI has leaf nodes in TC %d\n", i); 2186 status = ICE_ERR_IN_USE; 2187 goto exit_sched_rm_vsi_cfg; 2188 } 2189 while (j < vsi_node->num_children) { 2190 if (vsi_node->children[j]->owner == owner) { 2191 ice_free_sched_node(pi, vsi_node->children[j]); 2192 2193 /* reset the counter again since the num 2194 * children will be updated after node removal 2195 */ 2196 j = 0; 2197 } else { 2198 j++; 2199 } 2200 } 2201 /* remove the VSI if it has no children */ 2202 if (!vsi_node->num_children) { 2203 ice_free_sched_node(pi, vsi_node); 2204 vsi_ctx->sched.vsi_node[i] = NULL; 2205 2206 /* clean up aggregator related VSI info if any */ 2207 ice_sched_rm_agg_vsi_info(pi, vsi_handle); 2208 } 2209 if (owner == ICE_SCHED_NODE_OWNER_LAN) 2210 vsi_ctx->sched.max_lanq[i] = 0; 2211 else 2212 vsi_ctx->sched.max_rdmaq[i] = 0; 2213 } 2214 status = ICE_SUCCESS; 2215 2216 exit_sched_rm_vsi_cfg: 2217 ice_release_lock(&pi->sched_lock); 2218 return status; 2219 } 2220 2221 /** 2222 * ice_rm_vsi_lan_cfg - remove VSI and its LAN children nodes 2223 * @pi: port information structure 2224 * @vsi_handle: software VSI handle 2225 * 2226 * This function clears the VSI and its LAN children nodes from scheduler tree 2227 * for all TCs. 2228 */ 2229 enum ice_status ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle) 2230 { 2231 return ice_sched_rm_vsi_cfg(pi, vsi_handle, ICE_SCHED_NODE_OWNER_LAN); 2232 } 2233 2234 /** 2235 * ice_rm_vsi_rdma_cfg - remove VSI and its RDMA children nodes 2236 * @pi: port information structure 2237 * @vsi_handle: software VSI handle 2238 * 2239 * This function clears the VSI and its RDMA children nodes from scheduler tree 2240 * for all TCs. 2241 */ 2242 enum ice_status ice_rm_vsi_rdma_cfg(struct ice_port_info *pi, u16 vsi_handle) 2243 { 2244 return ice_sched_rm_vsi_cfg(pi, vsi_handle, ICE_SCHED_NODE_OWNER_RDMA); 2245 } 2246 2247 /** 2248 * ice_sched_is_tree_balanced - Check tree nodes are identical or not 2249 * @hw: pointer to the HW struct 2250 * @node: pointer to the ice_sched_node struct 2251 * 2252 * This function compares all the nodes for a given tree against HW DB nodes 2253 * This function needs to be called with the port_info->sched_lock held 2254 */ 2255 bool ice_sched_is_tree_balanced(struct ice_hw *hw, struct ice_sched_node *node) 2256 { 2257 u8 i; 2258 2259 /* start from the leaf node */ 2260 for (i = 0; i < node->num_children; i++) 2261 /* Fail if node doesn't match with the SW DB 2262 * this recursion is intentional, and wouldn't 2263 * go more than 9 calls 2264 */ 2265 if (!ice_sched_is_tree_balanced(hw, node->children[i])) 2266 return false; 2267 2268 return ice_sched_check_node(hw, node); 2269 } 2270 2271 /** 2272 * ice_aq_query_node_to_root - retrieve the tree topology for a given node TEID 2273 * @hw: pointer to the HW struct 2274 * @node_teid: node TEID 2275 * @buf: pointer to buffer 2276 * @buf_size: buffer size in bytes 2277 * @cd: pointer to command details structure or NULL 2278 * 2279 * This function retrieves the tree topology from the firmware for a given 2280 * node TEID to the root node. 2281 */ 2282 enum ice_status 2283 ice_aq_query_node_to_root(struct ice_hw *hw, u32 node_teid, 2284 struct ice_aqc_txsched_elem_data *buf, u16 buf_size, 2285 struct ice_sq_cd *cd) 2286 { 2287 struct ice_aqc_query_node_to_root *cmd; 2288 struct ice_aq_desc desc; 2289 2290 cmd = &desc.params.query_node_to_root; 2291 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_query_node_to_root); 2292 cmd->teid = CPU_TO_LE32(node_teid); 2293 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2294 } 2295 2296 /** 2297 * ice_get_agg_info - get the aggregator ID 2298 * @hw: pointer to the hardware structure 2299 * @agg_id: aggregator ID 2300 * 2301 * This function validates aggregator ID. The function returns info if 2302 * aggregator ID is present in list otherwise it returns null. 2303 */ 2304 static struct ice_sched_agg_info * 2305 ice_get_agg_info(struct ice_hw *hw, u32 agg_id) 2306 { 2307 struct ice_sched_agg_info *agg_info; 2308 2309 LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info, 2310 list_entry) 2311 if (agg_info->agg_id == agg_id) 2312 return agg_info; 2313 2314 return NULL; 2315 } 2316 2317 /** 2318 * ice_sched_get_free_vsi_parent - Find a free parent node in aggregator subtree 2319 * @hw: pointer to the HW struct 2320 * @node: pointer to a child node 2321 * @num_nodes: num nodes count array 2322 * 2323 * This function walks through the aggregator subtree to find a free parent 2324 * node 2325 */ 2326 static struct ice_sched_node * 2327 ice_sched_get_free_vsi_parent(struct ice_hw *hw, struct ice_sched_node *node, 2328 u16 *num_nodes) 2329 { 2330 u8 l = node->tx_sched_layer; 2331 u8 vsil, i; 2332 2333 vsil = ice_sched_get_vsi_layer(hw); 2334 2335 /* Is it VSI parent layer ? */ 2336 if (l == vsil - 1) 2337 return (node->num_children < hw->max_children[l]) ? node : NULL; 2338 2339 /* We have intermediate nodes. Let's walk through the subtree. If the 2340 * intermediate node has space to add a new node then clear the count 2341 */ 2342 if (node->num_children < hw->max_children[l]) 2343 num_nodes[l] = 0; 2344 /* The below recursive call is intentional and wouldn't go more than 2345 * 2 or 3 iterations. 2346 */ 2347 2348 for (i = 0; i < node->num_children; i++) { 2349 struct ice_sched_node *parent; 2350 2351 parent = ice_sched_get_free_vsi_parent(hw, node->children[i], 2352 num_nodes); 2353 if (parent) 2354 return parent; 2355 } 2356 2357 return NULL; 2358 } 2359 2360 /** 2361 * ice_sched_update_parent - update the new parent in SW DB 2362 * @new_parent: pointer to a new parent node 2363 * @node: pointer to a child node 2364 * 2365 * This function removes the child from the old parent and adds it to a new 2366 * parent 2367 */ 2368 static void 2369 ice_sched_update_parent(struct ice_sched_node *new_parent, 2370 struct ice_sched_node *node) 2371 { 2372 struct ice_sched_node *old_parent; 2373 u8 i, j; 2374 2375 old_parent = node->parent; 2376 2377 /* update the old parent children */ 2378 for (i = 0; i < old_parent->num_children; i++) 2379 if (old_parent->children[i] == node) { 2380 for (j = i + 1; j < old_parent->num_children; j++) 2381 old_parent->children[j - 1] = 2382 old_parent->children[j]; 2383 old_parent->num_children--; 2384 break; 2385 } 2386 2387 /* now move the node to a new parent */ 2388 new_parent->children[new_parent->num_children++] = node; 2389 node->parent = new_parent; 2390 node->info.parent_teid = new_parent->info.node_teid; 2391 } 2392 2393 /** 2394 * ice_sched_move_nodes - move child nodes to a given parent 2395 * @pi: port information structure 2396 * @parent: pointer to parent node 2397 * @num_items: number of child nodes to be moved 2398 * @list: pointer to child node teids 2399 * 2400 * This function move the child nodes to a given parent. 2401 */ 2402 static enum ice_status 2403 ice_sched_move_nodes(struct ice_port_info *pi, struct ice_sched_node *parent, 2404 u16 num_items, u32 *list) 2405 { 2406 struct ice_aqc_move_elem *buf; 2407 struct ice_sched_node *node; 2408 enum ice_status status = ICE_SUCCESS; 2409 u16 i, grps_movd = 0; 2410 struct ice_hw *hw; 2411 u16 buf_len; 2412 2413 hw = pi->hw; 2414 2415 if (!parent || !num_items) 2416 return ICE_ERR_PARAM; 2417 2418 /* Does parent have enough space */ 2419 if (parent->num_children + num_items > 2420 hw->max_children[parent->tx_sched_layer]) 2421 return ICE_ERR_AQ_FULL; 2422 2423 buf_len = ice_struct_size(buf, teid, 1); 2424 buf = (struct ice_aqc_move_elem *)ice_malloc(hw, buf_len); 2425 if (!buf) 2426 return ICE_ERR_NO_MEMORY; 2427 2428 for (i = 0; i < num_items; i++) { 2429 node = ice_sched_find_node_by_teid(pi->root, list[i]); 2430 if (!node) { 2431 status = ICE_ERR_PARAM; 2432 goto move_err_exit; 2433 } 2434 2435 buf->hdr.src_parent_teid = node->info.parent_teid; 2436 buf->hdr.dest_parent_teid = parent->info.node_teid; 2437 buf->teid[0] = node->info.node_teid; 2438 buf->hdr.num_elems = CPU_TO_LE16(1); 2439 status = ice_aq_move_sched_elems(hw, 1, buf, buf_len, 2440 &grps_movd, NULL); 2441 if (status && grps_movd != 1) { 2442 status = ICE_ERR_CFG; 2443 goto move_err_exit; 2444 } 2445 2446 /* update the SW DB */ 2447 ice_sched_update_parent(parent, node); 2448 } 2449 2450 move_err_exit: 2451 ice_free(hw, buf); 2452 return status; 2453 } 2454 2455 /** 2456 * ice_sched_move_vsi_to_agg - move VSI to aggregator node 2457 * @pi: port information structure 2458 * @vsi_handle: software VSI handle 2459 * @agg_id: aggregator ID 2460 * @tc: TC number 2461 * 2462 * This function moves a VSI to an aggregator node or its subtree. 2463 * Intermediate nodes may be created if required. 2464 */ 2465 static enum ice_status 2466 ice_sched_move_vsi_to_agg(struct ice_port_info *pi, u16 vsi_handle, u32 agg_id, 2467 u8 tc) 2468 { 2469 struct ice_sched_node *vsi_node, *agg_node, *tc_node, *parent; 2470 u16 num_nodes[ICE_AQC_TOPO_MAX_LEVEL_NUM] = { 0 }; 2471 u32 first_node_teid, vsi_teid; 2472 enum ice_status status; 2473 u16 num_nodes_added; 2474 u8 aggl, vsil, i; 2475 2476 tc_node = ice_sched_get_tc_node(pi, tc); 2477 if (!tc_node) 2478 return ICE_ERR_CFG; 2479 2480 agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); 2481 if (!agg_node) 2482 return ICE_ERR_DOES_NOT_EXIST; 2483 2484 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 2485 if (!vsi_node) 2486 return ICE_ERR_DOES_NOT_EXIST; 2487 2488 /* Is this VSI already part of given aggregator? */ 2489 if (ice_sched_find_node_in_subtree(pi->hw, agg_node, vsi_node)) 2490 return ICE_SUCCESS; 2491 2492 aggl = ice_sched_get_agg_layer(pi->hw); 2493 vsil = ice_sched_get_vsi_layer(pi->hw); 2494 2495 /* set intermediate node count to 1 between aggregator and VSI layers */ 2496 for (i = aggl + 1; i < vsil; i++) 2497 num_nodes[i] = 1; 2498 2499 /* Check if the aggregator subtree has any free node to add the VSI */ 2500 for (i = 0; i < agg_node->num_children; i++) { 2501 parent = ice_sched_get_free_vsi_parent(pi->hw, 2502 agg_node->children[i], 2503 num_nodes); 2504 if (parent) 2505 goto move_nodes; 2506 } 2507 2508 /* add new nodes */ 2509 parent = agg_node; 2510 for (i = aggl + 1; i < vsil; i++) { 2511 status = ice_sched_add_nodes_to_layer(pi, tc_node, parent, i, 2512 num_nodes[i], 2513 &first_node_teid, 2514 &num_nodes_added); 2515 if (status != ICE_SUCCESS || num_nodes[i] != num_nodes_added) 2516 return ICE_ERR_CFG; 2517 2518 /* The newly added node can be a new parent for the next 2519 * layer nodes 2520 */ 2521 if (num_nodes_added) 2522 parent = ice_sched_find_node_by_teid(tc_node, 2523 first_node_teid); 2524 else 2525 parent = parent->children[0]; 2526 2527 if (!parent) 2528 return ICE_ERR_CFG; 2529 } 2530 2531 move_nodes: 2532 vsi_teid = LE32_TO_CPU(vsi_node->info.node_teid); 2533 return ice_sched_move_nodes(pi, parent, 1, &vsi_teid); 2534 } 2535 2536 /** 2537 * ice_move_all_vsi_to_dflt_agg - move all VSI(s) to default aggregator 2538 * @pi: port information structure 2539 * @agg_info: aggregator info 2540 * @tc: traffic class number 2541 * @rm_vsi_info: true or false 2542 * 2543 * This function move all the VSI(s) to the default aggregator and delete 2544 * aggregator VSI info based on passed in boolean parameter rm_vsi_info. The 2545 * caller holds the scheduler lock. 2546 */ 2547 static enum ice_status 2548 ice_move_all_vsi_to_dflt_agg(struct ice_port_info *pi, 2549 struct ice_sched_agg_info *agg_info, u8 tc, 2550 bool rm_vsi_info) 2551 { 2552 struct ice_sched_agg_vsi_info *agg_vsi_info; 2553 struct ice_sched_agg_vsi_info *tmp; 2554 enum ice_status status = ICE_SUCCESS; 2555 2556 LIST_FOR_EACH_ENTRY_SAFE(agg_vsi_info, tmp, &agg_info->agg_vsi_list, 2557 ice_sched_agg_vsi_info, list_entry) { 2558 u16 vsi_handle = agg_vsi_info->vsi_handle; 2559 2560 /* Move VSI to default aggregator */ 2561 if (!ice_is_tc_ena(agg_vsi_info->tc_bitmap[0], tc)) 2562 continue; 2563 2564 status = ice_sched_move_vsi_to_agg(pi, vsi_handle, 2565 ICE_DFLT_AGG_ID, tc); 2566 if (status) 2567 break; 2568 2569 ice_clear_bit(tc, agg_vsi_info->tc_bitmap); 2570 if (rm_vsi_info && !agg_vsi_info->tc_bitmap[0]) { 2571 LIST_DEL(&agg_vsi_info->list_entry); 2572 ice_free(pi->hw, agg_vsi_info); 2573 } 2574 } 2575 2576 return status; 2577 } 2578 2579 /** 2580 * ice_sched_is_agg_inuse - check whether the aggregator is in use or not 2581 * @pi: port information structure 2582 * @node: node pointer 2583 * 2584 * This function checks whether the aggregator is attached with any VSI or not. 2585 */ 2586 static bool 2587 ice_sched_is_agg_inuse(struct ice_port_info *pi, struct ice_sched_node *node) 2588 { 2589 u8 vsil, i; 2590 2591 vsil = ice_sched_get_vsi_layer(pi->hw); 2592 if (node->tx_sched_layer < vsil - 1) { 2593 for (i = 0; i < node->num_children; i++) 2594 if (ice_sched_is_agg_inuse(pi, node->children[i])) 2595 return true; 2596 return false; 2597 } else { 2598 return node->num_children ? true : false; 2599 } 2600 } 2601 2602 /** 2603 * ice_sched_rm_agg_cfg - remove the aggregator node 2604 * @pi: port information structure 2605 * @agg_id: aggregator ID 2606 * @tc: TC number 2607 * 2608 * This function removes the aggregator node and intermediate nodes if any 2609 * from the given TC 2610 */ 2611 static enum ice_status 2612 ice_sched_rm_agg_cfg(struct ice_port_info *pi, u32 agg_id, u8 tc) 2613 { 2614 struct ice_sched_node *tc_node, *agg_node; 2615 struct ice_hw *hw = pi->hw; 2616 2617 tc_node = ice_sched_get_tc_node(pi, tc); 2618 if (!tc_node) 2619 return ICE_ERR_CFG; 2620 2621 agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); 2622 if (!agg_node) 2623 return ICE_ERR_DOES_NOT_EXIST; 2624 2625 /* Can't remove the aggregator node if it has children */ 2626 if (ice_sched_is_agg_inuse(pi, agg_node)) 2627 return ICE_ERR_IN_USE; 2628 2629 /* need to remove the whole subtree if aggregator node is the 2630 * only child. 2631 */ 2632 while (agg_node->tx_sched_layer > hw->sw_entry_point_layer) { 2633 struct ice_sched_node *parent = agg_node->parent; 2634 2635 if (!parent) 2636 return ICE_ERR_CFG; 2637 2638 if (parent->num_children > 1) 2639 break; 2640 2641 agg_node = parent; 2642 } 2643 2644 ice_free_sched_node(pi, agg_node); 2645 return ICE_SUCCESS; 2646 } 2647 2648 /** 2649 * ice_rm_agg_cfg_tc - remove aggregator configuration for TC 2650 * @pi: port information structure 2651 * @agg_info: aggregator ID 2652 * @tc: TC number 2653 * @rm_vsi_info: bool value true or false 2654 * 2655 * This function removes aggregator reference to VSI of given TC. It removes 2656 * the aggregator configuration completely for requested TC. The caller needs 2657 * to hold the scheduler lock. 2658 */ 2659 static enum ice_status 2660 ice_rm_agg_cfg_tc(struct ice_port_info *pi, struct ice_sched_agg_info *agg_info, 2661 u8 tc, bool rm_vsi_info) 2662 { 2663 enum ice_status status = ICE_SUCCESS; 2664 2665 /* If nothing to remove - return success */ 2666 if (!ice_is_tc_ena(agg_info->tc_bitmap[0], tc)) 2667 goto exit_rm_agg_cfg_tc; 2668 2669 status = ice_move_all_vsi_to_dflt_agg(pi, agg_info, tc, rm_vsi_info); 2670 if (status) 2671 goto exit_rm_agg_cfg_tc; 2672 2673 /* Delete aggregator node(s) */ 2674 status = ice_sched_rm_agg_cfg(pi, agg_info->agg_id, tc); 2675 if (status) 2676 goto exit_rm_agg_cfg_tc; 2677 2678 ice_clear_bit(tc, agg_info->tc_bitmap); 2679 exit_rm_agg_cfg_tc: 2680 return status; 2681 } 2682 2683 /** 2684 * ice_save_agg_tc_bitmap - save aggregator TC bitmap 2685 * @pi: port information structure 2686 * @agg_id: aggregator ID 2687 * @tc_bitmap: 8 bits TC bitmap 2688 * 2689 * Save aggregator TC bitmap. This function needs to be called with scheduler 2690 * lock held. 2691 */ 2692 static enum ice_status 2693 ice_save_agg_tc_bitmap(struct ice_port_info *pi, u32 agg_id, 2694 ice_bitmap_t *tc_bitmap) 2695 { 2696 struct ice_sched_agg_info *agg_info; 2697 2698 agg_info = ice_get_agg_info(pi->hw, agg_id); 2699 if (!agg_info) 2700 return ICE_ERR_PARAM; 2701 ice_cp_bitmap(agg_info->replay_tc_bitmap, tc_bitmap, 2702 ICE_MAX_TRAFFIC_CLASS); 2703 return ICE_SUCCESS; 2704 } 2705 2706 /** 2707 * ice_sched_add_agg_cfg - create an aggregator node 2708 * @pi: port information structure 2709 * @agg_id: aggregator ID 2710 * @tc: TC number 2711 * 2712 * This function creates an aggregator node and intermediate nodes if required 2713 * for the given TC 2714 */ 2715 static enum ice_status 2716 ice_sched_add_agg_cfg(struct ice_port_info *pi, u32 agg_id, u8 tc) 2717 { 2718 struct ice_sched_node *parent, *agg_node, *tc_node; 2719 u16 num_nodes[ICE_AQC_TOPO_MAX_LEVEL_NUM] = { 0 }; 2720 enum ice_status status = ICE_SUCCESS; 2721 struct ice_hw *hw = pi->hw; 2722 u32 first_node_teid; 2723 u16 num_nodes_added; 2724 u8 i, aggl; 2725 2726 tc_node = ice_sched_get_tc_node(pi, tc); 2727 if (!tc_node) 2728 return ICE_ERR_CFG; 2729 2730 agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); 2731 /* Does Agg node already exist ? */ 2732 if (agg_node) 2733 return status; 2734 2735 aggl = ice_sched_get_agg_layer(hw); 2736 2737 /* need one node in Agg layer */ 2738 num_nodes[aggl] = 1; 2739 2740 /* Check whether the intermediate nodes have space to add the 2741 * new aggregator. If they are full, then SW needs to allocate a new 2742 * intermediate node on those layers 2743 */ 2744 for (i = hw->sw_entry_point_layer; i < aggl; i++) { 2745 parent = ice_sched_get_first_node(pi, tc_node, i); 2746 2747 /* scan all the siblings */ 2748 while (parent) { 2749 if (parent->num_children < hw->max_children[i]) 2750 break; 2751 parent = parent->sibling; 2752 } 2753 2754 /* all the nodes are full, reserve one for this layer */ 2755 if (!parent) 2756 num_nodes[i]++; 2757 } 2758 2759 /* add the aggregator node */ 2760 parent = tc_node; 2761 for (i = hw->sw_entry_point_layer; i <= aggl; i++) { 2762 if (!parent) 2763 return ICE_ERR_CFG; 2764 2765 status = ice_sched_add_nodes_to_layer(pi, tc_node, parent, i, 2766 num_nodes[i], 2767 &first_node_teid, 2768 &num_nodes_added); 2769 if (status != ICE_SUCCESS || num_nodes[i] != num_nodes_added) 2770 return ICE_ERR_CFG; 2771 2772 /* The newly added node can be a new parent for the next 2773 * layer nodes 2774 */ 2775 if (num_nodes_added) { 2776 parent = ice_sched_find_node_by_teid(tc_node, 2777 first_node_teid); 2778 /* register aggregator ID with the aggregator node */ 2779 if (parent && i == aggl) 2780 parent->agg_id = agg_id; 2781 } else { 2782 parent = parent->children[0]; 2783 } 2784 } 2785 2786 return ICE_SUCCESS; 2787 } 2788 2789 /** 2790 * ice_sched_cfg_agg - configure aggregator node 2791 * @pi: port information structure 2792 * @agg_id: aggregator ID 2793 * @agg_type: aggregator type queue, VSI, or aggregator group 2794 * @tc_bitmap: bits TC bitmap 2795 * 2796 * It registers a unique aggregator node into scheduler services. It 2797 * allows a user to register with a unique ID to track it's resources. 2798 * The aggregator type determines if this is a queue group, VSI group 2799 * or aggregator group. It then creates the aggregator node(s) for requested 2800 * TC(s) or removes an existing aggregator node including its configuration 2801 * if indicated via tc_bitmap. Call ice_rm_agg_cfg to release aggregator 2802 * resources and remove aggregator ID. 2803 * This function needs to be called with scheduler lock held. 2804 */ 2805 static enum ice_status 2806 ice_sched_cfg_agg(struct ice_port_info *pi, u32 agg_id, 2807 enum ice_agg_type agg_type, ice_bitmap_t *tc_bitmap) 2808 { 2809 struct ice_sched_agg_info *agg_info; 2810 enum ice_status status = ICE_SUCCESS; 2811 struct ice_hw *hw = pi->hw; 2812 u8 tc; 2813 2814 agg_info = ice_get_agg_info(hw, agg_id); 2815 if (!agg_info) { 2816 /* Create new entry for new aggregator ID */ 2817 agg_info = (struct ice_sched_agg_info *) 2818 ice_malloc(hw, sizeof(*agg_info)); 2819 if (!agg_info) 2820 return ICE_ERR_NO_MEMORY; 2821 2822 agg_info->agg_id = agg_id; 2823 agg_info->agg_type = agg_type; 2824 agg_info->tc_bitmap[0] = 0; 2825 2826 /* Initialize the aggregator VSI list head */ 2827 INIT_LIST_HEAD(&agg_info->agg_vsi_list); 2828 2829 /* Add new entry in aggregator list */ 2830 LIST_ADD(&agg_info->list_entry, &hw->agg_list); 2831 } 2832 /* Create aggregator node(s) for requested TC(s) */ 2833 ice_for_each_traffic_class(tc) { 2834 if (!ice_is_tc_ena(*tc_bitmap, tc)) { 2835 /* Delete aggregator cfg TC if it exists previously */ 2836 status = ice_rm_agg_cfg_tc(pi, agg_info, tc, false); 2837 if (status) 2838 break; 2839 continue; 2840 } 2841 2842 /* Check if aggregator node for TC already exists */ 2843 if (ice_is_tc_ena(agg_info->tc_bitmap[0], tc)) 2844 continue; 2845 2846 /* Create new aggregator node for TC */ 2847 status = ice_sched_add_agg_cfg(pi, agg_id, tc); 2848 if (status) 2849 break; 2850 2851 /* Save aggregator node's TC information */ 2852 ice_set_bit(tc, agg_info->tc_bitmap); 2853 } 2854 2855 return status; 2856 } 2857 2858 /** 2859 * ice_cfg_agg - config aggregator node 2860 * @pi: port information structure 2861 * @agg_id: aggregator ID 2862 * @agg_type: aggregator type queue, VSI, or aggregator group 2863 * @tc_bitmap: bits TC bitmap 2864 * 2865 * This function configures aggregator node(s). 2866 */ 2867 enum ice_status 2868 ice_cfg_agg(struct ice_port_info *pi, u32 agg_id, enum ice_agg_type agg_type, 2869 u8 tc_bitmap) 2870 { 2871 ice_bitmap_t bitmap = tc_bitmap; 2872 enum ice_status status; 2873 2874 ice_acquire_lock(&pi->sched_lock); 2875 status = ice_sched_cfg_agg(pi, agg_id, agg_type, 2876 (ice_bitmap_t *)&bitmap); 2877 if (!status) 2878 status = ice_save_agg_tc_bitmap(pi, agg_id, 2879 (ice_bitmap_t *)&bitmap); 2880 ice_release_lock(&pi->sched_lock); 2881 return status; 2882 } 2883 2884 /** 2885 * ice_get_agg_vsi_info - get the aggregator ID 2886 * @agg_info: aggregator info 2887 * @vsi_handle: software VSI handle 2888 * 2889 * The function returns aggregator VSI info based on VSI handle. This function 2890 * needs to be called with scheduler lock held. 2891 */ 2892 static struct ice_sched_agg_vsi_info * 2893 ice_get_agg_vsi_info(struct ice_sched_agg_info *agg_info, u16 vsi_handle) 2894 { 2895 struct ice_sched_agg_vsi_info *agg_vsi_info; 2896 2897 LIST_FOR_EACH_ENTRY(agg_vsi_info, &agg_info->agg_vsi_list, 2898 ice_sched_agg_vsi_info, list_entry) 2899 if (agg_vsi_info->vsi_handle == vsi_handle) 2900 return agg_vsi_info; 2901 2902 return NULL; 2903 } 2904 2905 /** 2906 * ice_get_vsi_agg_info - get the aggregator info of VSI 2907 * @hw: pointer to the hardware structure 2908 * @vsi_handle: Sw VSI handle 2909 * 2910 * The function returns aggregator info of VSI represented via vsi_handle. The 2911 * VSI has in this case a different aggregator than the default one. This 2912 * function needs to be called with scheduler lock held. 2913 */ 2914 static struct ice_sched_agg_info * 2915 ice_get_vsi_agg_info(struct ice_hw *hw, u16 vsi_handle) 2916 { 2917 struct ice_sched_agg_info *agg_info; 2918 2919 LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info, 2920 list_entry) { 2921 struct ice_sched_agg_vsi_info *agg_vsi_info; 2922 2923 agg_vsi_info = ice_get_agg_vsi_info(agg_info, vsi_handle); 2924 if (agg_vsi_info) 2925 return agg_info; 2926 } 2927 return NULL; 2928 } 2929 2930 /** 2931 * ice_save_agg_vsi_tc_bitmap - save aggregator VSI TC bitmap 2932 * @pi: port information structure 2933 * @agg_id: aggregator ID 2934 * @vsi_handle: software VSI handle 2935 * @tc_bitmap: TC bitmap of enabled TC(s) 2936 * 2937 * Save VSI to aggregator TC bitmap. This function needs to call with scheduler 2938 * lock held. 2939 */ 2940 static enum ice_status 2941 ice_save_agg_vsi_tc_bitmap(struct ice_port_info *pi, u32 agg_id, u16 vsi_handle, 2942 ice_bitmap_t *tc_bitmap) 2943 { 2944 struct ice_sched_agg_vsi_info *agg_vsi_info; 2945 struct ice_sched_agg_info *agg_info; 2946 2947 agg_info = ice_get_agg_info(pi->hw, agg_id); 2948 if (!agg_info) 2949 return ICE_ERR_PARAM; 2950 /* check if entry already exist */ 2951 agg_vsi_info = ice_get_agg_vsi_info(agg_info, vsi_handle); 2952 if (!agg_vsi_info) 2953 return ICE_ERR_PARAM; 2954 ice_cp_bitmap(agg_vsi_info->replay_tc_bitmap, tc_bitmap, 2955 ICE_MAX_TRAFFIC_CLASS); 2956 return ICE_SUCCESS; 2957 } 2958 2959 /** 2960 * ice_sched_assoc_vsi_to_agg - associate/move VSI to new/default aggregator 2961 * @pi: port information structure 2962 * @agg_id: aggregator ID 2963 * @vsi_handle: software VSI handle 2964 * @tc_bitmap: TC bitmap of enabled TC(s) 2965 * 2966 * This function moves VSI to a new or default aggregator node. If VSI is 2967 * already associated to the aggregator node then no operation is performed on 2968 * the tree. This function needs to be called with scheduler lock held. 2969 */ 2970 static enum ice_status 2971 ice_sched_assoc_vsi_to_agg(struct ice_port_info *pi, u32 agg_id, 2972 u16 vsi_handle, ice_bitmap_t *tc_bitmap) 2973 { 2974 struct ice_sched_agg_vsi_info *agg_vsi_info, *old_agg_vsi_info = NULL; 2975 struct ice_sched_agg_info *agg_info, *old_agg_info; 2976 enum ice_status status = ICE_SUCCESS; 2977 struct ice_hw *hw = pi->hw; 2978 u8 tc; 2979 2980 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 2981 return ICE_ERR_PARAM; 2982 agg_info = ice_get_agg_info(hw, agg_id); 2983 if (!agg_info) 2984 return ICE_ERR_PARAM; 2985 /* If the vsi is already part of another aggregator then update 2986 * its vsi info list 2987 */ 2988 old_agg_info = ice_get_vsi_agg_info(hw, vsi_handle); 2989 if (old_agg_info && old_agg_info != agg_info) { 2990 struct ice_sched_agg_vsi_info *vtmp; 2991 2992 LIST_FOR_EACH_ENTRY_SAFE(old_agg_vsi_info, vtmp, 2993 &old_agg_info->agg_vsi_list, 2994 ice_sched_agg_vsi_info, list_entry) 2995 if (old_agg_vsi_info->vsi_handle == vsi_handle) 2996 break; 2997 } 2998 2999 /* check if entry already exist */ 3000 agg_vsi_info = ice_get_agg_vsi_info(agg_info, vsi_handle); 3001 if (!agg_vsi_info) { 3002 /* Create new entry for VSI under aggregator list */ 3003 agg_vsi_info = (struct ice_sched_agg_vsi_info *) 3004 ice_malloc(hw, sizeof(*agg_vsi_info)); 3005 if (!agg_vsi_info) 3006 return ICE_ERR_PARAM; 3007 3008 /* add VSI ID into the aggregator list */ 3009 agg_vsi_info->vsi_handle = vsi_handle; 3010 LIST_ADD(&agg_vsi_info->list_entry, &agg_info->agg_vsi_list); 3011 } 3012 /* Move VSI node to new aggregator node for requested TC(s) */ 3013 ice_for_each_traffic_class(tc) { 3014 if (!ice_is_tc_ena(*tc_bitmap, tc)) 3015 continue; 3016 3017 /* Move VSI to new aggregator */ 3018 status = ice_sched_move_vsi_to_agg(pi, vsi_handle, agg_id, tc); 3019 if (status) 3020 break; 3021 3022 ice_set_bit(tc, agg_vsi_info->tc_bitmap); 3023 if (old_agg_vsi_info) 3024 ice_clear_bit(tc, old_agg_vsi_info->tc_bitmap); 3025 } 3026 if (old_agg_vsi_info && !old_agg_vsi_info->tc_bitmap[0]) { 3027 LIST_DEL(&old_agg_vsi_info->list_entry); 3028 ice_free(pi->hw, old_agg_vsi_info); 3029 } 3030 return status; 3031 } 3032 3033 /** 3034 * ice_sched_rm_unused_rl_prof - remove unused RL profile 3035 * @hw: pointer to the hardware structure 3036 * 3037 * This function removes unused rate limit profiles from the HW and 3038 * SW DB. The caller needs to hold scheduler lock. 3039 */ 3040 static void ice_sched_rm_unused_rl_prof(struct ice_hw *hw) 3041 { 3042 u16 ln; 3043 3044 for (ln = 0; ln < hw->num_tx_sched_layers; ln++) { 3045 struct ice_aqc_rl_profile_info *rl_prof_elem; 3046 struct ice_aqc_rl_profile_info *rl_prof_tmp; 3047 3048 LIST_FOR_EACH_ENTRY_SAFE(rl_prof_elem, rl_prof_tmp, 3049 &hw->rl_prof_list[ln], 3050 ice_aqc_rl_profile_info, list_entry) { 3051 if (!ice_sched_del_rl_profile(hw, rl_prof_elem)) 3052 ice_debug(hw, ICE_DBG_SCHED, "Removed rl profile\n"); 3053 } 3054 } 3055 } 3056 3057 /** 3058 * ice_sched_update_elem - update element 3059 * @hw: pointer to the HW struct 3060 * @node: pointer to node 3061 * @info: node info to update 3062 * 3063 * Update the HW DB, and local SW DB of node. Update the scheduling 3064 * parameters of node from argument info data buffer (Info->data buf) and 3065 * returns success or error on config sched element failure. The caller 3066 * needs to hold scheduler lock. 3067 */ 3068 static enum ice_status 3069 ice_sched_update_elem(struct ice_hw *hw, struct ice_sched_node *node, 3070 struct ice_aqc_txsched_elem_data *info) 3071 { 3072 struct ice_aqc_txsched_elem_data buf; 3073 enum ice_status status; 3074 u16 elem_cfgd = 0; 3075 u16 num_elems = 1; 3076 3077 buf = *info; 3078 /* For TC nodes, CIR config is not supported */ 3079 if (node->info.data.elem_type == ICE_AQC_ELEM_TYPE_TC) 3080 buf.data.valid_sections &= ~ICE_AQC_ELEM_VALID_CIR; 3081 /* Parent TEID is reserved field in this aq call */ 3082 buf.parent_teid = 0; 3083 /* Element type is reserved field in this aq call */ 3084 buf.data.elem_type = 0; 3085 /* Flags is reserved field in this aq call */ 3086 buf.data.flags = 0; 3087 3088 /* Update HW DB */ 3089 /* Configure element node */ 3090 status = ice_aq_cfg_sched_elems(hw, num_elems, &buf, sizeof(buf), 3091 &elem_cfgd, NULL); 3092 if (status || elem_cfgd != num_elems) { 3093 ice_debug(hw, ICE_DBG_SCHED, "Config sched elem error\n"); 3094 return ICE_ERR_CFG; 3095 } 3096 3097 /* Config success case */ 3098 /* Now update local SW DB */ 3099 /* Only copy the data portion of info buffer */ 3100 node->info.data = info->data; 3101 return status; 3102 } 3103 3104 /** 3105 * ice_sched_cfg_node_bw_alloc - configure node BW weight/alloc params 3106 * @hw: pointer to the HW struct 3107 * @node: sched node to configure 3108 * @rl_type: rate limit type CIR, EIR, or shared 3109 * @bw_alloc: BW weight/allocation 3110 * 3111 * This function configures node element's BW allocation. 3112 */ 3113 static enum ice_status 3114 ice_sched_cfg_node_bw_alloc(struct ice_hw *hw, struct ice_sched_node *node, 3115 enum ice_rl_type rl_type, u16 bw_alloc) 3116 { 3117 struct ice_aqc_txsched_elem_data buf; 3118 struct ice_aqc_txsched_elem *data; 3119 enum ice_status status; 3120 3121 buf = node->info; 3122 data = &buf.data; 3123 if (rl_type == ICE_MIN_BW) { 3124 data->valid_sections |= ICE_AQC_ELEM_VALID_CIR; 3125 data->cir_bw.bw_alloc = CPU_TO_LE16(bw_alloc); 3126 } else if (rl_type == ICE_MAX_BW) { 3127 data->valid_sections |= ICE_AQC_ELEM_VALID_EIR; 3128 data->eir_bw.bw_alloc = CPU_TO_LE16(bw_alloc); 3129 } else { 3130 return ICE_ERR_PARAM; 3131 } 3132 3133 /* Configure element */ 3134 status = ice_sched_update_elem(hw, node, &buf); 3135 return status; 3136 } 3137 3138 /** 3139 * ice_move_vsi_to_agg - moves VSI to new or default aggregator 3140 * @pi: port information structure 3141 * @agg_id: aggregator ID 3142 * @vsi_handle: software VSI handle 3143 * @tc_bitmap: TC bitmap of enabled TC(s) 3144 * 3145 * Move or associate VSI to a new or default aggregator node. 3146 */ 3147 enum ice_status 3148 ice_move_vsi_to_agg(struct ice_port_info *pi, u32 agg_id, u16 vsi_handle, 3149 u8 tc_bitmap) 3150 { 3151 ice_bitmap_t bitmap = tc_bitmap; 3152 enum ice_status status; 3153 3154 ice_acquire_lock(&pi->sched_lock); 3155 status = ice_sched_assoc_vsi_to_agg(pi, agg_id, vsi_handle, 3156 (ice_bitmap_t *)&bitmap); 3157 if (!status) 3158 status = ice_save_agg_vsi_tc_bitmap(pi, agg_id, vsi_handle, 3159 (ice_bitmap_t *)&bitmap); 3160 ice_release_lock(&pi->sched_lock); 3161 return status; 3162 } 3163 3164 /** 3165 * ice_rm_agg_cfg - remove aggregator configuration 3166 * @pi: port information structure 3167 * @agg_id: aggregator ID 3168 * 3169 * This function removes aggregator reference to VSI and delete aggregator ID 3170 * info. It removes the aggregator configuration completely. 3171 */ 3172 enum ice_status ice_rm_agg_cfg(struct ice_port_info *pi, u32 agg_id) 3173 { 3174 struct ice_sched_agg_info *agg_info; 3175 enum ice_status status = ICE_SUCCESS; 3176 u8 tc; 3177 3178 ice_acquire_lock(&pi->sched_lock); 3179 agg_info = ice_get_agg_info(pi->hw, agg_id); 3180 if (!agg_info) { 3181 status = ICE_ERR_DOES_NOT_EXIST; 3182 goto exit_ice_rm_agg_cfg; 3183 } 3184 3185 ice_for_each_traffic_class(tc) { 3186 status = ice_rm_agg_cfg_tc(pi, agg_info, tc, true); 3187 if (status) 3188 goto exit_ice_rm_agg_cfg; 3189 } 3190 3191 if (ice_is_any_bit_set(agg_info->tc_bitmap, ICE_MAX_TRAFFIC_CLASS)) { 3192 status = ICE_ERR_IN_USE; 3193 goto exit_ice_rm_agg_cfg; 3194 } 3195 3196 /* Safe to delete entry now */ 3197 LIST_DEL(&agg_info->list_entry); 3198 ice_free(pi->hw, agg_info); 3199 3200 /* Remove unused RL profile IDs from HW and SW DB */ 3201 ice_sched_rm_unused_rl_prof(pi->hw); 3202 3203 exit_ice_rm_agg_cfg: 3204 ice_release_lock(&pi->sched_lock); 3205 return status; 3206 } 3207 3208 /** 3209 * ice_set_clear_cir_bw_alloc - set or clear CIR BW alloc information 3210 * @bw_t_info: bandwidth type information structure 3211 * @bw_alloc: Bandwidth allocation information 3212 * 3213 * Save or clear CIR BW alloc information (bw_alloc) in the passed param 3214 * bw_t_info. 3215 */ 3216 static void 3217 ice_set_clear_cir_bw_alloc(struct ice_bw_type_info *bw_t_info, u16 bw_alloc) 3218 { 3219 bw_t_info->cir_bw.bw_alloc = bw_alloc; 3220 if (bw_t_info->cir_bw.bw_alloc) 3221 ice_set_bit(ICE_BW_TYPE_CIR_WT, bw_t_info->bw_t_bitmap); 3222 else 3223 ice_clear_bit(ICE_BW_TYPE_CIR_WT, bw_t_info->bw_t_bitmap); 3224 } 3225 3226 /** 3227 * ice_set_clear_eir_bw_alloc - set or clear EIR BW alloc information 3228 * @bw_t_info: bandwidth type information structure 3229 * @bw_alloc: Bandwidth allocation information 3230 * 3231 * Save or clear EIR BW alloc information (bw_alloc) in the passed param 3232 * bw_t_info. 3233 */ 3234 static void 3235 ice_set_clear_eir_bw_alloc(struct ice_bw_type_info *bw_t_info, u16 bw_alloc) 3236 { 3237 bw_t_info->eir_bw.bw_alloc = bw_alloc; 3238 if (bw_t_info->eir_bw.bw_alloc) 3239 ice_set_bit(ICE_BW_TYPE_EIR_WT, bw_t_info->bw_t_bitmap); 3240 else 3241 ice_clear_bit(ICE_BW_TYPE_EIR_WT, bw_t_info->bw_t_bitmap); 3242 } 3243 3244 /** 3245 * ice_sched_save_vsi_bw_alloc - save VSI node's BW alloc information 3246 * @pi: port information structure 3247 * @vsi_handle: sw VSI handle 3248 * @tc: traffic class 3249 * @rl_type: rate limit type min or max 3250 * @bw_alloc: Bandwidth allocation information 3251 * 3252 * Save BW alloc information of VSI type node for post replay use. 3253 */ 3254 static enum ice_status 3255 ice_sched_save_vsi_bw_alloc(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 3256 enum ice_rl_type rl_type, u16 bw_alloc) 3257 { 3258 struct ice_vsi_ctx *vsi_ctx; 3259 3260 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 3261 return ICE_ERR_PARAM; 3262 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 3263 if (!vsi_ctx) 3264 return ICE_ERR_PARAM; 3265 switch (rl_type) { 3266 case ICE_MIN_BW: 3267 ice_set_clear_cir_bw_alloc(&vsi_ctx->sched.bw_t_info[tc], 3268 bw_alloc); 3269 break; 3270 case ICE_MAX_BW: 3271 ice_set_clear_eir_bw_alloc(&vsi_ctx->sched.bw_t_info[tc], 3272 bw_alloc); 3273 break; 3274 default: 3275 return ICE_ERR_PARAM; 3276 } 3277 return ICE_SUCCESS; 3278 } 3279 3280 /** 3281 * ice_set_clear_cir_bw - set or clear CIR BW 3282 * @bw_t_info: bandwidth type information structure 3283 * @bw: bandwidth in Kbps - Kilo bits per sec 3284 * 3285 * Save or clear CIR bandwidth (BW) in the passed param bw_t_info. 3286 */ 3287 static void ice_set_clear_cir_bw(struct ice_bw_type_info *bw_t_info, u32 bw) 3288 { 3289 if (bw == ICE_SCHED_DFLT_BW) { 3290 ice_clear_bit(ICE_BW_TYPE_CIR, bw_t_info->bw_t_bitmap); 3291 bw_t_info->cir_bw.bw = 0; 3292 } else { 3293 /* Save type of BW information */ 3294 ice_set_bit(ICE_BW_TYPE_CIR, bw_t_info->bw_t_bitmap); 3295 bw_t_info->cir_bw.bw = bw; 3296 } 3297 } 3298 3299 /** 3300 * ice_set_clear_eir_bw - set or clear EIR BW 3301 * @bw_t_info: bandwidth type information structure 3302 * @bw: bandwidth in Kbps - Kilo bits per sec 3303 * 3304 * Save or clear EIR bandwidth (BW) in the passed param bw_t_info. 3305 */ 3306 static void ice_set_clear_eir_bw(struct ice_bw_type_info *bw_t_info, u32 bw) 3307 { 3308 if (bw == ICE_SCHED_DFLT_BW) { 3309 ice_clear_bit(ICE_BW_TYPE_EIR, bw_t_info->bw_t_bitmap); 3310 bw_t_info->eir_bw.bw = 0; 3311 } else { 3312 /* save EIR BW information */ 3313 ice_set_bit(ICE_BW_TYPE_EIR, bw_t_info->bw_t_bitmap); 3314 bw_t_info->eir_bw.bw = bw; 3315 } 3316 } 3317 3318 /** 3319 * ice_set_clear_shared_bw - set or clear shared BW 3320 * @bw_t_info: bandwidth type information structure 3321 * @bw: bandwidth in Kbps - Kilo bits per sec 3322 * 3323 * Save or clear shared bandwidth (BW) in the passed param bw_t_info. 3324 */ 3325 static void ice_set_clear_shared_bw(struct ice_bw_type_info *bw_t_info, u32 bw) 3326 { 3327 if (bw == ICE_SCHED_DFLT_BW) { 3328 ice_clear_bit(ICE_BW_TYPE_SHARED, bw_t_info->bw_t_bitmap); 3329 bw_t_info->shared_bw = 0; 3330 } else { 3331 /* save shared BW information */ 3332 ice_set_bit(ICE_BW_TYPE_SHARED, bw_t_info->bw_t_bitmap); 3333 bw_t_info->shared_bw = bw; 3334 } 3335 } 3336 3337 /** 3338 * ice_sched_save_vsi_bw - save VSI node's BW information 3339 * @pi: port information structure 3340 * @vsi_handle: sw VSI handle 3341 * @tc: traffic class 3342 * @rl_type: rate limit type min, max, or shared 3343 * @bw: bandwidth in Kbps - Kilo bits per sec 3344 * 3345 * Save BW information of VSI type node for post replay use. 3346 */ 3347 static enum ice_status 3348 ice_sched_save_vsi_bw(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 3349 enum ice_rl_type rl_type, u32 bw) 3350 { 3351 struct ice_vsi_ctx *vsi_ctx; 3352 3353 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 3354 return ICE_ERR_PARAM; 3355 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 3356 if (!vsi_ctx) 3357 return ICE_ERR_PARAM; 3358 switch (rl_type) { 3359 case ICE_MIN_BW: 3360 ice_set_clear_cir_bw(&vsi_ctx->sched.bw_t_info[tc], bw); 3361 break; 3362 case ICE_MAX_BW: 3363 ice_set_clear_eir_bw(&vsi_ctx->sched.bw_t_info[tc], bw); 3364 break; 3365 case ICE_SHARED_BW: 3366 ice_set_clear_shared_bw(&vsi_ctx->sched.bw_t_info[tc], bw); 3367 break; 3368 default: 3369 return ICE_ERR_PARAM; 3370 } 3371 return ICE_SUCCESS; 3372 } 3373 3374 /** 3375 * ice_set_clear_prio - set or clear priority information 3376 * @bw_t_info: bandwidth type information structure 3377 * @prio: priority to save 3378 * 3379 * Save or clear priority (prio) in the passed param bw_t_info. 3380 */ 3381 static void ice_set_clear_prio(struct ice_bw_type_info *bw_t_info, u8 prio) 3382 { 3383 bw_t_info->generic = prio; 3384 if (bw_t_info->generic) 3385 ice_set_bit(ICE_BW_TYPE_PRIO, bw_t_info->bw_t_bitmap); 3386 else 3387 ice_clear_bit(ICE_BW_TYPE_PRIO, bw_t_info->bw_t_bitmap); 3388 } 3389 3390 /** 3391 * ice_sched_save_vsi_prio - save VSI node's priority information 3392 * @pi: port information structure 3393 * @vsi_handle: Software VSI handle 3394 * @tc: traffic class 3395 * @prio: priority to save 3396 * 3397 * Save priority information of VSI type node for post replay use. 3398 */ 3399 static enum ice_status 3400 ice_sched_save_vsi_prio(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 3401 u8 prio) 3402 { 3403 struct ice_vsi_ctx *vsi_ctx; 3404 3405 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 3406 return ICE_ERR_PARAM; 3407 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 3408 if (!vsi_ctx) 3409 return ICE_ERR_PARAM; 3410 if (tc >= ICE_MAX_TRAFFIC_CLASS) 3411 return ICE_ERR_PARAM; 3412 ice_set_clear_prio(&vsi_ctx->sched.bw_t_info[tc], prio); 3413 return ICE_SUCCESS; 3414 } 3415 3416 /** 3417 * ice_sched_save_agg_bw_alloc - save aggregator node's BW alloc information 3418 * @pi: port information structure 3419 * @agg_id: node aggregator ID 3420 * @tc: traffic class 3421 * @rl_type: rate limit type min or max 3422 * @bw_alloc: bandwidth alloc information 3423 * 3424 * Save BW alloc information of AGG type node for post replay use. 3425 */ 3426 static enum ice_status 3427 ice_sched_save_agg_bw_alloc(struct ice_port_info *pi, u32 agg_id, u8 tc, 3428 enum ice_rl_type rl_type, u16 bw_alloc) 3429 { 3430 struct ice_sched_agg_info *agg_info; 3431 3432 agg_info = ice_get_agg_info(pi->hw, agg_id); 3433 if (!agg_info) 3434 return ICE_ERR_PARAM; 3435 if (!ice_is_tc_ena(agg_info->tc_bitmap[0], tc)) 3436 return ICE_ERR_PARAM; 3437 switch (rl_type) { 3438 case ICE_MIN_BW: 3439 ice_set_clear_cir_bw_alloc(&agg_info->bw_t_info[tc], bw_alloc); 3440 break; 3441 case ICE_MAX_BW: 3442 ice_set_clear_eir_bw_alloc(&agg_info->bw_t_info[tc], bw_alloc); 3443 break; 3444 default: 3445 return ICE_ERR_PARAM; 3446 } 3447 return ICE_SUCCESS; 3448 } 3449 3450 /** 3451 * ice_sched_save_agg_bw - save aggregator node's BW information 3452 * @pi: port information structure 3453 * @agg_id: node aggregator ID 3454 * @tc: traffic class 3455 * @rl_type: rate limit type min, max, or shared 3456 * @bw: bandwidth in Kbps - Kilo bits per sec 3457 * 3458 * Save BW information of AGG type node for post replay use. 3459 */ 3460 static enum ice_status 3461 ice_sched_save_agg_bw(struct ice_port_info *pi, u32 agg_id, u8 tc, 3462 enum ice_rl_type rl_type, u32 bw) 3463 { 3464 struct ice_sched_agg_info *agg_info; 3465 3466 agg_info = ice_get_agg_info(pi->hw, agg_id); 3467 if (!agg_info) 3468 return ICE_ERR_PARAM; 3469 if (!ice_is_tc_ena(agg_info->tc_bitmap[0], tc)) 3470 return ICE_ERR_PARAM; 3471 switch (rl_type) { 3472 case ICE_MIN_BW: 3473 ice_set_clear_cir_bw(&agg_info->bw_t_info[tc], bw); 3474 break; 3475 case ICE_MAX_BW: 3476 ice_set_clear_eir_bw(&agg_info->bw_t_info[tc], bw); 3477 break; 3478 case ICE_SHARED_BW: 3479 ice_set_clear_shared_bw(&agg_info->bw_t_info[tc], bw); 3480 break; 3481 default: 3482 return ICE_ERR_PARAM; 3483 } 3484 return ICE_SUCCESS; 3485 } 3486 3487 /** 3488 * ice_cfg_vsi_bw_lmt_per_tc - configure VSI BW limit per TC 3489 * @pi: port information structure 3490 * @vsi_handle: software VSI handle 3491 * @tc: traffic class 3492 * @rl_type: min or max 3493 * @bw: bandwidth in Kbps 3494 * 3495 * This function configures BW limit of VSI scheduling node based on TC 3496 * information. 3497 */ 3498 enum ice_status 3499 ice_cfg_vsi_bw_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 3500 enum ice_rl_type rl_type, u32 bw) 3501 { 3502 enum ice_status status; 3503 3504 status = ice_sched_set_node_bw_lmt_per_tc(pi, vsi_handle, 3505 ICE_AGG_TYPE_VSI, 3506 tc, rl_type, bw); 3507 if (!status) { 3508 ice_acquire_lock(&pi->sched_lock); 3509 status = ice_sched_save_vsi_bw(pi, vsi_handle, tc, rl_type, bw); 3510 ice_release_lock(&pi->sched_lock); 3511 } 3512 return status; 3513 } 3514 3515 /** 3516 * ice_cfg_vsi_bw_dflt_lmt_per_tc - configure default VSI BW limit per TC 3517 * @pi: port information structure 3518 * @vsi_handle: software VSI handle 3519 * @tc: traffic class 3520 * @rl_type: min or max 3521 * 3522 * This function configures default BW limit of VSI scheduling node based on TC 3523 * information. 3524 */ 3525 enum ice_status 3526 ice_cfg_vsi_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 3527 enum ice_rl_type rl_type) 3528 { 3529 enum ice_status status; 3530 3531 status = ice_sched_set_node_bw_lmt_per_tc(pi, vsi_handle, 3532 ICE_AGG_TYPE_VSI, 3533 tc, rl_type, 3534 ICE_SCHED_DFLT_BW); 3535 if (!status) { 3536 ice_acquire_lock(&pi->sched_lock); 3537 status = ice_sched_save_vsi_bw(pi, vsi_handle, tc, rl_type, 3538 ICE_SCHED_DFLT_BW); 3539 ice_release_lock(&pi->sched_lock); 3540 } 3541 return status; 3542 } 3543 3544 /** 3545 * ice_cfg_agg_bw_lmt_per_tc - configure aggregator BW limit per TC 3546 * @pi: port information structure 3547 * @agg_id: aggregator ID 3548 * @tc: traffic class 3549 * @rl_type: min or max 3550 * @bw: bandwidth in Kbps 3551 * 3552 * This function applies BW limit to aggregator scheduling node based on TC 3553 * information. 3554 */ 3555 enum ice_status 3556 ice_cfg_agg_bw_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc, 3557 enum ice_rl_type rl_type, u32 bw) 3558 { 3559 enum ice_status status; 3560 3561 status = ice_sched_set_node_bw_lmt_per_tc(pi, agg_id, ICE_AGG_TYPE_AGG, 3562 tc, rl_type, bw); 3563 if (!status) { 3564 ice_acquire_lock(&pi->sched_lock); 3565 status = ice_sched_save_agg_bw(pi, agg_id, tc, rl_type, bw); 3566 ice_release_lock(&pi->sched_lock); 3567 } 3568 return status; 3569 } 3570 3571 /** 3572 * ice_cfg_agg_bw_dflt_lmt_per_tc - configure aggregator BW default limit per TC 3573 * @pi: port information structure 3574 * @agg_id: aggregator ID 3575 * @tc: traffic class 3576 * @rl_type: min or max 3577 * 3578 * This function applies default BW limit to aggregator scheduling node based 3579 * on TC information. 3580 */ 3581 enum ice_status 3582 ice_cfg_agg_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc, 3583 enum ice_rl_type rl_type) 3584 { 3585 enum ice_status status; 3586 3587 status = ice_sched_set_node_bw_lmt_per_tc(pi, agg_id, ICE_AGG_TYPE_AGG, 3588 tc, rl_type, 3589 ICE_SCHED_DFLT_BW); 3590 if (!status) { 3591 ice_acquire_lock(&pi->sched_lock); 3592 status = ice_sched_save_agg_bw(pi, agg_id, tc, rl_type, 3593 ICE_SCHED_DFLT_BW); 3594 ice_release_lock(&pi->sched_lock); 3595 } 3596 return status; 3597 } 3598 3599 /** 3600 * ice_cfg_vsi_bw_shared_lmt - configure VSI BW shared limit 3601 * @pi: port information structure 3602 * @vsi_handle: software VSI handle 3603 * @min_bw: minimum bandwidth in Kbps 3604 * @max_bw: maximum bandwidth in Kbps 3605 * @shared_bw: shared bandwidth in Kbps 3606 * 3607 * Configure shared rate limiter(SRL) of all VSI type nodes across all traffic 3608 * classes for VSI matching handle. 3609 */ 3610 enum ice_status 3611 ice_cfg_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle, u32 min_bw, 3612 u32 max_bw, u32 shared_bw) 3613 { 3614 return ice_sched_set_vsi_bw_shared_lmt(pi, vsi_handle, min_bw, max_bw, 3615 shared_bw); 3616 } 3617 3618 /** 3619 * ice_cfg_vsi_bw_no_shared_lmt - configure VSI BW for no shared limiter 3620 * @pi: port information structure 3621 * @vsi_handle: software VSI handle 3622 * 3623 * This function removes the shared rate limiter(SRL) of all VSI type nodes 3624 * across all traffic classes for VSI matching handle. 3625 */ 3626 enum ice_status 3627 ice_cfg_vsi_bw_no_shared_lmt(struct ice_port_info *pi, u16 vsi_handle) 3628 { 3629 return ice_sched_set_vsi_bw_shared_lmt(pi, vsi_handle, 3630 ICE_SCHED_DFLT_BW, 3631 ICE_SCHED_DFLT_BW, 3632 ICE_SCHED_DFLT_BW); 3633 } 3634 3635 /** 3636 * ice_cfg_agg_bw_shared_lmt - configure aggregator BW shared limit 3637 * @pi: port information structure 3638 * @agg_id: aggregator ID 3639 * @min_bw: minimum bandwidth in Kbps 3640 * @max_bw: maximum bandwidth in Kbps 3641 * @shared_bw: shared bandwidth in Kbps 3642 * 3643 * This function configures the shared rate limiter(SRL) of all aggregator type 3644 * nodes across all traffic classes for aggregator matching agg_id. 3645 */ 3646 enum ice_status 3647 ice_cfg_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 min_bw, 3648 u32 max_bw, u32 shared_bw) 3649 { 3650 return ice_sched_set_agg_bw_shared_lmt(pi, agg_id, min_bw, max_bw, 3651 shared_bw); 3652 } 3653 3654 /** 3655 * ice_cfg_agg_bw_no_shared_lmt - configure aggregator BW for no shared limiter 3656 * @pi: port information structure 3657 * @agg_id: aggregator ID 3658 * 3659 * This function removes the shared rate limiter(SRL) of all aggregator type 3660 * nodes across all traffic classes for aggregator matching agg_id. 3661 */ 3662 enum ice_status 3663 ice_cfg_agg_bw_no_shared_lmt(struct ice_port_info *pi, u32 agg_id) 3664 { 3665 return ice_sched_set_agg_bw_shared_lmt(pi, agg_id, ICE_SCHED_DFLT_BW, 3666 ICE_SCHED_DFLT_BW, 3667 ICE_SCHED_DFLT_BW); 3668 } 3669 3670 /** 3671 * ice_cfg_agg_bw_shared_lmt_per_tc - config aggregator BW shared limit per tc 3672 * @pi: port information structure 3673 * @agg_id: aggregator ID 3674 * @tc: traffic class 3675 * @min_bw: minimum bandwidth in Kbps 3676 * @max_bw: maximum bandwidth in Kbps 3677 * @shared_bw: shared bandwidth in Kbps 3678 * 3679 * This function configures the shared rate limiter(SRL) of all aggregator type 3680 * nodes across all traffic classes for aggregator matching agg_id. 3681 */ 3682 enum ice_status 3683 ice_cfg_agg_bw_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc, 3684 u32 min_bw, u32 max_bw, u32 shared_bw) 3685 { 3686 return ice_sched_set_agg_bw_shared_lmt_per_tc(pi, agg_id, tc, min_bw, 3687 max_bw, shared_bw); 3688 } 3689 3690 /** 3691 * ice_cfg_agg_bw_no_shared_lmt_per_tc - cfg aggregator BW shared limit per tc 3692 * @pi: port information structure 3693 * @agg_id: aggregator ID 3694 * @tc: traffic class 3695 * 3696 * This function configures the shared rate limiter(SRL) of all aggregator type 3697 * nodes across all traffic classes for aggregator matching agg_id. 3698 */ 3699 enum ice_status 3700 ice_cfg_agg_bw_no_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc) 3701 { 3702 return ice_sched_set_agg_bw_shared_lmt_per_tc(pi, agg_id, tc, 3703 ICE_SCHED_DFLT_BW, 3704 ICE_SCHED_DFLT_BW, 3705 ICE_SCHED_DFLT_BW); 3706 } 3707 3708 /** 3709 * ice_cfg_vsi_q_priority - config VSI queue priority of node 3710 * @pi: port information structure 3711 * @num_qs: number of VSI queues 3712 * @q_ids: queue IDs array 3713 * @q_prio: queue priority array 3714 * 3715 * This function configures the queue node priority (Sibling Priority) of the 3716 * passed in VSI's queue(s) for a given traffic class (TC). 3717 */ 3718 enum ice_status 3719 ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 num_qs, u32 *q_ids, 3720 u8 *q_prio) 3721 { 3722 enum ice_status status = ICE_ERR_PARAM; 3723 u16 i; 3724 3725 ice_acquire_lock(&pi->sched_lock); 3726 3727 for (i = 0; i < num_qs; i++) { 3728 struct ice_sched_node *node; 3729 3730 node = ice_sched_find_node_by_teid(pi->root, q_ids[i]); 3731 if (!node || node->info.data.elem_type != 3732 ICE_AQC_ELEM_TYPE_LEAF) { 3733 status = ICE_ERR_PARAM; 3734 break; 3735 } 3736 /* Configure Priority */ 3737 status = ice_sched_cfg_sibl_node_prio(pi, node, q_prio[i]); 3738 if (status) 3739 break; 3740 } 3741 3742 ice_release_lock(&pi->sched_lock); 3743 return status; 3744 } 3745 3746 /** 3747 * ice_cfg_agg_vsi_priority_per_tc - config aggregator's VSI priority per TC 3748 * @pi: port information structure 3749 * @agg_id: Aggregator ID 3750 * @num_vsis: number of VSI(s) 3751 * @vsi_handle_arr: array of software VSI handles 3752 * @node_prio: pointer to node priority 3753 * @tc: traffic class 3754 * 3755 * This function configures the node priority (Sibling Priority) of the 3756 * passed in VSI's for a given traffic class (TC) of an Aggregator ID. 3757 */ 3758 enum ice_status 3759 ice_cfg_agg_vsi_priority_per_tc(struct ice_port_info *pi, u32 agg_id, 3760 u16 num_vsis, u16 *vsi_handle_arr, 3761 u8 *node_prio, u8 tc) 3762 { 3763 struct ice_sched_agg_vsi_info *agg_vsi_info; 3764 struct ice_sched_node *tc_node, *agg_node; 3765 enum ice_status status = ICE_ERR_PARAM; 3766 struct ice_sched_agg_info *agg_info; 3767 bool agg_id_present = false; 3768 struct ice_hw *hw = pi->hw; 3769 u16 i; 3770 3771 ice_acquire_lock(&pi->sched_lock); 3772 LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info, 3773 list_entry) 3774 if (agg_info->agg_id == agg_id) { 3775 agg_id_present = true; 3776 break; 3777 } 3778 if (!agg_id_present) 3779 goto exit_agg_priority_per_tc; 3780 3781 tc_node = ice_sched_get_tc_node(pi, tc); 3782 if (!tc_node) 3783 goto exit_agg_priority_per_tc; 3784 3785 agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); 3786 if (!agg_node) 3787 goto exit_agg_priority_per_tc; 3788 3789 if (num_vsis > hw->max_children[agg_node->tx_sched_layer]) 3790 goto exit_agg_priority_per_tc; 3791 3792 for (i = 0; i < num_vsis; i++) { 3793 struct ice_sched_node *vsi_node; 3794 bool vsi_handle_valid = false; 3795 u16 vsi_handle; 3796 3797 status = ICE_ERR_PARAM; 3798 vsi_handle = vsi_handle_arr[i]; 3799 if (!ice_is_vsi_valid(hw, vsi_handle)) 3800 goto exit_agg_priority_per_tc; 3801 /* Verify child nodes before applying settings */ 3802 LIST_FOR_EACH_ENTRY(agg_vsi_info, &agg_info->agg_vsi_list, 3803 ice_sched_agg_vsi_info, list_entry) 3804 if (agg_vsi_info->vsi_handle == vsi_handle) { 3805 vsi_handle_valid = true; 3806 break; 3807 } 3808 3809 if (!vsi_handle_valid) 3810 goto exit_agg_priority_per_tc; 3811 3812 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 3813 if (!vsi_node) 3814 goto exit_agg_priority_per_tc; 3815 3816 if (ice_sched_find_node_in_subtree(hw, agg_node, vsi_node)) { 3817 /* Configure Priority */ 3818 status = ice_sched_cfg_sibl_node_prio(pi, vsi_node, 3819 node_prio[i]); 3820 if (status) 3821 break; 3822 status = ice_sched_save_vsi_prio(pi, vsi_handle, tc, 3823 node_prio[i]); 3824 if (status) 3825 break; 3826 } 3827 } 3828 3829 exit_agg_priority_per_tc: 3830 ice_release_lock(&pi->sched_lock); 3831 return status; 3832 } 3833 3834 /** 3835 * ice_cfg_vsi_bw_alloc - config VSI BW alloc per TC 3836 * @pi: port information structure 3837 * @vsi_handle: software VSI handle 3838 * @ena_tcmap: enabled TC map 3839 * @rl_type: Rate limit type CIR/EIR 3840 * @bw_alloc: Array of BW alloc 3841 * 3842 * This function configures the BW allocation of the passed in VSI's 3843 * node(s) for enabled traffic class. 3844 */ 3845 enum ice_status 3846 ice_cfg_vsi_bw_alloc(struct ice_port_info *pi, u16 vsi_handle, u8 ena_tcmap, 3847 enum ice_rl_type rl_type, u8 *bw_alloc) 3848 { 3849 enum ice_status status = ICE_SUCCESS; 3850 u8 tc; 3851 3852 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 3853 return ICE_ERR_PARAM; 3854 3855 ice_acquire_lock(&pi->sched_lock); 3856 3857 /* Return success if no nodes are present across TC */ 3858 ice_for_each_traffic_class(tc) { 3859 struct ice_sched_node *tc_node, *vsi_node; 3860 3861 if (!ice_is_tc_ena(ena_tcmap, tc)) 3862 continue; 3863 3864 tc_node = ice_sched_get_tc_node(pi, tc); 3865 if (!tc_node) 3866 continue; 3867 3868 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 3869 if (!vsi_node) 3870 continue; 3871 3872 status = ice_sched_cfg_node_bw_alloc(pi->hw, vsi_node, rl_type, 3873 bw_alloc[tc]); 3874 if (status) 3875 break; 3876 status = ice_sched_save_vsi_bw_alloc(pi, vsi_handle, tc, 3877 rl_type, bw_alloc[tc]); 3878 if (status) 3879 break; 3880 } 3881 3882 ice_release_lock(&pi->sched_lock); 3883 return status; 3884 } 3885 3886 /** 3887 * ice_cfg_agg_bw_alloc - config aggregator BW alloc 3888 * @pi: port information structure 3889 * @agg_id: aggregator ID 3890 * @ena_tcmap: enabled TC map 3891 * @rl_type: rate limit type CIR/EIR 3892 * @bw_alloc: array of BW alloc 3893 * 3894 * This function configures the BW allocation of passed in aggregator for 3895 * enabled traffic class(s). 3896 */ 3897 enum ice_status 3898 ice_cfg_agg_bw_alloc(struct ice_port_info *pi, u32 agg_id, u8 ena_tcmap, 3899 enum ice_rl_type rl_type, u8 *bw_alloc) 3900 { 3901 struct ice_sched_agg_info *agg_info; 3902 bool agg_id_present = false; 3903 enum ice_status status = ICE_SUCCESS; 3904 struct ice_hw *hw = pi->hw; 3905 u8 tc; 3906 3907 ice_acquire_lock(&pi->sched_lock); 3908 LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info, 3909 list_entry) 3910 if (agg_info->agg_id == agg_id) { 3911 agg_id_present = true; 3912 break; 3913 } 3914 if (!agg_id_present) { 3915 status = ICE_ERR_PARAM; 3916 goto exit_cfg_agg_bw_alloc; 3917 } 3918 3919 /* Return success if no nodes are present across TC */ 3920 ice_for_each_traffic_class(tc) { 3921 struct ice_sched_node *tc_node, *agg_node; 3922 3923 if (!ice_is_tc_ena(ena_tcmap, tc)) 3924 continue; 3925 3926 tc_node = ice_sched_get_tc_node(pi, tc); 3927 if (!tc_node) 3928 continue; 3929 3930 agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); 3931 if (!agg_node) 3932 continue; 3933 3934 status = ice_sched_cfg_node_bw_alloc(hw, agg_node, rl_type, 3935 bw_alloc[tc]); 3936 if (status) 3937 break; 3938 status = ice_sched_save_agg_bw_alloc(pi, agg_id, tc, rl_type, 3939 bw_alloc[tc]); 3940 if (status) 3941 break; 3942 } 3943 3944 exit_cfg_agg_bw_alloc: 3945 ice_release_lock(&pi->sched_lock); 3946 return status; 3947 } 3948 3949 /** 3950 * ice_sched_calc_wakeup - calculate RL profile wakeup parameter 3951 * @hw: pointer to the HW struct 3952 * @bw: bandwidth in Kbps 3953 * 3954 * This function calculates the wakeup parameter of RL profile. 3955 */ 3956 static u16 ice_sched_calc_wakeup(struct ice_hw *hw, s32 bw) 3957 { 3958 s64 bytes_per_sec, wakeup_int, wakeup_a, wakeup_b, wakeup_f; 3959 s32 wakeup_f_int; 3960 u16 wakeup = 0; 3961 3962 /* Get the wakeup integer value */ 3963 bytes_per_sec = DIV_S64((s64)bw * 1000, BITS_PER_BYTE); 3964 wakeup_int = DIV_S64(hw->psm_clk_freq, bytes_per_sec); 3965 if (wakeup_int > 63) { 3966 wakeup = (u16)((1 << 15) | wakeup_int); 3967 } else { 3968 /* Calculate fraction value up to 4 decimals 3969 * Convert Integer value to a constant multiplier 3970 */ 3971 wakeup_b = (s64)ICE_RL_PROF_MULTIPLIER * wakeup_int; 3972 wakeup_a = DIV_S64((s64)ICE_RL_PROF_MULTIPLIER * 3973 hw->psm_clk_freq, bytes_per_sec); 3974 3975 /* Get Fraction value */ 3976 wakeup_f = wakeup_a - wakeup_b; 3977 3978 /* Round up the Fractional value via Ceil(Fractional value) */ 3979 if (wakeup_f > DIV_S64(ICE_RL_PROF_MULTIPLIER, 2)) 3980 wakeup_f += 1; 3981 3982 wakeup_f_int = (s32)DIV_S64(wakeup_f * ICE_RL_PROF_FRACTION, 3983 ICE_RL_PROF_MULTIPLIER); 3984 wakeup |= (u16)(wakeup_int << 9); 3985 wakeup |= (u16)(0x1ff & wakeup_f_int); 3986 } 3987 3988 return wakeup; 3989 } 3990 3991 /** 3992 * ice_sched_bw_to_rl_profile - convert BW to profile parameters 3993 * @hw: pointer to the HW struct 3994 * @bw: bandwidth in Kbps 3995 * @profile: profile parameters to return 3996 * 3997 * This function converts the BW to profile structure format. 3998 */ 3999 static enum ice_status 4000 ice_sched_bw_to_rl_profile(struct ice_hw *hw, u32 bw, 4001 struct ice_aqc_rl_profile_elem *profile) 4002 { 4003 enum ice_status status = ICE_ERR_PARAM; 4004 s64 bytes_per_sec, ts_rate, mv_tmp; 4005 bool found = false; 4006 s32 encode = 0; 4007 s64 mv = 0; 4008 s32 i; 4009 4010 /* Bw settings range is from 0.5Mb/sec to 100Gb/sec */ 4011 if (bw < ICE_SCHED_MIN_BW || bw > ICE_SCHED_MAX_BW) 4012 return status; 4013 4014 /* Bytes per second from Kbps */ 4015 bytes_per_sec = DIV_S64((s64)bw * 1000, BITS_PER_BYTE); 4016 4017 /* encode is 6 bits but really useful are 5 bits */ 4018 for (i = 0; i < 64; i++) { 4019 u64 pow_result = BIT_ULL(i); 4020 4021 ts_rate = DIV_S64((s64)hw->psm_clk_freq, 4022 pow_result * ICE_RL_PROF_TS_MULTIPLIER); 4023 if (ts_rate <= 0) 4024 continue; 4025 4026 /* Multiplier value */ 4027 mv_tmp = DIV_S64(bytes_per_sec * ICE_RL_PROF_MULTIPLIER, 4028 ts_rate); 4029 4030 /* Round to the nearest ICE_RL_PROF_MULTIPLIER */ 4031 mv = round_up_64bit(mv_tmp, ICE_RL_PROF_MULTIPLIER); 4032 4033 /* First multiplier value greater than the given 4034 * accuracy bytes 4035 */ 4036 if (mv > ICE_RL_PROF_ACCURACY_BYTES) { 4037 encode = i; 4038 found = true; 4039 break; 4040 } 4041 } 4042 if (found) { 4043 u16 wm; 4044 4045 wm = ice_sched_calc_wakeup(hw, bw); 4046 profile->rl_multiply = CPU_TO_LE16(mv); 4047 profile->wake_up_calc = CPU_TO_LE16(wm); 4048 profile->rl_encode = CPU_TO_LE16(encode); 4049 status = ICE_SUCCESS; 4050 } else { 4051 status = ICE_ERR_DOES_NOT_EXIST; 4052 } 4053 4054 return status; 4055 } 4056 4057 /** 4058 * ice_sched_add_rl_profile - add RL profile 4059 * @hw: pointer to the hardware structure 4060 * @rl_type: type of rate limit BW - min, max, or shared 4061 * @bw: bandwidth in Kbps - Kilo bits per sec 4062 * @layer_num: specifies in which layer to create profile 4063 * 4064 * This function first checks the existing list for corresponding BW 4065 * parameter. If it exists, it returns the associated profile otherwise 4066 * it creates a new rate limit profile for requested BW, and adds it to 4067 * the HW DB and local list. It returns the new profile or null on error. 4068 * The caller needs to hold the scheduler lock. 4069 */ 4070 static struct ice_aqc_rl_profile_info * 4071 ice_sched_add_rl_profile(struct ice_hw *hw, enum ice_rl_type rl_type, 4072 u32 bw, u8 layer_num) 4073 { 4074 struct ice_aqc_rl_profile_info *rl_prof_elem; 4075 u16 profiles_added = 0, num_profiles = 1; 4076 struct ice_aqc_rl_profile_elem *buf; 4077 enum ice_status status; 4078 u8 profile_type; 4079 4080 if (!hw || layer_num >= hw->num_tx_sched_layers) 4081 return NULL; 4082 switch (rl_type) { 4083 case ICE_MIN_BW: 4084 profile_type = ICE_AQC_RL_PROFILE_TYPE_CIR; 4085 break; 4086 case ICE_MAX_BW: 4087 profile_type = ICE_AQC_RL_PROFILE_TYPE_EIR; 4088 break; 4089 case ICE_SHARED_BW: 4090 profile_type = ICE_AQC_RL_PROFILE_TYPE_SRL; 4091 break; 4092 default: 4093 return NULL; 4094 } 4095 4096 LIST_FOR_EACH_ENTRY(rl_prof_elem, &hw->rl_prof_list[layer_num], 4097 ice_aqc_rl_profile_info, list_entry) 4098 if ((rl_prof_elem->profile.flags & ICE_AQC_RL_PROFILE_TYPE_M) == 4099 profile_type && rl_prof_elem->bw == bw) 4100 /* Return existing profile ID info */ 4101 return rl_prof_elem; 4102 4103 /* Create new profile ID */ 4104 rl_prof_elem = (struct ice_aqc_rl_profile_info *) 4105 ice_malloc(hw, sizeof(*rl_prof_elem)); 4106 4107 if (!rl_prof_elem) 4108 return NULL; 4109 4110 status = ice_sched_bw_to_rl_profile(hw, bw, &rl_prof_elem->profile); 4111 if (status != ICE_SUCCESS) 4112 goto exit_add_rl_prof; 4113 4114 rl_prof_elem->bw = bw; 4115 /* layer_num is zero relative, and fw expects level from 1 to 9 */ 4116 rl_prof_elem->profile.level = layer_num + 1; 4117 rl_prof_elem->profile.flags = profile_type; 4118 rl_prof_elem->profile.max_burst_size = CPU_TO_LE16(hw->max_burst_size); 4119 4120 /* Create new entry in HW DB */ 4121 buf = &rl_prof_elem->profile; 4122 status = ice_aq_add_rl_profile(hw, num_profiles, buf, sizeof(*buf), 4123 &profiles_added, NULL); 4124 if (status || profiles_added != num_profiles) 4125 goto exit_add_rl_prof; 4126 4127 /* Good entry - add in the list */ 4128 rl_prof_elem->prof_id_ref = 0; 4129 LIST_ADD(&rl_prof_elem->list_entry, &hw->rl_prof_list[layer_num]); 4130 return rl_prof_elem; 4131 4132 exit_add_rl_prof: 4133 ice_free(hw, rl_prof_elem); 4134 return NULL; 4135 } 4136 4137 /** 4138 * ice_sched_cfg_node_bw_lmt - configure node sched params 4139 * @hw: pointer to the HW struct 4140 * @node: sched node to configure 4141 * @rl_type: rate limit type CIR, EIR, or shared 4142 * @rl_prof_id: rate limit profile ID 4143 * 4144 * This function configures node element's BW limit. 4145 */ 4146 static enum ice_status 4147 ice_sched_cfg_node_bw_lmt(struct ice_hw *hw, struct ice_sched_node *node, 4148 enum ice_rl_type rl_type, u16 rl_prof_id) 4149 { 4150 struct ice_aqc_txsched_elem_data buf; 4151 struct ice_aqc_txsched_elem *data; 4152 4153 buf = node->info; 4154 data = &buf.data; 4155 switch (rl_type) { 4156 case ICE_MIN_BW: 4157 data->valid_sections |= ICE_AQC_ELEM_VALID_CIR; 4158 data->cir_bw.bw_profile_idx = CPU_TO_LE16(rl_prof_id); 4159 break; 4160 case ICE_MAX_BW: 4161 data->valid_sections |= ICE_AQC_ELEM_VALID_EIR; 4162 data->eir_bw.bw_profile_idx = CPU_TO_LE16(rl_prof_id); 4163 break; 4164 case ICE_SHARED_BW: 4165 data->valid_sections |= ICE_AQC_ELEM_VALID_SHARED; 4166 data->srl_id = CPU_TO_LE16(rl_prof_id); 4167 break; 4168 default: 4169 /* Unknown rate limit type */ 4170 return ICE_ERR_PARAM; 4171 } 4172 4173 /* Configure element */ 4174 return ice_sched_update_elem(hw, node, &buf); 4175 } 4176 4177 /** 4178 * ice_sched_get_node_rl_prof_id - get node's rate limit profile ID 4179 * @node: sched node 4180 * @rl_type: rate limit type 4181 * 4182 * If existing profile matches, it returns the corresponding rate 4183 * limit profile ID, otherwise it returns an invalid ID as error. 4184 */ 4185 static u16 4186 ice_sched_get_node_rl_prof_id(struct ice_sched_node *node, 4187 enum ice_rl_type rl_type) 4188 { 4189 u16 rl_prof_id = ICE_SCHED_INVAL_PROF_ID; 4190 struct ice_aqc_txsched_elem *data; 4191 4192 data = &node->info.data; 4193 switch (rl_type) { 4194 case ICE_MIN_BW: 4195 if (data->valid_sections & ICE_AQC_ELEM_VALID_CIR) 4196 rl_prof_id = LE16_TO_CPU(data->cir_bw.bw_profile_idx); 4197 break; 4198 case ICE_MAX_BW: 4199 if (data->valid_sections & ICE_AQC_ELEM_VALID_EIR) 4200 rl_prof_id = LE16_TO_CPU(data->eir_bw.bw_profile_idx); 4201 break; 4202 case ICE_SHARED_BW: 4203 if (data->valid_sections & ICE_AQC_ELEM_VALID_SHARED) 4204 rl_prof_id = LE16_TO_CPU(data->srl_id); 4205 break; 4206 default: 4207 break; 4208 } 4209 4210 return rl_prof_id; 4211 } 4212 4213 /** 4214 * ice_sched_get_rl_prof_layer - selects rate limit profile creation layer 4215 * @pi: port information structure 4216 * @rl_type: type of rate limit BW - min, max, or shared 4217 * @layer_index: layer index 4218 * 4219 * This function returns requested profile creation layer. 4220 */ 4221 static u8 4222 ice_sched_get_rl_prof_layer(struct ice_port_info *pi, enum ice_rl_type rl_type, 4223 u8 layer_index) 4224 { 4225 struct ice_hw *hw = pi->hw; 4226 4227 if (layer_index >= hw->num_tx_sched_layers) 4228 return ICE_SCHED_INVAL_LAYER_NUM; 4229 switch (rl_type) { 4230 case ICE_MIN_BW: 4231 if (hw->layer_info[layer_index].max_cir_rl_profiles) 4232 return layer_index; 4233 break; 4234 case ICE_MAX_BW: 4235 if (hw->layer_info[layer_index].max_eir_rl_profiles) 4236 return layer_index; 4237 break; 4238 case ICE_SHARED_BW: 4239 /* if current layer doesn't support SRL profile creation 4240 * then try a layer up or down. 4241 */ 4242 if (hw->layer_info[layer_index].max_srl_profiles) 4243 return layer_index; 4244 else if (layer_index < hw->num_tx_sched_layers - 1 && 4245 hw->layer_info[layer_index + 1].max_srl_profiles) 4246 return layer_index + 1; 4247 else if (layer_index > 0 && 4248 hw->layer_info[layer_index - 1].max_srl_profiles) 4249 return layer_index - 1; 4250 break; 4251 default: 4252 break; 4253 } 4254 return ICE_SCHED_INVAL_LAYER_NUM; 4255 } 4256 4257 /** 4258 * ice_sched_get_srl_node - get shared rate limit node 4259 * @node: tree node 4260 * @srl_layer: shared rate limit layer 4261 * 4262 * This function returns SRL node to be used for shared rate limit purpose. 4263 * The caller needs to hold scheduler lock. 4264 */ 4265 static struct ice_sched_node * 4266 ice_sched_get_srl_node(struct ice_sched_node *node, u8 srl_layer) 4267 { 4268 if (srl_layer > node->tx_sched_layer) 4269 return node->children[0]; 4270 else if (srl_layer < node->tx_sched_layer) 4271 /* Node can't be created without a parent. It will always 4272 * have a valid parent except root node. 4273 */ 4274 return node->parent; 4275 else 4276 return node; 4277 } 4278 4279 /** 4280 * ice_sched_rm_rl_profile - remove RL profile ID 4281 * @hw: pointer to the hardware structure 4282 * @layer_num: layer number where profiles are saved 4283 * @profile_type: profile type like EIR, CIR, or SRL 4284 * @profile_id: profile ID to remove 4285 * 4286 * This function removes rate limit profile from layer 'layer_num' of type 4287 * 'profile_type' and profile ID as 'profile_id'. The caller needs to hold 4288 * scheduler lock. 4289 */ 4290 static enum ice_status 4291 ice_sched_rm_rl_profile(struct ice_hw *hw, u8 layer_num, u8 profile_type, 4292 u16 profile_id) 4293 { 4294 struct ice_aqc_rl_profile_info *rl_prof_elem; 4295 enum ice_status status = ICE_SUCCESS; 4296 4297 if (!hw || layer_num >= hw->num_tx_sched_layers) 4298 return ICE_ERR_PARAM; 4299 /* Check the existing list for RL profile */ 4300 LIST_FOR_EACH_ENTRY(rl_prof_elem, &hw->rl_prof_list[layer_num], 4301 ice_aqc_rl_profile_info, list_entry) 4302 if ((rl_prof_elem->profile.flags & ICE_AQC_RL_PROFILE_TYPE_M) == 4303 profile_type && 4304 LE16_TO_CPU(rl_prof_elem->profile.profile_id) == 4305 profile_id) { 4306 if (rl_prof_elem->prof_id_ref) 4307 rl_prof_elem->prof_id_ref--; 4308 4309 /* Remove old profile ID from database */ 4310 status = ice_sched_del_rl_profile(hw, rl_prof_elem); 4311 if (status && status != ICE_ERR_IN_USE) 4312 ice_debug(hw, ICE_DBG_SCHED, "Remove rl profile failed\n"); 4313 break; 4314 } 4315 if (status == ICE_ERR_IN_USE) 4316 status = ICE_SUCCESS; 4317 return status; 4318 } 4319 4320 /** 4321 * ice_sched_set_node_bw_dflt - set node's bandwidth limit to default 4322 * @pi: port information structure 4323 * @node: pointer to node structure 4324 * @rl_type: rate limit type min, max, or shared 4325 * @layer_num: layer number where RL profiles are saved 4326 * 4327 * This function configures node element's BW rate limit profile ID of 4328 * type CIR, EIR, or SRL to default. This function needs to be called 4329 * with the scheduler lock held. 4330 */ 4331 static enum ice_status 4332 ice_sched_set_node_bw_dflt(struct ice_port_info *pi, 4333 struct ice_sched_node *node, 4334 enum ice_rl_type rl_type, u8 layer_num) 4335 { 4336 enum ice_status status; 4337 struct ice_hw *hw; 4338 u8 profile_type; 4339 u16 rl_prof_id; 4340 u16 old_id; 4341 4342 hw = pi->hw; 4343 switch (rl_type) { 4344 case ICE_MIN_BW: 4345 profile_type = ICE_AQC_RL_PROFILE_TYPE_CIR; 4346 rl_prof_id = ICE_SCHED_DFLT_RL_PROF_ID; 4347 break; 4348 case ICE_MAX_BW: 4349 profile_type = ICE_AQC_RL_PROFILE_TYPE_EIR; 4350 rl_prof_id = ICE_SCHED_DFLT_RL_PROF_ID; 4351 break; 4352 case ICE_SHARED_BW: 4353 profile_type = ICE_AQC_RL_PROFILE_TYPE_SRL; 4354 /* No SRL is configured for default case */ 4355 rl_prof_id = ICE_SCHED_NO_SHARED_RL_PROF_ID; 4356 break; 4357 default: 4358 return ICE_ERR_PARAM; 4359 } 4360 /* Save existing RL prof ID for later clean up */ 4361 old_id = ice_sched_get_node_rl_prof_id(node, rl_type); 4362 /* Configure BW scheduling parameters */ 4363 status = ice_sched_cfg_node_bw_lmt(hw, node, rl_type, rl_prof_id); 4364 if (status) 4365 return status; 4366 4367 /* Remove stale RL profile ID */ 4368 if (old_id == ICE_SCHED_DFLT_RL_PROF_ID || 4369 old_id == ICE_SCHED_INVAL_PROF_ID) 4370 return ICE_SUCCESS; 4371 4372 return ice_sched_rm_rl_profile(hw, layer_num, profile_type, old_id); 4373 } 4374 4375 /** 4376 * ice_sched_set_node_bw - set node's bandwidth 4377 * @pi: port information structure 4378 * @node: tree node 4379 * @rl_type: rate limit type min, max, or shared 4380 * @bw: bandwidth in Kbps - Kilo bits per sec 4381 * @layer_num: layer number 4382 * 4383 * This function adds new profile corresponding to requested BW, configures 4384 * node's RL profile ID of type CIR, EIR, or SRL, and removes old profile 4385 * ID from local database. The caller needs to hold scheduler lock. 4386 */ 4387 static enum ice_status 4388 ice_sched_set_node_bw(struct ice_port_info *pi, struct ice_sched_node *node, 4389 enum ice_rl_type rl_type, u32 bw, u8 layer_num) 4390 { 4391 struct ice_aqc_rl_profile_info *rl_prof_info; 4392 enum ice_status status = ICE_ERR_PARAM; 4393 struct ice_hw *hw = pi->hw; 4394 u16 old_id, rl_prof_id; 4395 4396 rl_prof_info = ice_sched_add_rl_profile(hw, rl_type, bw, layer_num); 4397 if (!rl_prof_info) 4398 return status; 4399 4400 rl_prof_id = LE16_TO_CPU(rl_prof_info->profile.profile_id); 4401 4402 /* Save existing RL prof ID for later clean up */ 4403 old_id = ice_sched_get_node_rl_prof_id(node, rl_type); 4404 /* Configure BW scheduling parameters */ 4405 status = ice_sched_cfg_node_bw_lmt(hw, node, rl_type, rl_prof_id); 4406 if (status) 4407 return status; 4408 4409 /* New changes has been applied */ 4410 /* Increment the profile ID reference count */ 4411 rl_prof_info->prof_id_ref++; 4412 4413 /* Check for old ID removal */ 4414 if ((old_id == ICE_SCHED_DFLT_RL_PROF_ID && rl_type != ICE_SHARED_BW) || 4415 old_id == ICE_SCHED_INVAL_PROF_ID || old_id == rl_prof_id) 4416 return ICE_SUCCESS; 4417 4418 return ice_sched_rm_rl_profile(hw, layer_num, 4419 rl_prof_info->profile.flags & 4420 ICE_AQC_RL_PROFILE_TYPE_M, old_id); 4421 } 4422 4423 /** 4424 * ice_sched_set_node_bw_lmt - set node's BW limit 4425 * @pi: port information structure 4426 * @node: tree node 4427 * @rl_type: rate limit type min, max, or shared 4428 * @bw: bandwidth in Kbps - Kilo bits per sec 4429 * 4430 * It updates node's BW limit parameters like BW RL profile ID of type CIR, 4431 * EIR, or SRL. The caller needs to hold scheduler lock. 4432 * 4433 * NOTE: Caller provides the correct SRL node in case of shared profile 4434 * settings. 4435 */ 4436 static enum ice_status 4437 ice_sched_set_node_bw_lmt(struct ice_port_info *pi, struct ice_sched_node *node, 4438 enum ice_rl_type rl_type, u32 bw) 4439 { 4440 struct ice_hw *hw; 4441 u8 layer_num; 4442 4443 if (!pi) 4444 return ICE_ERR_PARAM; 4445 hw = pi->hw; 4446 /* Remove unused RL profile IDs from HW and SW DB */ 4447 ice_sched_rm_unused_rl_prof(hw); 4448 4449 layer_num = ice_sched_get_rl_prof_layer(pi, rl_type, 4450 node->tx_sched_layer); 4451 if (layer_num >= hw->num_tx_sched_layers) 4452 return ICE_ERR_PARAM; 4453 4454 if (bw == ICE_SCHED_DFLT_BW) 4455 return ice_sched_set_node_bw_dflt(pi, node, rl_type, layer_num); 4456 return ice_sched_set_node_bw(pi, node, rl_type, bw, layer_num); 4457 } 4458 4459 /** 4460 * ice_sched_set_node_bw_dflt_lmt - set node's BW limit to default 4461 * @pi: port information structure 4462 * @node: pointer to node structure 4463 * @rl_type: rate limit type min, max, or shared 4464 * 4465 * This function configures node element's BW rate limit profile ID of 4466 * type CIR, EIR, or SRL to default. This function needs to be called 4467 * with the scheduler lock held. 4468 */ 4469 static enum ice_status 4470 ice_sched_set_node_bw_dflt_lmt(struct ice_port_info *pi, 4471 struct ice_sched_node *node, 4472 enum ice_rl_type rl_type) 4473 { 4474 return ice_sched_set_node_bw_lmt(pi, node, rl_type, 4475 ICE_SCHED_DFLT_BW); 4476 } 4477 4478 /** 4479 * ice_sched_validate_srl_node - Check node for SRL applicability 4480 * @node: sched node to configure 4481 * @sel_layer: selected SRL layer 4482 * 4483 * This function checks if the SRL can be applied to a selceted layer node on 4484 * behalf of the requested node (first argument). This function needs to be 4485 * called with scheduler lock held. 4486 */ 4487 static enum ice_status 4488 ice_sched_validate_srl_node(struct ice_sched_node *node, u8 sel_layer) 4489 { 4490 /* SRL profiles are not available on all layers. Check if the 4491 * SRL profile can be applied to a node above or below the 4492 * requested node. SRL configuration is possible only if the 4493 * selected layer's node has single child. 4494 */ 4495 if (sel_layer == node->tx_sched_layer || 4496 ((sel_layer == node->tx_sched_layer + 1) && 4497 node->num_children == 1) || 4498 ((sel_layer == node->tx_sched_layer - 1) && 4499 (node->parent && node->parent->num_children == 1))) 4500 return ICE_SUCCESS; 4501 4502 return ICE_ERR_CFG; 4503 } 4504 4505 /** 4506 * ice_sched_save_q_bw - save queue node's BW information 4507 * @q_ctx: queue context structure 4508 * @rl_type: rate limit type min, max, or shared 4509 * @bw: bandwidth in Kbps - Kilo bits per sec 4510 * 4511 * Save BW information of queue type node for post replay use. 4512 */ 4513 static enum ice_status 4514 ice_sched_save_q_bw(struct ice_q_ctx *q_ctx, enum ice_rl_type rl_type, u32 bw) 4515 { 4516 switch (rl_type) { 4517 case ICE_MIN_BW: 4518 ice_set_clear_cir_bw(&q_ctx->bw_t_info, bw); 4519 break; 4520 case ICE_MAX_BW: 4521 ice_set_clear_eir_bw(&q_ctx->bw_t_info, bw); 4522 break; 4523 case ICE_SHARED_BW: 4524 ice_set_clear_shared_bw(&q_ctx->bw_t_info, bw); 4525 break; 4526 default: 4527 return ICE_ERR_PARAM; 4528 } 4529 return ICE_SUCCESS; 4530 } 4531 4532 /** 4533 * ice_sched_set_q_bw_lmt - sets queue BW limit 4534 * @pi: port information structure 4535 * @vsi_handle: sw VSI handle 4536 * @tc: traffic class 4537 * @q_handle: software queue handle 4538 * @rl_type: min, max, or shared 4539 * @bw: bandwidth in Kbps 4540 * 4541 * This function sets BW limit of queue scheduling node. 4542 */ 4543 static enum ice_status 4544 ice_sched_set_q_bw_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 4545 u16 q_handle, enum ice_rl_type rl_type, u32 bw) 4546 { 4547 enum ice_status status = ICE_ERR_PARAM; 4548 struct ice_sched_node *node; 4549 struct ice_q_ctx *q_ctx; 4550 4551 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4552 return ICE_ERR_PARAM; 4553 ice_acquire_lock(&pi->sched_lock); 4554 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handle); 4555 if (!q_ctx) 4556 goto exit_q_bw_lmt; 4557 node = ice_sched_find_node_by_teid(pi->root, q_ctx->q_teid); 4558 if (!node) { 4559 ice_debug(pi->hw, ICE_DBG_SCHED, "Wrong q_teid\n"); 4560 goto exit_q_bw_lmt; 4561 } 4562 4563 /* Return error if it is not a leaf node */ 4564 if (node->info.data.elem_type != ICE_AQC_ELEM_TYPE_LEAF) 4565 goto exit_q_bw_lmt; 4566 4567 /* SRL bandwidth layer selection */ 4568 if (rl_type == ICE_SHARED_BW) { 4569 u8 sel_layer; /* selected layer */ 4570 4571 sel_layer = ice_sched_get_rl_prof_layer(pi, rl_type, 4572 node->tx_sched_layer); 4573 if (sel_layer >= pi->hw->num_tx_sched_layers) { 4574 status = ICE_ERR_PARAM; 4575 goto exit_q_bw_lmt; 4576 } 4577 status = ice_sched_validate_srl_node(node, sel_layer); 4578 if (status) 4579 goto exit_q_bw_lmt; 4580 } 4581 4582 if (bw == ICE_SCHED_DFLT_BW) 4583 status = ice_sched_set_node_bw_dflt_lmt(pi, node, rl_type); 4584 else 4585 status = ice_sched_set_node_bw_lmt(pi, node, rl_type, bw); 4586 4587 if (!status) 4588 status = ice_sched_save_q_bw(q_ctx, rl_type, bw); 4589 4590 exit_q_bw_lmt: 4591 ice_release_lock(&pi->sched_lock); 4592 return status; 4593 } 4594 4595 /** 4596 * ice_cfg_q_bw_lmt - configure queue BW limit 4597 * @pi: port information structure 4598 * @vsi_handle: sw VSI handle 4599 * @tc: traffic class 4600 * @q_handle: software queue handle 4601 * @rl_type: min, max, or shared 4602 * @bw: bandwidth in Kbps 4603 * 4604 * This function configures BW limit of queue scheduling node. 4605 */ 4606 enum ice_status 4607 ice_cfg_q_bw_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 4608 u16 q_handle, enum ice_rl_type rl_type, u32 bw) 4609 { 4610 return ice_sched_set_q_bw_lmt(pi, vsi_handle, tc, q_handle, rl_type, 4611 bw); 4612 } 4613 4614 /** 4615 * ice_cfg_q_bw_dflt_lmt - configure queue BW default limit 4616 * @pi: port information structure 4617 * @vsi_handle: sw VSI handle 4618 * @tc: traffic class 4619 * @q_handle: software queue handle 4620 * @rl_type: min, max, or shared 4621 * 4622 * This function configures BW default limit of queue scheduling node. 4623 */ 4624 enum ice_status 4625 ice_cfg_q_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 4626 u16 q_handle, enum ice_rl_type rl_type) 4627 { 4628 return ice_sched_set_q_bw_lmt(pi, vsi_handle, tc, q_handle, rl_type, 4629 ICE_SCHED_DFLT_BW); 4630 } 4631 4632 /** 4633 * ice_sched_save_tc_node_bw - save TC node BW limit 4634 * @pi: port information structure 4635 * @tc: TC number 4636 * @rl_type: min or max 4637 * @bw: bandwidth in Kbps 4638 * 4639 * This function saves the modified values of bandwidth settings for later 4640 * replay purpose (restore) after reset. 4641 */ 4642 static enum ice_status 4643 ice_sched_save_tc_node_bw(struct ice_port_info *pi, u8 tc, 4644 enum ice_rl_type rl_type, u32 bw) 4645 { 4646 if (tc >= ICE_MAX_TRAFFIC_CLASS) 4647 return ICE_ERR_PARAM; 4648 switch (rl_type) { 4649 case ICE_MIN_BW: 4650 ice_set_clear_cir_bw(&pi->tc_node_bw_t_info[tc], bw); 4651 break; 4652 case ICE_MAX_BW: 4653 ice_set_clear_eir_bw(&pi->tc_node_bw_t_info[tc], bw); 4654 break; 4655 case ICE_SHARED_BW: 4656 ice_set_clear_shared_bw(&pi->tc_node_bw_t_info[tc], bw); 4657 break; 4658 default: 4659 return ICE_ERR_PARAM; 4660 } 4661 return ICE_SUCCESS; 4662 } 4663 4664 /** 4665 * ice_sched_set_tc_node_bw_lmt - sets TC node BW limit 4666 * @pi: port information structure 4667 * @tc: TC number 4668 * @rl_type: min or max 4669 * @bw: bandwidth in Kbps 4670 * 4671 * This function configures bandwidth limit of TC node. 4672 */ 4673 static enum ice_status 4674 ice_sched_set_tc_node_bw_lmt(struct ice_port_info *pi, u8 tc, 4675 enum ice_rl_type rl_type, u32 bw) 4676 { 4677 enum ice_status status = ICE_ERR_PARAM; 4678 struct ice_sched_node *tc_node; 4679 4680 if (tc >= ICE_MAX_TRAFFIC_CLASS) 4681 return status; 4682 ice_acquire_lock(&pi->sched_lock); 4683 tc_node = ice_sched_get_tc_node(pi, tc); 4684 if (!tc_node) 4685 goto exit_set_tc_node_bw; 4686 if (bw == ICE_SCHED_DFLT_BW) 4687 status = ice_sched_set_node_bw_dflt_lmt(pi, tc_node, rl_type); 4688 else 4689 status = ice_sched_set_node_bw_lmt(pi, tc_node, rl_type, bw); 4690 if (!status) 4691 status = ice_sched_save_tc_node_bw(pi, tc, rl_type, bw); 4692 4693 exit_set_tc_node_bw: 4694 ice_release_lock(&pi->sched_lock); 4695 return status; 4696 } 4697 4698 /** 4699 * ice_cfg_tc_node_bw_lmt - configure TC node BW limit 4700 * @pi: port information structure 4701 * @tc: TC number 4702 * @rl_type: min or max 4703 * @bw: bandwidth in Kbps 4704 * 4705 * This function configures BW limit of TC node. 4706 * Note: The minimum guaranteed reservation is done via DCBX. 4707 */ 4708 enum ice_status 4709 ice_cfg_tc_node_bw_lmt(struct ice_port_info *pi, u8 tc, 4710 enum ice_rl_type rl_type, u32 bw) 4711 { 4712 return ice_sched_set_tc_node_bw_lmt(pi, tc, rl_type, bw); 4713 } 4714 4715 /** 4716 * ice_cfg_tc_node_bw_dflt_lmt - configure TC node BW default limit 4717 * @pi: port information structure 4718 * @tc: TC number 4719 * @rl_type: min or max 4720 * 4721 * This function configures BW default limit of TC node. 4722 */ 4723 enum ice_status 4724 ice_cfg_tc_node_bw_dflt_lmt(struct ice_port_info *pi, u8 tc, 4725 enum ice_rl_type rl_type) 4726 { 4727 return ice_sched_set_tc_node_bw_lmt(pi, tc, rl_type, ICE_SCHED_DFLT_BW); 4728 } 4729 4730 /** 4731 * ice_sched_save_tc_node_bw_alloc - save TC node's BW alloc information 4732 * @pi: port information structure 4733 * @tc: traffic class 4734 * @rl_type: rate limit type min or max 4735 * @bw_alloc: Bandwidth allocation information 4736 * 4737 * Save BW alloc information of VSI type node for post replay use. 4738 */ 4739 static enum ice_status 4740 ice_sched_save_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc, 4741 enum ice_rl_type rl_type, u16 bw_alloc) 4742 { 4743 if (tc >= ICE_MAX_TRAFFIC_CLASS) 4744 return ICE_ERR_PARAM; 4745 switch (rl_type) { 4746 case ICE_MIN_BW: 4747 ice_set_clear_cir_bw_alloc(&pi->tc_node_bw_t_info[tc], 4748 bw_alloc); 4749 break; 4750 case ICE_MAX_BW: 4751 ice_set_clear_eir_bw_alloc(&pi->tc_node_bw_t_info[tc], 4752 bw_alloc); 4753 break; 4754 default: 4755 return ICE_ERR_PARAM; 4756 } 4757 return ICE_SUCCESS; 4758 } 4759 4760 /** 4761 * ice_sched_set_tc_node_bw_alloc - set TC node BW alloc 4762 * @pi: port information structure 4763 * @tc: TC number 4764 * @rl_type: min or max 4765 * @bw_alloc: bandwidth alloc 4766 * 4767 * This function configures bandwidth alloc of TC node, also saves the 4768 * changed settings for replay purpose, and return success if it succeeds 4769 * in modifying bandwidth alloc setting. 4770 */ 4771 static enum ice_status 4772 ice_sched_set_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc, 4773 enum ice_rl_type rl_type, u8 bw_alloc) 4774 { 4775 enum ice_status status = ICE_ERR_PARAM; 4776 struct ice_sched_node *tc_node; 4777 4778 if (tc >= ICE_MAX_TRAFFIC_CLASS) 4779 return status; 4780 ice_acquire_lock(&pi->sched_lock); 4781 tc_node = ice_sched_get_tc_node(pi, tc); 4782 if (!tc_node) 4783 goto exit_set_tc_node_bw_alloc; 4784 status = ice_sched_cfg_node_bw_alloc(pi->hw, tc_node, rl_type, 4785 bw_alloc); 4786 if (status) 4787 goto exit_set_tc_node_bw_alloc; 4788 status = ice_sched_save_tc_node_bw_alloc(pi, tc, rl_type, bw_alloc); 4789 4790 exit_set_tc_node_bw_alloc: 4791 ice_release_lock(&pi->sched_lock); 4792 return status; 4793 } 4794 4795 /** 4796 * ice_cfg_tc_node_bw_alloc - configure TC node BW alloc 4797 * @pi: port information structure 4798 * @tc: TC number 4799 * @rl_type: min or max 4800 * @bw_alloc: bandwidth alloc 4801 * 4802 * This function configures BW limit of TC node. 4803 * Note: The minimum guaranteed reservation is done via DCBX. 4804 */ 4805 enum ice_status 4806 ice_cfg_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc, 4807 enum ice_rl_type rl_type, u8 bw_alloc) 4808 { 4809 return ice_sched_set_tc_node_bw_alloc(pi, tc, rl_type, bw_alloc); 4810 } 4811 4812 /** 4813 * ice_sched_set_agg_bw_dflt_lmt - set aggregator node's BW limit to default 4814 * @pi: port information structure 4815 * @vsi_handle: software VSI handle 4816 * 4817 * This function retrieves the aggregator ID based on VSI ID and TC, 4818 * and sets node's BW limit to default. This function needs to be 4819 * called with the scheduler lock held. 4820 */ 4821 enum ice_status 4822 ice_sched_set_agg_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle) 4823 { 4824 struct ice_vsi_ctx *vsi_ctx; 4825 enum ice_status status = ICE_SUCCESS; 4826 u8 tc; 4827 4828 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4829 return ICE_ERR_PARAM; 4830 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 4831 if (!vsi_ctx) 4832 return ICE_ERR_PARAM; 4833 4834 ice_for_each_traffic_class(tc) { 4835 struct ice_sched_node *node; 4836 4837 node = vsi_ctx->sched.ag_node[tc]; 4838 if (!node) 4839 continue; 4840 4841 /* Set min profile to default */ 4842 status = ice_sched_set_node_bw_dflt_lmt(pi, node, ICE_MIN_BW); 4843 if (status) 4844 break; 4845 4846 /* Set max profile to default */ 4847 status = ice_sched_set_node_bw_dflt_lmt(pi, node, ICE_MAX_BW); 4848 if (status) 4849 break; 4850 4851 /* Remove shared profile, if there is one */ 4852 status = ice_sched_set_node_bw_dflt_lmt(pi, node, 4853 ICE_SHARED_BW); 4854 if (status) 4855 break; 4856 } 4857 4858 return status; 4859 } 4860 4861 /** 4862 * ice_sched_get_node_by_id_type - get node from ID type 4863 * @pi: port information structure 4864 * @id: identifier 4865 * @agg_type: type of aggregator 4866 * @tc: traffic class 4867 * 4868 * This function returns node identified by ID of type aggregator, and 4869 * based on traffic class (TC). This function needs to be called with 4870 * the scheduler lock held. 4871 */ 4872 static struct ice_sched_node * 4873 ice_sched_get_node_by_id_type(struct ice_port_info *pi, u32 id, 4874 enum ice_agg_type agg_type, u8 tc) 4875 { 4876 struct ice_sched_node *node = NULL; 4877 4878 switch (agg_type) { 4879 case ICE_AGG_TYPE_VSI: { 4880 struct ice_vsi_ctx *vsi_ctx; 4881 u16 vsi_handle = (u16)id; 4882 4883 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4884 break; 4885 /* Get sched_vsi_info */ 4886 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 4887 if (!vsi_ctx) 4888 break; 4889 node = vsi_ctx->sched.vsi_node[tc]; 4890 break; 4891 } 4892 4893 case ICE_AGG_TYPE_AGG: { 4894 struct ice_sched_node *tc_node; 4895 4896 tc_node = ice_sched_get_tc_node(pi, tc); 4897 if (tc_node) 4898 node = ice_sched_get_agg_node(pi, tc_node, id); 4899 break; 4900 } 4901 4902 case ICE_AGG_TYPE_Q: 4903 /* The current implementation allows single queue to modify */ 4904 node = ice_sched_find_node_by_teid(pi->root, id); 4905 break; 4906 4907 case ICE_AGG_TYPE_QG: { 4908 struct ice_sched_node *child_node; 4909 4910 /* The current implementation allows single qg to modify */ 4911 child_node = ice_sched_find_node_by_teid(pi->root, id); 4912 if (!child_node) 4913 break; 4914 node = child_node->parent; 4915 break; 4916 } 4917 4918 default: 4919 break; 4920 } 4921 4922 return node; 4923 } 4924 4925 /** 4926 * ice_sched_set_node_bw_lmt_per_tc - set node BW limit per TC 4927 * @pi: port information structure 4928 * @id: ID (software VSI handle or AGG ID) 4929 * @agg_type: aggregator type (VSI or AGG type node) 4930 * @tc: traffic class 4931 * @rl_type: min or max 4932 * @bw: bandwidth in Kbps 4933 * 4934 * This function sets BW limit of VSI or Aggregator scheduling node 4935 * based on TC information from passed in argument BW. 4936 */ 4937 enum ice_status 4938 ice_sched_set_node_bw_lmt_per_tc(struct ice_port_info *pi, u32 id, 4939 enum ice_agg_type agg_type, u8 tc, 4940 enum ice_rl_type rl_type, u32 bw) 4941 { 4942 enum ice_status status = ICE_ERR_PARAM; 4943 struct ice_sched_node *node; 4944 4945 if (!pi) 4946 return status; 4947 4948 if (rl_type == ICE_UNKNOWN_BW) 4949 return status; 4950 4951 ice_acquire_lock(&pi->sched_lock); 4952 node = ice_sched_get_node_by_id_type(pi, id, agg_type, tc); 4953 if (!node) { 4954 ice_debug(pi->hw, ICE_DBG_SCHED, "Wrong id, agg type, or tc\n"); 4955 goto exit_set_node_bw_lmt_per_tc; 4956 } 4957 if (bw == ICE_SCHED_DFLT_BW) 4958 status = ice_sched_set_node_bw_dflt_lmt(pi, node, rl_type); 4959 else 4960 status = ice_sched_set_node_bw_lmt(pi, node, rl_type, bw); 4961 4962 exit_set_node_bw_lmt_per_tc: 4963 ice_release_lock(&pi->sched_lock); 4964 return status; 4965 } 4966 4967 /** 4968 * ice_sched_validate_vsi_srl_node - validate VSI SRL node 4969 * @pi: port information structure 4970 * @vsi_handle: software VSI handle 4971 * 4972 * This function validates SRL node of the VSI node if available SRL layer is 4973 * different than the VSI node layer on all TC(s).This function needs to be 4974 * called with scheduler lock held. 4975 */ 4976 static enum ice_status 4977 ice_sched_validate_vsi_srl_node(struct ice_port_info *pi, u16 vsi_handle) 4978 { 4979 u8 sel_layer = ICE_SCHED_INVAL_LAYER_NUM; 4980 u8 tc; 4981 4982 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4983 return ICE_ERR_PARAM; 4984 4985 /* Return success if no nodes are present across TC */ 4986 ice_for_each_traffic_class(tc) { 4987 struct ice_sched_node *tc_node, *vsi_node; 4988 enum ice_rl_type rl_type = ICE_SHARED_BW; 4989 enum ice_status status; 4990 4991 tc_node = ice_sched_get_tc_node(pi, tc); 4992 if (!tc_node) 4993 continue; 4994 4995 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 4996 if (!vsi_node) 4997 continue; 4998 4999 /* SRL bandwidth layer selection */ 5000 if (sel_layer == ICE_SCHED_INVAL_LAYER_NUM) { 5001 u8 node_layer = vsi_node->tx_sched_layer; 5002 u8 layer_num; 5003 5004 layer_num = ice_sched_get_rl_prof_layer(pi, rl_type, 5005 node_layer); 5006 if (layer_num >= pi->hw->num_tx_sched_layers) 5007 return ICE_ERR_PARAM; 5008 sel_layer = layer_num; 5009 } 5010 5011 status = ice_sched_validate_srl_node(vsi_node, sel_layer); 5012 if (status) 5013 return status; 5014 } 5015 return ICE_SUCCESS; 5016 } 5017 5018 /** 5019 * ice_sched_set_save_vsi_srl_node_bw - set VSI shared limit values 5020 * @pi: port information structure 5021 * @vsi_handle: software VSI handle 5022 * @tc: traffic class 5023 * @srl_node: sched node to configure 5024 * @rl_type: rate limit type minimum, maximum, or shared 5025 * @bw: minimum, maximum, or shared bandwidth in Kbps 5026 * 5027 * Configure shared rate limiter(SRL) of VSI type nodes across given traffic 5028 * class, and saves those value for later use for replaying purposes. The 5029 * caller holds the scheduler lock. 5030 */ 5031 static enum ice_status 5032 ice_sched_set_save_vsi_srl_node_bw(struct ice_port_info *pi, u16 vsi_handle, 5033 u8 tc, struct ice_sched_node *srl_node, 5034 enum ice_rl_type rl_type, u32 bw) 5035 { 5036 enum ice_status status; 5037 5038 if (bw == ICE_SCHED_DFLT_BW) { 5039 status = ice_sched_set_node_bw_dflt_lmt(pi, srl_node, rl_type); 5040 } else { 5041 status = ice_sched_set_node_bw_lmt(pi, srl_node, rl_type, bw); 5042 if (status) 5043 return status; 5044 status = ice_sched_save_vsi_bw(pi, vsi_handle, tc, rl_type, bw); 5045 } 5046 return status; 5047 } 5048 5049 /** 5050 * ice_sched_set_vsi_node_srl_per_tc - set VSI node BW shared limit for tc 5051 * @pi: port information structure 5052 * @vsi_handle: software VSI handle 5053 * @tc: traffic class 5054 * @min_bw: minimum bandwidth in Kbps 5055 * @max_bw: maximum bandwidth in Kbps 5056 * @shared_bw: shared bandwidth in Kbps 5057 * 5058 * Configure shared rate limiter(SRL) of VSI type nodes across requested 5059 * traffic class for VSI matching handle. When BW value of ICE_SCHED_DFLT_BW 5060 * is passed, it removes the corresponding bw from the node. The caller 5061 * holds scheduler lock. 5062 */ 5063 static enum ice_status 5064 ice_sched_set_vsi_node_srl_per_tc(struct ice_port_info *pi, u16 vsi_handle, 5065 u8 tc, u32 min_bw, u32 max_bw, u32 shared_bw) 5066 { 5067 struct ice_sched_node *tc_node, *vsi_node, *cfg_node; 5068 enum ice_status status; 5069 u8 layer_num; 5070 5071 tc_node = ice_sched_get_tc_node(pi, tc); 5072 if (!tc_node) 5073 return ICE_ERR_CFG; 5074 5075 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 5076 if (!vsi_node) 5077 return ICE_ERR_CFG; 5078 5079 layer_num = ice_sched_get_rl_prof_layer(pi, ICE_SHARED_BW, 5080 vsi_node->tx_sched_layer); 5081 if (layer_num >= pi->hw->num_tx_sched_layers) 5082 return ICE_ERR_PARAM; 5083 5084 /* SRL node may be different */ 5085 cfg_node = ice_sched_get_srl_node(vsi_node, layer_num); 5086 if (!cfg_node) 5087 return ICE_ERR_CFG; 5088 5089 status = ice_sched_set_save_vsi_srl_node_bw(pi, vsi_handle, tc, 5090 cfg_node, ICE_MIN_BW, 5091 min_bw); 5092 if (status) 5093 return status; 5094 5095 status = ice_sched_set_save_vsi_srl_node_bw(pi, vsi_handle, tc, 5096 cfg_node, ICE_MAX_BW, 5097 max_bw); 5098 if (status) 5099 return status; 5100 5101 return ice_sched_set_save_vsi_srl_node_bw(pi, vsi_handle, tc, cfg_node, 5102 ICE_SHARED_BW, shared_bw); 5103 } 5104 5105 /** 5106 * ice_sched_set_vsi_bw_shared_lmt - set VSI BW shared limit 5107 * @pi: port information structure 5108 * @vsi_handle: software VSI handle 5109 * @min_bw: minimum bandwidth in Kbps 5110 * @max_bw: maximum bandwidth in Kbps 5111 * @shared_bw: shared bandwidth in Kbps 5112 * 5113 * Configure shared rate limiter(SRL) of all VSI type nodes across all traffic 5114 * classes for VSI matching handle. When BW value of ICE_SCHED_DFLT_BW is 5115 * passed, it removes those value(s) from the node. 5116 */ 5117 enum ice_status 5118 ice_sched_set_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle, 5119 u32 min_bw, u32 max_bw, u32 shared_bw) 5120 { 5121 enum ice_status status = ICE_SUCCESS; 5122 u8 tc; 5123 5124 if (!pi) 5125 return ICE_ERR_PARAM; 5126 5127 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 5128 return ICE_ERR_PARAM; 5129 5130 ice_acquire_lock(&pi->sched_lock); 5131 status = ice_sched_validate_vsi_srl_node(pi, vsi_handle); 5132 if (status) 5133 goto exit_set_vsi_bw_shared_lmt; 5134 /* Return success if no nodes are present across TC */ 5135 ice_for_each_traffic_class(tc) { 5136 struct ice_sched_node *tc_node, *vsi_node; 5137 5138 tc_node = ice_sched_get_tc_node(pi, tc); 5139 if (!tc_node) 5140 continue; 5141 5142 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 5143 if (!vsi_node) 5144 continue; 5145 5146 status = ice_sched_set_vsi_node_srl_per_tc(pi, vsi_handle, tc, 5147 min_bw, max_bw, 5148 shared_bw); 5149 if (status) 5150 break; 5151 } 5152 5153 exit_set_vsi_bw_shared_lmt: 5154 ice_release_lock(&pi->sched_lock); 5155 return status; 5156 } 5157 5158 /** 5159 * ice_sched_validate_agg_srl_node - validate AGG SRL node 5160 * @pi: port information structure 5161 * @agg_id: aggregator ID 5162 * 5163 * This function validates SRL node of the AGG node if available SRL layer is 5164 * different than the AGG node layer on all TC(s).This function needs to be 5165 * called with scheduler lock held. 5166 */ 5167 static enum ice_status 5168 ice_sched_validate_agg_srl_node(struct ice_port_info *pi, u32 agg_id) 5169 { 5170 u8 sel_layer = ICE_SCHED_INVAL_LAYER_NUM; 5171 struct ice_sched_agg_info *agg_info; 5172 bool agg_id_present = false; 5173 enum ice_status status = ICE_SUCCESS; 5174 u8 tc; 5175 5176 LIST_FOR_EACH_ENTRY(agg_info, &pi->hw->agg_list, ice_sched_agg_info, 5177 list_entry) 5178 if (agg_info->agg_id == agg_id) { 5179 agg_id_present = true; 5180 break; 5181 } 5182 if (!agg_id_present) 5183 return ICE_ERR_PARAM; 5184 /* Return success if no nodes are present across TC */ 5185 ice_for_each_traffic_class(tc) { 5186 struct ice_sched_node *tc_node, *agg_node; 5187 enum ice_rl_type rl_type = ICE_SHARED_BW; 5188 5189 tc_node = ice_sched_get_tc_node(pi, tc); 5190 if (!tc_node) 5191 continue; 5192 5193 agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); 5194 if (!agg_node) 5195 continue; 5196 /* SRL bandwidth layer selection */ 5197 if (sel_layer == ICE_SCHED_INVAL_LAYER_NUM) { 5198 u8 node_layer = agg_node->tx_sched_layer; 5199 u8 layer_num; 5200 5201 layer_num = ice_sched_get_rl_prof_layer(pi, rl_type, 5202 node_layer); 5203 if (layer_num >= pi->hw->num_tx_sched_layers) 5204 return ICE_ERR_PARAM; 5205 sel_layer = layer_num; 5206 } 5207 5208 status = ice_sched_validate_srl_node(agg_node, sel_layer); 5209 if (status) 5210 break; 5211 } 5212 return status; 5213 } 5214 5215 /** 5216 * ice_sched_validate_agg_id - Validate aggregator id 5217 * @pi: port information structure 5218 * @agg_id: aggregator ID 5219 * 5220 * This function validates aggregator id. Caller holds the scheduler lock. 5221 */ 5222 static enum ice_status 5223 ice_sched_validate_agg_id(struct ice_port_info *pi, u32 agg_id) 5224 { 5225 struct ice_sched_agg_info *agg_info; 5226 struct ice_sched_agg_info *tmp; 5227 bool agg_id_present = false; 5228 enum ice_status status; 5229 5230 status = ice_sched_validate_agg_srl_node(pi, agg_id); 5231 if (status) 5232 return status; 5233 5234 LIST_FOR_EACH_ENTRY_SAFE(agg_info, tmp, &pi->hw->agg_list, 5235 ice_sched_agg_info, list_entry) 5236 if (agg_info->agg_id == agg_id) { 5237 agg_id_present = true; 5238 break; 5239 } 5240 5241 if (!agg_id_present) 5242 return ICE_ERR_PARAM; 5243 5244 return ICE_SUCCESS; 5245 } 5246 5247 /** 5248 * ice_sched_set_save_agg_srl_node_bw - set aggregator shared limit values 5249 * @pi: port information structure 5250 * @agg_id: aggregator ID 5251 * @tc: traffic class 5252 * @srl_node: sched node to configure 5253 * @rl_type: rate limit type minimum, maximum, or shared 5254 * @bw: minimum, maximum, or shared bandwidth in Kbps 5255 * 5256 * Configure shared rate limiter(SRL) of aggregator type nodes across 5257 * requested traffic class, and saves those value for later use for 5258 * replaying purposes. The caller holds the scheduler lock. 5259 */ 5260 static enum ice_status 5261 ice_sched_set_save_agg_srl_node_bw(struct ice_port_info *pi, u32 agg_id, u8 tc, 5262 struct ice_sched_node *srl_node, 5263 enum ice_rl_type rl_type, u32 bw) 5264 { 5265 enum ice_status status; 5266 5267 if (bw == ICE_SCHED_DFLT_BW) { 5268 status = ice_sched_set_node_bw_dflt_lmt(pi, srl_node, rl_type); 5269 } else { 5270 status = ice_sched_set_node_bw_lmt(pi, srl_node, rl_type, bw); 5271 if (status) 5272 return status; 5273 status = ice_sched_save_agg_bw(pi, agg_id, tc, rl_type, bw); 5274 } 5275 return status; 5276 } 5277 5278 /** 5279 * ice_sched_set_agg_node_srl_per_tc - set aggregator SRL per tc 5280 * @pi: port information structure 5281 * @agg_id: aggregator ID 5282 * @tc: traffic class 5283 * @min_bw: minimum bandwidth in Kbps 5284 * @max_bw: maximum bandwidth in Kbps 5285 * @shared_bw: shared bandwidth in Kbps 5286 * 5287 * This function configures the shared rate limiter(SRL) of aggregator type 5288 * node for a given traffic class for aggregator matching agg_id. When BW 5289 * value of ICE_SCHED_DFLT_BW is passed, it removes SRL from the node. Caller 5290 * holds the scheduler lock. 5291 */ 5292 static enum ice_status 5293 ice_sched_set_agg_node_srl_per_tc(struct ice_port_info *pi, u32 agg_id, 5294 u8 tc, u32 min_bw, u32 max_bw, u32 shared_bw) 5295 { 5296 struct ice_sched_node *tc_node, *agg_node, *cfg_node; 5297 enum ice_rl_type rl_type = ICE_SHARED_BW; 5298 enum ice_status status = ICE_ERR_CFG; 5299 u8 layer_num; 5300 5301 tc_node = ice_sched_get_tc_node(pi, tc); 5302 if (!tc_node) 5303 return ICE_ERR_CFG; 5304 5305 agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); 5306 if (!agg_node) 5307 return ICE_ERR_CFG; 5308 5309 layer_num = ice_sched_get_rl_prof_layer(pi, rl_type, 5310 agg_node->tx_sched_layer); 5311 if (layer_num >= pi->hw->num_tx_sched_layers) 5312 return ICE_ERR_PARAM; 5313 5314 /* SRL node may be different */ 5315 cfg_node = ice_sched_get_srl_node(agg_node, layer_num); 5316 if (!cfg_node) 5317 return ICE_ERR_CFG; 5318 5319 status = ice_sched_set_save_agg_srl_node_bw(pi, agg_id, tc, cfg_node, 5320 ICE_MIN_BW, min_bw); 5321 if (status) 5322 return status; 5323 5324 status = ice_sched_set_save_agg_srl_node_bw(pi, agg_id, tc, cfg_node, 5325 ICE_MAX_BW, max_bw); 5326 if (status) 5327 return status; 5328 5329 status = ice_sched_set_save_agg_srl_node_bw(pi, agg_id, tc, cfg_node, 5330 ICE_SHARED_BW, shared_bw); 5331 return status; 5332 } 5333 5334 /** 5335 * ice_sched_set_agg_bw_shared_lmt - set aggregator BW shared limit 5336 * @pi: port information structure 5337 * @agg_id: aggregator ID 5338 * @min_bw: minimum bandwidth in Kbps 5339 * @max_bw: maximum bandwidth in Kbps 5340 * @shared_bw: shared bandwidth in Kbps 5341 * 5342 * This function configures the shared rate limiter(SRL) of all aggregator type 5343 * nodes across all traffic classes for aggregator matching agg_id. When 5344 * BW value of ICE_SCHED_DFLT_BW is passed, it removes SRL from the 5345 * node(s). 5346 */ 5347 enum ice_status 5348 ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, 5349 u32 min_bw, u32 max_bw, u32 shared_bw) 5350 { 5351 enum ice_status status; 5352 u8 tc; 5353 5354 if (!pi) 5355 return ICE_ERR_PARAM; 5356 5357 ice_acquire_lock(&pi->sched_lock); 5358 status = ice_sched_validate_agg_id(pi, agg_id); 5359 if (status) 5360 goto exit_agg_bw_shared_lmt; 5361 5362 /* Return success if no nodes are present across TC */ 5363 ice_for_each_traffic_class(tc) { 5364 struct ice_sched_node *tc_node, *agg_node; 5365 5366 tc_node = ice_sched_get_tc_node(pi, tc); 5367 if (!tc_node) 5368 continue; 5369 5370 agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); 5371 if (!agg_node) 5372 continue; 5373 5374 status = ice_sched_set_agg_node_srl_per_tc(pi, agg_id, tc, 5375 min_bw, max_bw, 5376 shared_bw); 5377 if (status) 5378 break; 5379 } 5380 5381 exit_agg_bw_shared_lmt: 5382 ice_release_lock(&pi->sched_lock); 5383 return status; 5384 } 5385 5386 /** 5387 * ice_sched_set_agg_bw_shared_lmt_per_tc - set aggregator BW shared lmt per tc 5388 * @pi: port information structure 5389 * @agg_id: aggregator ID 5390 * @tc: traffic class 5391 * @min_bw: minimum bandwidth in Kbps 5392 * @max_bw: maximum bandwidth in Kbps 5393 * @shared_bw: shared bandwidth in Kbps 5394 * 5395 * This function configures the shared rate limiter(SRL) of aggregator type 5396 * node for a given traffic class for aggregator matching agg_id. When BW 5397 * value of ICE_SCHED_DFLT_BW is passed, it removes SRL from the node. 5398 */ 5399 enum ice_status 5400 ice_sched_set_agg_bw_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, 5401 u8 tc, u32 min_bw, u32 max_bw, 5402 u32 shared_bw) 5403 { 5404 enum ice_status status; 5405 5406 if (!pi) 5407 return ICE_ERR_PARAM; 5408 ice_acquire_lock(&pi->sched_lock); 5409 status = ice_sched_validate_agg_id(pi, agg_id); 5410 if (status) 5411 goto exit_agg_bw_shared_lmt_per_tc; 5412 5413 status = ice_sched_set_agg_node_srl_per_tc(pi, agg_id, tc, min_bw, 5414 max_bw, shared_bw); 5415 5416 exit_agg_bw_shared_lmt_per_tc: 5417 ice_release_lock(&pi->sched_lock); 5418 return status; 5419 } 5420 5421 /** 5422 * ice_sched_cfg_sibl_node_prio - configure node sibling priority 5423 * @pi: port information structure 5424 * @node: sched node to configure 5425 * @priority: sibling priority 5426 * 5427 * This function configures node element's sibling priority only. This 5428 * function needs to be called with scheduler lock held. 5429 */ 5430 enum ice_status 5431 ice_sched_cfg_sibl_node_prio(struct ice_port_info *pi, 5432 struct ice_sched_node *node, u8 priority) 5433 { 5434 struct ice_aqc_txsched_elem_data buf; 5435 struct ice_aqc_txsched_elem *data; 5436 struct ice_hw *hw = pi->hw; 5437 enum ice_status status; 5438 5439 if (!hw) 5440 return ICE_ERR_PARAM; 5441 buf = node->info; 5442 data = &buf.data; 5443 data->valid_sections |= ICE_AQC_ELEM_VALID_GENERIC; 5444 priority = (priority << ICE_AQC_ELEM_GENERIC_PRIO_S) & 5445 ICE_AQC_ELEM_GENERIC_PRIO_M; 5446 data->generic &= ~ICE_AQC_ELEM_GENERIC_PRIO_M; 5447 data->generic |= priority; 5448 5449 /* Configure element */ 5450 status = ice_sched_update_elem(hw, node, &buf); 5451 return status; 5452 } 5453 5454 /** 5455 * ice_cfg_rl_burst_size - Set burst size value 5456 * @hw: pointer to the HW struct 5457 * @bytes: burst size in bytes 5458 * 5459 * This function configures/set the burst size to requested new value. The new 5460 * burst size value is used for future rate limit calls. It doesn't change the 5461 * existing or previously created RL profiles. 5462 */ 5463 enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes) 5464 { 5465 u16 burst_size_to_prog; 5466 5467 if (bytes < ICE_MIN_BURST_SIZE_ALLOWED || 5468 bytes > ICE_MAX_BURST_SIZE_ALLOWED) 5469 return ICE_ERR_PARAM; 5470 if (ice_round_to_num(bytes, 64) <= 5471 ICE_MAX_BURST_SIZE_64_BYTE_GRANULARITY) { 5472 /* 64 byte granularity case */ 5473 /* Disable MSB granularity bit */ 5474 burst_size_to_prog = ICE_64_BYTE_GRANULARITY; 5475 /* round number to nearest 64 byte granularity */ 5476 bytes = ice_round_to_num(bytes, 64); 5477 /* The value is in 64 byte chunks */ 5478 burst_size_to_prog |= (u16)(bytes / 64); 5479 } else { 5480 /* k bytes granularity case */ 5481 /* Enable MSB granularity bit */ 5482 burst_size_to_prog = ICE_KBYTE_GRANULARITY; 5483 /* round number to nearest 1024 granularity */ 5484 bytes = ice_round_to_num(bytes, 1024); 5485 /* check rounding doesn't go beyond allowed */ 5486 if (bytes > ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY) 5487 bytes = ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY; 5488 /* The value is in k bytes */ 5489 burst_size_to_prog |= (u16)(bytes / 1024); 5490 } 5491 hw->max_burst_size = burst_size_to_prog; 5492 return ICE_SUCCESS; 5493 } 5494 5495 /** 5496 * ice_sched_replay_node_prio - re-configure node priority 5497 * @hw: pointer to the HW struct 5498 * @node: sched node to configure 5499 * @priority: priority value 5500 * 5501 * This function configures node element's priority value. It 5502 * needs to be called with scheduler lock held. 5503 */ 5504 static enum ice_status 5505 ice_sched_replay_node_prio(struct ice_hw *hw, struct ice_sched_node *node, 5506 u8 priority) 5507 { 5508 struct ice_aqc_txsched_elem_data buf; 5509 struct ice_aqc_txsched_elem *data; 5510 enum ice_status status; 5511 5512 buf = node->info; 5513 data = &buf.data; 5514 data->valid_sections |= ICE_AQC_ELEM_VALID_GENERIC; 5515 data->generic = priority; 5516 5517 /* Configure element */ 5518 status = ice_sched_update_elem(hw, node, &buf); 5519 return status; 5520 } 5521 5522 /** 5523 * ice_sched_replay_node_bw - replay node(s) BW 5524 * @hw: pointer to the HW struct 5525 * @node: sched node to configure 5526 * @bw_t_info: BW type information 5527 * 5528 * This function restores node's BW from bw_t_info. The caller needs 5529 * to hold the scheduler lock. 5530 */ 5531 static enum ice_status 5532 ice_sched_replay_node_bw(struct ice_hw *hw, struct ice_sched_node *node, 5533 struct ice_bw_type_info *bw_t_info) 5534 { 5535 struct ice_port_info *pi = hw->port_info; 5536 enum ice_status status = ICE_ERR_PARAM; 5537 u16 bw_alloc; 5538 5539 if (!node) 5540 return status; 5541 if (!ice_is_any_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_CNT)) 5542 return ICE_SUCCESS; 5543 if (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_PRIO)) { 5544 status = ice_sched_replay_node_prio(hw, node, 5545 bw_t_info->generic); 5546 if (status) 5547 return status; 5548 } 5549 if (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_CIR)) { 5550 status = ice_sched_set_node_bw_lmt(pi, node, ICE_MIN_BW, 5551 bw_t_info->cir_bw.bw); 5552 if (status) 5553 return status; 5554 } 5555 if (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_CIR_WT)) { 5556 bw_alloc = bw_t_info->cir_bw.bw_alloc; 5557 status = ice_sched_cfg_node_bw_alloc(hw, node, ICE_MIN_BW, 5558 bw_alloc); 5559 if (status) 5560 return status; 5561 } 5562 if (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_EIR)) { 5563 status = ice_sched_set_node_bw_lmt(pi, node, ICE_MAX_BW, 5564 bw_t_info->eir_bw.bw); 5565 if (status) 5566 return status; 5567 } 5568 if (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_EIR_WT)) { 5569 bw_alloc = bw_t_info->eir_bw.bw_alloc; 5570 status = ice_sched_cfg_node_bw_alloc(hw, node, ICE_MAX_BW, 5571 bw_alloc); 5572 if (status) 5573 return status; 5574 } 5575 if (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_SHARED)) 5576 status = ice_sched_set_node_bw_lmt(pi, node, ICE_SHARED_BW, 5577 bw_t_info->shared_bw); 5578 return status; 5579 } 5580 5581 /** 5582 * ice_sched_replay_agg_bw - replay aggregator node(s) BW 5583 * @hw: pointer to the HW struct 5584 * @agg_info: aggregator data structure 5585 * 5586 * This function re-creates aggregator type nodes. The caller needs to hold 5587 * the scheduler lock. 5588 */ 5589 static enum ice_status 5590 ice_sched_replay_agg_bw(struct ice_hw *hw, struct ice_sched_agg_info *agg_info) 5591 { 5592 struct ice_sched_node *tc_node, *agg_node; 5593 enum ice_status status = ICE_SUCCESS; 5594 u8 tc; 5595 5596 if (!agg_info) 5597 return ICE_ERR_PARAM; 5598 ice_for_each_traffic_class(tc) { 5599 if (!ice_is_any_bit_set(agg_info->bw_t_info[tc].bw_t_bitmap, 5600 ICE_BW_TYPE_CNT)) 5601 continue; 5602 tc_node = ice_sched_get_tc_node(hw->port_info, tc); 5603 if (!tc_node) { 5604 status = ICE_ERR_PARAM; 5605 break; 5606 } 5607 agg_node = ice_sched_get_agg_node(hw->port_info, tc_node, 5608 agg_info->agg_id); 5609 if (!agg_node) { 5610 status = ICE_ERR_PARAM; 5611 break; 5612 } 5613 status = ice_sched_replay_node_bw(hw, agg_node, 5614 &agg_info->bw_t_info[tc]); 5615 if (status) 5616 break; 5617 } 5618 return status; 5619 } 5620 5621 /** 5622 * ice_sched_get_ena_tc_bitmap - get enabled TC bitmap 5623 * @pi: port info struct 5624 * @tc_bitmap: 8 bits TC bitmap to check 5625 * @ena_tc_bitmap: 8 bits enabled TC bitmap to return 5626 * 5627 * This function returns enabled TC bitmap in variable ena_tc_bitmap. Some TCs 5628 * may be missing, it returns enabled TCs. This function needs to be called with 5629 * scheduler lock held. 5630 */ 5631 static void 5632 ice_sched_get_ena_tc_bitmap(struct ice_port_info *pi, ice_bitmap_t *tc_bitmap, 5633 ice_bitmap_t *ena_tc_bitmap) 5634 { 5635 u8 tc; 5636 5637 /* Some TC(s) may be missing after reset, adjust for replay */ 5638 ice_for_each_traffic_class(tc) 5639 if (ice_is_tc_ena(*tc_bitmap, tc) && 5640 (ice_sched_get_tc_node(pi, tc))) 5641 ice_set_bit(tc, ena_tc_bitmap); 5642 } 5643 5644 /** 5645 * ice_sched_replay_agg - recreate aggregator node(s) 5646 * @hw: pointer to the HW struct 5647 * 5648 * This function recreate aggregator type nodes which are not replayed earlier. 5649 * It also replay aggregator BW information. These aggregator nodes are not 5650 * associated with VSI type node yet. 5651 */ 5652 void ice_sched_replay_agg(struct ice_hw *hw) 5653 { 5654 struct ice_port_info *pi = hw->port_info; 5655 struct ice_sched_agg_info *agg_info; 5656 5657 ice_acquire_lock(&pi->sched_lock); 5658 LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info, 5659 list_entry) 5660 /* replay aggregator (re-create aggregator node) */ 5661 if (!ice_cmp_bitmap(agg_info->tc_bitmap, 5662 agg_info->replay_tc_bitmap, 5663 ICE_MAX_TRAFFIC_CLASS)) { 5664 ice_declare_bitmap(replay_bitmap, 5665 ICE_MAX_TRAFFIC_CLASS); 5666 enum ice_status status; 5667 5668 ice_zero_bitmap(replay_bitmap, ICE_MAX_TRAFFIC_CLASS); 5669 ice_sched_get_ena_tc_bitmap(pi, 5670 agg_info->replay_tc_bitmap, 5671 replay_bitmap); 5672 status = ice_sched_cfg_agg(hw->port_info, 5673 agg_info->agg_id, 5674 ICE_AGG_TYPE_AGG, 5675 replay_bitmap); 5676 if (status) { 5677 ice_info(hw, "Replay agg id[%d] failed\n", 5678 agg_info->agg_id); 5679 /* Move on to next one */ 5680 continue; 5681 } 5682 /* Replay aggregator node BW (restore aggregator BW) */ 5683 status = ice_sched_replay_agg_bw(hw, agg_info); 5684 if (status) 5685 ice_info(hw, "Replay agg bw [id=%d] failed\n", 5686 agg_info->agg_id); 5687 } 5688 ice_release_lock(&pi->sched_lock); 5689 } 5690 5691 /** 5692 * ice_sched_replay_agg_vsi_preinit - Agg/VSI replay pre initialization 5693 * @hw: pointer to the HW struct 5694 * 5695 * This function initialize aggregator(s) TC bitmap to zero. A required 5696 * preinit step for replaying aggregators. 5697 */ 5698 void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw) 5699 { 5700 struct ice_port_info *pi = hw->port_info; 5701 struct ice_sched_agg_info *agg_info; 5702 5703 ice_acquire_lock(&pi->sched_lock); 5704 LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info, 5705 list_entry) { 5706 struct ice_sched_agg_vsi_info *agg_vsi_info; 5707 5708 agg_info->tc_bitmap[0] = 0; 5709 LIST_FOR_EACH_ENTRY(agg_vsi_info, &agg_info->agg_vsi_list, 5710 ice_sched_agg_vsi_info, list_entry) 5711 agg_vsi_info->tc_bitmap[0] = 0; 5712 } 5713 ice_release_lock(&pi->sched_lock); 5714 } 5715 5716 /** 5717 * ice_sched_replay_root_node_bw - replay root node BW 5718 * @pi: port information structure 5719 * 5720 * Replay root node BW settings. 5721 */ 5722 enum ice_status ice_sched_replay_root_node_bw(struct ice_port_info *pi) 5723 { 5724 enum ice_status status = ICE_SUCCESS; 5725 5726 if (!pi->hw) 5727 return ICE_ERR_PARAM; 5728 ice_acquire_lock(&pi->sched_lock); 5729 5730 status = ice_sched_replay_node_bw(pi->hw, pi->root, 5731 &pi->root_node_bw_t_info); 5732 ice_release_lock(&pi->sched_lock); 5733 return status; 5734 } 5735 5736 /** 5737 * ice_sched_replay_tc_node_bw - replay TC node(s) BW 5738 * @pi: port information structure 5739 * 5740 * This function replay TC nodes. 5741 */ 5742 enum ice_status ice_sched_replay_tc_node_bw(struct ice_port_info *pi) 5743 { 5744 enum ice_status status = ICE_SUCCESS; 5745 u8 tc; 5746 5747 if (!pi->hw) 5748 return ICE_ERR_PARAM; 5749 ice_acquire_lock(&pi->sched_lock); 5750 ice_for_each_traffic_class(tc) { 5751 struct ice_sched_node *tc_node; 5752 5753 tc_node = ice_sched_get_tc_node(pi, tc); 5754 if (!tc_node) 5755 continue; /* TC not present */ 5756 status = ice_sched_replay_node_bw(pi->hw, tc_node, 5757 &pi->tc_node_bw_t_info[tc]); 5758 if (status) 5759 break; 5760 } 5761 ice_release_lock(&pi->sched_lock); 5762 return status; 5763 } 5764 5765 /** 5766 * ice_sched_replay_vsi_bw - replay VSI type node(s) BW 5767 * @hw: pointer to the HW struct 5768 * @vsi_handle: software VSI handle 5769 * @tc_bitmap: 8 bits TC bitmap 5770 * 5771 * This function replays VSI type nodes bandwidth. This function needs to be 5772 * called with scheduler lock held. 5773 */ 5774 static enum ice_status 5775 ice_sched_replay_vsi_bw(struct ice_hw *hw, u16 vsi_handle, 5776 ice_bitmap_t *tc_bitmap) 5777 { 5778 struct ice_sched_node *vsi_node, *tc_node; 5779 struct ice_port_info *pi = hw->port_info; 5780 struct ice_bw_type_info *bw_t_info; 5781 struct ice_vsi_ctx *vsi_ctx; 5782 enum ice_status status = ICE_SUCCESS; 5783 u8 tc; 5784 5785 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 5786 if (!vsi_ctx) 5787 return ICE_ERR_PARAM; 5788 ice_for_each_traffic_class(tc) { 5789 if (!ice_is_tc_ena(*tc_bitmap, tc)) 5790 continue; 5791 tc_node = ice_sched_get_tc_node(pi, tc); 5792 if (!tc_node) 5793 continue; 5794 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 5795 if (!vsi_node) 5796 continue; 5797 bw_t_info = &vsi_ctx->sched.bw_t_info[tc]; 5798 status = ice_sched_replay_node_bw(hw, vsi_node, bw_t_info); 5799 if (status) 5800 break; 5801 } 5802 return status; 5803 } 5804 5805 /** 5806 * ice_sched_replay_vsi_agg - replay aggregator & VSI to aggregator node(s) 5807 * @hw: pointer to the HW struct 5808 * @vsi_handle: software VSI handle 5809 * 5810 * This function replays aggregator node, VSI to aggregator type nodes, and 5811 * their node bandwidth information. This function needs to be called with 5812 * scheduler lock held. 5813 */ 5814 static enum ice_status 5815 ice_sched_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle) 5816 { 5817 ice_declare_bitmap(replay_bitmap, ICE_MAX_TRAFFIC_CLASS); 5818 struct ice_sched_agg_vsi_info *agg_vsi_info; 5819 struct ice_port_info *pi = hw->port_info; 5820 struct ice_sched_agg_info *agg_info; 5821 enum ice_status status; 5822 5823 ice_zero_bitmap(replay_bitmap, ICE_MAX_TRAFFIC_CLASS); 5824 if (!ice_is_vsi_valid(hw, vsi_handle)) 5825 return ICE_ERR_PARAM; 5826 agg_info = ice_get_vsi_agg_info(hw, vsi_handle); 5827 if (!agg_info) 5828 return ICE_SUCCESS; /* Not present in list - default Agg case */ 5829 agg_vsi_info = ice_get_agg_vsi_info(agg_info, vsi_handle); 5830 if (!agg_vsi_info) 5831 return ICE_SUCCESS; /* Not present in list - default Agg case */ 5832 ice_sched_get_ena_tc_bitmap(pi, agg_info->replay_tc_bitmap, 5833 replay_bitmap); 5834 /* Replay aggregator node associated to vsi_handle */ 5835 status = ice_sched_cfg_agg(hw->port_info, agg_info->agg_id, 5836 ICE_AGG_TYPE_AGG, replay_bitmap); 5837 if (status) 5838 return status; 5839 /* Replay aggregator node BW (restore aggregator BW) */ 5840 status = ice_sched_replay_agg_bw(hw, agg_info); 5841 if (status) 5842 return status; 5843 5844 ice_zero_bitmap(replay_bitmap, ICE_MAX_TRAFFIC_CLASS); 5845 ice_sched_get_ena_tc_bitmap(pi, agg_vsi_info->replay_tc_bitmap, 5846 replay_bitmap); 5847 /* Move this VSI (vsi_handle) to above aggregator */ 5848 status = ice_sched_assoc_vsi_to_agg(pi, agg_info->agg_id, vsi_handle, 5849 replay_bitmap); 5850 if (status) 5851 return status; 5852 /* Replay VSI BW (restore VSI BW) */ 5853 return ice_sched_replay_vsi_bw(hw, vsi_handle, 5854 agg_vsi_info->tc_bitmap); 5855 } 5856 5857 /** 5858 * ice_replay_vsi_agg - replay VSI to aggregator node 5859 * @hw: pointer to the HW struct 5860 * @vsi_handle: software VSI handle 5861 * 5862 * This function replays association of VSI to aggregator type nodes, and 5863 * node bandwidth information. 5864 */ 5865 enum ice_status ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle) 5866 { 5867 struct ice_port_info *pi = hw->port_info; 5868 enum ice_status status; 5869 5870 ice_acquire_lock(&pi->sched_lock); 5871 status = ice_sched_replay_vsi_agg(hw, vsi_handle); 5872 ice_release_lock(&pi->sched_lock); 5873 return status; 5874 } 5875 5876 /** 5877 * ice_sched_replay_q_bw - replay queue type node BW 5878 * @pi: port information structure 5879 * @q_ctx: queue context structure 5880 * 5881 * This function replays queue type node bandwidth. This function needs to be 5882 * called with scheduler lock held. 5883 */ 5884 enum ice_status 5885 ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx) 5886 { 5887 struct ice_sched_node *q_node; 5888 5889 /* Following also checks the presence of node in tree */ 5890 q_node = ice_sched_find_node_by_teid(pi->root, q_ctx->q_teid); 5891 if (!q_node) 5892 return ICE_ERR_PARAM; 5893 return ice_sched_replay_node_bw(pi->hw, q_node, &q_ctx->bw_t_info); 5894 } 5895