1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2021, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*$FreeBSD$*/ 32 33 #include "ice_sched.h" 34 35 /** 36 * ice_sched_add_root_node - Insert the Tx scheduler root node in SW DB 37 * @pi: port information structure 38 * @info: Scheduler element information from firmware 39 * 40 * This function inserts the root node of the scheduling tree topology 41 * to the SW DB. 42 */ 43 static enum ice_status 44 ice_sched_add_root_node(struct ice_port_info *pi, 45 struct ice_aqc_txsched_elem_data *info) 46 { 47 struct ice_sched_node *root; 48 struct ice_hw *hw; 49 50 if (!pi) 51 return ICE_ERR_PARAM; 52 53 hw = pi->hw; 54 55 root = (struct ice_sched_node *)ice_malloc(hw, sizeof(*root)); 56 if (!root) 57 return ICE_ERR_NO_MEMORY; 58 59 /* coverity[suspicious_sizeof] */ 60 root->children = (struct ice_sched_node **) 61 ice_calloc(hw, hw->max_children[0], sizeof(*root)); 62 if (!root->children) { 63 ice_free(hw, root); 64 return ICE_ERR_NO_MEMORY; 65 } 66 67 ice_memcpy(&root->info, info, sizeof(*info), ICE_DMA_TO_NONDMA); 68 pi->root = root; 69 return ICE_SUCCESS; 70 } 71 72 /** 73 * ice_sched_find_node_by_teid - Find the Tx scheduler node in SW DB 74 * @start_node: pointer to the starting ice_sched_node struct in a sub-tree 75 * @teid: node TEID to search 76 * 77 * This function searches for a node matching the TEID in the scheduling tree 78 * from the SW DB. The search is recursive and is restricted by the number of 79 * layers it has searched through; stopping at the max supported layer. 80 * 81 * This function needs to be called when holding the port_info->sched_lock 82 */ 83 struct ice_sched_node * 84 ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid) 85 { 86 u16 i; 87 88 /* The TEID is same as that of the start_node */ 89 if (ICE_TXSCHED_GET_NODE_TEID(start_node) == teid) 90 return start_node; 91 92 /* The node has no children or is at the max layer */ 93 if (!start_node->num_children || 94 start_node->tx_sched_layer >= ICE_AQC_TOPO_MAX_LEVEL_NUM || 95 start_node->info.data.elem_type == ICE_AQC_ELEM_TYPE_LEAF) 96 return NULL; 97 98 /* Check if TEID matches to any of the children nodes */ 99 for (i = 0; i < start_node->num_children; i++) 100 if (ICE_TXSCHED_GET_NODE_TEID(start_node->children[i]) == teid) 101 return start_node->children[i]; 102 103 /* Search within each child's sub-tree */ 104 for (i = 0; i < start_node->num_children; i++) { 105 struct ice_sched_node *tmp; 106 107 tmp = ice_sched_find_node_by_teid(start_node->children[i], 108 teid); 109 if (tmp) 110 return tmp; 111 } 112 113 return NULL; 114 } 115 116 /** 117 * ice_aqc_send_sched_elem_cmd - send scheduling elements cmd 118 * @hw: pointer to the HW struct 119 * @cmd_opc: cmd opcode 120 * @elems_req: number of elements to request 121 * @buf: pointer to buffer 122 * @buf_size: buffer size in bytes 123 * @elems_resp: returns total number of elements response 124 * @cd: pointer to command details structure or NULL 125 * 126 * This function sends a scheduling elements cmd (cmd_opc) 127 */ 128 static enum ice_status 129 ice_aqc_send_sched_elem_cmd(struct ice_hw *hw, enum ice_adminq_opc cmd_opc, 130 u16 elems_req, void *buf, u16 buf_size, 131 u16 *elems_resp, struct ice_sq_cd *cd) 132 { 133 struct ice_aqc_sched_elem_cmd *cmd; 134 struct ice_aq_desc desc; 135 enum ice_status status; 136 137 cmd = &desc.params.sched_elem_cmd; 138 ice_fill_dflt_direct_cmd_desc(&desc, cmd_opc); 139 cmd->num_elem_req = CPU_TO_LE16(elems_req); 140 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 141 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 142 if (!status && elems_resp) 143 *elems_resp = LE16_TO_CPU(cmd->num_elem_resp); 144 145 return status; 146 } 147 148 /** 149 * ice_aq_query_sched_elems - query scheduler elements 150 * @hw: pointer to the HW struct 151 * @elems_req: number of elements to query 152 * @buf: pointer to buffer 153 * @buf_size: buffer size in bytes 154 * @elems_ret: returns total number of elements returned 155 * @cd: pointer to command details structure or NULL 156 * 157 * Query scheduling elements (0x0404) 158 */ 159 enum ice_status 160 ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req, 161 struct ice_aqc_txsched_elem_data *buf, u16 buf_size, 162 u16 *elems_ret, struct ice_sq_cd *cd) 163 { 164 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_get_sched_elems, 165 elems_req, (void *)buf, buf_size, 166 elems_ret, cd); 167 } 168 169 /** 170 * ice_sched_add_node - Insert the Tx scheduler node in SW DB 171 * @pi: port information structure 172 * @layer: Scheduler layer of the node 173 * @info: Scheduler element information from firmware 174 * 175 * This function inserts a scheduler node to the SW DB. 176 */ 177 enum ice_status 178 ice_sched_add_node(struct ice_port_info *pi, u8 layer, 179 struct ice_aqc_txsched_elem_data *info) 180 { 181 struct ice_aqc_txsched_elem_data elem; 182 struct ice_sched_node *parent; 183 struct ice_sched_node *node; 184 enum ice_status status; 185 struct ice_hw *hw; 186 187 if (!pi) 188 return ICE_ERR_PARAM; 189 190 hw = pi->hw; 191 192 /* A valid parent node should be there */ 193 parent = ice_sched_find_node_by_teid(pi->root, 194 LE32_TO_CPU(info->parent_teid)); 195 if (!parent) { 196 ice_debug(hw, ICE_DBG_SCHED, "Parent Node not found for parent_teid=0x%x\n", 197 LE32_TO_CPU(info->parent_teid)); 198 return ICE_ERR_PARAM; 199 } 200 201 /* query the current node information from FW before adding it 202 * to the SW DB 203 */ 204 status = ice_sched_query_elem(hw, LE32_TO_CPU(info->node_teid), &elem); 205 if (status) 206 return status; 207 node = (struct ice_sched_node *)ice_malloc(hw, sizeof(*node)); 208 if (!node) 209 return ICE_ERR_NO_MEMORY; 210 if (hw->max_children[layer]) { 211 /* coverity[suspicious_sizeof] */ 212 node->children = (struct ice_sched_node **) 213 ice_calloc(hw, hw->max_children[layer], sizeof(*node)); 214 if (!node->children) { 215 ice_free(hw, node); 216 return ICE_ERR_NO_MEMORY; 217 } 218 } 219 220 node->in_use = true; 221 node->parent = parent; 222 node->tx_sched_layer = layer; 223 parent->children[parent->num_children++] = node; 224 node->info = elem; 225 return ICE_SUCCESS; 226 } 227 228 /** 229 * ice_aq_delete_sched_elems - delete scheduler elements 230 * @hw: pointer to the HW struct 231 * @grps_req: number of groups to delete 232 * @buf: pointer to buffer 233 * @buf_size: buffer size in bytes 234 * @grps_del: returns total number of elements deleted 235 * @cd: pointer to command details structure or NULL 236 * 237 * Delete scheduling elements (0x040F) 238 */ 239 static enum ice_status 240 ice_aq_delete_sched_elems(struct ice_hw *hw, u16 grps_req, 241 struct ice_aqc_delete_elem *buf, u16 buf_size, 242 u16 *grps_del, struct ice_sq_cd *cd) 243 { 244 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_delete_sched_elems, 245 grps_req, (void *)buf, buf_size, 246 grps_del, cd); 247 } 248 249 /** 250 * ice_sched_remove_elems - remove nodes from HW 251 * @hw: pointer to the HW struct 252 * @parent: pointer to the parent node 253 * @num_nodes: number of nodes 254 * @node_teids: array of node teids to be deleted 255 * 256 * This function remove nodes from HW 257 */ 258 static enum ice_status 259 ice_sched_remove_elems(struct ice_hw *hw, struct ice_sched_node *parent, 260 u16 num_nodes, u32 *node_teids) 261 { 262 struct ice_aqc_delete_elem *buf; 263 u16 i, num_groups_removed = 0; 264 enum ice_status status; 265 u16 buf_size; 266 267 buf_size = ice_struct_size(buf, teid, num_nodes); 268 buf = (struct ice_aqc_delete_elem *)ice_malloc(hw, buf_size); 269 if (!buf) 270 return ICE_ERR_NO_MEMORY; 271 272 buf->hdr.parent_teid = parent->info.node_teid; 273 buf->hdr.num_elems = CPU_TO_LE16(num_nodes); 274 for (i = 0; i < num_nodes; i++) 275 buf->teid[i] = CPU_TO_LE32(node_teids[i]); 276 277 status = ice_aq_delete_sched_elems(hw, 1, buf, buf_size, 278 &num_groups_removed, NULL); 279 if (status != ICE_SUCCESS || num_groups_removed != 1) 280 ice_debug(hw, ICE_DBG_SCHED, "remove node failed FW error %d\n", 281 hw->adminq.sq_last_status); 282 283 ice_free(hw, buf); 284 return status; 285 } 286 287 /** 288 * ice_sched_get_first_node - get the first node of the given layer 289 * @pi: port information structure 290 * @parent: pointer the base node of the subtree 291 * @layer: layer number 292 * 293 * This function retrieves the first node of the given layer from the subtree 294 */ 295 static struct ice_sched_node * 296 ice_sched_get_first_node(struct ice_port_info *pi, 297 struct ice_sched_node *parent, u8 layer) 298 { 299 return pi->sib_head[parent->tc_num][layer]; 300 } 301 302 /** 303 * ice_sched_get_tc_node - get pointer to TC node 304 * @pi: port information structure 305 * @tc: TC number 306 * 307 * This function returns the TC node pointer 308 */ 309 struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc) 310 { 311 u8 i; 312 313 if (!pi || !pi->root) 314 return NULL; 315 for (i = 0; i < pi->root->num_children; i++) 316 if (pi->root->children[i]->tc_num == tc) 317 return pi->root->children[i]; 318 return NULL; 319 } 320 321 /** 322 * ice_free_sched_node - Free a Tx scheduler node from SW DB 323 * @pi: port information structure 324 * @node: pointer to the ice_sched_node struct 325 * 326 * This function frees up a node from SW DB as well as from HW 327 * 328 * This function needs to be called with the port_info->sched_lock held 329 */ 330 void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node) 331 { 332 struct ice_sched_node *parent; 333 struct ice_hw *hw = pi->hw; 334 u8 i, j; 335 336 /* Free the children before freeing up the parent node 337 * The parent array is updated below and that shifts the nodes 338 * in the array. So always pick the first child if num children > 0 339 */ 340 while (node->num_children) 341 ice_free_sched_node(pi, node->children[0]); 342 343 /* Leaf, TC and root nodes can't be deleted by SW */ 344 if (node->tx_sched_layer >= hw->sw_entry_point_layer && 345 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_TC && 346 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_ROOT_PORT && 347 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_LEAF) { 348 u32 teid = LE32_TO_CPU(node->info.node_teid); 349 350 ice_sched_remove_elems(hw, node->parent, 1, &teid); 351 } 352 parent = node->parent; 353 /* root has no parent */ 354 if (parent) { 355 struct ice_sched_node *p; 356 357 /* update the parent */ 358 for (i = 0; i < parent->num_children; i++) 359 if (parent->children[i] == node) { 360 for (j = i + 1; j < parent->num_children; j++) 361 parent->children[j - 1] = 362 parent->children[j]; 363 parent->num_children--; 364 break; 365 } 366 367 p = ice_sched_get_first_node(pi, node, node->tx_sched_layer); 368 while (p) { 369 if (p->sibling == node) { 370 p->sibling = node->sibling; 371 break; 372 } 373 p = p->sibling; 374 } 375 376 /* update the sibling head if head is getting removed */ 377 if (pi->sib_head[node->tc_num][node->tx_sched_layer] == node) 378 pi->sib_head[node->tc_num][node->tx_sched_layer] = 379 node->sibling; 380 } 381 382 /* leaf nodes have no children */ 383 if (node->children) 384 ice_free(hw, node->children); 385 ice_free(hw, node); 386 } 387 388 /** 389 * ice_aq_get_dflt_topo - gets default scheduler topology 390 * @hw: pointer to the HW struct 391 * @lport: logical port number 392 * @buf: pointer to buffer 393 * @buf_size: buffer size in bytes 394 * @num_branches: returns total number of queue to port branches 395 * @cd: pointer to command details structure or NULL 396 * 397 * Get default scheduler topology (0x400) 398 */ 399 static enum ice_status 400 ice_aq_get_dflt_topo(struct ice_hw *hw, u8 lport, 401 struct ice_aqc_get_topo_elem *buf, u16 buf_size, 402 u8 *num_branches, struct ice_sq_cd *cd) 403 { 404 struct ice_aqc_get_topo *cmd; 405 struct ice_aq_desc desc; 406 enum ice_status status; 407 408 cmd = &desc.params.get_topo; 409 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_dflt_topo); 410 cmd->port_num = lport; 411 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 412 if (!status && num_branches) 413 *num_branches = cmd->num_branches; 414 415 return status; 416 } 417 418 /** 419 * ice_aq_add_sched_elems - adds scheduling element 420 * @hw: pointer to the HW struct 421 * @grps_req: the number of groups that are requested to be added 422 * @buf: pointer to buffer 423 * @buf_size: buffer size in bytes 424 * @grps_added: returns total number of groups added 425 * @cd: pointer to command details structure or NULL 426 * 427 * Add scheduling elements (0x0401) 428 */ 429 static enum ice_status 430 ice_aq_add_sched_elems(struct ice_hw *hw, u16 grps_req, 431 struct ice_aqc_add_elem *buf, u16 buf_size, 432 u16 *grps_added, struct ice_sq_cd *cd) 433 { 434 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_add_sched_elems, 435 grps_req, (void *)buf, buf_size, 436 grps_added, cd); 437 } 438 439 /** 440 * ice_aq_cfg_sched_elems - configures scheduler elements 441 * @hw: pointer to the HW struct 442 * @elems_req: number of elements to configure 443 * @buf: pointer to buffer 444 * @buf_size: buffer size in bytes 445 * @elems_cfgd: returns total number of elements configured 446 * @cd: pointer to command details structure or NULL 447 * 448 * Configure scheduling elements (0x0403) 449 */ 450 static enum ice_status 451 ice_aq_cfg_sched_elems(struct ice_hw *hw, u16 elems_req, 452 struct ice_aqc_txsched_elem_data *buf, u16 buf_size, 453 u16 *elems_cfgd, struct ice_sq_cd *cd) 454 { 455 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_cfg_sched_elems, 456 elems_req, (void *)buf, buf_size, 457 elems_cfgd, cd); 458 } 459 460 /** 461 * ice_aq_move_sched_elems - move scheduler elements 462 * @hw: pointer to the HW struct 463 * @grps_req: number of groups to move 464 * @buf: pointer to buffer 465 * @buf_size: buffer size in bytes 466 * @grps_movd: returns total number of groups moved 467 * @cd: pointer to command details structure or NULL 468 * 469 * Move scheduling elements (0x0408) 470 */ 471 static enum ice_status 472 ice_aq_move_sched_elems(struct ice_hw *hw, u16 grps_req, 473 struct ice_aqc_move_elem *buf, u16 buf_size, 474 u16 *grps_movd, struct ice_sq_cd *cd) 475 { 476 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_move_sched_elems, 477 grps_req, (void *)buf, buf_size, 478 grps_movd, cd); 479 } 480 481 /** 482 * ice_aq_suspend_sched_elems - suspend scheduler elements 483 * @hw: pointer to the HW struct 484 * @elems_req: number of elements to suspend 485 * @buf: pointer to buffer 486 * @buf_size: buffer size in bytes 487 * @elems_ret: returns total number of elements suspended 488 * @cd: pointer to command details structure or NULL 489 * 490 * Suspend scheduling elements (0x0409) 491 */ 492 static enum ice_status 493 ice_aq_suspend_sched_elems(struct ice_hw *hw, u16 elems_req, __le32 *buf, 494 u16 buf_size, u16 *elems_ret, struct ice_sq_cd *cd) 495 { 496 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_suspend_sched_elems, 497 elems_req, (void *)buf, buf_size, 498 elems_ret, cd); 499 } 500 501 /** 502 * ice_aq_resume_sched_elems - resume scheduler elements 503 * @hw: pointer to the HW struct 504 * @elems_req: number of elements to resume 505 * @buf: pointer to buffer 506 * @buf_size: buffer size in bytes 507 * @elems_ret: returns total number of elements resumed 508 * @cd: pointer to command details structure or NULL 509 * 510 * resume scheduling elements (0x040A) 511 */ 512 static enum ice_status 513 ice_aq_resume_sched_elems(struct ice_hw *hw, u16 elems_req, __le32 *buf, 514 u16 buf_size, u16 *elems_ret, struct ice_sq_cd *cd) 515 { 516 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_resume_sched_elems, 517 elems_req, (void *)buf, buf_size, 518 elems_ret, cd); 519 } 520 521 /** 522 * ice_aq_query_sched_res - query scheduler resource 523 * @hw: pointer to the HW struct 524 * @buf_size: buffer size in bytes 525 * @buf: pointer to buffer 526 * @cd: pointer to command details structure or NULL 527 * 528 * Query scheduler resource allocation (0x0412) 529 */ 530 static enum ice_status 531 ice_aq_query_sched_res(struct ice_hw *hw, u16 buf_size, 532 struct ice_aqc_query_txsched_res_resp *buf, 533 struct ice_sq_cd *cd) 534 { 535 struct ice_aq_desc desc; 536 537 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_query_sched_res); 538 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 539 } 540 541 /** 542 * ice_sched_suspend_resume_elems - suspend or resume HW nodes 543 * @hw: pointer to the HW struct 544 * @num_nodes: number of nodes 545 * @node_teids: array of node teids to be suspended or resumed 546 * @suspend: true means suspend / false means resume 547 * 548 * This function suspends or resumes HW nodes 549 */ 550 static enum ice_status 551 ice_sched_suspend_resume_elems(struct ice_hw *hw, u8 num_nodes, u32 *node_teids, 552 bool suspend) 553 { 554 u16 i, buf_size, num_elem_ret = 0; 555 enum ice_status status; 556 __le32 *buf; 557 558 buf_size = sizeof(*buf) * num_nodes; 559 buf = (__le32 *)ice_malloc(hw, buf_size); 560 if (!buf) 561 return ICE_ERR_NO_MEMORY; 562 563 for (i = 0; i < num_nodes; i++) 564 buf[i] = CPU_TO_LE32(node_teids[i]); 565 566 if (suspend) 567 status = ice_aq_suspend_sched_elems(hw, num_nodes, buf, 568 buf_size, &num_elem_ret, 569 NULL); 570 else 571 status = ice_aq_resume_sched_elems(hw, num_nodes, buf, 572 buf_size, &num_elem_ret, 573 NULL); 574 if (status != ICE_SUCCESS || num_elem_ret != num_nodes) 575 ice_debug(hw, ICE_DBG_SCHED, "suspend/resume failed\n"); 576 577 ice_free(hw, buf); 578 return status; 579 } 580 581 /** 582 * ice_alloc_lan_q_ctx - allocate LAN queue contexts for the given VSI and TC 583 * @hw: pointer to the HW struct 584 * @vsi_handle: VSI handle 585 * @tc: TC number 586 * @new_numqs: number of queues 587 */ 588 static enum ice_status 589 ice_alloc_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 new_numqs) 590 { 591 struct ice_vsi_ctx *vsi_ctx; 592 struct ice_q_ctx *q_ctx; 593 594 vsi_ctx = ice_get_vsi_ctx(hw, vsi_handle); 595 if (!vsi_ctx) 596 return ICE_ERR_PARAM; 597 /* allocate LAN queue contexts */ 598 if (!vsi_ctx->lan_q_ctx[tc]) { 599 vsi_ctx->lan_q_ctx[tc] = (struct ice_q_ctx *) 600 ice_calloc(hw, new_numqs, sizeof(*q_ctx)); 601 if (!vsi_ctx->lan_q_ctx[tc]) 602 return ICE_ERR_NO_MEMORY; 603 vsi_ctx->num_lan_q_entries[tc] = new_numqs; 604 return ICE_SUCCESS; 605 } 606 /* num queues are increased, update the queue contexts */ 607 if (new_numqs > vsi_ctx->num_lan_q_entries[tc]) { 608 u16 prev_num = vsi_ctx->num_lan_q_entries[tc]; 609 610 q_ctx = (struct ice_q_ctx *) 611 ice_calloc(hw, new_numqs, sizeof(*q_ctx)); 612 if (!q_ctx) 613 return ICE_ERR_NO_MEMORY; 614 ice_memcpy(q_ctx, vsi_ctx->lan_q_ctx[tc], 615 prev_num * sizeof(*q_ctx), ICE_DMA_TO_NONDMA); 616 ice_free(hw, vsi_ctx->lan_q_ctx[tc]); 617 vsi_ctx->lan_q_ctx[tc] = q_ctx; 618 vsi_ctx->num_lan_q_entries[tc] = new_numqs; 619 } 620 return ICE_SUCCESS; 621 } 622 623 /** 624 * ice_aq_rl_profile - performs a rate limiting task 625 * @hw: pointer to the HW struct 626 * @opcode: opcode for add, query, or remove profile(s) 627 * @num_profiles: the number of profiles 628 * @buf: pointer to buffer 629 * @buf_size: buffer size in bytes 630 * @num_processed: number of processed add or remove profile(s) to return 631 * @cd: pointer to command details structure 632 * 633 * RL profile function to add, query, or remove profile(s) 634 */ 635 static enum ice_status 636 ice_aq_rl_profile(struct ice_hw *hw, enum ice_adminq_opc opcode, 637 u16 num_profiles, struct ice_aqc_rl_profile_elem *buf, 638 u16 buf_size, u16 *num_processed, struct ice_sq_cd *cd) 639 { 640 struct ice_aqc_rl_profile *cmd; 641 struct ice_aq_desc desc; 642 enum ice_status status; 643 644 cmd = &desc.params.rl_profile; 645 646 ice_fill_dflt_direct_cmd_desc(&desc, opcode); 647 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 648 cmd->num_profiles = CPU_TO_LE16(num_profiles); 649 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 650 if (!status && num_processed) 651 *num_processed = LE16_TO_CPU(cmd->num_processed); 652 return status; 653 } 654 655 /** 656 * ice_aq_add_rl_profile - adds rate limiting profile(s) 657 * @hw: pointer to the HW struct 658 * @num_profiles: the number of profile(s) to be add 659 * @buf: pointer to buffer 660 * @buf_size: buffer size in bytes 661 * @num_profiles_added: total number of profiles added to return 662 * @cd: pointer to command details structure 663 * 664 * Add RL profile (0x0410) 665 */ 666 static enum ice_status 667 ice_aq_add_rl_profile(struct ice_hw *hw, u16 num_profiles, 668 struct ice_aqc_rl_profile_elem *buf, u16 buf_size, 669 u16 *num_profiles_added, struct ice_sq_cd *cd) 670 { 671 return ice_aq_rl_profile(hw, ice_aqc_opc_add_rl_profiles, num_profiles, 672 buf, buf_size, num_profiles_added, cd); 673 } 674 675 /** 676 * ice_aq_query_rl_profile - query rate limiting profile(s) 677 * @hw: pointer to the HW struct 678 * @num_profiles: the number of profile(s) to query 679 * @buf: pointer to buffer 680 * @buf_size: buffer size in bytes 681 * @cd: pointer to command details structure 682 * 683 * Query RL profile (0x0411) 684 */ 685 enum ice_status 686 ice_aq_query_rl_profile(struct ice_hw *hw, u16 num_profiles, 687 struct ice_aqc_rl_profile_elem *buf, u16 buf_size, 688 struct ice_sq_cd *cd) 689 { 690 return ice_aq_rl_profile(hw, ice_aqc_opc_query_rl_profiles, 691 num_profiles, buf, buf_size, NULL, cd); 692 } 693 694 /** 695 * ice_aq_remove_rl_profile - removes RL profile(s) 696 * @hw: pointer to the HW struct 697 * @num_profiles: the number of profile(s) to remove 698 * @buf: pointer to buffer 699 * @buf_size: buffer size in bytes 700 * @num_profiles_removed: total number of profiles removed to return 701 * @cd: pointer to command details structure or NULL 702 * 703 * Remove RL profile (0x0415) 704 */ 705 static enum ice_status 706 ice_aq_remove_rl_profile(struct ice_hw *hw, u16 num_profiles, 707 struct ice_aqc_rl_profile_elem *buf, u16 buf_size, 708 u16 *num_profiles_removed, struct ice_sq_cd *cd) 709 { 710 return ice_aq_rl_profile(hw, ice_aqc_opc_remove_rl_profiles, 711 num_profiles, buf, buf_size, 712 num_profiles_removed, cd); 713 } 714 715 /** 716 * ice_sched_del_rl_profile - remove RL profile 717 * @hw: pointer to the HW struct 718 * @rl_info: rate limit profile information 719 * 720 * If the profile ID is not referenced anymore, it removes profile ID with 721 * its associated parameters from HW DB,and locally. The caller needs to 722 * hold scheduler lock. 723 */ 724 static enum ice_status 725 ice_sched_del_rl_profile(struct ice_hw *hw, 726 struct ice_aqc_rl_profile_info *rl_info) 727 { 728 struct ice_aqc_rl_profile_elem *buf; 729 u16 num_profiles_removed; 730 enum ice_status status; 731 u16 num_profiles = 1; 732 733 if (rl_info->prof_id_ref != 0) 734 return ICE_ERR_IN_USE; 735 736 /* Safe to remove profile ID */ 737 buf = &rl_info->profile; 738 status = ice_aq_remove_rl_profile(hw, num_profiles, buf, sizeof(*buf), 739 &num_profiles_removed, NULL); 740 if (status || num_profiles_removed != num_profiles) 741 return ICE_ERR_CFG; 742 743 /* Delete stale entry now */ 744 LIST_DEL(&rl_info->list_entry); 745 ice_free(hw, rl_info); 746 return status; 747 } 748 749 /** 750 * ice_sched_clear_rl_prof - clears RL prof entries 751 * @pi: port information structure 752 * 753 * This function removes all RL profile from HW as well as from SW DB. 754 */ 755 static void ice_sched_clear_rl_prof(struct ice_port_info *pi) 756 { 757 u16 ln; 758 struct ice_hw *hw = pi->hw; 759 760 for (ln = 0; ln < hw->num_tx_sched_layers; ln++) { 761 struct ice_aqc_rl_profile_info *rl_prof_elem; 762 struct ice_aqc_rl_profile_info *rl_prof_tmp; 763 764 LIST_FOR_EACH_ENTRY_SAFE(rl_prof_elem, rl_prof_tmp, 765 &hw->rl_prof_list[ln], 766 ice_aqc_rl_profile_info, list_entry) { 767 enum ice_status status; 768 769 rl_prof_elem->prof_id_ref = 0; 770 status = ice_sched_del_rl_profile(hw, rl_prof_elem); 771 if (status) { 772 ice_debug(hw, ICE_DBG_SCHED, "Remove rl profile failed\n"); 773 /* On error, free mem required */ 774 LIST_DEL(&rl_prof_elem->list_entry); 775 ice_free(hw, rl_prof_elem); 776 } 777 } 778 } 779 } 780 781 /** 782 * ice_sched_clear_agg - clears the aggregator related information 783 * @hw: pointer to the hardware structure 784 * 785 * This function removes aggregator list and free up aggregator related memory 786 * previously allocated. 787 */ 788 void ice_sched_clear_agg(struct ice_hw *hw) 789 { 790 struct ice_sched_agg_info *agg_info; 791 struct ice_sched_agg_info *atmp; 792 793 LIST_FOR_EACH_ENTRY_SAFE(agg_info, atmp, &hw->agg_list, 794 ice_sched_agg_info, 795 list_entry) { 796 struct ice_sched_agg_vsi_info *agg_vsi_info; 797 struct ice_sched_agg_vsi_info *vtmp; 798 799 LIST_FOR_EACH_ENTRY_SAFE(agg_vsi_info, vtmp, 800 &agg_info->agg_vsi_list, 801 ice_sched_agg_vsi_info, list_entry) { 802 LIST_DEL(&agg_vsi_info->list_entry); 803 ice_free(hw, agg_vsi_info); 804 } 805 LIST_DEL(&agg_info->list_entry); 806 ice_free(hw, agg_info); 807 } 808 } 809 810 /** 811 * ice_sched_clear_tx_topo - clears the scheduler tree nodes 812 * @pi: port information structure 813 * 814 * This function removes all the nodes from HW as well as from SW DB. 815 */ 816 static void ice_sched_clear_tx_topo(struct ice_port_info *pi) 817 { 818 if (!pi) 819 return; 820 /* remove RL profiles related lists */ 821 ice_sched_clear_rl_prof(pi); 822 if (pi->root) { 823 ice_free_sched_node(pi, pi->root); 824 pi->root = NULL; 825 } 826 } 827 828 /** 829 * ice_sched_clear_port - clear the scheduler elements from SW DB for a port 830 * @pi: port information structure 831 * 832 * Cleanup scheduling elements from SW DB 833 */ 834 void ice_sched_clear_port(struct ice_port_info *pi) 835 { 836 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 837 return; 838 839 pi->port_state = ICE_SCHED_PORT_STATE_INIT; 840 ice_acquire_lock(&pi->sched_lock); 841 ice_sched_clear_tx_topo(pi); 842 ice_release_lock(&pi->sched_lock); 843 ice_destroy_lock(&pi->sched_lock); 844 } 845 846 /** 847 * ice_sched_cleanup_all - cleanup scheduler elements from SW DB for all ports 848 * @hw: pointer to the HW struct 849 * 850 * Cleanup scheduling elements from SW DB for all the ports 851 */ 852 void ice_sched_cleanup_all(struct ice_hw *hw) 853 { 854 if (!hw) 855 return; 856 857 if (hw->layer_info) { 858 ice_free(hw, hw->layer_info); 859 hw->layer_info = NULL; 860 } 861 862 ice_sched_clear_port(hw->port_info); 863 864 hw->num_tx_sched_layers = 0; 865 hw->num_tx_sched_phys_layers = 0; 866 hw->flattened_layers = 0; 867 hw->max_cgds = 0; 868 } 869 870 /** 871 * ice_aq_cfg_l2_node_cgd - configures L2 node to CGD mapping 872 * @hw: pointer to the HW struct 873 * @num_l2_nodes: the number of L2 nodes whose CGDs to configure 874 * @buf: pointer to buffer 875 * @buf_size: buffer size in bytes 876 * @cd: pointer to command details structure or NULL 877 * 878 * Configure L2 Node CGD (0x0414) 879 */ 880 enum ice_status 881 ice_aq_cfg_l2_node_cgd(struct ice_hw *hw, u16 num_l2_nodes, 882 struct ice_aqc_cfg_l2_node_cgd_elem *buf, 883 u16 buf_size, struct ice_sq_cd *cd) 884 { 885 struct ice_aqc_cfg_l2_node_cgd *cmd; 886 struct ice_aq_desc desc; 887 888 cmd = &desc.params.cfg_l2_node_cgd; 889 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_l2_node_cgd); 890 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 891 892 cmd->num_l2_nodes = CPU_TO_LE16(num_l2_nodes); 893 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 894 } 895 896 /** 897 * ice_sched_add_elems - add nodes to HW and SW DB 898 * @pi: port information structure 899 * @tc_node: pointer to the branch node 900 * @parent: pointer to the parent node 901 * @layer: layer number to add nodes 902 * @num_nodes: number of nodes 903 * @num_nodes_added: pointer to num nodes added 904 * @first_node_teid: if new nodes are added then return the TEID of first node 905 * 906 * This function add nodes to HW as well as to SW DB for a given layer 907 */ 908 static enum ice_status 909 ice_sched_add_elems(struct ice_port_info *pi, struct ice_sched_node *tc_node, 910 struct ice_sched_node *parent, u8 layer, u16 num_nodes, 911 u16 *num_nodes_added, u32 *first_node_teid) 912 { 913 struct ice_sched_node *prev, *new_node; 914 struct ice_aqc_add_elem *buf; 915 u16 i, num_groups_added = 0; 916 enum ice_status status = ICE_SUCCESS; 917 struct ice_hw *hw = pi->hw; 918 u16 buf_size; 919 u32 teid; 920 921 buf_size = ice_struct_size(buf, generic, num_nodes); 922 buf = (struct ice_aqc_add_elem *)ice_malloc(hw, buf_size); 923 if (!buf) 924 return ICE_ERR_NO_MEMORY; 925 926 buf->hdr.parent_teid = parent->info.node_teid; 927 buf->hdr.num_elems = CPU_TO_LE16(num_nodes); 928 for (i = 0; i < num_nodes; i++) { 929 buf->generic[i].parent_teid = parent->info.node_teid; 930 buf->generic[i].data.elem_type = ICE_AQC_ELEM_TYPE_SE_GENERIC; 931 buf->generic[i].data.valid_sections = 932 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 933 ICE_AQC_ELEM_VALID_EIR; 934 buf->generic[i].data.generic = 0; 935 buf->generic[i].data.cir_bw.bw_profile_idx = 936 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); 937 buf->generic[i].data.cir_bw.bw_alloc = 938 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); 939 buf->generic[i].data.eir_bw.bw_profile_idx = 940 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); 941 buf->generic[i].data.eir_bw.bw_alloc = 942 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); 943 } 944 945 status = ice_aq_add_sched_elems(hw, 1, buf, buf_size, 946 &num_groups_added, NULL); 947 if (status != ICE_SUCCESS || num_groups_added != 1) { 948 ice_debug(hw, ICE_DBG_SCHED, "add node failed FW Error %d\n", 949 hw->adminq.sq_last_status); 950 ice_free(hw, buf); 951 return ICE_ERR_CFG; 952 } 953 954 *num_nodes_added = num_nodes; 955 /* add nodes to the SW DB */ 956 for (i = 0; i < num_nodes; i++) { 957 status = ice_sched_add_node(pi, layer, &buf->generic[i]); 958 if (status != ICE_SUCCESS) { 959 ice_debug(hw, ICE_DBG_SCHED, "add nodes in SW DB failed status =%d\n", 960 status); 961 break; 962 } 963 964 teid = LE32_TO_CPU(buf->generic[i].node_teid); 965 new_node = ice_sched_find_node_by_teid(parent, teid); 966 if (!new_node) { 967 ice_debug(hw, ICE_DBG_SCHED, "Node is missing for teid =%d\n", teid); 968 break; 969 } 970 971 new_node->sibling = NULL; 972 new_node->tc_num = tc_node->tc_num; 973 974 /* add it to previous node sibling pointer */ 975 /* Note: siblings are not linked across branches */ 976 prev = ice_sched_get_first_node(pi, tc_node, layer); 977 if (prev && prev != new_node) { 978 while (prev->sibling) 979 prev = prev->sibling; 980 prev->sibling = new_node; 981 } 982 983 /* initialize the sibling head */ 984 if (!pi->sib_head[tc_node->tc_num][layer]) 985 pi->sib_head[tc_node->tc_num][layer] = new_node; 986 987 if (i == 0) 988 *first_node_teid = teid; 989 } 990 991 ice_free(hw, buf); 992 return status; 993 } 994 995 /** 996 * ice_sched_add_nodes_to_hw_layer - Add nodes to hw layer 997 * @pi: port information structure 998 * @tc_node: pointer to TC node 999 * @parent: pointer to parent node 1000 * @layer: layer number to add nodes 1001 * @num_nodes: number of nodes to be added 1002 * @first_node_teid: pointer to the first node TEID 1003 * @num_nodes_added: pointer to number of nodes added 1004 * 1005 * Add nodes into specific hw layer. 1006 */ 1007 static enum ice_status 1008 ice_sched_add_nodes_to_hw_layer(struct ice_port_info *pi, 1009 struct ice_sched_node *tc_node, 1010 struct ice_sched_node *parent, u8 layer, 1011 u16 num_nodes, u32 *first_node_teid, 1012 u16 *num_nodes_added) 1013 { 1014 u16 max_child_nodes; 1015 1016 *num_nodes_added = 0; 1017 1018 if (!num_nodes) 1019 return ICE_SUCCESS; 1020 1021 if (!parent || layer < pi->hw->sw_entry_point_layer) 1022 return ICE_ERR_PARAM; 1023 1024 /* max children per node per layer */ 1025 max_child_nodes = pi->hw->max_children[parent->tx_sched_layer]; 1026 1027 /* current number of children + required nodes exceed max children */ 1028 if ((parent->num_children + num_nodes) > max_child_nodes) { 1029 /* Fail if the parent is a TC node */ 1030 if (parent == tc_node) 1031 return ICE_ERR_CFG; 1032 return ICE_ERR_MAX_LIMIT; 1033 } 1034 1035 return ice_sched_add_elems(pi, tc_node, parent, layer, num_nodes, 1036 num_nodes_added, first_node_teid); 1037 } 1038 1039 /** 1040 * ice_sched_add_nodes_to_layer - Add nodes to a given layer 1041 * @pi: port information structure 1042 * @tc_node: pointer to TC node 1043 * @parent: pointer to parent node 1044 * @layer: layer number to add nodes 1045 * @num_nodes: number of nodes to be added 1046 * @first_node_teid: pointer to the first node TEID 1047 * @num_nodes_added: pointer to number of nodes added 1048 * 1049 * This function add nodes to a given layer. 1050 */ 1051 static enum ice_status 1052 ice_sched_add_nodes_to_layer(struct ice_port_info *pi, 1053 struct ice_sched_node *tc_node, 1054 struct ice_sched_node *parent, u8 layer, 1055 u16 num_nodes, u32 *first_node_teid, 1056 u16 *num_nodes_added) 1057 { 1058 u32 *first_teid_ptr = first_node_teid; 1059 u16 new_num_nodes = num_nodes; 1060 enum ice_status status = ICE_SUCCESS; 1061 1062 *num_nodes_added = 0; 1063 while (*num_nodes_added < num_nodes) { 1064 u16 max_child_nodes, num_added = 0; 1065 u32 temp; 1066 1067 status = ice_sched_add_nodes_to_hw_layer(pi, tc_node, parent, 1068 layer, new_num_nodes, 1069 first_teid_ptr, 1070 &num_added); 1071 if (status == ICE_SUCCESS) 1072 *num_nodes_added += num_added; 1073 /* added more nodes than requested ? */ 1074 if (*num_nodes_added > num_nodes) { 1075 ice_debug(pi->hw, ICE_DBG_SCHED, "added extra nodes %d %d\n", num_nodes, 1076 *num_nodes_added); 1077 status = ICE_ERR_CFG; 1078 break; 1079 } 1080 /* break if all the nodes are added successfully */ 1081 if (status == ICE_SUCCESS && (*num_nodes_added == num_nodes)) 1082 break; 1083 /* break if the error is not max limit */ 1084 if (status != ICE_SUCCESS && status != ICE_ERR_MAX_LIMIT) 1085 break; 1086 /* Exceeded the max children */ 1087 max_child_nodes = pi->hw->max_children[parent->tx_sched_layer]; 1088 /* utilize all the spaces if the parent is not full */ 1089 if (parent->num_children < max_child_nodes) { 1090 new_num_nodes = max_child_nodes - parent->num_children; 1091 } else { 1092 /* This parent is full, try the next sibling */ 1093 parent = parent->sibling; 1094 /* Don't modify the first node TEID memory if the 1095 * first node was added already in the above call. 1096 * Instead send some temp memory for all other 1097 * recursive calls. 1098 */ 1099 if (num_added) 1100 first_teid_ptr = &temp; 1101 1102 new_num_nodes = num_nodes - *num_nodes_added; 1103 } 1104 } 1105 return status; 1106 } 1107 1108 /** 1109 * ice_sched_get_qgrp_layer - get the current queue group layer number 1110 * @hw: pointer to the HW struct 1111 * 1112 * This function returns the current queue group layer number 1113 */ 1114 static u8 ice_sched_get_qgrp_layer(struct ice_hw *hw) 1115 { 1116 /* It's always total layers - 1, the array is 0 relative so -2 */ 1117 return hw->num_tx_sched_layers - ICE_QGRP_LAYER_OFFSET; 1118 } 1119 1120 /** 1121 * ice_sched_get_vsi_layer - get the current VSI layer number 1122 * @hw: pointer to the HW struct 1123 * 1124 * This function returns the current VSI layer number 1125 */ 1126 static u8 ice_sched_get_vsi_layer(struct ice_hw *hw) 1127 { 1128 /* Num Layers VSI layer 1129 * 9 6 1130 * 7 4 1131 * 5 or less sw_entry_point_layer 1132 */ 1133 /* calculate the VSI layer based on number of layers. */ 1134 if (hw->num_tx_sched_layers > ICE_VSI_LAYER_OFFSET + 1) { 1135 u8 layer = hw->num_tx_sched_layers - ICE_VSI_LAYER_OFFSET; 1136 1137 if (layer > hw->sw_entry_point_layer) 1138 return layer; 1139 } 1140 return hw->sw_entry_point_layer; 1141 } 1142 1143 /** 1144 * ice_sched_get_agg_layer - get the current aggregator layer number 1145 * @hw: pointer to the HW struct 1146 * 1147 * This function returns the current aggregator layer number 1148 */ 1149 static u8 ice_sched_get_agg_layer(struct ice_hw *hw) 1150 { 1151 /* Num Layers aggregator layer 1152 * 9 4 1153 * 7 or less sw_entry_point_layer 1154 */ 1155 /* calculate the aggregator layer based on number of layers. */ 1156 if (hw->num_tx_sched_layers > ICE_AGG_LAYER_OFFSET + 1) { 1157 u8 layer = hw->num_tx_sched_layers - ICE_AGG_LAYER_OFFSET; 1158 1159 if (layer > hw->sw_entry_point_layer) 1160 return layer; 1161 } 1162 return hw->sw_entry_point_layer; 1163 } 1164 1165 /** 1166 * ice_rm_dflt_leaf_node - remove the default leaf node in the tree 1167 * @pi: port information structure 1168 * 1169 * This function removes the leaf node that was created by the FW 1170 * during initialization 1171 */ 1172 static void ice_rm_dflt_leaf_node(struct ice_port_info *pi) 1173 { 1174 struct ice_sched_node *node; 1175 1176 node = pi->root; 1177 while (node) { 1178 if (!node->num_children) 1179 break; 1180 node = node->children[0]; 1181 } 1182 if (node && node->info.data.elem_type == ICE_AQC_ELEM_TYPE_LEAF) { 1183 u32 teid = LE32_TO_CPU(node->info.node_teid); 1184 enum ice_status status; 1185 1186 /* remove the default leaf node */ 1187 status = ice_sched_remove_elems(pi->hw, node->parent, 1, &teid); 1188 if (!status) 1189 ice_free_sched_node(pi, node); 1190 } 1191 } 1192 1193 /** 1194 * ice_sched_rm_dflt_nodes - free the default nodes in the tree 1195 * @pi: port information structure 1196 * 1197 * This function frees all the nodes except root and TC that were created by 1198 * the FW during initialization 1199 */ 1200 static void ice_sched_rm_dflt_nodes(struct ice_port_info *pi) 1201 { 1202 struct ice_sched_node *node; 1203 1204 ice_rm_dflt_leaf_node(pi); 1205 1206 /* remove the default nodes except TC and root nodes */ 1207 node = pi->root; 1208 while (node) { 1209 if (node->tx_sched_layer >= pi->hw->sw_entry_point_layer && 1210 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_TC && 1211 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_ROOT_PORT) { 1212 ice_free_sched_node(pi, node); 1213 break; 1214 } 1215 1216 if (!node->num_children) 1217 break; 1218 node = node->children[0]; 1219 } 1220 } 1221 1222 /** 1223 * ice_sched_init_port - Initialize scheduler by querying information from FW 1224 * @pi: port info structure for the tree to cleanup 1225 * 1226 * This function is the initial call to find the total number of Tx scheduler 1227 * resources, default topology created by firmware and storing the information 1228 * in SW DB. 1229 */ 1230 enum ice_status ice_sched_init_port(struct ice_port_info *pi) 1231 { 1232 struct ice_aqc_get_topo_elem *buf; 1233 enum ice_status status; 1234 struct ice_hw *hw; 1235 u8 num_branches; 1236 u16 num_elems; 1237 u8 i, j; 1238 1239 if (!pi) 1240 return ICE_ERR_PARAM; 1241 hw = pi->hw; 1242 1243 /* Query the Default Topology from FW */ 1244 buf = (struct ice_aqc_get_topo_elem *)ice_malloc(hw, 1245 ICE_AQ_MAX_BUF_LEN); 1246 if (!buf) 1247 return ICE_ERR_NO_MEMORY; 1248 1249 /* Query default scheduling tree topology */ 1250 status = ice_aq_get_dflt_topo(hw, pi->lport, buf, ICE_AQ_MAX_BUF_LEN, 1251 &num_branches, NULL); 1252 if (status) 1253 goto err_init_port; 1254 1255 /* num_branches should be between 1-8 */ 1256 if (num_branches < 1 || num_branches > ICE_TXSCHED_MAX_BRANCHES) { 1257 ice_debug(hw, ICE_DBG_SCHED, "num_branches unexpected %d\n", 1258 num_branches); 1259 status = ICE_ERR_PARAM; 1260 goto err_init_port; 1261 } 1262 1263 /* get the number of elements on the default/first branch */ 1264 num_elems = LE16_TO_CPU(buf[0].hdr.num_elems); 1265 1266 /* num_elems should always be between 1-9 */ 1267 if (num_elems < 1 || num_elems > ICE_AQC_TOPO_MAX_LEVEL_NUM) { 1268 ice_debug(hw, ICE_DBG_SCHED, "num_elems unexpected %d\n", 1269 num_elems); 1270 status = ICE_ERR_PARAM; 1271 goto err_init_port; 1272 } 1273 1274 /* If the last node is a leaf node then the index of the queue group 1275 * layer is two less than the number of elements. 1276 */ 1277 if (num_elems > 2 && buf[0].generic[num_elems - 1].data.elem_type == 1278 ICE_AQC_ELEM_TYPE_LEAF) 1279 pi->last_node_teid = 1280 LE32_TO_CPU(buf[0].generic[num_elems - 2].node_teid); 1281 else 1282 pi->last_node_teid = 1283 LE32_TO_CPU(buf[0].generic[num_elems - 1].node_teid); 1284 1285 /* Insert the Tx Sched root node */ 1286 status = ice_sched_add_root_node(pi, &buf[0].generic[0]); 1287 if (status) 1288 goto err_init_port; 1289 1290 /* Parse the default tree and cache the information */ 1291 for (i = 0; i < num_branches; i++) { 1292 num_elems = LE16_TO_CPU(buf[i].hdr.num_elems); 1293 1294 /* Skip root element as already inserted */ 1295 for (j = 1; j < num_elems; j++) { 1296 /* update the sw entry point */ 1297 if (buf[0].generic[j].data.elem_type == 1298 ICE_AQC_ELEM_TYPE_ENTRY_POINT) 1299 hw->sw_entry_point_layer = j; 1300 1301 status = ice_sched_add_node(pi, j, &buf[i].generic[j]); 1302 if (status) 1303 goto err_init_port; 1304 } 1305 } 1306 1307 /* Remove the default nodes. */ 1308 if (pi->root) 1309 ice_sched_rm_dflt_nodes(pi); 1310 1311 /* initialize the port for handling the scheduler tree */ 1312 pi->port_state = ICE_SCHED_PORT_STATE_READY; 1313 ice_init_lock(&pi->sched_lock); 1314 for (i = 0; i < ICE_AQC_TOPO_MAX_LEVEL_NUM; i++) 1315 INIT_LIST_HEAD(&hw->rl_prof_list[i]); 1316 1317 err_init_port: 1318 if (status && pi->root) { 1319 ice_free_sched_node(pi, pi->root); 1320 pi->root = NULL; 1321 } 1322 1323 ice_free(hw, buf); 1324 return status; 1325 } 1326 1327 /** 1328 * ice_sched_get_node - Get the struct ice_sched_node for given TEID 1329 * @pi: port information structure 1330 * @teid: Scheduler node TEID 1331 * 1332 * This function retrieves the ice_sched_node struct for given TEID from 1333 * the SW DB and returns it to the caller. 1334 */ 1335 struct ice_sched_node *ice_sched_get_node(struct ice_port_info *pi, u32 teid) 1336 { 1337 struct ice_sched_node *node; 1338 1339 if (!pi) 1340 return NULL; 1341 1342 /* Find the node starting from root */ 1343 ice_acquire_lock(&pi->sched_lock); 1344 node = ice_sched_find_node_by_teid(pi->root, teid); 1345 ice_release_lock(&pi->sched_lock); 1346 1347 if (!node) 1348 ice_debug(pi->hw, ICE_DBG_SCHED, "Node not found for teid=0x%x\n", teid); 1349 1350 return node; 1351 } 1352 1353 /** 1354 * ice_sched_query_res_alloc - query the FW for num of logical sched layers 1355 * @hw: pointer to the HW struct 1356 * 1357 * query FW for allocated scheduler resources and store in HW struct 1358 */ 1359 enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw) 1360 { 1361 struct ice_aqc_query_txsched_res_resp *buf; 1362 enum ice_status status = ICE_SUCCESS; 1363 __le16 max_sibl; 1364 u8 i; 1365 1366 if (hw->layer_info) 1367 return status; 1368 1369 buf = (struct ice_aqc_query_txsched_res_resp *) 1370 ice_malloc(hw, sizeof(*buf)); 1371 if (!buf) 1372 return ICE_ERR_NO_MEMORY; 1373 1374 status = ice_aq_query_sched_res(hw, sizeof(*buf), buf, NULL); 1375 if (status) 1376 goto sched_query_out; 1377 1378 hw->num_tx_sched_layers = LE16_TO_CPU(buf->sched_props.logical_levels); 1379 hw->num_tx_sched_phys_layers = 1380 LE16_TO_CPU(buf->sched_props.phys_levels); 1381 hw->flattened_layers = buf->sched_props.flattening_bitmap; 1382 hw->max_cgds = buf->sched_props.max_pf_cgds; 1383 1384 /* max sibling group size of current layer refers to the max children 1385 * of the below layer node. 1386 * layer 1 node max children will be layer 2 max sibling group size 1387 * layer 2 node max children will be layer 3 max sibling group size 1388 * and so on. This array will be populated from root (index 0) to 1389 * qgroup layer 7. Leaf node has no children. 1390 */ 1391 for (i = 0; i < hw->num_tx_sched_layers - 1; i++) { 1392 max_sibl = buf->layer_props[i + 1].max_sibl_grp_sz; 1393 hw->max_children[i] = LE16_TO_CPU(max_sibl); 1394 } 1395 1396 hw->layer_info = (struct ice_aqc_layer_props *) 1397 ice_memdup(hw, buf->layer_props, 1398 (hw->num_tx_sched_layers * 1399 sizeof(*hw->layer_info)), 1400 ICE_NONDMA_TO_NONDMA); 1401 if (!hw->layer_info) { 1402 status = ICE_ERR_NO_MEMORY; 1403 goto sched_query_out; 1404 } 1405 1406 sched_query_out: 1407 ice_free(hw, buf); 1408 return status; 1409 } 1410 1411 /** 1412 * ice_sched_get_psm_clk_freq - determine the PSM clock frequency 1413 * @hw: pointer to the HW struct 1414 * 1415 * Determine the PSM clock frequency and store in HW struct 1416 */ 1417 void ice_sched_get_psm_clk_freq(struct ice_hw *hw) 1418 { 1419 u32 val, clk_src; 1420 1421 val = rd32(hw, GLGEN_CLKSTAT_SRC); 1422 clk_src = (val & GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M) >> 1423 GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_S; 1424 1425 #define PSM_CLK_SRC_367_MHZ 0x0 1426 #define PSM_CLK_SRC_416_MHZ 0x1 1427 #define PSM_CLK_SRC_446_MHZ 0x2 1428 #define PSM_CLK_SRC_390_MHZ 0x3 1429 1430 switch (clk_src) { 1431 case PSM_CLK_SRC_367_MHZ: 1432 hw->psm_clk_freq = ICE_PSM_CLK_367MHZ_IN_HZ; 1433 break; 1434 case PSM_CLK_SRC_416_MHZ: 1435 hw->psm_clk_freq = ICE_PSM_CLK_416MHZ_IN_HZ; 1436 break; 1437 case PSM_CLK_SRC_446_MHZ: 1438 hw->psm_clk_freq = ICE_PSM_CLK_446MHZ_IN_HZ; 1439 break; 1440 case PSM_CLK_SRC_390_MHZ: 1441 hw->psm_clk_freq = ICE_PSM_CLK_390MHZ_IN_HZ; 1442 break; 1443 default: 1444 ice_debug(hw, ICE_DBG_SCHED, "PSM clk_src unexpected %u\n", 1445 clk_src); 1446 /* fall back to a safe default */ 1447 hw->psm_clk_freq = ICE_PSM_CLK_446MHZ_IN_HZ; 1448 } 1449 } 1450 1451 /** 1452 * ice_sched_find_node_in_subtree - Find node in part of base node subtree 1453 * @hw: pointer to the HW struct 1454 * @base: pointer to the base node 1455 * @node: pointer to the node to search 1456 * 1457 * This function checks whether a given node is part of the base node 1458 * subtree or not 1459 */ 1460 bool 1461 ice_sched_find_node_in_subtree(struct ice_hw *hw, struct ice_sched_node *base, 1462 struct ice_sched_node *node) 1463 { 1464 u8 i; 1465 1466 for (i = 0; i < base->num_children; i++) { 1467 struct ice_sched_node *child = base->children[i]; 1468 1469 if (node == child) 1470 return true; 1471 1472 if (child->tx_sched_layer > node->tx_sched_layer) 1473 return false; 1474 1475 /* this recursion is intentional, and wouldn't 1476 * go more than 8 calls 1477 */ 1478 if (ice_sched_find_node_in_subtree(hw, child, node)) 1479 return true; 1480 } 1481 return false; 1482 } 1483 1484 /** 1485 * ice_sched_get_free_qgrp - Scan all queue group siblings and find a free node 1486 * @pi: port information structure 1487 * @vsi_node: software VSI handle 1488 * @qgrp_node: first queue group node identified for scanning 1489 * @owner: LAN or RDMA 1490 * 1491 * This function retrieves a free LAN or RDMA queue group node by scanning 1492 * qgrp_node and its siblings for the queue group with the fewest number 1493 * of queues currently assigned. 1494 */ 1495 static struct ice_sched_node * 1496 ice_sched_get_free_qgrp(struct ice_port_info *pi, 1497 struct ice_sched_node *vsi_node, 1498 struct ice_sched_node *qgrp_node, u8 owner) 1499 { 1500 struct ice_sched_node *min_qgrp; 1501 u8 min_children; 1502 1503 if (!qgrp_node) 1504 return qgrp_node; 1505 min_children = qgrp_node->num_children; 1506 if (!min_children) 1507 return qgrp_node; 1508 min_qgrp = qgrp_node; 1509 /* scan all queue groups until find a node which has less than the 1510 * minimum number of children. This way all queue group nodes get 1511 * equal number of shares and active. The bandwidth will be equally 1512 * distributed across all queues. 1513 */ 1514 while (qgrp_node) { 1515 /* make sure the qgroup node is part of the VSI subtree */ 1516 if (ice_sched_find_node_in_subtree(pi->hw, vsi_node, qgrp_node)) 1517 if (qgrp_node->num_children < min_children && 1518 qgrp_node->owner == owner) { 1519 /* replace the new min queue group node */ 1520 min_qgrp = qgrp_node; 1521 min_children = min_qgrp->num_children; 1522 /* break if it has no children, */ 1523 if (!min_children) 1524 break; 1525 } 1526 qgrp_node = qgrp_node->sibling; 1527 } 1528 return min_qgrp; 1529 } 1530 1531 /** 1532 * ice_sched_get_free_qparent - Get a free LAN or RDMA queue group node 1533 * @pi: port information structure 1534 * @vsi_handle: software VSI handle 1535 * @tc: branch number 1536 * @owner: LAN or RDMA 1537 * 1538 * This function retrieves a free LAN or RDMA queue group node 1539 */ 1540 struct ice_sched_node * 1541 ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 1542 u8 owner) 1543 { 1544 struct ice_sched_node *vsi_node, *qgrp_node; 1545 struct ice_vsi_ctx *vsi_ctx; 1546 u16 max_children; 1547 u8 qgrp_layer; 1548 1549 qgrp_layer = ice_sched_get_qgrp_layer(pi->hw); 1550 max_children = pi->hw->max_children[qgrp_layer]; 1551 1552 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 1553 if (!vsi_ctx) 1554 return NULL; 1555 vsi_node = vsi_ctx->sched.vsi_node[tc]; 1556 /* validate invalid VSI ID */ 1557 if (!vsi_node) 1558 return NULL; 1559 1560 /* get the first queue group node from VSI sub-tree */ 1561 qgrp_node = ice_sched_get_first_node(pi, vsi_node, qgrp_layer); 1562 while (qgrp_node) { 1563 /* make sure the qgroup node is part of the VSI subtree */ 1564 if (ice_sched_find_node_in_subtree(pi->hw, vsi_node, qgrp_node)) 1565 if (qgrp_node->num_children < max_children && 1566 qgrp_node->owner == owner) 1567 break; 1568 qgrp_node = qgrp_node->sibling; 1569 } 1570 1571 /* Select the best queue group */ 1572 return ice_sched_get_free_qgrp(pi, vsi_node, qgrp_node, owner); 1573 } 1574 1575 /** 1576 * ice_sched_get_vsi_node - Get a VSI node based on VSI ID 1577 * @pi: pointer to the port information structure 1578 * @tc_node: pointer to the TC node 1579 * @vsi_handle: software VSI handle 1580 * 1581 * This function retrieves a VSI node for a given VSI ID from a given 1582 * TC branch 1583 */ 1584 struct ice_sched_node * 1585 ice_sched_get_vsi_node(struct ice_port_info *pi, struct ice_sched_node *tc_node, 1586 u16 vsi_handle) 1587 { 1588 struct ice_sched_node *node; 1589 u8 vsi_layer; 1590 1591 vsi_layer = ice_sched_get_vsi_layer(pi->hw); 1592 node = ice_sched_get_first_node(pi, tc_node, vsi_layer); 1593 1594 /* Check whether it already exists */ 1595 while (node) { 1596 if (node->vsi_handle == vsi_handle) 1597 return node; 1598 node = node->sibling; 1599 } 1600 1601 return node; 1602 } 1603 1604 /** 1605 * ice_sched_get_agg_node - Get an aggregator node based on aggregator ID 1606 * @pi: pointer to the port information structure 1607 * @tc_node: pointer to the TC node 1608 * @agg_id: aggregator ID 1609 * 1610 * This function retrieves an aggregator node for a given aggregator ID from 1611 * a given TC branch 1612 */ 1613 static struct ice_sched_node * 1614 ice_sched_get_agg_node(struct ice_port_info *pi, struct ice_sched_node *tc_node, 1615 u32 agg_id) 1616 { 1617 struct ice_sched_node *node; 1618 struct ice_hw *hw = pi->hw; 1619 u8 agg_layer; 1620 1621 if (!hw) 1622 return NULL; 1623 agg_layer = ice_sched_get_agg_layer(hw); 1624 node = ice_sched_get_first_node(pi, tc_node, agg_layer); 1625 1626 /* Check whether it already exists */ 1627 while (node) { 1628 if (node->agg_id == agg_id) 1629 return node; 1630 node = node->sibling; 1631 } 1632 1633 return node; 1634 } 1635 1636 /** 1637 * ice_sched_check_node - Compare node parameters between SW DB and HW DB 1638 * @hw: pointer to the HW struct 1639 * @node: pointer to the ice_sched_node struct 1640 * 1641 * This function queries and compares the HW element with SW DB node parameters 1642 */ 1643 static bool ice_sched_check_node(struct ice_hw *hw, struct ice_sched_node *node) 1644 { 1645 struct ice_aqc_txsched_elem_data buf; 1646 enum ice_status status; 1647 u32 node_teid; 1648 1649 node_teid = LE32_TO_CPU(node->info.node_teid); 1650 status = ice_sched_query_elem(hw, node_teid, &buf); 1651 if (status != ICE_SUCCESS) 1652 return false; 1653 1654 if (memcmp(&buf, &node->info, sizeof(buf))) { 1655 ice_debug(hw, ICE_DBG_SCHED, "Node mismatch for teid=0x%x\n", 1656 node_teid); 1657 return false; 1658 } 1659 1660 return true; 1661 } 1662 1663 /** 1664 * ice_sched_calc_vsi_child_nodes - calculate number of VSI child nodes 1665 * @hw: pointer to the HW struct 1666 * @num_qs: number of queues 1667 * @num_nodes: num nodes array 1668 * 1669 * This function calculates the number of VSI child nodes based on the 1670 * number of queues. 1671 */ 1672 static void 1673 ice_sched_calc_vsi_child_nodes(struct ice_hw *hw, u16 num_qs, u16 *num_nodes) 1674 { 1675 u16 num = num_qs; 1676 u8 i, qgl, vsil; 1677 1678 qgl = ice_sched_get_qgrp_layer(hw); 1679 vsil = ice_sched_get_vsi_layer(hw); 1680 1681 /* calculate num nodes from queue group to VSI layer */ 1682 for (i = qgl; i > vsil; i--) { 1683 /* round to the next integer if there is a remainder */ 1684 num = DIVIDE_AND_ROUND_UP(num, hw->max_children[i]); 1685 1686 /* need at least one node */ 1687 num_nodes[i] = num ? num : 1; 1688 } 1689 } 1690 1691 /** 1692 * ice_sched_add_vsi_child_nodes - add VSI child nodes to tree 1693 * @pi: port information structure 1694 * @vsi_handle: software VSI handle 1695 * @tc_node: pointer to the TC node 1696 * @num_nodes: pointer to the num nodes that needs to be added per layer 1697 * @owner: node owner (LAN or RDMA) 1698 * 1699 * This function adds the VSI child nodes to tree. It gets called for 1700 * LAN and RDMA separately. 1701 */ 1702 static enum ice_status 1703 ice_sched_add_vsi_child_nodes(struct ice_port_info *pi, u16 vsi_handle, 1704 struct ice_sched_node *tc_node, u16 *num_nodes, 1705 u8 owner) 1706 { 1707 struct ice_sched_node *parent, *node; 1708 struct ice_hw *hw = pi->hw; 1709 enum ice_status status; 1710 u32 first_node_teid; 1711 u16 num_added = 0; 1712 u8 i, qgl, vsil; 1713 1714 qgl = ice_sched_get_qgrp_layer(hw); 1715 vsil = ice_sched_get_vsi_layer(hw); 1716 parent = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 1717 for (i = vsil + 1; i <= qgl; i++) { 1718 if (!parent) 1719 return ICE_ERR_CFG; 1720 1721 status = ice_sched_add_nodes_to_layer(pi, tc_node, parent, i, 1722 num_nodes[i], 1723 &first_node_teid, 1724 &num_added); 1725 if (status != ICE_SUCCESS || num_nodes[i] != num_added) 1726 return ICE_ERR_CFG; 1727 1728 /* The newly added node can be a new parent for the next 1729 * layer nodes 1730 */ 1731 if (num_added) { 1732 parent = ice_sched_find_node_by_teid(tc_node, 1733 first_node_teid); 1734 node = parent; 1735 while (node) { 1736 node->owner = owner; 1737 node = node->sibling; 1738 } 1739 } else { 1740 parent = parent->children[0]; 1741 } 1742 } 1743 1744 return ICE_SUCCESS; 1745 } 1746 1747 /** 1748 * ice_sched_calc_vsi_support_nodes - calculate number of VSI support nodes 1749 * @pi: pointer to the port info structure 1750 * @tc_node: pointer to TC node 1751 * @num_nodes: pointer to num nodes array 1752 * 1753 * This function calculates the number of supported nodes needed to add this 1754 * VSI into Tx tree including the VSI, parent and intermediate nodes in below 1755 * layers 1756 */ 1757 static void 1758 ice_sched_calc_vsi_support_nodes(struct ice_port_info *pi, 1759 struct ice_sched_node *tc_node, u16 *num_nodes) 1760 { 1761 struct ice_sched_node *node; 1762 u8 vsil; 1763 int i; 1764 1765 vsil = ice_sched_get_vsi_layer(pi->hw); 1766 for (i = vsil; i >= pi->hw->sw_entry_point_layer; i--) 1767 /* Add intermediate nodes if TC has no children and 1768 * need at least one node for VSI 1769 */ 1770 if (!tc_node->num_children || i == vsil) { 1771 num_nodes[i]++; 1772 } else { 1773 /* If intermediate nodes are reached max children 1774 * then add a new one. 1775 */ 1776 node = ice_sched_get_first_node(pi, tc_node, (u8)i); 1777 /* scan all the siblings */ 1778 while (node) { 1779 if (node->num_children < 1780 pi->hw->max_children[i]) 1781 break; 1782 node = node->sibling; 1783 } 1784 1785 /* tree has one intermediate node to add this new VSI. 1786 * So no need to calculate supported nodes for below 1787 * layers. 1788 */ 1789 if (node) 1790 break; 1791 /* all the nodes are full, allocate a new one */ 1792 num_nodes[i]++; 1793 } 1794 } 1795 1796 /** 1797 * ice_sched_add_vsi_support_nodes - add VSI supported nodes into Tx tree 1798 * @pi: port information structure 1799 * @vsi_handle: software VSI handle 1800 * @tc_node: pointer to TC node 1801 * @num_nodes: pointer to num nodes array 1802 * 1803 * This function adds the VSI supported nodes into Tx tree including the 1804 * VSI, its parent and intermediate nodes in below layers 1805 */ 1806 static enum ice_status 1807 ice_sched_add_vsi_support_nodes(struct ice_port_info *pi, u16 vsi_handle, 1808 struct ice_sched_node *tc_node, u16 *num_nodes) 1809 { 1810 struct ice_sched_node *parent = tc_node; 1811 enum ice_status status; 1812 u32 first_node_teid; 1813 u16 num_added = 0; 1814 u8 i, vsil; 1815 1816 if (!pi) 1817 return ICE_ERR_PARAM; 1818 1819 vsil = ice_sched_get_vsi_layer(pi->hw); 1820 for (i = pi->hw->sw_entry_point_layer; i <= vsil; i++) { 1821 status = ice_sched_add_nodes_to_layer(pi, tc_node, parent, 1822 i, num_nodes[i], 1823 &first_node_teid, 1824 &num_added); 1825 if (status != ICE_SUCCESS || num_nodes[i] != num_added) 1826 return ICE_ERR_CFG; 1827 1828 /* The newly added node can be a new parent for the next 1829 * layer nodes 1830 */ 1831 if (num_added) 1832 parent = ice_sched_find_node_by_teid(tc_node, 1833 first_node_teid); 1834 else 1835 parent = parent->children[0]; 1836 1837 if (!parent) 1838 return ICE_ERR_CFG; 1839 1840 if (i == vsil) 1841 parent->vsi_handle = vsi_handle; 1842 } 1843 1844 return ICE_SUCCESS; 1845 } 1846 1847 /** 1848 * ice_sched_add_vsi_to_topo - add a new VSI into tree 1849 * @pi: port information structure 1850 * @vsi_handle: software VSI handle 1851 * @tc: TC number 1852 * 1853 * This function adds a new VSI into scheduler tree 1854 */ 1855 static enum ice_status 1856 ice_sched_add_vsi_to_topo(struct ice_port_info *pi, u16 vsi_handle, u8 tc) 1857 { 1858 u16 num_nodes[ICE_AQC_TOPO_MAX_LEVEL_NUM] = { 0 }; 1859 struct ice_sched_node *tc_node; 1860 1861 tc_node = ice_sched_get_tc_node(pi, tc); 1862 if (!tc_node) 1863 return ICE_ERR_PARAM; 1864 1865 /* calculate number of supported nodes needed for this VSI */ 1866 ice_sched_calc_vsi_support_nodes(pi, tc_node, num_nodes); 1867 1868 /* add VSI supported nodes to TC subtree */ 1869 return ice_sched_add_vsi_support_nodes(pi, vsi_handle, tc_node, 1870 num_nodes); 1871 } 1872 1873 /** 1874 * ice_sched_update_vsi_child_nodes - update VSI child nodes 1875 * @pi: port information structure 1876 * @vsi_handle: software VSI handle 1877 * @tc: TC number 1878 * @new_numqs: new number of max queues 1879 * @owner: owner of this subtree 1880 * 1881 * This function updates the VSI child nodes based on the number of queues 1882 */ 1883 static enum ice_status 1884 ice_sched_update_vsi_child_nodes(struct ice_port_info *pi, u16 vsi_handle, 1885 u8 tc, u16 new_numqs, u8 owner) 1886 { 1887 u16 new_num_nodes[ICE_AQC_TOPO_MAX_LEVEL_NUM] = { 0 }; 1888 struct ice_sched_node *vsi_node; 1889 struct ice_sched_node *tc_node; 1890 struct ice_vsi_ctx *vsi_ctx; 1891 enum ice_status status = ICE_SUCCESS; 1892 struct ice_hw *hw = pi->hw; 1893 u16 prev_numqs; 1894 1895 tc_node = ice_sched_get_tc_node(pi, tc); 1896 if (!tc_node) 1897 return ICE_ERR_CFG; 1898 1899 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 1900 if (!vsi_node) 1901 return ICE_ERR_CFG; 1902 1903 vsi_ctx = ice_get_vsi_ctx(hw, vsi_handle); 1904 if (!vsi_ctx) 1905 return ICE_ERR_PARAM; 1906 1907 prev_numqs = vsi_ctx->sched.max_lanq[tc]; 1908 /* num queues are not changed or less than the previous number */ 1909 if (new_numqs <= prev_numqs) 1910 return status; 1911 status = ice_alloc_lan_q_ctx(hw, vsi_handle, tc, new_numqs); 1912 if (status) 1913 return status; 1914 1915 if (new_numqs) 1916 ice_sched_calc_vsi_child_nodes(hw, new_numqs, new_num_nodes); 1917 /* Keep the max number of queue configuration all the time. Update the 1918 * tree only if number of queues > previous number of queues. This may 1919 * leave some extra nodes in the tree if number of queues < previous 1920 * number but that wouldn't harm anything. Removing those extra nodes 1921 * may complicate the code if those nodes are part of SRL or 1922 * individually rate limited. 1923 */ 1924 status = ice_sched_add_vsi_child_nodes(pi, vsi_handle, tc_node, 1925 new_num_nodes, owner); 1926 if (status) 1927 return status; 1928 vsi_ctx->sched.max_lanq[tc] = new_numqs; 1929 1930 return ICE_SUCCESS; 1931 } 1932 1933 /** 1934 * ice_sched_cfg_vsi - configure the new/existing VSI 1935 * @pi: port information structure 1936 * @vsi_handle: software VSI handle 1937 * @tc: TC number 1938 * @maxqs: max number of queues 1939 * @owner: LAN or RDMA 1940 * @enable: TC enabled or disabled 1941 * 1942 * This function adds/updates VSI nodes based on the number of queues. If TC is 1943 * enabled and VSI is in suspended state then resume the VSI back. If TC is 1944 * disabled then suspend the VSI if it is not already. 1945 */ 1946 enum ice_status 1947 ice_sched_cfg_vsi(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 maxqs, 1948 u8 owner, bool enable) 1949 { 1950 struct ice_sched_node *vsi_node, *tc_node; 1951 struct ice_vsi_ctx *vsi_ctx; 1952 enum ice_status status = ICE_SUCCESS; 1953 struct ice_hw *hw = pi->hw; 1954 1955 ice_debug(pi->hw, ICE_DBG_SCHED, "add/config VSI %d\n", vsi_handle); 1956 tc_node = ice_sched_get_tc_node(pi, tc); 1957 if (!tc_node) 1958 return ICE_ERR_PARAM; 1959 vsi_ctx = ice_get_vsi_ctx(hw, vsi_handle); 1960 if (!vsi_ctx) 1961 return ICE_ERR_PARAM; 1962 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 1963 1964 /* suspend the VSI if TC is not enabled */ 1965 if (!enable) { 1966 if (vsi_node && vsi_node->in_use) { 1967 u32 teid = LE32_TO_CPU(vsi_node->info.node_teid); 1968 1969 status = ice_sched_suspend_resume_elems(hw, 1, &teid, 1970 true); 1971 if (!status) 1972 vsi_node->in_use = false; 1973 } 1974 return status; 1975 } 1976 1977 /* TC is enabled, if it is a new VSI then add it to the tree */ 1978 if (!vsi_node) { 1979 status = ice_sched_add_vsi_to_topo(pi, vsi_handle, tc); 1980 if (status) 1981 return status; 1982 1983 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 1984 if (!vsi_node) 1985 return ICE_ERR_CFG; 1986 1987 vsi_ctx->sched.vsi_node[tc] = vsi_node; 1988 vsi_node->in_use = true; 1989 /* invalidate the max queues whenever VSI gets added first time 1990 * into the scheduler tree (boot or after reset). We need to 1991 * recreate the child nodes all the time in these cases. 1992 */ 1993 vsi_ctx->sched.max_lanq[tc] = 0; 1994 } 1995 1996 /* update the VSI child nodes */ 1997 status = ice_sched_update_vsi_child_nodes(pi, vsi_handle, tc, maxqs, 1998 owner); 1999 if (status) 2000 return status; 2001 2002 /* TC is enabled, resume the VSI if it is in the suspend state */ 2003 if (!vsi_node->in_use) { 2004 u32 teid = LE32_TO_CPU(vsi_node->info.node_teid); 2005 2006 status = ice_sched_suspend_resume_elems(hw, 1, &teid, false); 2007 if (!status) 2008 vsi_node->in_use = true; 2009 } 2010 2011 return status; 2012 } 2013 2014 /** 2015 * ice_sched_rm_agg_vsi_info - remove aggregator related VSI info entry 2016 * @pi: port information structure 2017 * @vsi_handle: software VSI handle 2018 * 2019 * This function removes single aggregator VSI info entry from 2020 * aggregator list. 2021 */ 2022 static void ice_sched_rm_agg_vsi_info(struct ice_port_info *pi, u16 vsi_handle) 2023 { 2024 struct ice_sched_agg_info *agg_info; 2025 struct ice_sched_agg_info *atmp; 2026 2027 LIST_FOR_EACH_ENTRY_SAFE(agg_info, atmp, &pi->hw->agg_list, 2028 ice_sched_agg_info, 2029 list_entry) { 2030 struct ice_sched_agg_vsi_info *agg_vsi_info; 2031 struct ice_sched_agg_vsi_info *vtmp; 2032 2033 LIST_FOR_EACH_ENTRY_SAFE(agg_vsi_info, vtmp, 2034 &agg_info->agg_vsi_list, 2035 ice_sched_agg_vsi_info, list_entry) 2036 if (agg_vsi_info->vsi_handle == vsi_handle) { 2037 LIST_DEL(&agg_vsi_info->list_entry); 2038 ice_free(pi->hw, agg_vsi_info); 2039 return; 2040 } 2041 } 2042 } 2043 2044 /** 2045 * ice_sched_is_leaf_node_present - check for a leaf node in the sub-tree 2046 * @node: pointer to the sub-tree node 2047 * 2048 * This function checks for a leaf node presence in a given sub-tree node. 2049 */ 2050 static bool ice_sched_is_leaf_node_present(struct ice_sched_node *node) 2051 { 2052 u8 i; 2053 2054 for (i = 0; i < node->num_children; i++) 2055 if (ice_sched_is_leaf_node_present(node->children[i])) 2056 return true; 2057 /* check for a leaf node */ 2058 return (node->info.data.elem_type == ICE_AQC_ELEM_TYPE_LEAF); 2059 } 2060 2061 /** 2062 * ice_sched_rm_vsi_cfg - remove the VSI and its children nodes 2063 * @pi: port information structure 2064 * @vsi_handle: software VSI handle 2065 * @owner: LAN or RDMA 2066 * 2067 * This function removes the VSI and its LAN or RDMA children nodes from the 2068 * scheduler tree. 2069 */ 2070 static enum ice_status 2071 ice_sched_rm_vsi_cfg(struct ice_port_info *pi, u16 vsi_handle, u8 owner) 2072 { 2073 enum ice_status status = ICE_ERR_PARAM; 2074 struct ice_vsi_ctx *vsi_ctx; 2075 u8 i; 2076 2077 ice_debug(pi->hw, ICE_DBG_SCHED, "removing VSI %d\n", vsi_handle); 2078 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 2079 return status; 2080 ice_acquire_lock(&pi->sched_lock); 2081 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 2082 if (!vsi_ctx) 2083 goto exit_sched_rm_vsi_cfg; 2084 2085 ice_for_each_traffic_class(i) { 2086 struct ice_sched_node *vsi_node, *tc_node; 2087 u8 j = 0; 2088 2089 tc_node = ice_sched_get_tc_node(pi, i); 2090 if (!tc_node) 2091 continue; 2092 2093 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 2094 if (!vsi_node) 2095 continue; 2096 2097 if (ice_sched_is_leaf_node_present(vsi_node)) { 2098 ice_debug(pi->hw, ICE_DBG_SCHED, "VSI has leaf nodes in TC %d\n", i); 2099 status = ICE_ERR_IN_USE; 2100 goto exit_sched_rm_vsi_cfg; 2101 } 2102 while (j < vsi_node->num_children) { 2103 if (vsi_node->children[j]->owner == owner) { 2104 ice_free_sched_node(pi, vsi_node->children[j]); 2105 2106 /* reset the counter again since the num 2107 * children will be updated after node removal 2108 */ 2109 j = 0; 2110 } else { 2111 j++; 2112 } 2113 } 2114 /* remove the VSI if it has no children */ 2115 if (!vsi_node->num_children) { 2116 ice_free_sched_node(pi, vsi_node); 2117 vsi_ctx->sched.vsi_node[i] = NULL; 2118 2119 /* clean up aggregator related VSI info if any */ 2120 ice_sched_rm_agg_vsi_info(pi, vsi_handle); 2121 } 2122 if (owner == ICE_SCHED_NODE_OWNER_LAN) 2123 vsi_ctx->sched.max_lanq[i] = 0; 2124 } 2125 status = ICE_SUCCESS; 2126 2127 exit_sched_rm_vsi_cfg: 2128 ice_release_lock(&pi->sched_lock); 2129 return status; 2130 } 2131 2132 /** 2133 * ice_rm_vsi_lan_cfg - remove VSI and its LAN children nodes 2134 * @pi: port information structure 2135 * @vsi_handle: software VSI handle 2136 * 2137 * This function clears the VSI and its LAN children nodes from scheduler tree 2138 * for all TCs. 2139 */ 2140 enum ice_status ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle) 2141 { 2142 return ice_sched_rm_vsi_cfg(pi, vsi_handle, ICE_SCHED_NODE_OWNER_LAN); 2143 } 2144 2145 /** 2146 * ice_sched_is_tree_balanced - Check tree nodes are identical or not 2147 * @hw: pointer to the HW struct 2148 * @node: pointer to the ice_sched_node struct 2149 * 2150 * This function compares all the nodes for a given tree against HW DB nodes 2151 * This function needs to be called with the port_info->sched_lock held 2152 */ 2153 bool ice_sched_is_tree_balanced(struct ice_hw *hw, struct ice_sched_node *node) 2154 { 2155 u8 i; 2156 2157 /* start from the leaf node */ 2158 for (i = 0; i < node->num_children; i++) 2159 /* Fail if node doesn't match with the SW DB 2160 * this recursion is intentional, and wouldn't 2161 * go more than 9 calls 2162 */ 2163 if (!ice_sched_is_tree_balanced(hw, node->children[i])) 2164 return false; 2165 2166 return ice_sched_check_node(hw, node); 2167 } 2168 2169 /** 2170 * ice_aq_query_node_to_root - retrieve the tree topology for a given node TEID 2171 * @hw: pointer to the HW struct 2172 * @node_teid: node TEID 2173 * @buf: pointer to buffer 2174 * @buf_size: buffer size in bytes 2175 * @cd: pointer to command details structure or NULL 2176 * 2177 * This function retrieves the tree topology from the firmware for a given 2178 * node TEID to the root node. 2179 */ 2180 enum ice_status 2181 ice_aq_query_node_to_root(struct ice_hw *hw, u32 node_teid, 2182 struct ice_aqc_txsched_elem_data *buf, u16 buf_size, 2183 struct ice_sq_cd *cd) 2184 { 2185 struct ice_aqc_query_node_to_root *cmd; 2186 struct ice_aq_desc desc; 2187 2188 cmd = &desc.params.query_node_to_root; 2189 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_query_node_to_root); 2190 cmd->teid = CPU_TO_LE32(node_teid); 2191 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2192 } 2193 2194 /** 2195 * ice_get_agg_info - get the aggregator ID 2196 * @hw: pointer to the hardware structure 2197 * @agg_id: aggregator ID 2198 * 2199 * This function validates aggregator ID. The function returns info if 2200 * aggregator ID is present in list otherwise it returns null. 2201 */ 2202 static struct ice_sched_agg_info * 2203 ice_get_agg_info(struct ice_hw *hw, u32 agg_id) 2204 { 2205 struct ice_sched_agg_info *agg_info; 2206 2207 LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info, 2208 list_entry) 2209 if (agg_info->agg_id == agg_id) 2210 return agg_info; 2211 2212 return NULL; 2213 } 2214 2215 /** 2216 * ice_sched_get_free_vsi_parent - Find a free parent node in aggregator subtree 2217 * @hw: pointer to the HW struct 2218 * @node: pointer to a child node 2219 * @num_nodes: num nodes count array 2220 * 2221 * This function walks through the aggregator subtree to find a free parent 2222 * node 2223 */ 2224 static struct ice_sched_node * 2225 ice_sched_get_free_vsi_parent(struct ice_hw *hw, struct ice_sched_node *node, 2226 u16 *num_nodes) 2227 { 2228 u8 l = node->tx_sched_layer; 2229 u8 vsil, i; 2230 2231 vsil = ice_sched_get_vsi_layer(hw); 2232 2233 /* Is it VSI parent layer ? */ 2234 if (l == vsil - 1) 2235 return (node->num_children < hw->max_children[l]) ? node : NULL; 2236 2237 /* We have intermediate nodes. Let's walk through the subtree. If the 2238 * intermediate node has space to add a new node then clear the count 2239 */ 2240 if (node->num_children < hw->max_children[l]) 2241 num_nodes[l] = 0; 2242 /* The below recursive call is intentional and wouldn't go more than 2243 * 2 or 3 iterations. 2244 */ 2245 2246 for (i = 0; i < node->num_children; i++) { 2247 struct ice_sched_node *parent; 2248 2249 parent = ice_sched_get_free_vsi_parent(hw, node->children[i], 2250 num_nodes); 2251 if (parent) 2252 return parent; 2253 } 2254 2255 return NULL; 2256 } 2257 2258 /** 2259 * ice_sched_update_parent - update the new parent in SW DB 2260 * @new_parent: pointer to a new parent node 2261 * @node: pointer to a child node 2262 * 2263 * This function removes the child from the old parent and adds it to a new 2264 * parent 2265 */ 2266 static void 2267 ice_sched_update_parent(struct ice_sched_node *new_parent, 2268 struct ice_sched_node *node) 2269 { 2270 struct ice_sched_node *old_parent; 2271 u8 i, j; 2272 2273 old_parent = node->parent; 2274 2275 /* update the old parent children */ 2276 for (i = 0; i < old_parent->num_children; i++) 2277 if (old_parent->children[i] == node) { 2278 for (j = i + 1; j < old_parent->num_children; j++) 2279 old_parent->children[j - 1] = 2280 old_parent->children[j]; 2281 old_parent->num_children--; 2282 break; 2283 } 2284 2285 /* now move the node to a new parent */ 2286 new_parent->children[new_parent->num_children++] = node; 2287 node->parent = new_parent; 2288 node->info.parent_teid = new_parent->info.node_teid; 2289 } 2290 2291 /** 2292 * ice_sched_move_nodes - move child nodes to a given parent 2293 * @pi: port information structure 2294 * @parent: pointer to parent node 2295 * @num_items: number of child nodes to be moved 2296 * @list: pointer to child node teids 2297 * 2298 * This function move the child nodes to a given parent. 2299 */ 2300 static enum ice_status 2301 ice_sched_move_nodes(struct ice_port_info *pi, struct ice_sched_node *parent, 2302 u16 num_items, u32 *list) 2303 { 2304 struct ice_aqc_move_elem *buf; 2305 struct ice_sched_node *node; 2306 enum ice_status status = ICE_SUCCESS; 2307 u16 i, grps_movd = 0; 2308 struct ice_hw *hw; 2309 u16 buf_len; 2310 2311 hw = pi->hw; 2312 2313 if (!parent || !num_items) 2314 return ICE_ERR_PARAM; 2315 2316 /* Does parent have enough space */ 2317 if (parent->num_children + num_items > 2318 hw->max_children[parent->tx_sched_layer]) 2319 return ICE_ERR_AQ_FULL; 2320 2321 buf_len = ice_struct_size(buf, teid, 1); 2322 buf = (struct ice_aqc_move_elem *)ice_malloc(hw, buf_len); 2323 if (!buf) 2324 return ICE_ERR_NO_MEMORY; 2325 2326 for (i = 0; i < num_items; i++) { 2327 node = ice_sched_find_node_by_teid(pi->root, list[i]); 2328 if (!node) { 2329 status = ICE_ERR_PARAM; 2330 goto move_err_exit; 2331 } 2332 2333 buf->hdr.src_parent_teid = node->info.parent_teid; 2334 buf->hdr.dest_parent_teid = parent->info.node_teid; 2335 buf->teid[0] = node->info.node_teid; 2336 buf->hdr.num_elems = CPU_TO_LE16(1); 2337 status = ice_aq_move_sched_elems(hw, 1, buf, buf_len, 2338 &grps_movd, NULL); 2339 if (status && grps_movd != 1) { 2340 status = ICE_ERR_CFG; 2341 goto move_err_exit; 2342 } 2343 2344 /* update the SW DB */ 2345 ice_sched_update_parent(parent, node); 2346 } 2347 2348 move_err_exit: 2349 ice_free(hw, buf); 2350 return status; 2351 } 2352 2353 /** 2354 * ice_sched_move_vsi_to_agg - move VSI to aggregator node 2355 * @pi: port information structure 2356 * @vsi_handle: software VSI handle 2357 * @agg_id: aggregator ID 2358 * @tc: TC number 2359 * 2360 * This function moves a VSI to an aggregator node or its subtree. 2361 * Intermediate nodes may be created if required. 2362 */ 2363 static enum ice_status 2364 ice_sched_move_vsi_to_agg(struct ice_port_info *pi, u16 vsi_handle, u32 agg_id, 2365 u8 tc) 2366 { 2367 struct ice_sched_node *vsi_node, *agg_node, *tc_node, *parent; 2368 u16 num_nodes[ICE_AQC_TOPO_MAX_LEVEL_NUM] = { 0 }; 2369 u32 first_node_teid, vsi_teid; 2370 enum ice_status status; 2371 u16 num_nodes_added; 2372 u8 aggl, vsil, i; 2373 2374 tc_node = ice_sched_get_tc_node(pi, tc); 2375 if (!tc_node) 2376 return ICE_ERR_CFG; 2377 2378 agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); 2379 if (!agg_node) 2380 return ICE_ERR_DOES_NOT_EXIST; 2381 2382 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 2383 if (!vsi_node) 2384 return ICE_ERR_DOES_NOT_EXIST; 2385 2386 /* Is this VSI already part of given aggregator? */ 2387 if (ice_sched_find_node_in_subtree(pi->hw, agg_node, vsi_node)) 2388 return ICE_SUCCESS; 2389 2390 aggl = ice_sched_get_agg_layer(pi->hw); 2391 vsil = ice_sched_get_vsi_layer(pi->hw); 2392 2393 /* set intermediate node count to 1 between aggregator and VSI layers */ 2394 for (i = aggl + 1; i < vsil; i++) 2395 num_nodes[i] = 1; 2396 2397 /* Check if the aggregator subtree has any free node to add the VSI */ 2398 for (i = 0; i < agg_node->num_children; i++) { 2399 parent = ice_sched_get_free_vsi_parent(pi->hw, 2400 agg_node->children[i], 2401 num_nodes); 2402 if (parent) 2403 goto move_nodes; 2404 } 2405 2406 /* add new nodes */ 2407 parent = agg_node; 2408 for (i = aggl + 1; i < vsil; i++) { 2409 status = ice_sched_add_nodes_to_layer(pi, tc_node, parent, i, 2410 num_nodes[i], 2411 &first_node_teid, 2412 &num_nodes_added); 2413 if (status != ICE_SUCCESS || num_nodes[i] != num_nodes_added) 2414 return ICE_ERR_CFG; 2415 2416 /* The newly added node can be a new parent for the next 2417 * layer nodes 2418 */ 2419 if (num_nodes_added) 2420 parent = ice_sched_find_node_by_teid(tc_node, 2421 first_node_teid); 2422 else 2423 parent = parent->children[0]; 2424 2425 if (!parent) 2426 return ICE_ERR_CFG; 2427 } 2428 2429 move_nodes: 2430 vsi_teid = LE32_TO_CPU(vsi_node->info.node_teid); 2431 return ice_sched_move_nodes(pi, parent, 1, &vsi_teid); 2432 } 2433 2434 /** 2435 * ice_move_all_vsi_to_dflt_agg - move all VSI(s) to default aggregator 2436 * @pi: port information structure 2437 * @agg_info: aggregator info 2438 * @tc: traffic class number 2439 * @rm_vsi_info: true or false 2440 * 2441 * This function move all the VSI(s) to the default aggregator and delete 2442 * aggregator VSI info based on passed in boolean parameter rm_vsi_info. The 2443 * caller holds the scheduler lock. 2444 */ 2445 static enum ice_status 2446 ice_move_all_vsi_to_dflt_agg(struct ice_port_info *pi, 2447 struct ice_sched_agg_info *agg_info, u8 tc, 2448 bool rm_vsi_info) 2449 { 2450 struct ice_sched_agg_vsi_info *agg_vsi_info; 2451 struct ice_sched_agg_vsi_info *tmp; 2452 enum ice_status status = ICE_SUCCESS; 2453 2454 LIST_FOR_EACH_ENTRY_SAFE(agg_vsi_info, tmp, &agg_info->agg_vsi_list, 2455 ice_sched_agg_vsi_info, list_entry) { 2456 u16 vsi_handle = agg_vsi_info->vsi_handle; 2457 2458 /* Move VSI to default aggregator */ 2459 if (!ice_is_tc_ena(agg_vsi_info->tc_bitmap[0], tc)) 2460 continue; 2461 2462 status = ice_sched_move_vsi_to_agg(pi, vsi_handle, 2463 ICE_DFLT_AGG_ID, tc); 2464 if (status) 2465 break; 2466 2467 ice_clear_bit(tc, agg_vsi_info->tc_bitmap); 2468 if (rm_vsi_info && !agg_vsi_info->tc_bitmap[0]) { 2469 LIST_DEL(&agg_vsi_info->list_entry); 2470 ice_free(pi->hw, agg_vsi_info); 2471 } 2472 } 2473 2474 return status; 2475 } 2476 2477 /** 2478 * ice_sched_is_agg_inuse - check whether the aggregator is in use or not 2479 * @pi: port information structure 2480 * @node: node pointer 2481 * 2482 * This function checks whether the aggregator is attached with any VSI or not. 2483 */ 2484 static bool 2485 ice_sched_is_agg_inuse(struct ice_port_info *pi, struct ice_sched_node *node) 2486 { 2487 u8 vsil, i; 2488 2489 vsil = ice_sched_get_vsi_layer(pi->hw); 2490 if (node->tx_sched_layer < vsil - 1) { 2491 for (i = 0; i < node->num_children; i++) 2492 if (ice_sched_is_agg_inuse(pi, node->children[i])) 2493 return true; 2494 return false; 2495 } else { 2496 return node->num_children ? true : false; 2497 } 2498 } 2499 2500 /** 2501 * ice_sched_rm_agg_cfg - remove the aggregator node 2502 * @pi: port information structure 2503 * @agg_id: aggregator ID 2504 * @tc: TC number 2505 * 2506 * This function removes the aggregator node and intermediate nodes if any 2507 * from the given TC 2508 */ 2509 static enum ice_status 2510 ice_sched_rm_agg_cfg(struct ice_port_info *pi, u32 agg_id, u8 tc) 2511 { 2512 struct ice_sched_node *tc_node, *agg_node; 2513 struct ice_hw *hw = pi->hw; 2514 2515 tc_node = ice_sched_get_tc_node(pi, tc); 2516 if (!tc_node) 2517 return ICE_ERR_CFG; 2518 2519 agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); 2520 if (!agg_node) 2521 return ICE_ERR_DOES_NOT_EXIST; 2522 2523 /* Can't remove the aggregator node if it has children */ 2524 if (ice_sched_is_agg_inuse(pi, agg_node)) 2525 return ICE_ERR_IN_USE; 2526 2527 /* need to remove the whole subtree if aggregator node is the 2528 * only child. 2529 */ 2530 while (agg_node->tx_sched_layer > hw->sw_entry_point_layer) { 2531 struct ice_sched_node *parent = agg_node->parent; 2532 2533 if (!parent) 2534 return ICE_ERR_CFG; 2535 2536 if (parent->num_children > 1) 2537 break; 2538 2539 agg_node = parent; 2540 } 2541 2542 ice_free_sched_node(pi, agg_node); 2543 return ICE_SUCCESS; 2544 } 2545 2546 /** 2547 * ice_rm_agg_cfg_tc - remove aggregator configuration for TC 2548 * @pi: port information structure 2549 * @agg_info: aggregator ID 2550 * @tc: TC number 2551 * @rm_vsi_info: bool value true or false 2552 * 2553 * This function removes aggregator reference to VSI of given TC. It removes 2554 * the aggregator configuration completely for requested TC. The caller needs 2555 * to hold the scheduler lock. 2556 */ 2557 static enum ice_status 2558 ice_rm_agg_cfg_tc(struct ice_port_info *pi, struct ice_sched_agg_info *agg_info, 2559 u8 tc, bool rm_vsi_info) 2560 { 2561 enum ice_status status = ICE_SUCCESS; 2562 2563 /* If nothing to remove - return success */ 2564 if (!ice_is_tc_ena(agg_info->tc_bitmap[0], tc)) 2565 goto exit_rm_agg_cfg_tc; 2566 2567 status = ice_move_all_vsi_to_dflt_agg(pi, agg_info, tc, rm_vsi_info); 2568 if (status) 2569 goto exit_rm_agg_cfg_tc; 2570 2571 /* Delete aggregator node(s) */ 2572 status = ice_sched_rm_agg_cfg(pi, agg_info->agg_id, tc); 2573 if (status) 2574 goto exit_rm_agg_cfg_tc; 2575 2576 ice_clear_bit(tc, agg_info->tc_bitmap); 2577 exit_rm_agg_cfg_tc: 2578 return status; 2579 } 2580 2581 /** 2582 * ice_save_agg_tc_bitmap - save aggregator TC bitmap 2583 * @pi: port information structure 2584 * @agg_id: aggregator ID 2585 * @tc_bitmap: 8 bits TC bitmap 2586 * 2587 * Save aggregator TC bitmap. This function needs to be called with scheduler 2588 * lock held. 2589 */ 2590 static enum ice_status 2591 ice_save_agg_tc_bitmap(struct ice_port_info *pi, u32 agg_id, 2592 ice_bitmap_t *tc_bitmap) 2593 { 2594 struct ice_sched_agg_info *agg_info; 2595 2596 agg_info = ice_get_agg_info(pi->hw, agg_id); 2597 if (!agg_info) 2598 return ICE_ERR_PARAM; 2599 ice_cp_bitmap(agg_info->replay_tc_bitmap, tc_bitmap, 2600 ICE_MAX_TRAFFIC_CLASS); 2601 return ICE_SUCCESS; 2602 } 2603 2604 /** 2605 * ice_sched_add_agg_cfg - create an aggregator node 2606 * @pi: port information structure 2607 * @agg_id: aggregator ID 2608 * @tc: TC number 2609 * 2610 * This function creates an aggregator node and intermediate nodes if required 2611 * for the given TC 2612 */ 2613 static enum ice_status 2614 ice_sched_add_agg_cfg(struct ice_port_info *pi, u32 agg_id, u8 tc) 2615 { 2616 struct ice_sched_node *parent, *agg_node, *tc_node; 2617 u16 num_nodes[ICE_AQC_TOPO_MAX_LEVEL_NUM] = { 0 }; 2618 enum ice_status status = ICE_SUCCESS; 2619 struct ice_hw *hw = pi->hw; 2620 u32 first_node_teid; 2621 u16 num_nodes_added; 2622 u8 i, aggl; 2623 2624 tc_node = ice_sched_get_tc_node(pi, tc); 2625 if (!tc_node) 2626 return ICE_ERR_CFG; 2627 2628 agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); 2629 /* Does Agg node already exist ? */ 2630 if (agg_node) 2631 return status; 2632 2633 aggl = ice_sched_get_agg_layer(hw); 2634 2635 /* need one node in Agg layer */ 2636 num_nodes[aggl] = 1; 2637 2638 /* Check whether the intermediate nodes have space to add the 2639 * new aggregator. If they are full, then SW needs to allocate a new 2640 * intermediate node on those layers 2641 */ 2642 for (i = hw->sw_entry_point_layer; i < aggl; i++) { 2643 parent = ice_sched_get_first_node(pi, tc_node, i); 2644 2645 /* scan all the siblings */ 2646 while (parent) { 2647 if (parent->num_children < hw->max_children[i]) 2648 break; 2649 parent = parent->sibling; 2650 } 2651 2652 /* all the nodes are full, reserve one for this layer */ 2653 if (!parent) 2654 num_nodes[i]++; 2655 } 2656 2657 /* add the aggregator node */ 2658 parent = tc_node; 2659 for (i = hw->sw_entry_point_layer; i <= aggl; i++) { 2660 if (!parent) 2661 return ICE_ERR_CFG; 2662 2663 status = ice_sched_add_nodes_to_layer(pi, tc_node, parent, i, 2664 num_nodes[i], 2665 &first_node_teid, 2666 &num_nodes_added); 2667 if (status != ICE_SUCCESS || num_nodes[i] != num_nodes_added) 2668 return ICE_ERR_CFG; 2669 2670 /* The newly added node can be a new parent for the next 2671 * layer nodes 2672 */ 2673 if (num_nodes_added) { 2674 parent = ice_sched_find_node_by_teid(tc_node, 2675 first_node_teid); 2676 /* register aggregator ID with the aggregator node */ 2677 if (parent && i == aggl) 2678 parent->agg_id = agg_id; 2679 } else { 2680 parent = parent->children[0]; 2681 } 2682 } 2683 2684 return ICE_SUCCESS; 2685 } 2686 2687 /** 2688 * ice_sched_cfg_agg - configure aggregator node 2689 * @pi: port information structure 2690 * @agg_id: aggregator ID 2691 * @agg_type: aggregator type queue, VSI, or aggregator group 2692 * @tc_bitmap: bits TC bitmap 2693 * 2694 * It registers a unique aggregator node into scheduler services. It 2695 * allows a user to register with a unique ID to track it's resources. 2696 * The aggregator type determines if this is a queue group, VSI group 2697 * or aggregator group. It then creates the aggregator node(s) for requested 2698 * TC(s) or removes an existing aggregator node including its configuration 2699 * if indicated via tc_bitmap. Call ice_rm_agg_cfg to release aggregator 2700 * resources and remove aggregator ID. 2701 * This function needs to be called with scheduler lock held. 2702 */ 2703 static enum ice_status 2704 ice_sched_cfg_agg(struct ice_port_info *pi, u32 agg_id, 2705 enum ice_agg_type agg_type, ice_bitmap_t *tc_bitmap) 2706 { 2707 struct ice_sched_agg_info *agg_info; 2708 enum ice_status status = ICE_SUCCESS; 2709 struct ice_hw *hw = pi->hw; 2710 u8 tc; 2711 2712 agg_info = ice_get_agg_info(hw, agg_id); 2713 if (!agg_info) { 2714 /* Create new entry for new aggregator ID */ 2715 agg_info = (struct ice_sched_agg_info *) 2716 ice_malloc(hw, sizeof(*agg_info)); 2717 if (!agg_info) 2718 return ICE_ERR_NO_MEMORY; 2719 2720 agg_info->agg_id = agg_id; 2721 agg_info->agg_type = agg_type; 2722 agg_info->tc_bitmap[0] = 0; 2723 2724 /* Initialize the aggregator VSI list head */ 2725 INIT_LIST_HEAD(&agg_info->agg_vsi_list); 2726 2727 /* Add new entry in aggregator list */ 2728 LIST_ADD(&agg_info->list_entry, &hw->agg_list); 2729 } 2730 /* Create aggregator node(s) for requested TC(s) */ 2731 ice_for_each_traffic_class(tc) { 2732 if (!ice_is_tc_ena(*tc_bitmap, tc)) { 2733 /* Delete aggregator cfg TC if it exists previously */ 2734 status = ice_rm_agg_cfg_tc(pi, agg_info, tc, false); 2735 if (status) 2736 break; 2737 continue; 2738 } 2739 2740 /* Check if aggregator node for TC already exists */ 2741 if (ice_is_tc_ena(agg_info->tc_bitmap[0], tc)) 2742 continue; 2743 2744 /* Create new aggregator node for TC */ 2745 status = ice_sched_add_agg_cfg(pi, agg_id, tc); 2746 if (status) 2747 break; 2748 2749 /* Save aggregator node's TC information */ 2750 ice_set_bit(tc, agg_info->tc_bitmap); 2751 } 2752 2753 return status; 2754 } 2755 2756 /** 2757 * ice_cfg_agg - config aggregator node 2758 * @pi: port information structure 2759 * @agg_id: aggregator ID 2760 * @agg_type: aggregator type queue, VSI, or aggregator group 2761 * @tc_bitmap: bits TC bitmap 2762 * 2763 * This function configures aggregator node(s). 2764 */ 2765 enum ice_status 2766 ice_cfg_agg(struct ice_port_info *pi, u32 agg_id, enum ice_agg_type agg_type, 2767 u8 tc_bitmap) 2768 { 2769 ice_bitmap_t bitmap = tc_bitmap; 2770 enum ice_status status; 2771 2772 ice_acquire_lock(&pi->sched_lock); 2773 status = ice_sched_cfg_agg(pi, agg_id, agg_type, 2774 (ice_bitmap_t *)&bitmap); 2775 if (!status) 2776 status = ice_save_agg_tc_bitmap(pi, agg_id, 2777 (ice_bitmap_t *)&bitmap); 2778 ice_release_lock(&pi->sched_lock); 2779 return status; 2780 } 2781 2782 /** 2783 * ice_get_agg_vsi_info - get the aggregator ID 2784 * @agg_info: aggregator info 2785 * @vsi_handle: software VSI handle 2786 * 2787 * The function returns aggregator VSI info based on VSI handle. This function 2788 * needs to be called with scheduler lock held. 2789 */ 2790 static struct ice_sched_agg_vsi_info * 2791 ice_get_agg_vsi_info(struct ice_sched_agg_info *agg_info, u16 vsi_handle) 2792 { 2793 struct ice_sched_agg_vsi_info *agg_vsi_info; 2794 2795 LIST_FOR_EACH_ENTRY(agg_vsi_info, &agg_info->agg_vsi_list, 2796 ice_sched_agg_vsi_info, list_entry) 2797 if (agg_vsi_info->vsi_handle == vsi_handle) 2798 return agg_vsi_info; 2799 2800 return NULL; 2801 } 2802 2803 /** 2804 * ice_get_vsi_agg_info - get the aggregator info of VSI 2805 * @hw: pointer to the hardware structure 2806 * @vsi_handle: Sw VSI handle 2807 * 2808 * The function returns aggregator info of VSI represented via vsi_handle. The 2809 * VSI has in this case a different aggregator than the default one. This 2810 * function needs to be called with scheduler lock held. 2811 */ 2812 static struct ice_sched_agg_info * 2813 ice_get_vsi_agg_info(struct ice_hw *hw, u16 vsi_handle) 2814 { 2815 struct ice_sched_agg_info *agg_info; 2816 2817 LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info, 2818 list_entry) { 2819 struct ice_sched_agg_vsi_info *agg_vsi_info; 2820 2821 agg_vsi_info = ice_get_agg_vsi_info(agg_info, vsi_handle); 2822 if (agg_vsi_info) 2823 return agg_info; 2824 } 2825 return NULL; 2826 } 2827 2828 /** 2829 * ice_save_agg_vsi_tc_bitmap - save aggregator VSI TC bitmap 2830 * @pi: port information structure 2831 * @agg_id: aggregator ID 2832 * @vsi_handle: software VSI handle 2833 * @tc_bitmap: TC bitmap of enabled TC(s) 2834 * 2835 * Save VSI to aggregator TC bitmap. This function needs to call with scheduler 2836 * lock held. 2837 */ 2838 static enum ice_status 2839 ice_save_agg_vsi_tc_bitmap(struct ice_port_info *pi, u32 agg_id, u16 vsi_handle, 2840 ice_bitmap_t *tc_bitmap) 2841 { 2842 struct ice_sched_agg_vsi_info *agg_vsi_info; 2843 struct ice_sched_agg_info *agg_info; 2844 2845 agg_info = ice_get_agg_info(pi->hw, agg_id); 2846 if (!agg_info) 2847 return ICE_ERR_PARAM; 2848 /* check if entry already exist */ 2849 agg_vsi_info = ice_get_agg_vsi_info(agg_info, vsi_handle); 2850 if (!agg_vsi_info) 2851 return ICE_ERR_PARAM; 2852 ice_cp_bitmap(agg_vsi_info->replay_tc_bitmap, tc_bitmap, 2853 ICE_MAX_TRAFFIC_CLASS); 2854 return ICE_SUCCESS; 2855 } 2856 2857 /** 2858 * ice_sched_assoc_vsi_to_agg - associate/move VSI to new/default aggregator 2859 * @pi: port information structure 2860 * @agg_id: aggregator ID 2861 * @vsi_handle: software VSI handle 2862 * @tc_bitmap: TC bitmap of enabled TC(s) 2863 * 2864 * This function moves VSI to a new or default aggregator node. If VSI is 2865 * already associated to the aggregator node then no operation is performed on 2866 * the tree. This function needs to be called with scheduler lock held. 2867 */ 2868 static enum ice_status 2869 ice_sched_assoc_vsi_to_agg(struct ice_port_info *pi, u32 agg_id, 2870 u16 vsi_handle, ice_bitmap_t *tc_bitmap) 2871 { 2872 struct ice_sched_agg_vsi_info *agg_vsi_info, *old_agg_vsi_info = NULL; 2873 struct ice_sched_agg_info *agg_info, *old_agg_info; 2874 enum ice_status status = ICE_SUCCESS; 2875 struct ice_hw *hw = pi->hw; 2876 u8 tc; 2877 2878 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 2879 return ICE_ERR_PARAM; 2880 agg_info = ice_get_agg_info(hw, agg_id); 2881 if (!agg_info) 2882 return ICE_ERR_PARAM; 2883 /* If the vsi is already part of another aggregator then update 2884 * its vsi info list 2885 */ 2886 old_agg_info = ice_get_vsi_agg_info(hw, vsi_handle); 2887 if (old_agg_info && old_agg_info != agg_info) { 2888 struct ice_sched_agg_vsi_info *vtmp; 2889 2890 LIST_FOR_EACH_ENTRY_SAFE(old_agg_vsi_info, vtmp, 2891 &old_agg_info->agg_vsi_list, 2892 ice_sched_agg_vsi_info, list_entry) 2893 if (old_agg_vsi_info->vsi_handle == vsi_handle) 2894 break; 2895 } 2896 2897 /* check if entry already exist */ 2898 agg_vsi_info = ice_get_agg_vsi_info(agg_info, vsi_handle); 2899 if (!agg_vsi_info) { 2900 /* Create new entry for VSI under aggregator list */ 2901 agg_vsi_info = (struct ice_sched_agg_vsi_info *) 2902 ice_malloc(hw, sizeof(*agg_vsi_info)); 2903 if (!agg_vsi_info) 2904 return ICE_ERR_PARAM; 2905 2906 /* add VSI ID into the aggregator list */ 2907 agg_vsi_info->vsi_handle = vsi_handle; 2908 LIST_ADD(&agg_vsi_info->list_entry, &agg_info->agg_vsi_list); 2909 } 2910 /* Move VSI node to new aggregator node for requested TC(s) */ 2911 ice_for_each_traffic_class(tc) { 2912 if (!ice_is_tc_ena(*tc_bitmap, tc)) 2913 continue; 2914 2915 /* Move VSI to new aggregator */ 2916 status = ice_sched_move_vsi_to_agg(pi, vsi_handle, agg_id, tc); 2917 if (status) 2918 break; 2919 2920 ice_set_bit(tc, agg_vsi_info->tc_bitmap); 2921 if (old_agg_vsi_info) 2922 ice_clear_bit(tc, old_agg_vsi_info->tc_bitmap); 2923 } 2924 if (old_agg_vsi_info && !old_agg_vsi_info->tc_bitmap[0]) { 2925 LIST_DEL(&old_agg_vsi_info->list_entry); 2926 ice_free(pi->hw, old_agg_vsi_info); 2927 } 2928 return status; 2929 } 2930 2931 /** 2932 * ice_sched_rm_unused_rl_prof - remove unused RL profile 2933 * @hw: pointer to the hardware structure 2934 * 2935 * This function removes unused rate limit profiles from the HW and 2936 * SW DB. The caller needs to hold scheduler lock. 2937 */ 2938 static void ice_sched_rm_unused_rl_prof(struct ice_hw *hw) 2939 { 2940 u16 ln; 2941 2942 for (ln = 0; ln < hw->num_tx_sched_layers; ln++) { 2943 struct ice_aqc_rl_profile_info *rl_prof_elem; 2944 struct ice_aqc_rl_profile_info *rl_prof_tmp; 2945 2946 LIST_FOR_EACH_ENTRY_SAFE(rl_prof_elem, rl_prof_tmp, 2947 &hw->rl_prof_list[ln], 2948 ice_aqc_rl_profile_info, list_entry) { 2949 if (!ice_sched_del_rl_profile(hw, rl_prof_elem)) 2950 ice_debug(hw, ICE_DBG_SCHED, "Removed rl profile\n"); 2951 } 2952 } 2953 } 2954 2955 /** 2956 * ice_sched_update_elem - update element 2957 * @hw: pointer to the HW struct 2958 * @node: pointer to node 2959 * @info: node info to update 2960 * 2961 * Update the HW DB, and local SW DB of node. Update the scheduling 2962 * parameters of node from argument info data buffer (Info->data buf) and 2963 * returns success or error on config sched element failure. The caller 2964 * needs to hold scheduler lock. 2965 */ 2966 static enum ice_status 2967 ice_sched_update_elem(struct ice_hw *hw, struct ice_sched_node *node, 2968 struct ice_aqc_txsched_elem_data *info) 2969 { 2970 struct ice_aqc_txsched_elem_data buf; 2971 enum ice_status status; 2972 u16 elem_cfgd = 0; 2973 u16 num_elems = 1; 2974 2975 buf = *info; 2976 /* For TC nodes, CIR config is not supported */ 2977 if (node->info.data.elem_type == ICE_AQC_ELEM_TYPE_TC) 2978 buf.data.valid_sections &= ~ICE_AQC_ELEM_VALID_CIR; 2979 /* Parent TEID is reserved field in this aq call */ 2980 buf.parent_teid = 0; 2981 /* Element type is reserved field in this aq call */ 2982 buf.data.elem_type = 0; 2983 /* Flags is reserved field in this aq call */ 2984 buf.data.flags = 0; 2985 2986 /* Update HW DB */ 2987 /* Configure element node */ 2988 status = ice_aq_cfg_sched_elems(hw, num_elems, &buf, sizeof(buf), 2989 &elem_cfgd, NULL); 2990 if (status || elem_cfgd != num_elems) { 2991 ice_debug(hw, ICE_DBG_SCHED, "Config sched elem error\n"); 2992 return ICE_ERR_CFG; 2993 } 2994 2995 /* Config success case */ 2996 /* Now update local SW DB */ 2997 /* Only copy the data portion of info buffer */ 2998 node->info.data = info->data; 2999 return status; 3000 } 3001 3002 /** 3003 * ice_sched_cfg_node_bw_alloc - configure node BW weight/alloc params 3004 * @hw: pointer to the HW struct 3005 * @node: sched node to configure 3006 * @rl_type: rate limit type CIR, EIR, or shared 3007 * @bw_alloc: BW weight/allocation 3008 * 3009 * This function configures node element's BW allocation. 3010 */ 3011 static enum ice_status 3012 ice_sched_cfg_node_bw_alloc(struct ice_hw *hw, struct ice_sched_node *node, 3013 enum ice_rl_type rl_type, u16 bw_alloc) 3014 { 3015 struct ice_aqc_txsched_elem_data buf; 3016 struct ice_aqc_txsched_elem *data; 3017 enum ice_status status; 3018 3019 buf = node->info; 3020 data = &buf.data; 3021 if (rl_type == ICE_MIN_BW) { 3022 data->valid_sections |= ICE_AQC_ELEM_VALID_CIR; 3023 data->cir_bw.bw_alloc = CPU_TO_LE16(bw_alloc); 3024 } else if (rl_type == ICE_MAX_BW) { 3025 data->valid_sections |= ICE_AQC_ELEM_VALID_EIR; 3026 data->eir_bw.bw_alloc = CPU_TO_LE16(bw_alloc); 3027 } else { 3028 return ICE_ERR_PARAM; 3029 } 3030 3031 /* Configure element */ 3032 status = ice_sched_update_elem(hw, node, &buf); 3033 return status; 3034 } 3035 3036 /** 3037 * ice_move_vsi_to_agg - moves VSI to new or default aggregator 3038 * @pi: port information structure 3039 * @agg_id: aggregator ID 3040 * @vsi_handle: software VSI handle 3041 * @tc_bitmap: TC bitmap of enabled TC(s) 3042 * 3043 * Move or associate VSI to a new or default aggregator node. 3044 */ 3045 enum ice_status 3046 ice_move_vsi_to_agg(struct ice_port_info *pi, u32 agg_id, u16 vsi_handle, 3047 u8 tc_bitmap) 3048 { 3049 ice_bitmap_t bitmap = tc_bitmap; 3050 enum ice_status status; 3051 3052 ice_acquire_lock(&pi->sched_lock); 3053 status = ice_sched_assoc_vsi_to_agg(pi, agg_id, vsi_handle, 3054 (ice_bitmap_t *)&bitmap); 3055 if (!status) 3056 status = ice_save_agg_vsi_tc_bitmap(pi, agg_id, vsi_handle, 3057 (ice_bitmap_t *)&bitmap); 3058 ice_release_lock(&pi->sched_lock); 3059 return status; 3060 } 3061 3062 /** 3063 * ice_rm_agg_cfg - remove aggregator configuration 3064 * @pi: port information structure 3065 * @agg_id: aggregator ID 3066 * 3067 * This function removes aggregator reference to VSI and delete aggregator ID 3068 * info. It removes the aggregator configuration completely. 3069 */ 3070 enum ice_status ice_rm_agg_cfg(struct ice_port_info *pi, u32 agg_id) 3071 { 3072 struct ice_sched_agg_info *agg_info; 3073 enum ice_status status = ICE_SUCCESS; 3074 u8 tc; 3075 3076 ice_acquire_lock(&pi->sched_lock); 3077 agg_info = ice_get_agg_info(pi->hw, agg_id); 3078 if (!agg_info) { 3079 status = ICE_ERR_DOES_NOT_EXIST; 3080 goto exit_ice_rm_agg_cfg; 3081 } 3082 3083 ice_for_each_traffic_class(tc) { 3084 status = ice_rm_agg_cfg_tc(pi, agg_info, tc, true); 3085 if (status) 3086 goto exit_ice_rm_agg_cfg; 3087 } 3088 3089 if (ice_is_any_bit_set(agg_info->tc_bitmap, ICE_MAX_TRAFFIC_CLASS)) { 3090 status = ICE_ERR_IN_USE; 3091 goto exit_ice_rm_agg_cfg; 3092 } 3093 3094 /* Safe to delete entry now */ 3095 LIST_DEL(&agg_info->list_entry); 3096 ice_free(pi->hw, agg_info); 3097 3098 /* Remove unused RL profile IDs from HW and SW DB */ 3099 ice_sched_rm_unused_rl_prof(pi->hw); 3100 3101 exit_ice_rm_agg_cfg: 3102 ice_release_lock(&pi->sched_lock); 3103 return status; 3104 } 3105 3106 /** 3107 * ice_set_clear_cir_bw_alloc - set or clear CIR BW alloc information 3108 * @bw_t_info: bandwidth type information structure 3109 * @bw_alloc: Bandwidth allocation information 3110 * 3111 * Save or clear CIR BW alloc information (bw_alloc) in the passed param 3112 * bw_t_info. 3113 */ 3114 static void 3115 ice_set_clear_cir_bw_alloc(struct ice_bw_type_info *bw_t_info, u16 bw_alloc) 3116 { 3117 bw_t_info->cir_bw.bw_alloc = bw_alloc; 3118 if (bw_t_info->cir_bw.bw_alloc) 3119 ice_set_bit(ICE_BW_TYPE_CIR_WT, bw_t_info->bw_t_bitmap); 3120 else 3121 ice_clear_bit(ICE_BW_TYPE_CIR_WT, bw_t_info->bw_t_bitmap); 3122 } 3123 3124 /** 3125 * ice_set_clear_eir_bw_alloc - set or clear EIR BW alloc information 3126 * @bw_t_info: bandwidth type information structure 3127 * @bw_alloc: Bandwidth allocation information 3128 * 3129 * Save or clear EIR BW alloc information (bw_alloc) in the passed param 3130 * bw_t_info. 3131 */ 3132 static void 3133 ice_set_clear_eir_bw_alloc(struct ice_bw_type_info *bw_t_info, u16 bw_alloc) 3134 { 3135 bw_t_info->eir_bw.bw_alloc = bw_alloc; 3136 if (bw_t_info->eir_bw.bw_alloc) 3137 ice_set_bit(ICE_BW_TYPE_EIR_WT, bw_t_info->bw_t_bitmap); 3138 else 3139 ice_clear_bit(ICE_BW_TYPE_EIR_WT, bw_t_info->bw_t_bitmap); 3140 } 3141 3142 /** 3143 * ice_sched_save_vsi_bw_alloc - save VSI node's BW alloc information 3144 * @pi: port information structure 3145 * @vsi_handle: sw VSI handle 3146 * @tc: traffic class 3147 * @rl_type: rate limit type min or max 3148 * @bw_alloc: Bandwidth allocation information 3149 * 3150 * Save BW alloc information of VSI type node for post replay use. 3151 */ 3152 static enum ice_status 3153 ice_sched_save_vsi_bw_alloc(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 3154 enum ice_rl_type rl_type, u16 bw_alloc) 3155 { 3156 struct ice_vsi_ctx *vsi_ctx; 3157 3158 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 3159 return ICE_ERR_PARAM; 3160 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 3161 if (!vsi_ctx) 3162 return ICE_ERR_PARAM; 3163 switch (rl_type) { 3164 case ICE_MIN_BW: 3165 ice_set_clear_cir_bw_alloc(&vsi_ctx->sched.bw_t_info[tc], 3166 bw_alloc); 3167 break; 3168 case ICE_MAX_BW: 3169 ice_set_clear_eir_bw_alloc(&vsi_ctx->sched.bw_t_info[tc], 3170 bw_alloc); 3171 break; 3172 default: 3173 return ICE_ERR_PARAM; 3174 } 3175 return ICE_SUCCESS; 3176 } 3177 3178 /** 3179 * ice_set_clear_cir_bw - set or clear CIR BW 3180 * @bw_t_info: bandwidth type information structure 3181 * @bw: bandwidth in Kbps - Kilo bits per sec 3182 * 3183 * Save or clear CIR bandwidth (BW) in the passed param bw_t_info. 3184 */ 3185 static void ice_set_clear_cir_bw(struct ice_bw_type_info *bw_t_info, u32 bw) 3186 { 3187 if (bw == ICE_SCHED_DFLT_BW) { 3188 ice_clear_bit(ICE_BW_TYPE_CIR, bw_t_info->bw_t_bitmap); 3189 bw_t_info->cir_bw.bw = 0; 3190 } else { 3191 /* Save type of BW information */ 3192 ice_set_bit(ICE_BW_TYPE_CIR, bw_t_info->bw_t_bitmap); 3193 bw_t_info->cir_bw.bw = bw; 3194 } 3195 } 3196 3197 /** 3198 * ice_set_clear_eir_bw - set or clear EIR BW 3199 * @bw_t_info: bandwidth type information structure 3200 * @bw: bandwidth in Kbps - Kilo bits per sec 3201 * 3202 * Save or clear EIR bandwidth (BW) in the passed param bw_t_info. 3203 */ 3204 static void ice_set_clear_eir_bw(struct ice_bw_type_info *bw_t_info, u32 bw) 3205 { 3206 if (bw == ICE_SCHED_DFLT_BW) { 3207 ice_clear_bit(ICE_BW_TYPE_EIR, bw_t_info->bw_t_bitmap); 3208 bw_t_info->eir_bw.bw = 0; 3209 } else { 3210 /* save EIR BW information */ 3211 ice_set_bit(ICE_BW_TYPE_EIR, bw_t_info->bw_t_bitmap); 3212 bw_t_info->eir_bw.bw = bw; 3213 } 3214 } 3215 3216 /** 3217 * ice_set_clear_shared_bw - set or clear shared BW 3218 * @bw_t_info: bandwidth type information structure 3219 * @bw: bandwidth in Kbps - Kilo bits per sec 3220 * 3221 * Save or clear shared bandwidth (BW) in the passed param bw_t_info. 3222 */ 3223 static void ice_set_clear_shared_bw(struct ice_bw_type_info *bw_t_info, u32 bw) 3224 { 3225 if (bw == ICE_SCHED_DFLT_BW) { 3226 ice_clear_bit(ICE_BW_TYPE_SHARED, bw_t_info->bw_t_bitmap); 3227 bw_t_info->shared_bw = 0; 3228 } else { 3229 /* save shared BW information */ 3230 ice_set_bit(ICE_BW_TYPE_SHARED, bw_t_info->bw_t_bitmap); 3231 bw_t_info->shared_bw = bw; 3232 } 3233 } 3234 3235 /** 3236 * ice_sched_save_vsi_bw - save VSI node's BW information 3237 * @pi: port information structure 3238 * @vsi_handle: sw VSI handle 3239 * @tc: traffic class 3240 * @rl_type: rate limit type min, max, or shared 3241 * @bw: bandwidth in Kbps - Kilo bits per sec 3242 * 3243 * Save BW information of VSI type node for post replay use. 3244 */ 3245 static enum ice_status 3246 ice_sched_save_vsi_bw(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 3247 enum ice_rl_type rl_type, u32 bw) 3248 { 3249 struct ice_vsi_ctx *vsi_ctx; 3250 3251 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 3252 return ICE_ERR_PARAM; 3253 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 3254 if (!vsi_ctx) 3255 return ICE_ERR_PARAM; 3256 switch (rl_type) { 3257 case ICE_MIN_BW: 3258 ice_set_clear_cir_bw(&vsi_ctx->sched.bw_t_info[tc], bw); 3259 break; 3260 case ICE_MAX_BW: 3261 ice_set_clear_eir_bw(&vsi_ctx->sched.bw_t_info[tc], bw); 3262 break; 3263 case ICE_SHARED_BW: 3264 ice_set_clear_shared_bw(&vsi_ctx->sched.bw_t_info[tc], bw); 3265 break; 3266 default: 3267 return ICE_ERR_PARAM; 3268 } 3269 return ICE_SUCCESS; 3270 } 3271 3272 /** 3273 * ice_set_clear_prio - set or clear priority information 3274 * @bw_t_info: bandwidth type information structure 3275 * @prio: priority to save 3276 * 3277 * Save or clear priority (prio) in the passed param bw_t_info. 3278 */ 3279 static void ice_set_clear_prio(struct ice_bw_type_info *bw_t_info, u8 prio) 3280 { 3281 bw_t_info->generic = prio; 3282 if (bw_t_info->generic) 3283 ice_set_bit(ICE_BW_TYPE_PRIO, bw_t_info->bw_t_bitmap); 3284 else 3285 ice_clear_bit(ICE_BW_TYPE_PRIO, bw_t_info->bw_t_bitmap); 3286 } 3287 3288 /** 3289 * ice_sched_save_vsi_prio - save VSI node's priority information 3290 * @pi: port information structure 3291 * @vsi_handle: Software VSI handle 3292 * @tc: traffic class 3293 * @prio: priority to save 3294 * 3295 * Save priority information of VSI type node for post replay use. 3296 */ 3297 static enum ice_status 3298 ice_sched_save_vsi_prio(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 3299 u8 prio) 3300 { 3301 struct ice_vsi_ctx *vsi_ctx; 3302 3303 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 3304 return ICE_ERR_PARAM; 3305 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 3306 if (!vsi_ctx) 3307 return ICE_ERR_PARAM; 3308 if (tc >= ICE_MAX_TRAFFIC_CLASS) 3309 return ICE_ERR_PARAM; 3310 ice_set_clear_prio(&vsi_ctx->sched.bw_t_info[tc], prio); 3311 return ICE_SUCCESS; 3312 } 3313 3314 /** 3315 * ice_sched_save_agg_bw_alloc - save aggregator node's BW alloc information 3316 * @pi: port information structure 3317 * @agg_id: node aggregator ID 3318 * @tc: traffic class 3319 * @rl_type: rate limit type min or max 3320 * @bw_alloc: bandwidth alloc information 3321 * 3322 * Save BW alloc information of AGG type node for post replay use. 3323 */ 3324 static enum ice_status 3325 ice_sched_save_agg_bw_alloc(struct ice_port_info *pi, u32 agg_id, u8 tc, 3326 enum ice_rl_type rl_type, u16 bw_alloc) 3327 { 3328 struct ice_sched_agg_info *agg_info; 3329 3330 agg_info = ice_get_agg_info(pi->hw, agg_id); 3331 if (!agg_info) 3332 return ICE_ERR_PARAM; 3333 if (!ice_is_tc_ena(agg_info->tc_bitmap[0], tc)) 3334 return ICE_ERR_PARAM; 3335 switch (rl_type) { 3336 case ICE_MIN_BW: 3337 ice_set_clear_cir_bw_alloc(&agg_info->bw_t_info[tc], bw_alloc); 3338 break; 3339 case ICE_MAX_BW: 3340 ice_set_clear_eir_bw_alloc(&agg_info->bw_t_info[tc], bw_alloc); 3341 break; 3342 default: 3343 return ICE_ERR_PARAM; 3344 } 3345 return ICE_SUCCESS; 3346 } 3347 3348 /** 3349 * ice_sched_save_agg_bw - save aggregator node's BW information 3350 * @pi: port information structure 3351 * @agg_id: node aggregator ID 3352 * @tc: traffic class 3353 * @rl_type: rate limit type min, max, or shared 3354 * @bw: bandwidth in Kbps - Kilo bits per sec 3355 * 3356 * Save BW information of AGG type node for post replay use. 3357 */ 3358 static enum ice_status 3359 ice_sched_save_agg_bw(struct ice_port_info *pi, u32 agg_id, u8 tc, 3360 enum ice_rl_type rl_type, u32 bw) 3361 { 3362 struct ice_sched_agg_info *agg_info; 3363 3364 agg_info = ice_get_agg_info(pi->hw, agg_id); 3365 if (!agg_info) 3366 return ICE_ERR_PARAM; 3367 if (!ice_is_tc_ena(agg_info->tc_bitmap[0], tc)) 3368 return ICE_ERR_PARAM; 3369 switch (rl_type) { 3370 case ICE_MIN_BW: 3371 ice_set_clear_cir_bw(&agg_info->bw_t_info[tc], bw); 3372 break; 3373 case ICE_MAX_BW: 3374 ice_set_clear_eir_bw(&agg_info->bw_t_info[tc], bw); 3375 break; 3376 case ICE_SHARED_BW: 3377 ice_set_clear_shared_bw(&agg_info->bw_t_info[tc], bw); 3378 break; 3379 default: 3380 return ICE_ERR_PARAM; 3381 } 3382 return ICE_SUCCESS; 3383 } 3384 3385 /** 3386 * ice_cfg_vsi_bw_lmt_per_tc - configure VSI BW limit per TC 3387 * @pi: port information structure 3388 * @vsi_handle: software VSI handle 3389 * @tc: traffic class 3390 * @rl_type: min or max 3391 * @bw: bandwidth in Kbps 3392 * 3393 * This function configures BW limit of VSI scheduling node based on TC 3394 * information. 3395 */ 3396 enum ice_status 3397 ice_cfg_vsi_bw_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 3398 enum ice_rl_type rl_type, u32 bw) 3399 { 3400 enum ice_status status; 3401 3402 status = ice_sched_set_node_bw_lmt_per_tc(pi, vsi_handle, 3403 ICE_AGG_TYPE_VSI, 3404 tc, rl_type, bw); 3405 if (!status) { 3406 ice_acquire_lock(&pi->sched_lock); 3407 status = ice_sched_save_vsi_bw(pi, vsi_handle, tc, rl_type, bw); 3408 ice_release_lock(&pi->sched_lock); 3409 } 3410 return status; 3411 } 3412 3413 /** 3414 * ice_cfg_vsi_bw_dflt_lmt_per_tc - configure default VSI BW limit per TC 3415 * @pi: port information structure 3416 * @vsi_handle: software VSI handle 3417 * @tc: traffic class 3418 * @rl_type: min or max 3419 * 3420 * This function configures default BW limit of VSI scheduling node based on TC 3421 * information. 3422 */ 3423 enum ice_status 3424 ice_cfg_vsi_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 3425 enum ice_rl_type rl_type) 3426 { 3427 enum ice_status status; 3428 3429 status = ice_sched_set_node_bw_lmt_per_tc(pi, vsi_handle, 3430 ICE_AGG_TYPE_VSI, 3431 tc, rl_type, 3432 ICE_SCHED_DFLT_BW); 3433 if (!status) { 3434 ice_acquire_lock(&pi->sched_lock); 3435 status = ice_sched_save_vsi_bw(pi, vsi_handle, tc, rl_type, 3436 ICE_SCHED_DFLT_BW); 3437 ice_release_lock(&pi->sched_lock); 3438 } 3439 return status; 3440 } 3441 3442 /** 3443 * ice_cfg_agg_bw_lmt_per_tc - configure aggregator BW limit per TC 3444 * @pi: port information structure 3445 * @agg_id: aggregator ID 3446 * @tc: traffic class 3447 * @rl_type: min or max 3448 * @bw: bandwidth in Kbps 3449 * 3450 * This function applies BW limit to aggregator scheduling node based on TC 3451 * information. 3452 */ 3453 enum ice_status 3454 ice_cfg_agg_bw_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc, 3455 enum ice_rl_type rl_type, u32 bw) 3456 { 3457 enum ice_status status; 3458 3459 status = ice_sched_set_node_bw_lmt_per_tc(pi, agg_id, ICE_AGG_TYPE_AGG, 3460 tc, rl_type, bw); 3461 if (!status) { 3462 ice_acquire_lock(&pi->sched_lock); 3463 status = ice_sched_save_agg_bw(pi, agg_id, tc, rl_type, bw); 3464 ice_release_lock(&pi->sched_lock); 3465 } 3466 return status; 3467 } 3468 3469 /** 3470 * ice_cfg_agg_bw_dflt_lmt_per_tc - configure aggregator BW default limit per TC 3471 * @pi: port information structure 3472 * @agg_id: aggregator ID 3473 * @tc: traffic class 3474 * @rl_type: min or max 3475 * 3476 * This function applies default BW limit to aggregator scheduling node based 3477 * on TC information. 3478 */ 3479 enum ice_status 3480 ice_cfg_agg_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc, 3481 enum ice_rl_type rl_type) 3482 { 3483 enum ice_status status; 3484 3485 status = ice_sched_set_node_bw_lmt_per_tc(pi, agg_id, ICE_AGG_TYPE_AGG, 3486 tc, rl_type, 3487 ICE_SCHED_DFLT_BW); 3488 if (!status) { 3489 ice_acquire_lock(&pi->sched_lock); 3490 status = ice_sched_save_agg_bw(pi, agg_id, tc, rl_type, 3491 ICE_SCHED_DFLT_BW); 3492 ice_release_lock(&pi->sched_lock); 3493 } 3494 return status; 3495 } 3496 3497 /** 3498 * ice_cfg_vsi_bw_shared_lmt - configure VSI BW shared limit 3499 * @pi: port information structure 3500 * @vsi_handle: software VSI handle 3501 * @min_bw: minimum bandwidth in Kbps 3502 * @max_bw: maximum bandwidth in Kbps 3503 * @shared_bw: shared bandwidth in Kbps 3504 * 3505 * Configure shared rate limiter(SRL) of all VSI type nodes across all traffic 3506 * classes for VSI matching handle. 3507 */ 3508 enum ice_status 3509 ice_cfg_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle, u32 min_bw, 3510 u32 max_bw, u32 shared_bw) 3511 { 3512 return ice_sched_set_vsi_bw_shared_lmt(pi, vsi_handle, min_bw, max_bw, 3513 shared_bw); 3514 } 3515 3516 /** 3517 * ice_cfg_vsi_bw_no_shared_lmt - configure VSI BW for no shared limiter 3518 * @pi: port information structure 3519 * @vsi_handle: software VSI handle 3520 * 3521 * This function removes the shared rate limiter(SRL) of all VSI type nodes 3522 * across all traffic classes for VSI matching handle. 3523 */ 3524 enum ice_status 3525 ice_cfg_vsi_bw_no_shared_lmt(struct ice_port_info *pi, u16 vsi_handle) 3526 { 3527 return ice_sched_set_vsi_bw_shared_lmt(pi, vsi_handle, 3528 ICE_SCHED_DFLT_BW, 3529 ICE_SCHED_DFLT_BW, 3530 ICE_SCHED_DFLT_BW); 3531 } 3532 3533 /** 3534 * ice_cfg_agg_bw_shared_lmt - configure aggregator BW shared limit 3535 * @pi: port information structure 3536 * @agg_id: aggregator ID 3537 * @min_bw: minimum bandwidth in Kbps 3538 * @max_bw: maximum bandwidth in Kbps 3539 * @shared_bw: shared bandwidth in Kbps 3540 * 3541 * This function configures the shared rate limiter(SRL) of all aggregator type 3542 * nodes across all traffic classes for aggregator matching agg_id. 3543 */ 3544 enum ice_status 3545 ice_cfg_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 min_bw, 3546 u32 max_bw, u32 shared_bw) 3547 { 3548 return ice_sched_set_agg_bw_shared_lmt(pi, agg_id, min_bw, max_bw, 3549 shared_bw); 3550 } 3551 3552 /** 3553 * ice_cfg_agg_bw_no_shared_lmt - configure aggregator BW for no shared limiter 3554 * @pi: port information structure 3555 * @agg_id: aggregator ID 3556 * 3557 * This function removes the shared rate limiter(SRL) of all aggregator type 3558 * nodes across all traffic classes for aggregator matching agg_id. 3559 */ 3560 enum ice_status 3561 ice_cfg_agg_bw_no_shared_lmt(struct ice_port_info *pi, u32 agg_id) 3562 { 3563 return ice_sched_set_agg_bw_shared_lmt(pi, agg_id, ICE_SCHED_DFLT_BW, 3564 ICE_SCHED_DFLT_BW, 3565 ICE_SCHED_DFLT_BW); 3566 } 3567 3568 /** 3569 * ice_cfg_agg_bw_shared_lmt_per_tc - config aggregator BW shared limit per tc 3570 * @pi: port information structure 3571 * @agg_id: aggregator ID 3572 * @tc: traffic class 3573 * @min_bw: minimum bandwidth in Kbps 3574 * @max_bw: maximum bandwidth in Kbps 3575 * @shared_bw: shared bandwidth in Kbps 3576 * 3577 * This function configures the shared rate limiter(SRL) of all aggregator type 3578 * nodes across all traffic classes for aggregator matching agg_id. 3579 */ 3580 enum ice_status 3581 ice_cfg_agg_bw_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc, 3582 u32 min_bw, u32 max_bw, u32 shared_bw) 3583 { 3584 return ice_sched_set_agg_bw_shared_lmt_per_tc(pi, agg_id, tc, min_bw, 3585 max_bw, shared_bw); 3586 } 3587 3588 /** 3589 * ice_cfg_agg_bw_no_shared_lmt_per_tc - cfg aggregator BW shared limit per tc 3590 * @pi: port information structure 3591 * @agg_id: aggregator ID 3592 * @tc: traffic class 3593 * 3594 * This function configures the shared rate limiter(SRL) of all aggregator type 3595 * nodes across all traffic classes for aggregator matching agg_id. 3596 */ 3597 enum ice_status 3598 ice_cfg_agg_bw_no_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc) 3599 { 3600 return ice_sched_set_agg_bw_shared_lmt_per_tc(pi, agg_id, tc, 3601 ICE_SCHED_DFLT_BW, 3602 ICE_SCHED_DFLT_BW, 3603 ICE_SCHED_DFLT_BW); 3604 } 3605 3606 /** 3607 * ice_cfg_vsi_q_priority - config VSI queue priority of node 3608 * @pi: port information structure 3609 * @num_qs: number of VSI queues 3610 * @q_ids: queue IDs array 3611 * @q_prio: queue priority array 3612 * 3613 * This function configures the queue node priority (Sibling Priority) of the 3614 * passed in VSI's queue(s) for a given traffic class (TC). 3615 */ 3616 enum ice_status 3617 ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 num_qs, u32 *q_ids, 3618 u8 *q_prio) 3619 { 3620 enum ice_status status = ICE_ERR_PARAM; 3621 u16 i; 3622 3623 ice_acquire_lock(&pi->sched_lock); 3624 3625 for (i = 0; i < num_qs; i++) { 3626 struct ice_sched_node *node; 3627 3628 node = ice_sched_find_node_by_teid(pi->root, q_ids[i]); 3629 if (!node || node->info.data.elem_type != 3630 ICE_AQC_ELEM_TYPE_LEAF) { 3631 status = ICE_ERR_PARAM; 3632 break; 3633 } 3634 /* Configure Priority */ 3635 status = ice_sched_cfg_sibl_node_prio(pi, node, q_prio[i]); 3636 if (status) 3637 break; 3638 } 3639 3640 ice_release_lock(&pi->sched_lock); 3641 return status; 3642 } 3643 3644 /** 3645 * ice_cfg_agg_vsi_priority_per_tc - config aggregator's VSI priority per TC 3646 * @pi: port information structure 3647 * @agg_id: Aggregator ID 3648 * @num_vsis: number of VSI(s) 3649 * @vsi_handle_arr: array of software VSI handles 3650 * @node_prio: pointer to node priority 3651 * @tc: traffic class 3652 * 3653 * This function configures the node priority (Sibling Priority) of the 3654 * passed in VSI's for a given traffic class (TC) of an Aggregator ID. 3655 */ 3656 enum ice_status 3657 ice_cfg_agg_vsi_priority_per_tc(struct ice_port_info *pi, u32 agg_id, 3658 u16 num_vsis, u16 *vsi_handle_arr, 3659 u8 *node_prio, u8 tc) 3660 { 3661 struct ice_sched_agg_vsi_info *agg_vsi_info; 3662 struct ice_sched_node *tc_node, *agg_node; 3663 enum ice_status status = ICE_ERR_PARAM; 3664 struct ice_sched_agg_info *agg_info; 3665 bool agg_id_present = false; 3666 struct ice_hw *hw = pi->hw; 3667 u16 i; 3668 3669 ice_acquire_lock(&pi->sched_lock); 3670 LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info, 3671 list_entry) 3672 if (agg_info->agg_id == agg_id) { 3673 agg_id_present = true; 3674 break; 3675 } 3676 if (!agg_id_present) 3677 goto exit_agg_priority_per_tc; 3678 3679 tc_node = ice_sched_get_tc_node(pi, tc); 3680 if (!tc_node) 3681 goto exit_agg_priority_per_tc; 3682 3683 agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); 3684 if (!agg_node) 3685 goto exit_agg_priority_per_tc; 3686 3687 if (num_vsis > hw->max_children[agg_node->tx_sched_layer]) 3688 goto exit_agg_priority_per_tc; 3689 3690 for (i = 0; i < num_vsis; i++) { 3691 struct ice_sched_node *vsi_node; 3692 bool vsi_handle_valid = false; 3693 u16 vsi_handle; 3694 3695 status = ICE_ERR_PARAM; 3696 vsi_handle = vsi_handle_arr[i]; 3697 if (!ice_is_vsi_valid(hw, vsi_handle)) 3698 goto exit_agg_priority_per_tc; 3699 /* Verify child nodes before applying settings */ 3700 LIST_FOR_EACH_ENTRY(agg_vsi_info, &agg_info->agg_vsi_list, 3701 ice_sched_agg_vsi_info, list_entry) 3702 if (agg_vsi_info->vsi_handle == vsi_handle) { 3703 vsi_handle_valid = true; 3704 break; 3705 } 3706 3707 if (!vsi_handle_valid) 3708 goto exit_agg_priority_per_tc; 3709 3710 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 3711 if (!vsi_node) 3712 goto exit_agg_priority_per_tc; 3713 3714 if (ice_sched_find_node_in_subtree(hw, agg_node, vsi_node)) { 3715 /* Configure Priority */ 3716 status = ice_sched_cfg_sibl_node_prio(pi, vsi_node, 3717 node_prio[i]); 3718 if (status) 3719 break; 3720 status = ice_sched_save_vsi_prio(pi, vsi_handle, tc, 3721 node_prio[i]); 3722 if (status) 3723 break; 3724 } 3725 } 3726 3727 exit_agg_priority_per_tc: 3728 ice_release_lock(&pi->sched_lock); 3729 return status; 3730 } 3731 3732 /** 3733 * ice_cfg_vsi_bw_alloc - config VSI BW alloc per TC 3734 * @pi: port information structure 3735 * @vsi_handle: software VSI handle 3736 * @ena_tcmap: enabled TC map 3737 * @rl_type: Rate limit type CIR/EIR 3738 * @bw_alloc: Array of BW alloc 3739 * 3740 * This function configures the BW allocation of the passed in VSI's 3741 * node(s) for enabled traffic class. 3742 */ 3743 enum ice_status 3744 ice_cfg_vsi_bw_alloc(struct ice_port_info *pi, u16 vsi_handle, u8 ena_tcmap, 3745 enum ice_rl_type rl_type, u8 *bw_alloc) 3746 { 3747 enum ice_status status = ICE_SUCCESS; 3748 u8 tc; 3749 3750 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 3751 return ICE_ERR_PARAM; 3752 3753 ice_acquire_lock(&pi->sched_lock); 3754 3755 /* Return success if no nodes are present across TC */ 3756 ice_for_each_traffic_class(tc) { 3757 struct ice_sched_node *tc_node, *vsi_node; 3758 3759 if (!ice_is_tc_ena(ena_tcmap, tc)) 3760 continue; 3761 3762 tc_node = ice_sched_get_tc_node(pi, tc); 3763 if (!tc_node) 3764 continue; 3765 3766 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 3767 if (!vsi_node) 3768 continue; 3769 3770 status = ice_sched_cfg_node_bw_alloc(pi->hw, vsi_node, rl_type, 3771 bw_alloc[tc]); 3772 if (status) 3773 break; 3774 status = ice_sched_save_vsi_bw_alloc(pi, vsi_handle, tc, 3775 rl_type, bw_alloc[tc]); 3776 if (status) 3777 break; 3778 } 3779 3780 ice_release_lock(&pi->sched_lock); 3781 return status; 3782 } 3783 3784 /** 3785 * ice_cfg_agg_bw_alloc - config aggregator BW alloc 3786 * @pi: port information structure 3787 * @agg_id: aggregator ID 3788 * @ena_tcmap: enabled TC map 3789 * @rl_type: rate limit type CIR/EIR 3790 * @bw_alloc: array of BW alloc 3791 * 3792 * This function configures the BW allocation of passed in aggregator for 3793 * enabled traffic class(s). 3794 */ 3795 enum ice_status 3796 ice_cfg_agg_bw_alloc(struct ice_port_info *pi, u32 agg_id, u8 ena_tcmap, 3797 enum ice_rl_type rl_type, u8 *bw_alloc) 3798 { 3799 struct ice_sched_agg_info *agg_info; 3800 bool agg_id_present = false; 3801 enum ice_status status = ICE_SUCCESS; 3802 struct ice_hw *hw = pi->hw; 3803 u8 tc; 3804 3805 ice_acquire_lock(&pi->sched_lock); 3806 LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info, 3807 list_entry) 3808 if (agg_info->agg_id == agg_id) { 3809 agg_id_present = true; 3810 break; 3811 } 3812 if (!agg_id_present) { 3813 status = ICE_ERR_PARAM; 3814 goto exit_cfg_agg_bw_alloc; 3815 } 3816 3817 /* Return success if no nodes are present across TC */ 3818 ice_for_each_traffic_class(tc) { 3819 struct ice_sched_node *tc_node, *agg_node; 3820 3821 if (!ice_is_tc_ena(ena_tcmap, tc)) 3822 continue; 3823 3824 tc_node = ice_sched_get_tc_node(pi, tc); 3825 if (!tc_node) 3826 continue; 3827 3828 agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); 3829 if (!agg_node) 3830 continue; 3831 3832 status = ice_sched_cfg_node_bw_alloc(hw, agg_node, rl_type, 3833 bw_alloc[tc]); 3834 if (status) 3835 break; 3836 status = ice_sched_save_agg_bw_alloc(pi, agg_id, tc, rl_type, 3837 bw_alloc[tc]); 3838 if (status) 3839 break; 3840 } 3841 3842 exit_cfg_agg_bw_alloc: 3843 ice_release_lock(&pi->sched_lock); 3844 return status; 3845 } 3846 3847 /** 3848 * ice_sched_calc_wakeup - calculate RL profile wakeup parameter 3849 * @hw: pointer to the HW struct 3850 * @bw: bandwidth in Kbps 3851 * 3852 * This function calculates the wakeup parameter of RL profile. 3853 */ 3854 static u16 ice_sched_calc_wakeup(struct ice_hw *hw, s32 bw) 3855 { 3856 s64 bytes_per_sec, wakeup_int, wakeup_a, wakeup_b, wakeup_f; 3857 s32 wakeup_f_int; 3858 u16 wakeup = 0; 3859 3860 /* Get the wakeup integer value */ 3861 bytes_per_sec = DIV_S64(bw * 1000, BITS_PER_BYTE); 3862 wakeup_int = DIV_S64(hw->psm_clk_freq, bytes_per_sec); 3863 if (wakeup_int > 63) { 3864 wakeup = (u16)((1 << 15) | wakeup_int); 3865 } else { 3866 /* Calculate fraction value up to 4 decimals 3867 * Convert Integer value to a constant multiplier 3868 */ 3869 wakeup_b = (s64)ICE_RL_PROF_MULTIPLIER * wakeup_int; 3870 wakeup_a = DIV_S64(ICE_RL_PROF_MULTIPLIER * 3871 hw->psm_clk_freq, bytes_per_sec); 3872 3873 /* Get Fraction value */ 3874 wakeup_f = wakeup_a - wakeup_b; 3875 3876 /* Round up the Fractional value via Ceil(Fractional value) */ 3877 if (wakeup_f > DIV_S64(ICE_RL_PROF_MULTIPLIER, 2)) 3878 wakeup_f += 1; 3879 3880 wakeup_f_int = (s32)DIV_S64(wakeup_f * ICE_RL_PROF_FRACTION, 3881 ICE_RL_PROF_MULTIPLIER); 3882 wakeup |= (u16)(wakeup_int << 9); 3883 wakeup |= (u16)(0x1ff & wakeup_f_int); 3884 } 3885 3886 return wakeup; 3887 } 3888 3889 /** 3890 * ice_sched_bw_to_rl_profile - convert BW to profile parameters 3891 * @hw: pointer to the HW struct 3892 * @bw: bandwidth in Kbps 3893 * @profile: profile parameters to return 3894 * 3895 * This function converts the BW to profile structure format. 3896 */ 3897 static enum ice_status 3898 ice_sched_bw_to_rl_profile(struct ice_hw *hw, u32 bw, 3899 struct ice_aqc_rl_profile_elem *profile) 3900 { 3901 enum ice_status status = ICE_ERR_PARAM; 3902 s64 bytes_per_sec, ts_rate, mv_tmp; 3903 bool found = false; 3904 s32 encode = 0; 3905 s64 mv = 0; 3906 s32 i; 3907 3908 /* Bw settings range is from 0.5Mb/sec to 100Gb/sec */ 3909 if (bw < ICE_SCHED_MIN_BW || bw > ICE_SCHED_MAX_BW) 3910 return status; 3911 3912 /* Bytes per second from Kbps */ 3913 bytes_per_sec = DIV_S64(bw * 1000, BITS_PER_BYTE); 3914 3915 /* encode is 6 bits but really useful are 5 bits */ 3916 for (i = 0; i < 64; i++) { 3917 u64 pow_result = BIT_ULL(i); 3918 3919 ts_rate = DIV_S64(hw->psm_clk_freq, 3920 pow_result * ICE_RL_PROF_TS_MULTIPLIER); 3921 if (ts_rate <= 0) 3922 continue; 3923 3924 /* Multiplier value */ 3925 mv_tmp = DIV_S64(bytes_per_sec * ICE_RL_PROF_MULTIPLIER, 3926 ts_rate); 3927 3928 /* Round to the nearest ICE_RL_PROF_MULTIPLIER */ 3929 mv = round_up_64bit(mv_tmp, ICE_RL_PROF_MULTIPLIER); 3930 3931 /* First multiplier value greater than the given 3932 * accuracy bytes 3933 */ 3934 if (mv > ICE_RL_PROF_ACCURACY_BYTES) { 3935 encode = i; 3936 found = true; 3937 break; 3938 } 3939 } 3940 if (found) { 3941 u16 wm; 3942 3943 wm = ice_sched_calc_wakeup(hw, bw); 3944 profile->rl_multiply = CPU_TO_LE16(mv); 3945 profile->wake_up_calc = CPU_TO_LE16(wm); 3946 profile->rl_encode = CPU_TO_LE16(encode); 3947 status = ICE_SUCCESS; 3948 } else { 3949 status = ICE_ERR_DOES_NOT_EXIST; 3950 } 3951 3952 return status; 3953 } 3954 3955 /** 3956 * ice_sched_add_rl_profile - add RL profile 3957 * @hw: pointer to the hardware structure 3958 * @rl_type: type of rate limit BW - min, max, or shared 3959 * @bw: bandwidth in Kbps - Kilo bits per sec 3960 * @layer_num: specifies in which layer to create profile 3961 * 3962 * This function first checks the existing list for corresponding BW 3963 * parameter. If it exists, it returns the associated profile otherwise 3964 * it creates a new rate limit profile for requested BW, and adds it to 3965 * the HW DB and local list. It returns the new profile or null on error. 3966 * The caller needs to hold the scheduler lock. 3967 */ 3968 static struct ice_aqc_rl_profile_info * 3969 ice_sched_add_rl_profile(struct ice_hw *hw, enum ice_rl_type rl_type, 3970 u32 bw, u8 layer_num) 3971 { 3972 struct ice_aqc_rl_profile_info *rl_prof_elem; 3973 u16 profiles_added = 0, num_profiles = 1; 3974 struct ice_aqc_rl_profile_elem *buf; 3975 enum ice_status status; 3976 u8 profile_type; 3977 3978 if (layer_num >= ICE_AQC_TOPO_MAX_LEVEL_NUM) 3979 return NULL; 3980 switch (rl_type) { 3981 case ICE_MIN_BW: 3982 profile_type = ICE_AQC_RL_PROFILE_TYPE_CIR; 3983 break; 3984 case ICE_MAX_BW: 3985 profile_type = ICE_AQC_RL_PROFILE_TYPE_EIR; 3986 break; 3987 case ICE_SHARED_BW: 3988 profile_type = ICE_AQC_RL_PROFILE_TYPE_SRL; 3989 break; 3990 default: 3991 return NULL; 3992 } 3993 3994 if (!hw) 3995 return NULL; 3996 LIST_FOR_EACH_ENTRY(rl_prof_elem, &hw->rl_prof_list[layer_num], 3997 ice_aqc_rl_profile_info, list_entry) 3998 if ((rl_prof_elem->profile.flags & ICE_AQC_RL_PROFILE_TYPE_M) == 3999 profile_type && rl_prof_elem->bw == bw) 4000 /* Return existing profile ID info */ 4001 return rl_prof_elem; 4002 4003 /* Create new profile ID */ 4004 rl_prof_elem = (struct ice_aqc_rl_profile_info *) 4005 ice_malloc(hw, sizeof(*rl_prof_elem)); 4006 4007 if (!rl_prof_elem) 4008 return NULL; 4009 4010 status = ice_sched_bw_to_rl_profile(hw, bw, &rl_prof_elem->profile); 4011 if (status != ICE_SUCCESS) 4012 goto exit_add_rl_prof; 4013 4014 rl_prof_elem->bw = bw; 4015 /* layer_num is zero relative, and fw expects level from 1 to 9 */ 4016 rl_prof_elem->profile.level = layer_num + 1; 4017 rl_prof_elem->profile.flags = profile_type; 4018 rl_prof_elem->profile.max_burst_size = CPU_TO_LE16(hw->max_burst_size); 4019 4020 /* Create new entry in HW DB */ 4021 buf = &rl_prof_elem->profile; 4022 status = ice_aq_add_rl_profile(hw, num_profiles, buf, sizeof(*buf), 4023 &profiles_added, NULL); 4024 if (status || profiles_added != num_profiles) 4025 goto exit_add_rl_prof; 4026 4027 /* Good entry - add in the list */ 4028 rl_prof_elem->prof_id_ref = 0; 4029 LIST_ADD(&rl_prof_elem->list_entry, &hw->rl_prof_list[layer_num]); 4030 return rl_prof_elem; 4031 4032 exit_add_rl_prof: 4033 ice_free(hw, rl_prof_elem); 4034 return NULL; 4035 } 4036 4037 /** 4038 * ice_sched_cfg_node_bw_lmt - configure node sched params 4039 * @hw: pointer to the HW struct 4040 * @node: sched node to configure 4041 * @rl_type: rate limit type CIR, EIR, or shared 4042 * @rl_prof_id: rate limit profile ID 4043 * 4044 * This function configures node element's BW limit. 4045 */ 4046 static enum ice_status 4047 ice_sched_cfg_node_bw_lmt(struct ice_hw *hw, struct ice_sched_node *node, 4048 enum ice_rl_type rl_type, u16 rl_prof_id) 4049 { 4050 struct ice_aqc_txsched_elem_data buf; 4051 struct ice_aqc_txsched_elem *data; 4052 4053 buf = node->info; 4054 data = &buf.data; 4055 switch (rl_type) { 4056 case ICE_MIN_BW: 4057 data->valid_sections |= ICE_AQC_ELEM_VALID_CIR; 4058 data->cir_bw.bw_profile_idx = CPU_TO_LE16(rl_prof_id); 4059 break; 4060 case ICE_MAX_BW: 4061 data->valid_sections |= ICE_AQC_ELEM_VALID_EIR; 4062 data->eir_bw.bw_profile_idx = CPU_TO_LE16(rl_prof_id); 4063 break; 4064 case ICE_SHARED_BW: 4065 data->valid_sections |= ICE_AQC_ELEM_VALID_SHARED; 4066 data->srl_id = CPU_TO_LE16(rl_prof_id); 4067 break; 4068 default: 4069 /* Unknown rate limit type */ 4070 return ICE_ERR_PARAM; 4071 } 4072 4073 /* Configure element */ 4074 return ice_sched_update_elem(hw, node, &buf); 4075 } 4076 4077 /** 4078 * ice_sched_get_node_rl_prof_id - get node's rate limit profile ID 4079 * @node: sched node 4080 * @rl_type: rate limit type 4081 * 4082 * If existing profile matches, it returns the corresponding rate 4083 * limit profile ID, otherwise it returns an invalid ID as error. 4084 */ 4085 static u16 4086 ice_sched_get_node_rl_prof_id(struct ice_sched_node *node, 4087 enum ice_rl_type rl_type) 4088 { 4089 u16 rl_prof_id = ICE_SCHED_INVAL_PROF_ID; 4090 struct ice_aqc_txsched_elem *data; 4091 4092 data = &node->info.data; 4093 switch (rl_type) { 4094 case ICE_MIN_BW: 4095 if (data->valid_sections & ICE_AQC_ELEM_VALID_CIR) 4096 rl_prof_id = LE16_TO_CPU(data->cir_bw.bw_profile_idx); 4097 break; 4098 case ICE_MAX_BW: 4099 if (data->valid_sections & ICE_AQC_ELEM_VALID_EIR) 4100 rl_prof_id = LE16_TO_CPU(data->eir_bw.bw_profile_idx); 4101 break; 4102 case ICE_SHARED_BW: 4103 if (data->valid_sections & ICE_AQC_ELEM_VALID_SHARED) 4104 rl_prof_id = LE16_TO_CPU(data->srl_id); 4105 break; 4106 default: 4107 break; 4108 } 4109 4110 return rl_prof_id; 4111 } 4112 4113 /** 4114 * ice_sched_get_rl_prof_layer - selects rate limit profile creation layer 4115 * @pi: port information structure 4116 * @rl_type: type of rate limit BW - min, max, or shared 4117 * @layer_index: layer index 4118 * 4119 * This function returns requested profile creation layer. 4120 */ 4121 static u8 4122 ice_sched_get_rl_prof_layer(struct ice_port_info *pi, enum ice_rl_type rl_type, 4123 u8 layer_index) 4124 { 4125 struct ice_hw *hw = pi->hw; 4126 4127 if (layer_index >= hw->num_tx_sched_layers) 4128 return ICE_SCHED_INVAL_LAYER_NUM; 4129 switch (rl_type) { 4130 case ICE_MIN_BW: 4131 if (hw->layer_info[layer_index].max_cir_rl_profiles) 4132 return layer_index; 4133 break; 4134 case ICE_MAX_BW: 4135 if (hw->layer_info[layer_index].max_eir_rl_profiles) 4136 return layer_index; 4137 break; 4138 case ICE_SHARED_BW: 4139 /* if current layer doesn't support SRL profile creation 4140 * then try a layer up or down. 4141 */ 4142 if (hw->layer_info[layer_index].max_srl_profiles) 4143 return layer_index; 4144 else if (layer_index < hw->num_tx_sched_layers - 1 && 4145 hw->layer_info[layer_index + 1].max_srl_profiles) 4146 return layer_index + 1; 4147 else if (layer_index > 0 && 4148 hw->layer_info[layer_index - 1].max_srl_profiles) 4149 return layer_index - 1; 4150 break; 4151 default: 4152 break; 4153 } 4154 return ICE_SCHED_INVAL_LAYER_NUM; 4155 } 4156 4157 /** 4158 * ice_sched_get_srl_node - get shared rate limit node 4159 * @node: tree node 4160 * @srl_layer: shared rate limit layer 4161 * 4162 * This function returns SRL node to be used for shared rate limit purpose. 4163 * The caller needs to hold scheduler lock. 4164 */ 4165 static struct ice_sched_node * 4166 ice_sched_get_srl_node(struct ice_sched_node *node, u8 srl_layer) 4167 { 4168 if (srl_layer > node->tx_sched_layer) 4169 return node->children[0]; 4170 else if (srl_layer < node->tx_sched_layer) 4171 /* Node can't be created without a parent. It will always 4172 * have a valid parent except root node. 4173 */ 4174 return node->parent; 4175 else 4176 return node; 4177 } 4178 4179 /** 4180 * ice_sched_rm_rl_profile - remove RL profile ID 4181 * @hw: pointer to the hardware structure 4182 * @layer_num: layer number where profiles are saved 4183 * @profile_type: profile type like EIR, CIR, or SRL 4184 * @profile_id: profile ID to remove 4185 * 4186 * This function removes rate limit profile from layer 'layer_num' of type 4187 * 'profile_type' and profile ID as 'profile_id'. The caller needs to hold 4188 * scheduler lock. 4189 */ 4190 static enum ice_status 4191 ice_sched_rm_rl_profile(struct ice_hw *hw, u8 layer_num, u8 profile_type, 4192 u16 profile_id) 4193 { 4194 struct ice_aqc_rl_profile_info *rl_prof_elem; 4195 enum ice_status status = ICE_SUCCESS; 4196 4197 if (layer_num >= ICE_AQC_TOPO_MAX_LEVEL_NUM) 4198 return ICE_ERR_PARAM; 4199 /* Check the existing list for RL profile */ 4200 LIST_FOR_EACH_ENTRY(rl_prof_elem, &hw->rl_prof_list[layer_num], 4201 ice_aqc_rl_profile_info, list_entry) 4202 if ((rl_prof_elem->profile.flags & ICE_AQC_RL_PROFILE_TYPE_M) == 4203 profile_type && 4204 LE16_TO_CPU(rl_prof_elem->profile.profile_id) == 4205 profile_id) { 4206 if (rl_prof_elem->prof_id_ref) 4207 rl_prof_elem->prof_id_ref--; 4208 4209 /* Remove old profile ID from database */ 4210 status = ice_sched_del_rl_profile(hw, rl_prof_elem); 4211 if (status && status != ICE_ERR_IN_USE) 4212 ice_debug(hw, ICE_DBG_SCHED, "Remove rl profile failed\n"); 4213 break; 4214 } 4215 if (status == ICE_ERR_IN_USE) 4216 status = ICE_SUCCESS; 4217 return status; 4218 } 4219 4220 /** 4221 * ice_sched_set_node_bw_dflt - set node's bandwidth limit to default 4222 * @pi: port information structure 4223 * @node: pointer to node structure 4224 * @rl_type: rate limit type min, max, or shared 4225 * @layer_num: layer number where RL profiles are saved 4226 * 4227 * This function configures node element's BW rate limit profile ID of 4228 * type CIR, EIR, or SRL to default. This function needs to be called 4229 * with the scheduler lock held. 4230 */ 4231 static enum ice_status 4232 ice_sched_set_node_bw_dflt(struct ice_port_info *pi, 4233 struct ice_sched_node *node, 4234 enum ice_rl_type rl_type, u8 layer_num) 4235 { 4236 enum ice_status status; 4237 struct ice_hw *hw; 4238 u8 profile_type; 4239 u16 rl_prof_id; 4240 u16 old_id; 4241 4242 hw = pi->hw; 4243 switch (rl_type) { 4244 case ICE_MIN_BW: 4245 profile_type = ICE_AQC_RL_PROFILE_TYPE_CIR; 4246 rl_prof_id = ICE_SCHED_DFLT_RL_PROF_ID; 4247 break; 4248 case ICE_MAX_BW: 4249 profile_type = ICE_AQC_RL_PROFILE_TYPE_EIR; 4250 rl_prof_id = ICE_SCHED_DFLT_RL_PROF_ID; 4251 break; 4252 case ICE_SHARED_BW: 4253 profile_type = ICE_AQC_RL_PROFILE_TYPE_SRL; 4254 /* No SRL is configured for default case */ 4255 rl_prof_id = ICE_SCHED_NO_SHARED_RL_PROF_ID; 4256 break; 4257 default: 4258 return ICE_ERR_PARAM; 4259 } 4260 /* Save existing RL prof ID for later clean up */ 4261 old_id = ice_sched_get_node_rl_prof_id(node, rl_type); 4262 /* Configure BW scheduling parameters */ 4263 status = ice_sched_cfg_node_bw_lmt(hw, node, rl_type, rl_prof_id); 4264 if (status) 4265 return status; 4266 4267 /* Remove stale RL profile ID */ 4268 if (old_id == ICE_SCHED_DFLT_RL_PROF_ID || 4269 old_id == ICE_SCHED_INVAL_PROF_ID) 4270 return ICE_SUCCESS; 4271 4272 return ice_sched_rm_rl_profile(hw, layer_num, profile_type, old_id); 4273 } 4274 4275 /** 4276 * ice_sched_set_node_bw - set node's bandwidth 4277 * @pi: port information structure 4278 * @node: tree node 4279 * @rl_type: rate limit type min, max, or shared 4280 * @bw: bandwidth in Kbps - Kilo bits per sec 4281 * @layer_num: layer number 4282 * 4283 * This function adds new profile corresponding to requested BW, configures 4284 * node's RL profile ID of type CIR, EIR, or SRL, and removes old profile 4285 * ID from local database. The caller needs to hold scheduler lock. 4286 */ 4287 static enum ice_status 4288 ice_sched_set_node_bw(struct ice_port_info *pi, struct ice_sched_node *node, 4289 enum ice_rl_type rl_type, u32 bw, u8 layer_num) 4290 { 4291 struct ice_aqc_rl_profile_info *rl_prof_info; 4292 enum ice_status status = ICE_ERR_PARAM; 4293 struct ice_hw *hw = pi->hw; 4294 u16 old_id, rl_prof_id; 4295 4296 rl_prof_info = ice_sched_add_rl_profile(hw, rl_type, bw, layer_num); 4297 if (!rl_prof_info) 4298 return status; 4299 4300 rl_prof_id = LE16_TO_CPU(rl_prof_info->profile.profile_id); 4301 4302 /* Save existing RL prof ID for later clean up */ 4303 old_id = ice_sched_get_node_rl_prof_id(node, rl_type); 4304 /* Configure BW scheduling parameters */ 4305 status = ice_sched_cfg_node_bw_lmt(hw, node, rl_type, rl_prof_id); 4306 if (status) 4307 return status; 4308 4309 /* New changes has been applied */ 4310 /* Increment the profile ID reference count */ 4311 rl_prof_info->prof_id_ref++; 4312 4313 /* Check for old ID removal */ 4314 if ((old_id == ICE_SCHED_DFLT_RL_PROF_ID && rl_type != ICE_SHARED_BW) || 4315 old_id == ICE_SCHED_INVAL_PROF_ID || old_id == rl_prof_id) 4316 return ICE_SUCCESS; 4317 4318 return ice_sched_rm_rl_profile(hw, layer_num, 4319 rl_prof_info->profile.flags & 4320 ICE_AQC_RL_PROFILE_TYPE_M, old_id); 4321 } 4322 4323 /** 4324 * ice_sched_set_node_bw_lmt - set node's BW limit 4325 * @pi: port information structure 4326 * @node: tree node 4327 * @rl_type: rate limit type min, max, or shared 4328 * @bw: bandwidth in Kbps - Kilo bits per sec 4329 * 4330 * It updates node's BW limit parameters like BW RL profile ID of type CIR, 4331 * EIR, or SRL. The caller needs to hold scheduler lock. 4332 * 4333 * NOTE: Caller provides the correct SRL node in case of shared profile 4334 * settings. 4335 */ 4336 static enum ice_status 4337 ice_sched_set_node_bw_lmt(struct ice_port_info *pi, struct ice_sched_node *node, 4338 enum ice_rl_type rl_type, u32 bw) 4339 { 4340 struct ice_hw *hw; 4341 u8 layer_num; 4342 4343 if (!pi) 4344 return ICE_ERR_PARAM; 4345 hw = pi->hw; 4346 /* Remove unused RL profile IDs from HW and SW DB */ 4347 ice_sched_rm_unused_rl_prof(hw); 4348 4349 layer_num = ice_sched_get_rl_prof_layer(pi, rl_type, 4350 node->tx_sched_layer); 4351 if (layer_num >= hw->num_tx_sched_layers) 4352 return ICE_ERR_PARAM; 4353 4354 if (bw == ICE_SCHED_DFLT_BW) 4355 return ice_sched_set_node_bw_dflt(pi, node, rl_type, layer_num); 4356 return ice_sched_set_node_bw(pi, node, rl_type, bw, layer_num); 4357 } 4358 4359 /** 4360 * ice_sched_set_node_bw_dflt_lmt - set node's BW limit to default 4361 * @pi: port information structure 4362 * @node: pointer to node structure 4363 * @rl_type: rate limit type min, max, or shared 4364 * 4365 * This function configures node element's BW rate limit profile ID of 4366 * type CIR, EIR, or SRL to default. This function needs to be called 4367 * with the scheduler lock held. 4368 */ 4369 static enum ice_status 4370 ice_sched_set_node_bw_dflt_lmt(struct ice_port_info *pi, 4371 struct ice_sched_node *node, 4372 enum ice_rl_type rl_type) 4373 { 4374 return ice_sched_set_node_bw_lmt(pi, node, rl_type, 4375 ICE_SCHED_DFLT_BW); 4376 } 4377 4378 /** 4379 * ice_sched_validate_srl_node - Check node for SRL applicability 4380 * @node: sched node to configure 4381 * @sel_layer: selected SRL layer 4382 * 4383 * This function checks if the SRL can be applied to a selceted layer node on 4384 * behalf of the requested node (first argument). This function needs to be 4385 * called with scheduler lock held. 4386 */ 4387 static enum ice_status 4388 ice_sched_validate_srl_node(struct ice_sched_node *node, u8 sel_layer) 4389 { 4390 /* SRL profiles are not available on all layers. Check if the 4391 * SRL profile can be applied to a node above or below the 4392 * requested node. SRL configuration is possible only if the 4393 * selected layer's node has single child. 4394 */ 4395 if (sel_layer == node->tx_sched_layer || 4396 ((sel_layer == node->tx_sched_layer + 1) && 4397 node->num_children == 1) || 4398 ((sel_layer == node->tx_sched_layer - 1) && 4399 (node->parent && node->parent->num_children == 1))) 4400 return ICE_SUCCESS; 4401 4402 return ICE_ERR_CFG; 4403 } 4404 4405 /** 4406 * ice_sched_save_q_bw - save queue node's BW information 4407 * @q_ctx: queue context structure 4408 * @rl_type: rate limit type min, max, or shared 4409 * @bw: bandwidth in Kbps - Kilo bits per sec 4410 * 4411 * Save BW information of queue type node for post replay use. 4412 */ 4413 static enum ice_status 4414 ice_sched_save_q_bw(struct ice_q_ctx *q_ctx, enum ice_rl_type rl_type, u32 bw) 4415 { 4416 switch (rl_type) { 4417 case ICE_MIN_BW: 4418 ice_set_clear_cir_bw(&q_ctx->bw_t_info, bw); 4419 break; 4420 case ICE_MAX_BW: 4421 ice_set_clear_eir_bw(&q_ctx->bw_t_info, bw); 4422 break; 4423 case ICE_SHARED_BW: 4424 ice_set_clear_shared_bw(&q_ctx->bw_t_info, bw); 4425 break; 4426 default: 4427 return ICE_ERR_PARAM; 4428 } 4429 return ICE_SUCCESS; 4430 } 4431 4432 /** 4433 * ice_sched_set_q_bw_lmt - sets queue BW limit 4434 * @pi: port information structure 4435 * @vsi_handle: sw VSI handle 4436 * @tc: traffic class 4437 * @q_handle: software queue handle 4438 * @rl_type: min, max, or shared 4439 * @bw: bandwidth in Kbps 4440 * 4441 * This function sets BW limit of queue scheduling node. 4442 */ 4443 static enum ice_status 4444 ice_sched_set_q_bw_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 4445 u16 q_handle, enum ice_rl_type rl_type, u32 bw) 4446 { 4447 enum ice_status status = ICE_ERR_PARAM; 4448 struct ice_sched_node *node; 4449 struct ice_q_ctx *q_ctx; 4450 4451 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4452 return ICE_ERR_PARAM; 4453 ice_acquire_lock(&pi->sched_lock); 4454 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handle); 4455 if (!q_ctx) 4456 goto exit_q_bw_lmt; 4457 node = ice_sched_find_node_by_teid(pi->root, q_ctx->q_teid); 4458 if (!node) { 4459 ice_debug(pi->hw, ICE_DBG_SCHED, "Wrong q_teid\n"); 4460 goto exit_q_bw_lmt; 4461 } 4462 4463 /* Return error if it is not a leaf node */ 4464 if (node->info.data.elem_type != ICE_AQC_ELEM_TYPE_LEAF) 4465 goto exit_q_bw_lmt; 4466 4467 /* SRL bandwidth layer selection */ 4468 if (rl_type == ICE_SHARED_BW) { 4469 u8 sel_layer; /* selected layer */ 4470 4471 sel_layer = ice_sched_get_rl_prof_layer(pi, rl_type, 4472 node->tx_sched_layer); 4473 if (sel_layer >= pi->hw->num_tx_sched_layers) { 4474 status = ICE_ERR_PARAM; 4475 goto exit_q_bw_lmt; 4476 } 4477 status = ice_sched_validate_srl_node(node, sel_layer); 4478 if (status) 4479 goto exit_q_bw_lmt; 4480 } 4481 4482 if (bw == ICE_SCHED_DFLT_BW) 4483 status = ice_sched_set_node_bw_dflt_lmt(pi, node, rl_type); 4484 else 4485 status = ice_sched_set_node_bw_lmt(pi, node, rl_type, bw); 4486 4487 if (!status) 4488 status = ice_sched_save_q_bw(q_ctx, rl_type, bw); 4489 4490 exit_q_bw_lmt: 4491 ice_release_lock(&pi->sched_lock); 4492 return status; 4493 } 4494 4495 /** 4496 * ice_cfg_q_bw_lmt - configure queue BW limit 4497 * @pi: port information structure 4498 * @vsi_handle: sw VSI handle 4499 * @tc: traffic class 4500 * @q_handle: software queue handle 4501 * @rl_type: min, max, or shared 4502 * @bw: bandwidth in Kbps 4503 * 4504 * This function configures BW limit of queue scheduling node. 4505 */ 4506 enum ice_status 4507 ice_cfg_q_bw_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 4508 u16 q_handle, enum ice_rl_type rl_type, u32 bw) 4509 { 4510 return ice_sched_set_q_bw_lmt(pi, vsi_handle, tc, q_handle, rl_type, 4511 bw); 4512 } 4513 4514 /** 4515 * ice_cfg_q_bw_dflt_lmt - configure queue BW default limit 4516 * @pi: port information structure 4517 * @vsi_handle: sw VSI handle 4518 * @tc: traffic class 4519 * @q_handle: software queue handle 4520 * @rl_type: min, max, or shared 4521 * 4522 * This function configures BW default limit of queue scheduling node. 4523 */ 4524 enum ice_status 4525 ice_cfg_q_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 4526 u16 q_handle, enum ice_rl_type rl_type) 4527 { 4528 return ice_sched_set_q_bw_lmt(pi, vsi_handle, tc, q_handle, rl_type, 4529 ICE_SCHED_DFLT_BW); 4530 } 4531 4532 /** 4533 * ice_sched_save_tc_node_bw - save TC node BW limit 4534 * @pi: port information structure 4535 * @tc: TC number 4536 * @rl_type: min or max 4537 * @bw: bandwidth in Kbps 4538 * 4539 * This function saves the modified values of bandwidth settings for later 4540 * replay purpose (restore) after reset. 4541 */ 4542 static enum ice_status 4543 ice_sched_save_tc_node_bw(struct ice_port_info *pi, u8 tc, 4544 enum ice_rl_type rl_type, u32 bw) 4545 { 4546 if (tc >= ICE_MAX_TRAFFIC_CLASS) 4547 return ICE_ERR_PARAM; 4548 switch (rl_type) { 4549 case ICE_MIN_BW: 4550 ice_set_clear_cir_bw(&pi->tc_node_bw_t_info[tc], bw); 4551 break; 4552 case ICE_MAX_BW: 4553 ice_set_clear_eir_bw(&pi->tc_node_bw_t_info[tc], bw); 4554 break; 4555 case ICE_SHARED_BW: 4556 ice_set_clear_shared_bw(&pi->tc_node_bw_t_info[tc], bw); 4557 break; 4558 default: 4559 return ICE_ERR_PARAM; 4560 } 4561 return ICE_SUCCESS; 4562 } 4563 4564 /** 4565 * ice_sched_set_tc_node_bw_lmt - sets TC node BW limit 4566 * @pi: port information structure 4567 * @tc: TC number 4568 * @rl_type: min or max 4569 * @bw: bandwidth in Kbps 4570 * 4571 * This function configures bandwidth limit of TC node. 4572 */ 4573 static enum ice_status 4574 ice_sched_set_tc_node_bw_lmt(struct ice_port_info *pi, u8 tc, 4575 enum ice_rl_type rl_type, u32 bw) 4576 { 4577 enum ice_status status = ICE_ERR_PARAM; 4578 struct ice_sched_node *tc_node; 4579 4580 if (tc >= ICE_MAX_TRAFFIC_CLASS) 4581 return status; 4582 ice_acquire_lock(&pi->sched_lock); 4583 tc_node = ice_sched_get_tc_node(pi, tc); 4584 if (!tc_node) 4585 goto exit_set_tc_node_bw; 4586 if (bw == ICE_SCHED_DFLT_BW) 4587 status = ice_sched_set_node_bw_dflt_lmt(pi, tc_node, rl_type); 4588 else 4589 status = ice_sched_set_node_bw_lmt(pi, tc_node, rl_type, bw); 4590 if (!status) 4591 status = ice_sched_save_tc_node_bw(pi, tc, rl_type, bw); 4592 4593 exit_set_tc_node_bw: 4594 ice_release_lock(&pi->sched_lock); 4595 return status; 4596 } 4597 4598 /** 4599 * ice_cfg_tc_node_bw_lmt - configure TC node BW limit 4600 * @pi: port information structure 4601 * @tc: TC number 4602 * @rl_type: min or max 4603 * @bw: bandwidth in Kbps 4604 * 4605 * This function configures BW limit of TC node. 4606 * Note: The minimum guaranteed reservation is done via DCBX. 4607 */ 4608 enum ice_status 4609 ice_cfg_tc_node_bw_lmt(struct ice_port_info *pi, u8 tc, 4610 enum ice_rl_type rl_type, u32 bw) 4611 { 4612 return ice_sched_set_tc_node_bw_lmt(pi, tc, rl_type, bw); 4613 } 4614 4615 /** 4616 * ice_cfg_tc_node_bw_dflt_lmt - configure TC node BW default limit 4617 * @pi: port information structure 4618 * @tc: TC number 4619 * @rl_type: min or max 4620 * 4621 * This function configures BW default limit of TC node. 4622 */ 4623 enum ice_status 4624 ice_cfg_tc_node_bw_dflt_lmt(struct ice_port_info *pi, u8 tc, 4625 enum ice_rl_type rl_type) 4626 { 4627 return ice_sched_set_tc_node_bw_lmt(pi, tc, rl_type, ICE_SCHED_DFLT_BW); 4628 } 4629 4630 /** 4631 * ice_sched_save_tc_node_bw_alloc - save TC node's BW alloc information 4632 * @pi: port information structure 4633 * @tc: traffic class 4634 * @rl_type: rate limit type min or max 4635 * @bw_alloc: Bandwidth allocation information 4636 * 4637 * Save BW alloc information of VSI type node for post replay use. 4638 */ 4639 static enum ice_status 4640 ice_sched_save_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc, 4641 enum ice_rl_type rl_type, u16 bw_alloc) 4642 { 4643 if (tc >= ICE_MAX_TRAFFIC_CLASS) 4644 return ICE_ERR_PARAM; 4645 switch (rl_type) { 4646 case ICE_MIN_BW: 4647 ice_set_clear_cir_bw_alloc(&pi->tc_node_bw_t_info[tc], 4648 bw_alloc); 4649 break; 4650 case ICE_MAX_BW: 4651 ice_set_clear_eir_bw_alloc(&pi->tc_node_bw_t_info[tc], 4652 bw_alloc); 4653 break; 4654 default: 4655 return ICE_ERR_PARAM; 4656 } 4657 return ICE_SUCCESS; 4658 } 4659 4660 /** 4661 * ice_sched_set_tc_node_bw_alloc - set TC node BW alloc 4662 * @pi: port information structure 4663 * @tc: TC number 4664 * @rl_type: min or max 4665 * @bw_alloc: bandwidth alloc 4666 * 4667 * This function configures bandwidth alloc of TC node, also saves the 4668 * changed settings for replay purpose, and return success if it succeeds 4669 * in modifying bandwidth alloc setting. 4670 */ 4671 static enum ice_status 4672 ice_sched_set_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc, 4673 enum ice_rl_type rl_type, u8 bw_alloc) 4674 { 4675 enum ice_status status = ICE_ERR_PARAM; 4676 struct ice_sched_node *tc_node; 4677 4678 if (tc >= ICE_MAX_TRAFFIC_CLASS) 4679 return status; 4680 ice_acquire_lock(&pi->sched_lock); 4681 tc_node = ice_sched_get_tc_node(pi, tc); 4682 if (!tc_node) 4683 goto exit_set_tc_node_bw_alloc; 4684 status = ice_sched_cfg_node_bw_alloc(pi->hw, tc_node, rl_type, 4685 bw_alloc); 4686 if (status) 4687 goto exit_set_tc_node_bw_alloc; 4688 status = ice_sched_save_tc_node_bw_alloc(pi, tc, rl_type, bw_alloc); 4689 4690 exit_set_tc_node_bw_alloc: 4691 ice_release_lock(&pi->sched_lock); 4692 return status; 4693 } 4694 4695 /** 4696 * ice_cfg_tc_node_bw_alloc - configure TC node BW alloc 4697 * @pi: port information structure 4698 * @tc: TC number 4699 * @rl_type: min or max 4700 * @bw_alloc: bandwidth alloc 4701 * 4702 * This function configures BW limit of TC node. 4703 * Note: The minimum guaranteed reservation is done via DCBX. 4704 */ 4705 enum ice_status 4706 ice_cfg_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc, 4707 enum ice_rl_type rl_type, u8 bw_alloc) 4708 { 4709 return ice_sched_set_tc_node_bw_alloc(pi, tc, rl_type, bw_alloc); 4710 } 4711 4712 /** 4713 * ice_sched_set_agg_bw_dflt_lmt - set aggregator node's BW limit to default 4714 * @pi: port information structure 4715 * @vsi_handle: software VSI handle 4716 * 4717 * This function retrieves the aggregator ID based on VSI ID and TC, 4718 * and sets node's BW limit to default. This function needs to be 4719 * called with the scheduler lock held. 4720 */ 4721 enum ice_status 4722 ice_sched_set_agg_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle) 4723 { 4724 struct ice_vsi_ctx *vsi_ctx; 4725 enum ice_status status = ICE_SUCCESS; 4726 u8 tc; 4727 4728 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4729 return ICE_ERR_PARAM; 4730 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 4731 if (!vsi_ctx) 4732 return ICE_ERR_PARAM; 4733 4734 ice_for_each_traffic_class(tc) { 4735 struct ice_sched_node *node; 4736 4737 node = vsi_ctx->sched.ag_node[tc]; 4738 if (!node) 4739 continue; 4740 4741 /* Set min profile to default */ 4742 status = ice_sched_set_node_bw_dflt_lmt(pi, node, ICE_MIN_BW); 4743 if (status) 4744 break; 4745 4746 /* Set max profile to default */ 4747 status = ice_sched_set_node_bw_dflt_lmt(pi, node, ICE_MAX_BW); 4748 if (status) 4749 break; 4750 4751 /* Remove shared profile, if there is one */ 4752 status = ice_sched_set_node_bw_dflt_lmt(pi, node, 4753 ICE_SHARED_BW); 4754 if (status) 4755 break; 4756 } 4757 4758 return status; 4759 } 4760 4761 /** 4762 * ice_sched_get_node_by_id_type - get node from ID type 4763 * @pi: port information structure 4764 * @id: identifier 4765 * @agg_type: type of aggregator 4766 * @tc: traffic class 4767 * 4768 * This function returns node identified by ID of type aggregator, and 4769 * based on traffic class (TC). This function needs to be called with 4770 * the scheduler lock held. 4771 */ 4772 static struct ice_sched_node * 4773 ice_sched_get_node_by_id_type(struct ice_port_info *pi, u32 id, 4774 enum ice_agg_type agg_type, u8 tc) 4775 { 4776 struct ice_sched_node *node = NULL; 4777 struct ice_sched_node *child_node; 4778 4779 switch (agg_type) { 4780 case ICE_AGG_TYPE_VSI: { 4781 struct ice_vsi_ctx *vsi_ctx; 4782 u16 vsi_handle = (u16)id; 4783 4784 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4785 break; 4786 /* Get sched_vsi_info */ 4787 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 4788 if (!vsi_ctx) 4789 break; 4790 node = vsi_ctx->sched.vsi_node[tc]; 4791 break; 4792 } 4793 4794 case ICE_AGG_TYPE_AGG: { 4795 struct ice_sched_node *tc_node; 4796 4797 tc_node = ice_sched_get_tc_node(pi, tc); 4798 if (tc_node) 4799 node = ice_sched_get_agg_node(pi, tc_node, id); 4800 break; 4801 } 4802 4803 case ICE_AGG_TYPE_Q: 4804 /* The current implementation allows single queue to modify */ 4805 node = ice_sched_get_node(pi, id); 4806 break; 4807 4808 case ICE_AGG_TYPE_QG: 4809 /* The current implementation allows single qg to modify */ 4810 child_node = ice_sched_get_node(pi, id); 4811 if (!child_node) 4812 break; 4813 node = child_node->parent; 4814 break; 4815 4816 default: 4817 break; 4818 } 4819 4820 return node; 4821 } 4822 4823 /** 4824 * ice_sched_set_node_bw_lmt_per_tc - set node BW limit per TC 4825 * @pi: port information structure 4826 * @id: ID (software VSI handle or AGG ID) 4827 * @agg_type: aggregator type (VSI or AGG type node) 4828 * @tc: traffic class 4829 * @rl_type: min or max 4830 * @bw: bandwidth in Kbps 4831 * 4832 * This function sets BW limit of VSI or Aggregator scheduling node 4833 * based on TC information from passed in argument BW. 4834 */ 4835 enum ice_status 4836 ice_sched_set_node_bw_lmt_per_tc(struct ice_port_info *pi, u32 id, 4837 enum ice_agg_type agg_type, u8 tc, 4838 enum ice_rl_type rl_type, u32 bw) 4839 { 4840 enum ice_status status = ICE_ERR_PARAM; 4841 struct ice_sched_node *node; 4842 4843 if (!pi) 4844 return status; 4845 4846 if (rl_type == ICE_UNKNOWN_BW) 4847 return status; 4848 4849 ice_acquire_lock(&pi->sched_lock); 4850 node = ice_sched_get_node_by_id_type(pi, id, agg_type, tc); 4851 if (!node) { 4852 ice_debug(pi->hw, ICE_DBG_SCHED, "Wrong id, agg type, or tc\n"); 4853 goto exit_set_node_bw_lmt_per_tc; 4854 } 4855 if (bw == ICE_SCHED_DFLT_BW) 4856 status = ice_sched_set_node_bw_dflt_lmt(pi, node, rl_type); 4857 else 4858 status = ice_sched_set_node_bw_lmt(pi, node, rl_type, bw); 4859 4860 exit_set_node_bw_lmt_per_tc: 4861 ice_release_lock(&pi->sched_lock); 4862 return status; 4863 } 4864 4865 /** 4866 * ice_sched_validate_vsi_srl_node - validate VSI SRL node 4867 * @pi: port information structure 4868 * @vsi_handle: software VSI handle 4869 * 4870 * This function validates SRL node of the VSI node if available SRL layer is 4871 * different than the VSI node layer on all TC(s).This function needs to be 4872 * called with scheduler lock held. 4873 */ 4874 static enum ice_status 4875 ice_sched_validate_vsi_srl_node(struct ice_port_info *pi, u16 vsi_handle) 4876 { 4877 u8 sel_layer = ICE_SCHED_INVAL_LAYER_NUM; 4878 u8 tc; 4879 4880 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4881 return ICE_ERR_PARAM; 4882 4883 /* Return success if no nodes are present across TC */ 4884 ice_for_each_traffic_class(tc) { 4885 struct ice_sched_node *tc_node, *vsi_node; 4886 enum ice_rl_type rl_type = ICE_SHARED_BW; 4887 enum ice_status status; 4888 4889 tc_node = ice_sched_get_tc_node(pi, tc); 4890 if (!tc_node) 4891 continue; 4892 4893 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 4894 if (!vsi_node) 4895 continue; 4896 4897 /* SRL bandwidth layer selection */ 4898 if (sel_layer == ICE_SCHED_INVAL_LAYER_NUM) { 4899 u8 node_layer = vsi_node->tx_sched_layer; 4900 u8 layer_num; 4901 4902 layer_num = ice_sched_get_rl_prof_layer(pi, rl_type, 4903 node_layer); 4904 if (layer_num >= pi->hw->num_tx_sched_layers) 4905 return ICE_ERR_PARAM; 4906 sel_layer = layer_num; 4907 } 4908 4909 status = ice_sched_validate_srl_node(vsi_node, sel_layer); 4910 if (status) 4911 return status; 4912 } 4913 return ICE_SUCCESS; 4914 } 4915 4916 /** 4917 * ice_sched_set_save_vsi_srl_node_bw - set VSI shared limit values 4918 * @pi: port information structure 4919 * @vsi_handle: software VSI handle 4920 * @tc: traffic class 4921 * @srl_node: sched node to configure 4922 * @rl_type: rate limit type minimum, maximum, or shared 4923 * @bw: minimum, maximum, or shared bandwidth in Kbps 4924 * 4925 * Configure shared rate limiter(SRL) of VSI type nodes across given traffic 4926 * class, and saves those value for later use for replaying purposes. The 4927 * caller holds the scheduler lock. 4928 */ 4929 static enum ice_status 4930 ice_sched_set_save_vsi_srl_node_bw(struct ice_port_info *pi, u16 vsi_handle, 4931 u8 tc, struct ice_sched_node *srl_node, 4932 enum ice_rl_type rl_type, u32 bw) 4933 { 4934 enum ice_status status; 4935 4936 if (bw == ICE_SCHED_DFLT_BW) { 4937 status = ice_sched_set_node_bw_dflt_lmt(pi, srl_node, rl_type); 4938 } else { 4939 status = ice_sched_set_node_bw_lmt(pi, srl_node, rl_type, bw); 4940 if (status) 4941 return status; 4942 status = ice_sched_save_vsi_bw(pi, vsi_handle, tc, rl_type, bw); 4943 } 4944 return status; 4945 } 4946 4947 /** 4948 * ice_sched_set_vsi_node_srl_per_tc - set VSI node BW shared limit for tc 4949 * @pi: port information structure 4950 * @vsi_handle: software VSI handle 4951 * @tc: traffic class 4952 * @min_bw: minimum bandwidth in Kbps 4953 * @max_bw: maximum bandwidth in Kbps 4954 * @shared_bw: shared bandwidth in Kbps 4955 * 4956 * Configure shared rate limiter(SRL) of VSI type nodes across requested 4957 * traffic class for VSI matching handle. When BW value of ICE_SCHED_DFLT_BW 4958 * is passed, it removes the corresponding bw from the node. The caller 4959 * holds scheduler lock. 4960 */ 4961 static enum ice_status 4962 ice_sched_set_vsi_node_srl_per_tc(struct ice_port_info *pi, u16 vsi_handle, 4963 u8 tc, u32 min_bw, u32 max_bw, u32 shared_bw) 4964 { 4965 struct ice_sched_node *tc_node, *vsi_node, *cfg_node; 4966 enum ice_status status; 4967 u8 layer_num; 4968 4969 tc_node = ice_sched_get_tc_node(pi, tc); 4970 if (!tc_node) 4971 return ICE_ERR_CFG; 4972 4973 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 4974 if (!vsi_node) 4975 return ICE_ERR_CFG; 4976 4977 layer_num = ice_sched_get_rl_prof_layer(pi, ICE_SHARED_BW, 4978 vsi_node->tx_sched_layer); 4979 if (layer_num >= pi->hw->num_tx_sched_layers) 4980 return ICE_ERR_PARAM; 4981 4982 /* SRL node may be different */ 4983 cfg_node = ice_sched_get_srl_node(vsi_node, layer_num); 4984 if (!cfg_node) 4985 return ICE_ERR_CFG; 4986 4987 status = ice_sched_set_save_vsi_srl_node_bw(pi, vsi_handle, tc, 4988 cfg_node, ICE_MIN_BW, 4989 min_bw); 4990 if (status) 4991 return status; 4992 4993 status = ice_sched_set_save_vsi_srl_node_bw(pi, vsi_handle, tc, 4994 cfg_node, ICE_MAX_BW, 4995 max_bw); 4996 if (status) 4997 return status; 4998 4999 return ice_sched_set_save_vsi_srl_node_bw(pi, vsi_handle, tc, cfg_node, 5000 ICE_SHARED_BW, shared_bw); 5001 } 5002 5003 /** 5004 * ice_sched_set_vsi_bw_shared_lmt - set VSI BW shared limit 5005 * @pi: port information structure 5006 * @vsi_handle: software VSI handle 5007 * @min_bw: minimum bandwidth in Kbps 5008 * @max_bw: maximum bandwidth in Kbps 5009 * @shared_bw: shared bandwidth in Kbps 5010 * 5011 * Configure shared rate limiter(SRL) of all VSI type nodes across all traffic 5012 * classes for VSI matching handle. When BW value of ICE_SCHED_DFLT_BW is 5013 * passed, it removes those value(s) from the node. 5014 */ 5015 enum ice_status 5016 ice_sched_set_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle, 5017 u32 min_bw, u32 max_bw, u32 shared_bw) 5018 { 5019 enum ice_status status = ICE_SUCCESS; 5020 u8 tc; 5021 5022 if (!pi) 5023 return ICE_ERR_PARAM; 5024 5025 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 5026 return ICE_ERR_PARAM; 5027 5028 ice_acquire_lock(&pi->sched_lock); 5029 status = ice_sched_validate_vsi_srl_node(pi, vsi_handle); 5030 if (status) 5031 goto exit_set_vsi_bw_shared_lmt; 5032 /* Return success if no nodes are present across TC */ 5033 ice_for_each_traffic_class(tc) { 5034 struct ice_sched_node *tc_node, *vsi_node; 5035 5036 tc_node = ice_sched_get_tc_node(pi, tc); 5037 if (!tc_node) 5038 continue; 5039 5040 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 5041 if (!vsi_node) 5042 continue; 5043 5044 status = ice_sched_set_vsi_node_srl_per_tc(pi, vsi_handle, tc, 5045 min_bw, max_bw, 5046 shared_bw); 5047 if (status) 5048 break; 5049 } 5050 5051 exit_set_vsi_bw_shared_lmt: 5052 ice_release_lock(&pi->sched_lock); 5053 return status; 5054 } 5055 5056 /** 5057 * ice_sched_validate_agg_srl_node - validate AGG SRL node 5058 * @pi: port information structure 5059 * @agg_id: aggregator ID 5060 * 5061 * This function validates SRL node of the AGG node if available SRL layer is 5062 * different than the AGG node layer on all TC(s).This function needs to be 5063 * called with scheduler lock held. 5064 */ 5065 static enum ice_status 5066 ice_sched_validate_agg_srl_node(struct ice_port_info *pi, u32 agg_id) 5067 { 5068 u8 sel_layer = ICE_SCHED_INVAL_LAYER_NUM; 5069 struct ice_sched_agg_info *agg_info; 5070 bool agg_id_present = false; 5071 enum ice_status status = ICE_SUCCESS; 5072 u8 tc; 5073 5074 LIST_FOR_EACH_ENTRY(agg_info, &pi->hw->agg_list, ice_sched_agg_info, 5075 list_entry) 5076 if (agg_info->agg_id == agg_id) { 5077 agg_id_present = true; 5078 break; 5079 } 5080 if (!agg_id_present) 5081 return ICE_ERR_PARAM; 5082 /* Return success if no nodes are present across TC */ 5083 ice_for_each_traffic_class(tc) { 5084 struct ice_sched_node *tc_node, *agg_node; 5085 enum ice_rl_type rl_type = ICE_SHARED_BW; 5086 5087 tc_node = ice_sched_get_tc_node(pi, tc); 5088 if (!tc_node) 5089 continue; 5090 5091 agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); 5092 if (!agg_node) 5093 continue; 5094 /* SRL bandwidth layer selection */ 5095 if (sel_layer == ICE_SCHED_INVAL_LAYER_NUM) { 5096 u8 node_layer = agg_node->tx_sched_layer; 5097 u8 layer_num; 5098 5099 layer_num = ice_sched_get_rl_prof_layer(pi, rl_type, 5100 node_layer); 5101 if (layer_num >= pi->hw->num_tx_sched_layers) 5102 return ICE_ERR_PARAM; 5103 sel_layer = layer_num; 5104 } 5105 5106 status = ice_sched_validate_srl_node(agg_node, sel_layer); 5107 if (status) 5108 break; 5109 } 5110 return status; 5111 } 5112 5113 /** 5114 * ice_sched_validate_agg_id - Validate aggregator id 5115 * @pi: port information structure 5116 * @agg_id: aggregator ID 5117 * 5118 * This function validates aggregator id. Caller holds the scheduler lock. 5119 */ 5120 static enum ice_status 5121 ice_sched_validate_agg_id(struct ice_port_info *pi, u32 agg_id) 5122 { 5123 struct ice_sched_agg_info *agg_info; 5124 struct ice_sched_agg_info *tmp; 5125 bool agg_id_present = false; 5126 enum ice_status status; 5127 5128 status = ice_sched_validate_agg_srl_node(pi, agg_id); 5129 if (status) 5130 return status; 5131 5132 LIST_FOR_EACH_ENTRY_SAFE(agg_info, tmp, &pi->hw->agg_list, 5133 ice_sched_agg_info, list_entry) 5134 if (agg_info->agg_id == agg_id) { 5135 agg_id_present = true; 5136 break; 5137 } 5138 5139 if (!agg_id_present) 5140 return ICE_ERR_PARAM; 5141 5142 return ICE_SUCCESS; 5143 } 5144 5145 /** 5146 * ice_sched_set_save_agg_srl_node_bw - set aggregator shared limit values 5147 * @pi: port information structure 5148 * @agg_id: aggregator ID 5149 * @tc: traffic class 5150 * @srl_node: sched node to configure 5151 * @rl_type: rate limit type minimum, maximum, or shared 5152 * @bw: minimum, maximum, or shared bandwidth in Kbps 5153 * 5154 * Configure shared rate limiter(SRL) of aggregator type nodes across 5155 * requested traffic class, and saves those value for later use for 5156 * replaying purposes. The caller holds the scheduler lock. 5157 */ 5158 static enum ice_status 5159 ice_sched_set_save_agg_srl_node_bw(struct ice_port_info *pi, u32 agg_id, u8 tc, 5160 struct ice_sched_node *srl_node, 5161 enum ice_rl_type rl_type, u32 bw) 5162 { 5163 enum ice_status status; 5164 5165 if (bw == ICE_SCHED_DFLT_BW) { 5166 status = ice_sched_set_node_bw_dflt_lmt(pi, srl_node, rl_type); 5167 } else { 5168 status = ice_sched_set_node_bw_lmt(pi, srl_node, rl_type, bw); 5169 if (status) 5170 return status; 5171 status = ice_sched_save_agg_bw(pi, agg_id, tc, rl_type, bw); 5172 } 5173 return status; 5174 } 5175 5176 /** 5177 * ice_sched_set_agg_node_srl_per_tc - set aggregator SRL per tc 5178 * @pi: port information structure 5179 * @agg_id: aggregator ID 5180 * @tc: traffic class 5181 * @min_bw: minimum bandwidth in Kbps 5182 * @max_bw: maximum bandwidth in Kbps 5183 * @shared_bw: shared bandwidth in Kbps 5184 * 5185 * This function configures the shared rate limiter(SRL) of aggregator type 5186 * node for a given traffic class for aggregator matching agg_id. When BW 5187 * value of ICE_SCHED_DFLT_BW is passed, it removes SRL from the node. Caller 5188 * holds the scheduler lock. 5189 */ 5190 static enum ice_status 5191 ice_sched_set_agg_node_srl_per_tc(struct ice_port_info *pi, u32 agg_id, 5192 u8 tc, u32 min_bw, u32 max_bw, u32 shared_bw) 5193 { 5194 struct ice_sched_node *tc_node, *agg_node, *cfg_node; 5195 enum ice_rl_type rl_type = ICE_SHARED_BW; 5196 enum ice_status status = ICE_ERR_CFG; 5197 u8 layer_num; 5198 5199 tc_node = ice_sched_get_tc_node(pi, tc); 5200 if (!tc_node) 5201 return ICE_ERR_CFG; 5202 5203 agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); 5204 if (!agg_node) 5205 return ICE_ERR_CFG; 5206 5207 layer_num = ice_sched_get_rl_prof_layer(pi, rl_type, 5208 agg_node->tx_sched_layer); 5209 if (layer_num >= pi->hw->num_tx_sched_layers) 5210 return ICE_ERR_PARAM; 5211 5212 /* SRL node may be different */ 5213 cfg_node = ice_sched_get_srl_node(agg_node, layer_num); 5214 if (!cfg_node) 5215 return ICE_ERR_CFG; 5216 5217 status = ice_sched_set_save_agg_srl_node_bw(pi, agg_id, tc, cfg_node, 5218 ICE_MIN_BW, min_bw); 5219 if (status) 5220 return status; 5221 5222 status = ice_sched_set_save_agg_srl_node_bw(pi, agg_id, tc, cfg_node, 5223 ICE_MAX_BW, max_bw); 5224 if (status) 5225 return status; 5226 5227 status = ice_sched_set_save_agg_srl_node_bw(pi, agg_id, tc, cfg_node, 5228 ICE_SHARED_BW, shared_bw); 5229 return status; 5230 } 5231 5232 /** 5233 * ice_sched_set_agg_bw_shared_lmt - set aggregator BW shared limit 5234 * @pi: port information structure 5235 * @agg_id: aggregator ID 5236 * @min_bw: minimum bandwidth in Kbps 5237 * @max_bw: maximum bandwidth in Kbps 5238 * @shared_bw: shared bandwidth in Kbps 5239 * 5240 * This function configures the shared rate limiter(SRL) of all aggregator type 5241 * nodes across all traffic classes for aggregator matching agg_id. When 5242 * BW value of ICE_SCHED_DFLT_BW is passed, it removes SRL from the 5243 * node(s). 5244 */ 5245 enum ice_status 5246 ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, 5247 u32 min_bw, u32 max_bw, u32 shared_bw) 5248 { 5249 enum ice_status status; 5250 u8 tc; 5251 5252 if (!pi) 5253 return ICE_ERR_PARAM; 5254 5255 ice_acquire_lock(&pi->sched_lock); 5256 status = ice_sched_validate_agg_id(pi, agg_id); 5257 if (status) 5258 goto exit_agg_bw_shared_lmt; 5259 5260 /* Return success if no nodes are present across TC */ 5261 ice_for_each_traffic_class(tc) { 5262 struct ice_sched_node *tc_node, *agg_node; 5263 5264 tc_node = ice_sched_get_tc_node(pi, tc); 5265 if (!tc_node) 5266 continue; 5267 5268 agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); 5269 if (!agg_node) 5270 continue; 5271 5272 status = ice_sched_set_agg_node_srl_per_tc(pi, agg_id, tc, 5273 min_bw, max_bw, 5274 shared_bw); 5275 if (status) 5276 break; 5277 } 5278 5279 exit_agg_bw_shared_lmt: 5280 ice_release_lock(&pi->sched_lock); 5281 return status; 5282 } 5283 5284 /** 5285 * ice_sched_set_agg_bw_shared_lmt_per_tc - set aggregator BW shared lmt per tc 5286 * @pi: port information structure 5287 * @agg_id: aggregator ID 5288 * @tc: traffic class 5289 * @min_bw: minimum bandwidth in Kbps 5290 * @max_bw: maximum bandwidth in Kbps 5291 * @shared_bw: shared bandwidth in Kbps 5292 * 5293 * This function configures the shared rate limiter(SRL) of aggregator type 5294 * node for a given traffic class for aggregator matching agg_id. When BW 5295 * value of ICE_SCHED_DFLT_BW is passed, it removes SRL from the node. 5296 */ 5297 enum ice_status 5298 ice_sched_set_agg_bw_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, 5299 u8 tc, u32 min_bw, u32 max_bw, 5300 u32 shared_bw) 5301 { 5302 enum ice_status status; 5303 5304 if (!pi) 5305 return ICE_ERR_PARAM; 5306 ice_acquire_lock(&pi->sched_lock); 5307 status = ice_sched_validate_agg_id(pi, agg_id); 5308 if (status) 5309 goto exit_agg_bw_shared_lmt_per_tc; 5310 5311 status = ice_sched_set_agg_node_srl_per_tc(pi, agg_id, tc, min_bw, 5312 max_bw, shared_bw); 5313 5314 exit_agg_bw_shared_lmt_per_tc: 5315 ice_release_lock(&pi->sched_lock); 5316 return status; 5317 } 5318 5319 /** 5320 * ice_sched_cfg_sibl_node_prio - configure node sibling priority 5321 * @pi: port information structure 5322 * @node: sched node to configure 5323 * @priority: sibling priority 5324 * 5325 * This function configures node element's sibling priority only. This 5326 * function needs to be called with scheduler lock held. 5327 */ 5328 enum ice_status 5329 ice_sched_cfg_sibl_node_prio(struct ice_port_info *pi, 5330 struct ice_sched_node *node, u8 priority) 5331 { 5332 struct ice_aqc_txsched_elem_data buf; 5333 struct ice_aqc_txsched_elem *data; 5334 struct ice_hw *hw = pi->hw; 5335 enum ice_status status; 5336 5337 if (!hw) 5338 return ICE_ERR_PARAM; 5339 buf = node->info; 5340 data = &buf.data; 5341 data->valid_sections |= ICE_AQC_ELEM_VALID_GENERIC; 5342 priority = (priority << ICE_AQC_ELEM_GENERIC_PRIO_S) & 5343 ICE_AQC_ELEM_GENERIC_PRIO_M; 5344 data->generic &= ~ICE_AQC_ELEM_GENERIC_PRIO_M; 5345 data->generic |= priority; 5346 5347 /* Configure element */ 5348 status = ice_sched_update_elem(hw, node, &buf); 5349 return status; 5350 } 5351 5352 /** 5353 * ice_cfg_rl_burst_size - Set burst size value 5354 * @hw: pointer to the HW struct 5355 * @bytes: burst size in bytes 5356 * 5357 * This function configures/set the burst size to requested new value. The new 5358 * burst size value is used for future rate limit calls. It doesn't change the 5359 * existing or previously created RL profiles. 5360 */ 5361 enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes) 5362 { 5363 u16 burst_size_to_prog; 5364 5365 if (bytes < ICE_MIN_BURST_SIZE_ALLOWED || 5366 bytes > ICE_MAX_BURST_SIZE_ALLOWED) 5367 return ICE_ERR_PARAM; 5368 if (ice_round_to_num(bytes, 64) <= 5369 ICE_MAX_BURST_SIZE_64_BYTE_GRANULARITY) { 5370 /* 64 byte granularity case */ 5371 /* Disable MSB granularity bit */ 5372 burst_size_to_prog = ICE_64_BYTE_GRANULARITY; 5373 /* round number to nearest 64 byte granularity */ 5374 bytes = ice_round_to_num(bytes, 64); 5375 /* The value is in 64 byte chunks */ 5376 burst_size_to_prog |= (u16)(bytes / 64); 5377 } else { 5378 /* k bytes granularity case */ 5379 /* Enable MSB granularity bit */ 5380 burst_size_to_prog = ICE_KBYTE_GRANULARITY; 5381 /* round number to nearest 1024 granularity */ 5382 bytes = ice_round_to_num(bytes, 1024); 5383 /* check rounding doesn't go beyond allowed */ 5384 if (bytes > ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY) 5385 bytes = ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY; 5386 /* The value is in k bytes */ 5387 burst_size_to_prog |= (u16)(bytes / 1024); 5388 } 5389 hw->max_burst_size = burst_size_to_prog; 5390 return ICE_SUCCESS; 5391 } 5392 5393 /** 5394 * ice_sched_replay_node_prio - re-configure node priority 5395 * @hw: pointer to the HW struct 5396 * @node: sched node to configure 5397 * @priority: priority value 5398 * 5399 * This function configures node element's priority value. It 5400 * needs to be called with scheduler lock held. 5401 */ 5402 static enum ice_status 5403 ice_sched_replay_node_prio(struct ice_hw *hw, struct ice_sched_node *node, 5404 u8 priority) 5405 { 5406 struct ice_aqc_txsched_elem_data buf; 5407 struct ice_aqc_txsched_elem *data; 5408 enum ice_status status; 5409 5410 buf = node->info; 5411 data = &buf.data; 5412 data->valid_sections |= ICE_AQC_ELEM_VALID_GENERIC; 5413 data->generic = priority; 5414 5415 /* Configure element */ 5416 status = ice_sched_update_elem(hw, node, &buf); 5417 return status; 5418 } 5419 5420 /** 5421 * ice_sched_replay_node_bw - replay node(s) BW 5422 * @hw: pointer to the HW struct 5423 * @node: sched node to configure 5424 * @bw_t_info: BW type information 5425 * 5426 * This function restores node's BW from bw_t_info. The caller needs 5427 * to hold the scheduler lock. 5428 */ 5429 static enum ice_status 5430 ice_sched_replay_node_bw(struct ice_hw *hw, struct ice_sched_node *node, 5431 struct ice_bw_type_info *bw_t_info) 5432 { 5433 struct ice_port_info *pi = hw->port_info; 5434 enum ice_status status = ICE_ERR_PARAM; 5435 u16 bw_alloc; 5436 5437 if (!node) 5438 return status; 5439 if (!ice_is_any_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_CNT)) 5440 return ICE_SUCCESS; 5441 if (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_PRIO)) { 5442 status = ice_sched_replay_node_prio(hw, node, 5443 bw_t_info->generic); 5444 if (status) 5445 return status; 5446 } 5447 if (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_CIR)) { 5448 status = ice_sched_set_node_bw_lmt(pi, node, ICE_MIN_BW, 5449 bw_t_info->cir_bw.bw); 5450 if (status) 5451 return status; 5452 } 5453 if (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_CIR_WT)) { 5454 bw_alloc = bw_t_info->cir_bw.bw_alloc; 5455 status = ice_sched_cfg_node_bw_alloc(hw, node, ICE_MIN_BW, 5456 bw_alloc); 5457 if (status) 5458 return status; 5459 } 5460 if (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_EIR)) { 5461 status = ice_sched_set_node_bw_lmt(pi, node, ICE_MAX_BW, 5462 bw_t_info->eir_bw.bw); 5463 if (status) 5464 return status; 5465 } 5466 if (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_EIR_WT)) { 5467 bw_alloc = bw_t_info->eir_bw.bw_alloc; 5468 status = ice_sched_cfg_node_bw_alloc(hw, node, ICE_MAX_BW, 5469 bw_alloc); 5470 if (status) 5471 return status; 5472 } 5473 if (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_SHARED)) 5474 status = ice_sched_set_node_bw_lmt(pi, node, ICE_SHARED_BW, 5475 bw_t_info->shared_bw); 5476 return status; 5477 } 5478 5479 /** 5480 * ice_sched_replay_agg_bw - replay aggregator node(s) BW 5481 * @hw: pointer to the HW struct 5482 * @agg_info: aggregator data structure 5483 * 5484 * This function re-creates aggregator type nodes. The caller needs to hold 5485 * the scheduler lock. 5486 */ 5487 static enum ice_status 5488 ice_sched_replay_agg_bw(struct ice_hw *hw, struct ice_sched_agg_info *agg_info) 5489 { 5490 struct ice_sched_node *tc_node, *agg_node; 5491 enum ice_status status = ICE_SUCCESS; 5492 u8 tc; 5493 5494 if (!agg_info) 5495 return ICE_ERR_PARAM; 5496 ice_for_each_traffic_class(tc) { 5497 if (!ice_is_any_bit_set(agg_info->bw_t_info[tc].bw_t_bitmap, 5498 ICE_BW_TYPE_CNT)) 5499 continue; 5500 tc_node = ice_sched_get_tc_node(hw->port_info, tc); 5501 if (!tc_node) { 5502 status = ICE_ERR_PARAM; 5503 break; 5504 } 5505 agg_node = ice_sched_get_agg_node(hw->port_info, tc_node, 5506 agg_info->agg_id); 5507 if (!agg_node) { 5508 status = ICE_ERR_PARAM; 5509 break; 5510 } 5511 status = ice_sched_replay_node_bw(hw, agg_node, 5512 &agg_info->bw_t_info[tc]); 5513 if (status) 5514 break; 5515 } 5516 return status; 5517 } 5518 5519 /** 5520 * ice_sched_get_ena_tc_bitmap - get enabled TC bitmap 5521 * @pi: port info struct 5522 * @tc_bitmap: 8 bits TC bitmap to check 5523 * @ena_tc_bitmap: 8 bits enabled TC bitmap to return 5524 * 5525 * This function returns enabled TC bitmap in variable ena_tc_bitmap. Some TCs 5526 * may be missing, it returns enabled TCs. This function needs to be called with 5527 * scheduler lock held. 5528 */ 5529 static void 5530 ice_sched_get_ena_tc_bitmap(struct ice_port_info *pi, ice_bitmap_t *tc_bitmap, 5531 ice_bitmap_t *ena_tc_bitmap) 5532 { 5533 u8 tc; 5534 5535 /* Some TC(s) may be missing after reset, adjust for replay */ 5536 ice_for_each_traffic_class(tc) 5537 if (ice_is_tc_ena(*tc_bitmap, tc) && 5538 (ice_sched_get_tc_node(pi, tc))) 5539 ice_set_bit(tc, ena_tc_bitmap); 5540 } 5541 5542 /** 5543 * ice_sched_replay_agg - recreate aggregator node(s) 5544 * @hw: pointer to the HW struct 5545 * 5546 * This function recreate aggregator type nodes which are not replayed earlier. 5547 * It also replay aggregator BW information. These aggregator nodes are not 5548 * associated with VSI type node yet. 5549 */ 5550 void ice_sched_replay_agg(struct ice_hw *hw) 5551 { 5552 struct ice_port_info *pi = hw->port_info; 5553 struct ice_sched_agg_info *agg_info; 5554 5555 ice_acquire_lock(&pi->sched_lock); 5556 LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info, 5557 list_entry) 5558 /* replay aggregator (re-create aggregator node) */ 5559 if (!ice_cmp_bitmap(agg_info->tc_bitmap, 5560 agg_info->replay_tc_bitmap, 5561 ICE_MAX_TRAFFIC_CLASS)) { 5562 ice_declare_bitmap(replay_bitmap, 5563 ICE_MAX_TRAFFIC_CLASS); 5564 enum ice_status status; 5565 5566 ice_zero_bitmap(replay_bitmap, ICE_MAX_TRAFFIC_CLASS); 5567 ice_sched_get_ena_tc_bitmap(pi, 5568 agg_info->replay_tc_bitmap, 5569 replay_bitmap); 5570 status = ice_sched_cfg_agg(hw->port_info, 5571 agg_info->agg_id, 5572 ICE_AGG_TYPE_AGG, 5573 replay_bitmap); 5574 if (status) { 5575 ice_info(hw, "Replay agg id[%d] failed\n", 5576 agg_info->agg_id); 5577 /* Move on to next one */ 5578 continue; 5579 } 5580 /* Replay aggregator node BW (restore aggregator BW) */ 5581 status = ice_sched_replay_agg_bw(hw, agg_info); 5582 if (status) 5583 ice_info(hw, "Replay agg bw [id=%d] failed\n", 5584 agg_info->agg_id); 5585 } 5586 ice_release_lock(&pi->sched_lock); 5587 } 5588 5589 /** 5590 * ice_sched_replay_agg_vsi_preinit - Agg/VSI replay pre initialization 5591 * @hw: pointer to the HW struct 5592 * 5593 * This function initialize aggregator(s) TC bitmap to zero. A required 5594 * preinit step for replaying aggregators. 5595 */ 5596 void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw) 5597 { 5598 struct ice_port_info *pi = hw->port_info; 5599 struct ice_sched_agg_info *agg_info; 5600 5601 ice_acquire_lock(&pi->sched_lock); 5602 LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info, 5603 list_entry) { 5604 struct ice_sched_agg_vsi_info *agg_vsi_info; 5605 5606 agg_info->tc_bitmap[0] = 0; 5607 LIST_FOR_EACH_ENTRY(agg_vsi_info, &agg_info->agg_vsi_list, 5608 ice_sched_agg_vsi_info, list_entry) 5609 agg_vsi_info->tc_bitmap[0] = 0; 5610 } 5611 ice_release_lock(&pi->sched_lock); 5612 } 5613 5614 /** 5615 * ice_sched_replay_root_node_bw - replay root node BW 5616 * @pi: port information structure 5617 * 5618 * Replay root node BW settings. 5619 */ 5620 enum ice_status ice_sched_replay_root_node_bw(struct ice_port_info *pi) 5621 { 5622 enum ice_status status = ICE_SUCCESS; 5623 5624 if (!pi->hw) 5625 return ICE_ERR_PARAM; 5626 ice_acquire_lock(&pi->sched_lock); 5627 5628 status = ice_sched_replay_node_bw(pi->hw, pi->root, 5629 &pi->root_node_bw_t_info); 5630 ice_release_lock(&pi->sched_lock); 5631 return status; 5632 } 5633 5634 /** 5635 * ice_sched_replay_tc_node_bw - replay TC node(s) BW 5636 * @pi: port information structure 5637 * 5638 * This function replay TC nodes. 5639 */ 5640 enum ice_status ice_sched_replay_tc_node_bw(struct ice_port_info *pi) 5641 { 5642 enum ice_status status = ICE_SUCCESS; 5643 u8 tc; 5644 5645 if (!pi->hw) 5646 return ICE_ERR_PARAM; 5647 ice_acquire_lock(&pi->sched_lock); 5648 ice_for_each_traffic_class(tc) { 5649 struct ice_sched_node *tc_node; 5650 5651 tc_node = ice_sched_get_tc_node(pi, tc); 5652 if (!tc_node) 5653 continue; /* TC not present */ 5654 status = ice_sched_replay_node_bw(pi->hw, tc_node, 5655 &pi->tc_node_bw_t_info[tc]); 5656 if (status) 5657 break; 5658 } 5659 ice_release_lock(&pi->sched_lock); 5660 return status; 5661 } 5662 5663 /** 5664 * ice_sched_replay_vsi_bw - replay VSI type node(s) BW 5665 * @hw: pointer to the HW struct 5666 * @vsi_handle: software VSI handle 5667 * @tc_bitmap: 8 bits TC bitmap 5668 * 5669 * This function replays VSI type nodes bandwidth. This function needs to be 5670 * called with scheduler lock held. 5671 */ 5672 static enum ice_status 5673 ice_sched_replay_vsi_bw(struct ice_hw *hw, u16 vsi_handle, 5674 ice_bitmap_t *tc_bitmap) 5675 { 5676 struct ice_sched_node *vsi_node, *tc_node; 5677 struct ice_port_info *pi = hw->port_info; 5678 struct ice_bw_type_info *bw_t_info; 5679 struct ice_vsi_ctx *vsi_ctx; 5680 enum ice_status status = ICE_SUCCESS; 5681 u8 tc; 5682 5683 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 5684 if (!vsi_ctx) 5685 return ICE_ERR_PARAM; 5686 ice_for_each_traffic_class(tc) { 5687 if (!ice_is_tc_ena(*tc_bitmap, tc)) 5688 continue; 5689 tc_node = ice_sched_get_tc_node(pi, tc); 5690 if (!tc_node) 5691 continue; 5692 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 5693 if (!vsi_node) 5694 continue; 5695 bw_t_info = &vsi_ctx->sched.bw_t_info[tc]; 5696 status = ice_sched_replay_node_bw(hw, vsi_node, bw_t_info); 5697 if (status) 5698 break; 5699 } 5700 return status; 5701 } 5702 5703 /** 5704 * ice_sched_replay_vsi_agg - replay aggregator & VSI to aggregator node(s) 5705 * @hw: pointer to the HW struct 5706 * @vsi_handle: software VSI handle 5707 * 5708 * This function replays aggregator node, VSI to aggregator type nodes, and 5709 * their node bandwidth information. This function needs to be called with 5710 * scheduler lock held. 5711 */ 5712 static enum ice_status 5713 ice_sched_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle) 5714 { 5715 ice_declare_bitmap(replay_bitmap, ICE_MAX_TRAFFIC_CLASS); 5716 struct ice_sched_agg_vsi_info *agg_vsi_info; 5717 struct ice_port_info *pi = hw->port_info; 5718 struct ice_sched_agg_info *agg_info; 5719 enum ice_status status; 5720 5721 ice_zero_bitmap(replay_bitmap, ICE_MAX_TRAFFIC_CLASS); 5722 if (!ice_is_vsi_valid(hw, vsi_handle)) 5723 return ICE_ERR_PARAM; 5724 agg_info = ice_get_vsi_agg_info(hw, vsi_handle); 5725 if (!agg_info) 5726 return ICE_SUCCESS; /* Not present in list - default Agg case */ 5727 agg_vsi_info = ice_get_agg_vsi_info(agg_info, vsi_handle); 5728 if (!agg_vsi_info) 5729 return ICE_SUCCESS; /* Not present in list - default Agg case */ 5730 ice_sched_get_ena_tc_bitmap(pi, agg_info->replay_tc_bitmap, 5731 replay_bitmap); 5732 /* Replay aggregator node associated to vsi_handle */ 5733 status = ice_sched_cfg_agg(hw->port_info, agg_info->agg_id, 5734 ICE_AGG_TYPE_AGG, replay_bitmap); 5735 if (status) 5736 return status; 5737 /* Replay aggregator node BW (restore aggregator BW) */ 5738 status = ice_sched_replay_agg_bw(hw, agg_info); 5739 if (status) 5740 return status; 5741 5742 ice_zero_bitmap(replay_bitmap, ICE_MAX_TRAFFIC_CLASS); 5743 ice_sched_get_ena_tc_bitmap(pi, agg_vsi_info->replay_tc_bitmap, 5744 replay_bitmap); 5745 /* Move this VSI (vsi_handle) to above aggregator */ 5746 status = ice_sched_assoc_vsi_to_agg(pi, agg_info->agg_id, vsi_handle, 5747 replay_bitmap); 5748 if (status) 5749 return status; 5750 /* Replay VSI BW (restore VSI BW) */ 5751 return ice_sched_replay_vsi_bw(hw, vsi_handle, 5752 agg_vsi_info->tc_bitmap); 5753 } 5754 5755 /** 5756 * ice_replay_vsi_agg - replay VSI to aggregator node 5757 * @hw: pointer to the HW struct 5758 * @vsi_handle: software VSI handle 5759 * 5760 * This function replays association of VSI to aggregator type nodes, and 5761 * node bandwidth information. 5762 */ 5763 enum ice_status ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle) 5764 { 5765 struct ice_port_info *pi = hw->port_info; 5766 enum ice_status status; 5767 5768 ice_acquire_lock(&pi->sched_lock); 5769 status = ice_sched_replay_vsi_agg(hw, vsi_handle); 5770 ice_release_lock(&pi->sched_lock); 5771 return status; 5772 } 5773 5774 /** 5775 * ice_sched_replay_q_bw - replay queue type node BW 5776 * @pi: port information structure 5777 * @q_ctx: queue context structure 5778 * 5779 * This function replays queue type node bandwidth. This function needs to be 5780 * called with scheduler lock held. 5781 */ 5782 enum ice_status 5783 ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx) 5784 { 5785 struct ice_sched_node *q_node; 5786 5787 /* Following also checks the presence of node in tree */ 5788 q_node = ice_sched_find_node_by_teid(pi->root, q_ctx->q_teid); 5789 if (!q_node) 5790 return ICE_ERR_PARAM; 5791 return ice_sched_replay_node_bw(pi->hw, q_node, &q_ctx->bw_t_info); 5792 } 5793