1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2021, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*$FreeBSD$*/ 32 33 #include "ice_sched.h" 34 35 /** 36 * ice_sched_add_root_node - Insert the Tx scheduler root node in SW DB 37 * @pi: port information structure 38 * @info: Scheduler element information from firmware 39 * 40 * This function inserts the root node of the scheduling tree topology 41 * to the SW DB. 42 */ 43 static enum ice_status 44 ice_sched_add_root_node(struct ice_port_info *pi, 45 struct ice_aqc_txsched_elem_data *info) 46 { 47 struct ice_sched_node *root; 48 struct ice_hw *hw; 49 50 if (!pi) 51 return ICE_ERR_PARAM; 52 53 hw = pi->hw; 54 55 root = (struct ice_sched_node *)ice_malloc(hw, sizeof(*root)); 56 if (!root) 57 return ICE_ERR_NO_MEMORY; 58 59 /* coverity[suspicious_sizeof] */ 60 root->children = (struct ice_sched_node **) 61 ice_calloc(hw, hw->max_children[0], sizeof(*root)); 62 if (!root->children) { 63 ice_free(hw, root); 64 return ICE_ERR_NO_MEMORY; 65 } 66 67 ice_memcpy(&root->info, info, sizeof(*info), ICE_DMA_TO_NONDMA); 68 pi->root = root; 69 return ICE_SUCCESS; 70 } 71 72 /** 73 * ice_sched_find_node_by_teid - Find the Tx scheduler node in SW DB 74 * @start_node: pointer to the starting ice_sched_node struct in a sub-tree 75 * @teid: node TEID to search 76 * 77 * This function searches for a node matching the TEID in the scheduling tree 78 * from the SW DB. The search is recursive and is restricted by the number of 79 * layers it has searched through; stopping at the max supported layer. 80 * 81 * This function needs to be called when holding the port_info->sched_lock 82 */ 83 struct ice_sched_node * 84 ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid) 85 { 86 u16 i; 87 88 /* The TEID is same as that of the start_node */ 89 if (ICE_TXSCHED_GET_NODE_TEID(start_node) == teid) 90 return start_node; 91 92 /* The node has no children or is at the max layer */ 93 if (!start_node->num_children || 94 start_node->tx_sched_layer >= ICE_AQC_TOPO_MAX_LEVEL_NUM || 95 start_node->info.data.elem_type == ICE_AQC_ELEM_TYPE_LEAF) 96 return NULL; 97 98 /* Check if TEID matches to any of the children nodes */ 99 for (i = 0; i < start_node->num_children; i++) 100 if (ICE_TXSCHED_GET_NODE_TEID(start_node->children[i]) == teid) 101 return start_node->children[i]; 102 103 /* Search within each child's sub-tree */ 104 for (i = 0; i < start_node->num_children; i++) { 105 struct ice_sched_node *tmp; 106 107 tmp = ice_sched_find_node_by_teid(start_node->children[i], 108 teid); 109 if (tmp) 110 return tmp; 111 } 112 113 return NULL; 114 } 115 116 /** 117 * ice_aqc_send_sched_elem_cmd - send scheduling elements cmd 118 * @hw: pointer to the HW struct 119 * @cmd_opc: cmd opcode 120 * @elems_req: number of elements to request 121 * @buf: pointer to buffer 122 * @buf_size: buffer size in bytes 123 * @elems_resp: returns total number of elements response 124 * @cd: pointer to command details structure or NULL 125 * 126 * This function sends a scheduling elements cmd (cmd_opc) 127 */ 128 static enum ice_status 129 ice_aqc_send_sched_elem_cmd(struct ice_hw *hw, enum ice_adminq_opc cmd_opc, 130 u16 elems_req, void *buf, u16 buf_size, 131 u16 *elems_resp, struct ice_sq_cd *cd) 132 { 133 struct ice_aqc_sched_elem_cmd *cmd; 134 struct ice_aq_desc desc; 135 enum ice_status status; 136 137 cmd = &desc.params.sched_elem_cmd; 138 ice_fill_dflt_direct_cmd_desc(&desc, cmd_opc); 139 cmd->num_elem_req = CPU_TO_LE16(elems_req); 140 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 141 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 142 if (!status && elems_resp) 143 *elems_resp = LE16_TO_CPU(cmd->num_elem_resp); 144 145 return status; 146 } 147 148 /** 149 * ice_aq_query_sched_elems - query scheduler elements 150 * @hw: pointer to the HW struct 151 * @elems_req: number of elements to query 152 * @buf: pointer to buffer 153 * @buf_size: buffer size in bytes 154 * @elems_ret: returns total number of elements returned 155 * @cd: pointer to command details structure or NULL 156 * 157 * Query scheduling elements (0x0404) 158 */ 159 enum ice_status 160 ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req, 161 struct ice_aqc_txsched_elem_data *buf, u16 buf_size, 162 u16 *elems_ret, struct ice_sq_cd *cd) 163 { 164 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_get_sched_elems, 165 elems_req, (void *)buf, buf_size, 166 elems_ret, cd); 167 } 168 169 /** 170 * ice_sched_add_node - Insert the Tx scheduler node in SW DB 171 * @pi: port information structure 172 * @layer: Scheduler layer of the node 173 * @info: Scheduler element information from firmware 174 * 175 * This function inserts a scheduler node to the SW DB. 176 */ 177 enum ice_status 178 ice_sched_add_node(struct ice_port_info *pi, u8 layer, 179 struct ice_aqc_txsched_elem_data *info) 180 { 181 struct ice_aqc_txsched_elem_data elem; 182 struct ice_sched_node *parent; 183 struct ice_sched_node *node; 184 enum ice_status status; 185 struct ice_hw *hw; 186 187 if (!pi) 188 return ICE_ERR_PARAM; 189 190 hw = pi->hw; 191 192 /* A valid parent node should be there */ 193 parent = ice_sched_find_node_by_teid(pi->root, 194 LE32_TO_CPU(info->parent_teid)); 195 if (!parent) { 196 ice_debug(hw, ICE_DBG_SCHED, "Parent Node not found for parent_teid=0x%x\n", 197 LE32_TO_CPU(info->parent_teid)); 198 return ICE_ERR_PARAM; 199 } 200 201 /* query the current node information from FW before adding it 202 * to the SW DB 203 */ 204 status = ice_sched_query_elem(hw, LE32_TO_CPU(info->node_teid), &elem); 205 if (status) 206 return status; 207 node = (struct ice_sched_node *)ice_malloc(hw, sizeof(*node)); 208 if (!node) 209 return ICE_ERR_NO_MEMORY; 210 if (hw->max_children[layer]) { 211 /* coverity[suspicious_sizeof] */ 212 node->children = (struct ice_sched_node **) 213 ice_calloc(hw, hw->max_children[layer], sizeof(*node)); 214 if (!node->children) { 215 ice_free(hw, node); 216 return ICE_ERR_NO_MEMORY; 217 } 218 } 219 220 node->in_use = true; 221 node->parent = parent; 222 node->tx_sched_layer = layer; 223 parent->children[parent->num_children++] = node; 224 node->info = elem; 225 return ICE_SUCCESS; 226 } 227 228 /** 229 * ice_aq_delete_sched_elems - delete scheduler elements 230 * @hw: pointer to the HW struct 231 * @grps_req: number of groups to delete 232 * @buf: pointer to buffer 233 * @buf_size: buffer size in bytes 234 * @grps_del: returns total number of elements deleted 235 * @cd: pointer to command details structure or NULL 236 * 237 * Delete scheduling elements (0x040F) 238 */ 239 static enum ice_status 240 ice_aq_delete_sched_elems(struct ice_hw *hw, u16 grps_req, 241 struct ice_aqc_delete_elem *buf, u16 buf_size, 242 u16 *grps_del, struct ice_sq_cd *cd) 243 { 244 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_delete_sched_elems, 245 grps_req, (void *)buf, buf_size, 246 grps_del, cd); 247 } 248 249 /** 250 * ice_sched_remove_elems - remove nodes from HW 251 * @hw: pointer to the HW struct 252 * @parent: pointer to the parent node 253 * @num_nodes: number of nodes 254 * @node_teids: array of node teids to be deleted 255 * 256 * This function remove nodes from HW 257 */ 258 static enum ice_status 259 ice_sched_remove_elems(struct ice_hw *hw, struct ice_sched_node *parent, 260 u16 num_nodes, u32 *node_teids) 261 { 262 struct ice_aqc_delete_elem *buf; 263 u16 i, num_groups_removed = 0; 264 enum ice_status status; 265 u16 buf_size; 266 267 buf_size = ice_struct_size(buf, teid, num_nodes); 268 buf = (struct ice_aqc_delete_elem *)ice_malloc(hw, buf_size); 269 if (!buf) 270 return ICE_ERR_NO_MEMORY; 271 272 buf->hdr.parent_teid = parent->info.node_teid; 273 buf->hdr.num_elems = CPU_TO_LE16(num_nodes); 274 for (i = 0; i < num_nodes; i++) 275 buf->teid[i] = CPU_TO_LE32(node_teids[i]); 276 277 status = ice_aq_delete_sched_elems(hw, 1, buf, buf_size, 278 &num_groups_removed, NULL); 279 if (status != ICE_SUCCESS || num_groups_removed != 1) 280 ice_debug(hw, ICE_DBG_SCHED, "remove node failed FW error %d\n", 281 hw->adminq.sq_last_status); 282 283 ice_free(hw, buf); 284 return status; 285 } 286 287 /** 288 * ice_sched_get_first_node - get the first node of the given layer 289 * @pi: port information structure 290 * @parent: pointer the base node of the subtree 291 * @layer: layer number 292 * 293 * This function retrieves the first node of the given layer from the subtree 294 */ 295 static struct ice_sched_node * 296 ice_sched_get_first_node(struct ice_port_info *pi, 297 struct ice_sched_node *parent, u8 layer) 298 { 299 return pi->sib_head[parent->tc_num][layer]; 300 } 301 302 /** 303 * ice_sched_get_tc_node - get pointer to TC node 304 * @pi: port information structure 305 * @tc: TC number 306 * 307 * This function returns the TC node pointer 308 */ 309 struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc) 310 { 311 u8 i; 312 313 if (!pi || !pi->root) 314 return NULL; 315 for (i = 0; i < pi->root->num_children; i++) 316 if (pi->root->children[i]->tc_num == tc) 317 return pi->root->children[i]; 318 return NULL; 319 } 320 321 /** 322 * ice_free_sched_node - Free a Tx scheduler node from SW DB 323 * @pi: port information structure 324 * @node: pointer to the ice_sched_node struct 325 * 326 * This function frees up a node from SW DB as well as from HW 327 * 328 * This function needs to be called with the port_info->sched_lock held 329 */ 330 void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node) 331 { 332 struct ice_sched_node *parent; 333 struct ice_hw *hw = pi->hw; 334 u8 i, j; 335 336 /* Free the children before freeing up the parent node 337 * The parent array is updated below and that shifts the nodes 338 * in the array. So always pick the first child if num children > 0 339 */ 340 while (node->num_children) 341 ice_free_sched_node(pi, node->children[0]); 342 343 /* Leaf, TC and root nodes can't be deleted by SW */ 344 if (node->tx_sched_layer >= hw->sw_entry_point_layer && 345 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_TC && 346 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_ROOT_PORT && 347 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_LEAF) { 348 u32 teid = LE32_TO_CPU(node->info.node_teid); 349 350 ice_sched_remove_elems(hw, node->parent, 1, &teid); 351 } 352 parent = node->parent; 353 /* root has no parent */ 354 if (parent) { 355 struct ice_sched_node *p; 356 357 /* update the parent */ 358 for (i = 0; i < parent->num_children; i++) 359 if (parent->children[i] == node) { 360 for (j = i + 1; j < parent->num_children; j++) 361 parent->children[j - 1] = 362 parent->children[j]; 363 parent->num_children--; 364 break; 365 } 366 367 p = ice_sched_get_first_node(pi, node, node->tx_sched_layer); 368 while (p) { 369 if (p->sibling == node) { 370 p->sibling = node->sibling; 371 break; 372 } 373 p = p->sibling; 374 } 375 376 /* update the sibling head if head is getting removed */ 377 if (pi->sib_head[node->tc_num][node->tx_sched_layer] == node) 378 pi->sib_head[node->tc_num][node->tx_sched_layer] = 379 node->sibling; 380 } 381 382 /* leaf nodes have no children */ 383 if (node->children) 384 ice_free(hw, node->children); 385 ice_free(hw, node); 386 } 387 388 /** 389 * ice_aq_get_dflt_topo - gets default scheduler topology 390 * @hw: pointer to the HW struct 391 * @lport: logical port number 392 * @buf: pointer to buffer 393 * @buf_size: buffer size in bytes 394 * @num_branches: returns total number of queue to port branches 395 * @cd: pointer to command details structure or NULL 396 * 397 * Get default scheduler topology (0x400) 398 */ 399 static enum ice_status 400 ice_aq_get_dflt_topo(struct ice_hw *hw, u8 lport, 401 struct ice_aqc_get_topo_elem *buf, u16 buf_size, 402 u8 *num_branches, struct ice_sq_cd *cd) 403 { 404 struct ice_aqc_get_topo *cmd; 405 struct ice_aq_desc desc; 406 enum ice_status status; 407 408 cmd = &desc.params.get_topo; 409 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_dflt_topo); 410 cmd->port_num = lport; 411 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 412 if (!status && num_branches) 413 *num_branches = cmd->num_branches; 414 415 return status; 416 } 417 418 /** 419 * ice_aq_add_sched_elems - adds scheduling element 420 * @hw: pointer to the HW struct 421 * @grps_req: the number of groups that are requested to be added 422 * @buf: pointer to buffer 423 * @buf_size: buffer size in bytes 424 * @grps_added: returns total number of groups added 425 * @cd: pointer to command details structure or NULL 426 * 427 * Add scheduling elements (0x0401) 428 */ 429 static enum ice_status 430 ice_aq_add_sched_elems(struct ice_hw *hw, u16 grps_req, 431 struct ice_aqc_add_elem *buf, u16 buf_size, 432 u16 *grps_added, struct ice_sq_cd *cd) 433 { 434 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_add_sched_elems, 435 grps_req, (void *)buf, buf_size, 436 grps_added, cd); 437 } 438 439 /** 440 * ice_aq_cfg_sched_elems - configures scheduler elements 441 * @hw: pointer to the HW struct 442 * @elems_req: number of elements to configure 443 * @buf: pointer to buffer 444 * @buf_size: buffer size in bytes 445 * @elems_cfgd: returns total number of elements configured 446 * @cd: pointer to command details structure or NULL 447 * 448 * Configure scheduling elements (0x0403) 449 */ 450 static enum ice_status 451 ice_aq_cfg_sched_elems(struct ice_hw *hw, u16 elems_req, 452 struct ice_aqc_txsched_elem_data *buf, u16 buf_size, 453 u16 *elems_cfgd, struct ice_sq_cd *cd) 454 { 455 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_cfg_sched_elems, 456 elems_req, (void *)buf, buf_size, 457 elems_cfgd, cd); 458 } 459 460 /** 461 * ice_aq_move_sched_elems - move scheduler elements 462 * @hw: pointer to the HW struct 463 * @grps_req: number of groups to move 464 * @buf: pointer to buffer 465 * @buf_size: buffer size in bytes 466 * @grps_movd: returns total number of groups moved 467 * @cd: pointer to command details structure or NULL 468 * 469 * Move scheduling elements (0x0408) 470 */ 471 static enum ice_status 472 ice_aq_move_sched_elems(struct ice_hw *hw, u16 grps_req, 473 struct ice_aqc_move_elem *buf, u16 buf_size, 474 u16 *grps_movd, struct ice_sq_cd *cd) 475 { 476 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_move_sched_elems, 477 grps_req, (void *)buf, buf_size, 478 grps_movd, cd); 479 } 480 481 /** 482 * ice_aq_suspend_sched_elems - suspend scheduler elements 483 * @hw: pointer to the HW struct 484 * @elems_req: number of elements to suspend 485 * @buf: pointer to buffer 486 * @buf_size: buffer size in bytes 487 * @elems_ret: returns total number of elements suspended 488 * @cd: pointer to command details structure or NULL 489 * 490 * Suspend scheduling elements (0x0409) 491 */ 492 static enum ice_status 493 ice_aq_suspend_sched_elems(struct ice_hw *hw, u16 elems_req, __le32 *buf, 494 u16 buf_size, u16 *elems_ret, struct ice_sq_cd *cd) 495 { 496 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_suspend_sched_elems, 497 elems_req, (void *)buf, buf_size, 498 elems_ret, cd); 499 } 500 501 /** 502 * ice_aq_resume_sched_elems - resume scheduler elements 503 * @hw: pointer to the HW struct 504 * @elems_req: number of elements to resume 505 * @buf: pointer to buffer 506 * @buf_size: buffer size in bytes 507 * @elems_ret: returns total number of elements resumed 508 * @cd: pointer to command details structure or NULL 509 * 510 * resume scheduling elements (0x040A) 511 */ 512 static enum ice_status 513 ice_aq_resume_sched_elems(struct ice_hw *hw, u16 elems_req, __le32 *buf, 514 u16 buf_size, u16 *elems_ret, struct ice_sq_cd *cd) 515 { 516 return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_resume_sched_elems, 517 elems_req, (void *)buf, buf_size, 518 elems_ret, cd); 519 } 520 521 /** 522 * ice_aq_query_sched_res - query scheduler resource 523 * @hw: pointer to the HW struct 524 * @buf_size: buffer size in bytes 525 * @buf: pointer to buffer 526 * @cd: pointer to command details structure or NULL 527 * 528 * Query scheduler resource allocation (0x0412) 529 */ 530 static enum ice_status 531 ice_aq_query_sched_res(struct ice_hw *hw, u16 buf_size, 532 struct ice_aqc_query_txsched_res_resp *buf, 533 struct ice_sq_cd *cd) 534 { 535 struct ice_aq_desc desc; 536 537 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_query_sched_res); 538 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 539 } 540 541 /** 542 * ice_sched_suspend_resume_elems - suspend or resume HW nodes 543 * @hw: pointer to the HW struct 544 * @num_nodes: number of nodes 545 * @node_teids: array of node teids to be suspended or resumed 546 * @suspend: true means suspend / false means resume 547 * 548 * This function suspends or resumes HW nodes 549 */ 550 static enum ice_status 551 ice_sched_suspend_resume_elems(struct ice_hw *hw, u8 num_nodes, u32 *node_teids, 552 bool suspend) 553 { 554 u16 i, buf_size, num_elem_ret = 0; 555 enum ice_status status; 556 __le32 *buf; 557 558 buf_size = sizeof(*buf) * num_nodes; 559 buf = (__le32 *)ice_malloc(hw, buf_size); 560 if (!buf) 561 return ICE_ERR_NO_MEMORY; 562 563 for (i = 0; i < num_nodes; i++) 564 buf[i] = CPU_TO_LE32(node_teids[i]); 565 566 if (suspend) 567 status = ice_aq_suspend_sched_elems(hw, num_nodes, buf, 568 buf_size, &num_elem_ret, 569 NULL); 570 else 571 status = ice_aq_resume_sched_elems(hw, num_nodes, buf, 572 buf_size, &num_elem_ret, 573 NULL); 574 if (status != ICE_SUCCESS || num_elem_ret != num_nodes) 575 ice_debug(hw, ICE_DBG_SCHED, "suspend/resume failed\n"); 576 577 ice_free(hw, buf); 578 return status; 579 } 580 581 /** 582 * ice_alloc_lan_q_ctx - allocate LAN queue contexts for the given VSI and TC 583 * @hw: pointer to the HW struct 584 * @vsi_handle: VSI handle 585 * @tc: TC number 586 * @new_numqs: number of queues 587 */ 588 static enum ice_status 589 ice_alloc_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 new_numqs) 590 { 591 struct ice_vsi_ctx *vsi_ctx; 592 struct ice_q_ctx *q_ctx; 593 594 vsi_ctx = ice_get_vsi_ctx(hw, vsi_handle); 595 if (!vsi_ctx) 596 return ICE_ERR_PARAM; 597 /* allocate LAN queue contexts */ 598 if (!vsi_ctx->lan_q_ctx[tc]) { 599 vsi_ctx->lan_q_ctx[tc] = (struct ice_q_ctx *) 600 ice_calloc(hw, new_numqs, sizeof(*q_ctx)); 601 if (!vsi_ctx->lan_q_ctx[tc]) 602 return ICE_ERR_NO_MEMORY; 603 vsi_ctx->num_lan_q_entries[tc] = new_numqs; 604 return ICE_SUCCESS; 605 } 606 /* num queues are increased, update the queue contexts */ 607 if (new_numqs > vsi_ctx->num_lan_q_entries[tc]) { 608 u16 prev_num = vsi_ctx->num_lan_q_entries[tc]; 609 610 q_ctx = (struct ice_q_ctx *) 611 ice_calloc(hw, new_numqs, sizeof(*q_ctx)); 612 if (!q_ctx) 613 return ICE_ERR_NO_MEMORY; 614 ice_memcpy(q_ctx, vsi_ctx->lan_q_ctx[tc], 615 prev_num * sizeof(*q_ctx), ICE_DMA_TO_NONDMA); 616 ice_free(hw, vsi_ctx->lan_q_ctx[tc]); 617 vsi_ctx->lan_q_ctx[tc] = q_ctx; 618 vsi_ctx->num_lan_q_entries[tc] = new_numqs; 619 } 620 return ICE_SUCCESS; 621 } 622 623 /** 624 * ice_aq_rl_profile - performs a rate limiting task 625 * @hw: pointer to the HW struct 626 * @opcode: opcode for add, query, or remove profile(s) 627 * @num_profiles: the number of profiles 628 * @buf: pointer to buffer 629 * @buf_size: buffer size in bytes 630 * @num_processed: number of processed add or remove profile(s) to return 631 * @cd: pointer to command details structure 632 * 633 * RL profile function to add, query, or remove profile(s) 634 */ 635 static enum ice_status 636 ice_aq_rl_profile(struct ice_hw *hw, enum ice_adminq_opc opcode, 637 u16 num_profiles, struct ice_aqc_rl_profile_elem *buf, 638 u16 buf_size, u16 *num_processed, struct ice_sq_cd *cd) 639 { 640 struct ice_aqc_rl_profile *cmd; 641 struct ice_aq_desc desc; 642 enum ice_status status; 643 644 cmd = &desc.params.rl_profile; 645 646 ice_fill_dflt_direct_cmd_desc(&desc, opcode); 647 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 648 cmd->num_profiles = CPU_TO_LE16(num_profiles); 649 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 650 if (!status && num_processed) 651 *num_processed = LE16_TO_CPU(cmd->num_processed); 652 return status; 653 } 654 655 /** 656 * ice_aq_add_rl_profile - adds rate limiting profile(s) 657 * @hw: pointer to the HW struct 658 * @num_profiles: the number of profile(s) to be add 659 * @buf: pointer to buffer 660 * @buf_size: buffer size in bytes 661 * @num_profiles_added: total number of profiles added to return 662 * @cd: pointer to command details structure 663 * 664 * Add RL profile (0x0410) 665 */ 666 static enum ice_status 667 ice_aq_add_rl_profile(struct ice_hw *hw, u16 num_profiles, 668 struct ice_aqc_rl_profile_elem *buf, u16 buf_size, 669 u16 *num_profiles_added, struct ice_sq_cd *cd) 670 { 671 return ice_aq_rl_profile(hw, ice_aqc_opc_add_rl_profiles, num_profiles, 672 buf, buf_size, num_profiles_added, cd); 673 } 674 675 /** 676 * ice_aq_query_rl_profile - query rate limiting profile(s) 677 * @hw: pointer to the HW struct 678 * @num_profiles: the number of profile(s) to query 679 * @buf: pointer to buffer 680 * @buf_size: buffer size in bytes 681 * @cd: pointer to command details structure 682 * 683 * Query RL profile (0x0411) 684 */ 685 enum ice_status 686 ice_aq_query_rl_profile(struct ice_hw *hw, u16 num_profiles, 687 struct ice_aqc_rl_profile_elem *buf, u16 buf_size, 688 struct ice_sq_cd *cd) 689 { 690 return ice_aq_rl_profile(hw, ice_aqc_opc_query_rl_profiles, 691 num_profiles, buf, buf_size, NULL, cd); 692 } 693 694 /** 695 * ice_aq_remove_rl_profile - removes RL profile(s) 696 * @hw: pointer to the HW struct 697 * @num_profiles: the number of profile(s) to remove 698 * @buf: pointer to buffer 699 * @buf_size: buffer size in bytes 700 * @num_profiles_removed: total number of profiles removed to return 701 * @cd: pointer to command details structure or NULL 702 * 703 * Remove RL profile (0x0415) 704 */ 705 static enum ice_status 706 ice_aq_remove_rl_profile(struct ice_hw *hw, u16 num_profiles, 707 struct ice_aqc_rl_profile_elem *buf, u16 buf_size, 708 u16 *num_profiles_removed, struct ice_sq_cd *cd) 709 { 710 return ice_aq_rl_profile(hw, ice_aqc_opc_remove_rl_profiles, 711 num_profiles, buf, buf_size, 712 num_profiles_removed, cd); 713 } 714 715 /** 716 * ice_sched_del_rl_profile - remove RL profile 717 * @hw: pointer to the HW struct 718 * @rl_info: rate limit profile information 719 * 720 * If the profile ID is not referenced anymore, it removes profile ID with 721 * its associated parameters from HW DB,and locally. The caller needs to 722 * hold scheduler lock. 723 */ 724 static enum ice_status 725 ice_sched_del_rl_profile(struct ice_hw *hw, 726 struct ice_aqc_rl_profile_info *rl_info) 727 { 728 struct ice_aqc_rl_profile_elem *buf; 729 u16 num_profiles_removed; 730 enum ice_status status; 731 u16 num_profiles = 1; 732 733 if (rl_info->prof_id_ref != 0) 734 return ICE_ERR_IN_USE; 735 736 /* Safe to remove profile ID */ 737 buf = &rl_info->profile; 738 status = ice_aq_remove_rl_profile(hw, num_profiles, buf, sizeof(*buf), 739 &num_profiles_removed, NULL); 740 if (status || num_profiles_removed != num_profiles) 741 return ICE_ERR_CFG; 742 743 /* Delete stale entry now */ 744 LIST_DEL(&rl_info->list_entry); 745 ice_free(hw, rl_info); 746 return status; 747 } 748 749 /** 750 * ice_sched_clear_rl_prof - clears RL prof entries 751 * @pi: port information structure 752 * 753 * This function removes all RL profile from HW as well as from SW DB. 754 */ 755 static void ice_sched_clear_rl_prof(struct ice_port_info *pi) 756 { 757 u16 ln; 758 struct ice_hw *hw = pi->hw; 759 760 for (ln = 0; ln < hw->num_tx_sched_layers; ln++) { 761 struct ice_aqc_rl_profile_info *rl_prof_elem; 762 struct ice_aqc_rl_profile_info *rl_prof_tmp; 763 764 LIST_FOR_EACH_ENTRY_SAFE(rl_prof_elem, rl_prof_tmp, 765 &hw->rl_prof_list[ln], 766 ice_aqc_rl_profile_info, list_entry) { 767 enum ice_status status; 768 769 rl_prof_elem->prof_id_ref = 0; 770 status = ice_sched_del_rl_profile(hw, rl_prof_elem); 771 if (status) { 772 ice_debug(hw, ICE_DBG_SCHED, "Remove rl profile failed\n"); 773 /* On error, free mem required */ 774 LIST_DEL(&rl_prof_elem->list_entry); 775 ice_free(hw, rl_prof_elem); 776 } 777 } 778 } 779 } 780 781 /** 782 * ice_sched_clear_agg - clears the aggregator related information 783 * @hw: pointer to the hardware structure 784 * 785 * This function removes aggregator list and free up aggregator related memory 786 * previously allocated. 787 */ 788 void ice_sched_clear_agg(struct ice_hw *hw) 789 { 790 struct ice_sched_agg_info *agg_info; 791 struct ice_sched_agg_info *atmp; 792 793 LIST_FOR_EACH_ENTRY_SAFE(agg_info, atmp, &hw->agg_list, 794 ice_sched_agg_info, 795 list_entry) { 796 struct ice_sched_agg_vsi_info *agg_vsi_info; 797 struct ice_sched_agg_vsi_info *vtmp; 798 799 LIST_FOR_EACH_ENTRY_SAFE(agg_vsi_info, vtmp, 800 &agg_info->agg_vsi_list, 801 ice_sched_agg_vsi_info, list_entry) { 802 LIST_DEL(&agg_vsi_info->list_entry); 803 ice_free(hw, agg_vsi_info); 804 } 805 LIST_DEL(&agg_info->list_entry); 806 ice_free(hw, agg_info); 807 } 808 } 809 810 /** 811 * ice_sched_clear_tx_topo - clears the scheduler tree nodes 812 * @pi: port information structure 813 * 814 * This function removes all the nodes from HW as well as from SW DB. 815 */ 816 static void ice_sched_clear_tx_topo(struct ice_port_info *pi) 817 { 818 if (!pi) 819 return; 820 /* remove RL profiles related lists */ 821 ice_sched_clear_rl_prof(pi); 822 if (pi->root) { 823 ice_free_sched_node(pi, pi->root); 824 pi->root = NULL; 825 } 826 } 827 828 /** 829 * ice_sched_clear_port - clear the scheduler elements from SW DB for a port 830 * @pi: port information structure 831 * 832 * Cleanup scheduling elements from SW DB 833 */ 834 void ice_sched_clear_port(struct ice_port_info *pi) 835 { 836 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 837 return; 838 839 pi->port_state = ICE_SCHED_PORT_STATE_INIT; 840 ice_acquire_lock(&pi->sched_lock); 841 ice_sched_clear_tx_topo(pi); 842 ice_release_lock(&pi->sched_lock); 843 ice_destroy_lock(&pi->sched_lock); 844 } 845 846 /** 847 * ice_sched_cleanup_all - cleanup scheduler elements from SW DB for all ports 848 * @hw: pointer to the HW struct 849 * 850 * Cleanup scheduling elements from SW DB for all the ports 851 */ 852 void ice_sched_cleanup_all(struct ice_hw *hw) 853 { 854 if (!hw) 855 return; 856 857 if (hw->layer_info) { 858 ice_free(hw, hw->layer_info); 859 hw->layer_info = NULL; 860 } 861 862 ice_sched_clear_port(hw->port_info); 863 864 hw->num_tx_sched_layers = 0; 865 hw->num_tx_sched_phys_layers = 0; 866 hw->flattened_layers = 0; 867 hw->max_cgds = 0; 868 } 869 870 /** 871 * ice_aq_cfg_l2_node_cgd - configures L2 node to CGD mapping 872 * @hw: pointer to the HW struct 873 * @num_l2_nodes: the number of L2 nodes whose CGDs to configure 874 * @buf: pointer to buffer 875 * @buf_size: buffer size in bytes 876 * @cd: pointer to command details structure or NULL 877 * 878 * Configure L2 Node CGD (0x0414) 879 */ 880 enum ice_status 881 ice_aq_cfg_l2_node_cgd(struct ice_hw *hw, u16 num_l2_nodes, 882 struct ice_aqc_cfg_l2_node_cgd_elem *buf, 883 u16 buf_size, struct ice_sq_cd *cd) 884 { 885 struct ice_aqc_cfg_l2_node_cgd *cmd; 886 struct ice_aq_desc desc; 887 888 cmd = &desc.params.cfg_l2_node_cgd; 889 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_cfg_l2_node_cgd); 890 desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 891 892 cmd->num_l2_nodes = CPU_TO_LE16(num_l2_nodes); 893 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 894 } 895 896 /** 897 * ice_sched_add_elems - add nodes to HW and SW DB 898 * @pi: port information structure 899 * @tc_node: pointer to the branch node 900 * @parent: pointer to the parent node 901 * @layer: layer number to add nodes 902 * @num_nodes: number of nodes 903 * @num_nodes_added: pointer to num nodes added 904 * @first_node_teid: if new nodes are added then return the TEID of first node 905 * 906 * This function add nodes to HW as well as to SW DB for a given layer 907 */ 908 static enum ice_status 909 ice_sched_add_elems(struct ice_port_info *pi, struct ice_sched_node *tc_node, 910 struct ice_sched_node *parent, u8 layer, u16 num_nodes, 911 u16 *num_nodes_added, u32 *first_node_teid) 912 { 913 struct ice_sched_node *prev, *new_node; 914 struct ice_aqc_add_elem *buf; 915 u16 i, num_groups_added = 0; 916 enum ice_status status = ICE_SUCCESS; 917 struct ice_hw *hw = pi->hw; 918 u16 buf_size; 919 u32 teid; 920 921 buf_size = ice_struct_size(buf, generic, num_nodes); 922 buf = (struct ice_aqc_add_elem *)ice_malloc(hw, buf_size); 923 if (!buf) 924 return ICE_ERR_NO_MEMORY; 925 926 buf->hdr.parent_teid = parent->info.node_teid; 927 buf->hdr.num_elems = CPU_TO_LE16(num_nodes); 928 for (i = 0; i < num_nodes; i++) { 929 buf->generic[i].parent_teid = parent->info.node_teid; 930 buf->generic[i].data.elem_type = ICE_AQC_ELEM_TYPE_SE_GENERIC; 931 buf->generic[i].data.valid_sections = 932 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 933 ICE_AQC_ELEM_VALID_EIR; 934 buf->generic[i].data.generic = 0; 935 buf->generic[i].data.cir_bw.bw_profile_idx = 936 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); 937 buf->generic[i].data.cir_bw.bw_alloc = 938 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); 939 buf->generic[i].data.eir_bw.bw_profile_idx = 940 CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); 941 buf->generic[i].data.eir_bw.bw_alloc = 942 CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); 943 } 944 945 status = ice_aq_add_sched_elems(hw, 1, buf, buf_size, 946 &num_groups_added, NULL); 947 if (status != ICE_SUCCESS || num_groups_added != 1) { 948 ice_debug(hw, ICE_DBG_SCHED, "add node failed FW Error %d\n", 949 hw->adminq.sq_last_status); 950 ice_free(hw, buf); 951 return ICE_ERR_CFG; 952 } 953 954 *num_nodes_added = num_nodes; 955 /* add nodes to the SW DB */ 956 for (i = 0; i < num_nodes; i++) { 957 status = ice_sched_add_node(pi, layer, &buf->generic[i]); 958 if (status != ICE_SUCCESS) { 959 ice_debug(hw, ICE_DBG_SCHED, "add nodes in SW DB failed status =%d\n", 960 status); 961 break; 962 } 963 964 teid = LE32_TO_CPU(buf->generic[i].node_teid); 965 new_node = ice_sched_find_node_by_teid(parent, teid); 966 if (!new_node) { 967 ice_debug(hw, ICE_DBG_SCHED, "Node is missing for teid =%d\n", teid); 968 break; 969 } 970 971 new_node->sibling = NULL; 972 new_node->tc_num = tc_node->tc_num; 973 974 /* add it to previous node sibling pointer */ 975 /* Note: siblings are not linked across branches */ 976 prev = ice_sched_get_first_node(pi, tc_node, layer); 977 if (prev && prev != new_node) { 978 while (prev->sibling) 979 prev = prev->sibling; 980 prev->sibling = new_node; 981 } 982 983 /* initialize the sibling head */ 984 if (!pi->sib_head[tc_node->tc_num][layer]) 985 pi->sib_head[tc_node->tc_num][layer] = new_node; 986 987 if (i == 0) 988 *first_node_teid = teid; 989 } 990 991 ice_free(hw, buf); 992 return status; 993 } 994 995 /** 996 * ice_sched_add_nodes_to_hw_layer - Add nodes to hw layer 997 * @pi: port information structure 998 * @tc_node: pointer to TC node 999 * @parent: pointer to parent node 1000 * @layer: layer number to add nodes 1001 * @num_nodes: number of nodes to be added 1002 * @first_node_teid: pointer to the first node TEID 1003 * @num_nodes_added: pointer to number of nodes added 1004 * 1005 * Add nodes into specific hw layer. 1006 */ 1007 static enum ice_status 1008 ice_sched_add_nodes_to_hw_layer(struct ice_port_info *pi, 1009 struct ice_sched_node *tc_node, 1010 struct ice_sched_node *parent, u8 layer, 1011 u16 num_nodes, u32 *first_node_teid, 1012 u16 *num_nodes_added) 1013 { 1014 u16 max_child_nodes; 1015 1016 *num_nodes_added = 0; 1017 1018 if (!num_nodes) 1019 return ICE_SUCCESS; 1020 1021 if (!parent || layer < pi->hw->sw_entry_point_layer) 1022 return ICE_ERR_PARAM; 1023 1024 /* max children per node per layer */ 1025 max_child_nodes = pi->hw->max_children[parent->tx_sched_layer]; 1026 1027 /* current number of children + required nodes exceed max children */ 1028 if ((parent->num_children + num_nodes) > max_child_nodes) { 1029 /* Fail if the parent is a TC node */ 1030 if (parent == tc_node) 1031 return ICE_ERR_CFG; 1032 return ICE_ERR_MAX_LIMIT; 1033 } 1034 1035 return ice_sched_add_elems(pi, tc_node, parent, layer, num_nodes, 1036 num_nodes_added, first_node_teid); 1037 } 1038 1039 /** 1040 * ice_sched_add_nodes_to_layer - Add nodes to a given layer 1041 * @pi: port information structure 1042 * @tc_node: pointer to TC node 1043 * @parent: pointer to parent node 1044 * @layer: layer number to add nodes 1045 * @num_nodes: number of nodes to be added 1046 * @first_node_teid: pointer to the first node TEID 1047 * @num_nodes_added: pointer to number of nodes added 1048 * 1049 * This function add nodes to a given layer. 1050 */ 1051 static enum ice_status 1052 ice_sched_add_nodes_to_layer(struct ice_port_info *pi, 1053 struct ice_sched_node *tc_node, 1054 struct ice_sched_node *parent, u8 layer, 1055 u16 num_nodes, u32 *first_node_teid, 1056 u16 *num_nodes_added) 1057 { 1058 u32 *first_teid_ptr = first_node_teid; 1059 u16 new_num_nodes = num_nodes; 1060 enum ice_status status = ICE_SUCCESS; 1061 1062 *num_nodes_added = 0; 1063 while (*num_nodes_added < num_nodes) { 1064 u16 max_child_nodes, num_added = 0; 1065 /* cppcheck-suppress unusedVariable */ 1066 u32 temp; 1067 1068 status = ice_sched_add_nodes_to_hw_layer(pi, tc_node, parent, 1069 layer, new_num_nodes, 1070 first_teid_ptr, 1071 &num_added); 1072 if (status == ICE_SUCCESS) 1073 *num_nodes_added += num_added; 1074 /* added more nodes than requested ? */ 1075 if (*num_nodes_added > num_nodes) { 1076 ice_debug(pi->hw, ICE_DBG_SCHED, "added extra nodes %d %d\n", num_nodes, 1077 *num_nodes_added); 1078 status = ICE_ERR_CFG; 1079 break; 1080 } 1081 /* break if all the nodes are added successfully */ 1082 if (status == ICE_SUCCESS && (*num_nodes_added == num_nodes)) 1083 break; 1084 /* break if the error is not max limit */ 1085 if (status != ICE_SUCCESS && status != ICE_ERR_MAX_LIMIT) 1086 break; 1087 /* Exceeded the max children */ 1088 max_child_nodes = pi->hw->max_children[parent->tx_sched_layer]; 1089 /* utilize all the spaces if the parent is not full */ 1090 if (parent->num_children < max_child_nodes) { 1091 new_num_nodes = max_child_nodes - parent->num_children; 1092 } else { 1093 /* This parent is full, try the next sibling */ 1094 parent = parent->sibling; 1095 /* Don't modify the first node TEID memory if the 1096 * first node was added already in the above call. 1097 * Instead send some temp memory for all other 1098 * recursive calls. 1099 */ 1100 if (num_added) 1101 first_teid_ptr = &temp; 1102 1103 new_num_nodes = num_nodes - *num_nodes_added; 1104 } 1105 } 1106 return status; 1107 } 1108 1109 /** 1110 * ice_sched_get_qgrp_layer - get the current queue group layer number 1111 * @hw: pointer to the HW struct 1112 * 1113 * This function returns the current queue group layer number 1114 */ 1115 static u8 ice_sched_get_qgrp_layer(struct ice_hw *hw) 1116 { 1117 /* It's always total layers - 1, the array is 0 relative so -2 */ 1118 return hw->num_tx_sched_layers - ICE_QGRP_LAYER_OFFSET; 1119 } 1120 1121 /** 1122 * ice_sched_get_vsi_layer - get the current VSI layer number 1123 * @hw: pointer to the HW struct 1124 * 1125 * This function returns the current VSI layer number 1126 */ 1127 static u8 ice_sched_get_vsi_layer(struct ice_hw *hw) 1128 { 1129 /* Num Layers VSI layer 1130 * 9 6 1131 * 7 4 1132 * 5 or less sw_entry_point_layer 1133 */ 1134 /* calculate the VSI layer based on number of layers. */ 1135 if (hw->num_tx_sched_layers > ICE_VSI_LAYER_OFFSET + 1) { 1136 u8 layer = hw->num_tx_sched_layers - ICE_VSI_LAYER_OFFSET; 1137 1138 if (layer > hw->sw_entry_point_layer) 1139 return layer; 1140 } 1141 return hw->sw_entry_point_layer; 1142 } 1143 1144 /** 1145 * ice_sched_get_agg_layer - get the current aggregator layer number 1146 * @hw: pointer to the HW struct 1147 * 1148 * This function returns the current aggregator layer number 1149 */ 1150 static u8 ice_sched_get_agg_layer(struct ice_hw *hw) 1151 { 1152 /* Num Layers aggregator layer 1153 * 9 4 1154 * 7 or less sw_entry_point_layer 1155 */ 1156 /* calculate the aggregator layer based on number of layers. */ 1157 if (hw->num_tx_sched_layers > ICE_AGG_LAYER_OFFSET + 1) { 1158 u8 layer = hw->num_tx_sched_layers - ICE_AGG_LAYER_OFFSET; 1159 1160 if (layer > hw->sw_entry_point_layer) 1161 return layer; 1162 } 1163 return hw->sw_entry_point_layer; 1164 } 1165 1166 /** 1167 * ice_rm_dflt_leaf_node - remove the default leaf node in the tree 1168 * @pi: port information structure 1169 * 1170 * This function removes the leaf node that was created by the FW 1171 * during initialization 1172 */ 1173 static void ice_rm_dflt_leaf_node(struct ice_port_info *pi) 1174 { 1175 struct ice_sched_node *node; 1176 1177 node = pi->root; 1178 while (node) { 1179 if (!node->num_children) 1180 break; 1181 node = node->children[0]; 1182 } 1183 if (node && node->info.data.elem_type == ICE_AQC_ELEM_TYPE_LEAF) { 1184 u32 teid = LE32_TO_CPU(node->info.node_teid); 1185 enum ice_status status; 1186 1187 /* remove the default leaf node */ 1188 status = ice_sched_remove_elems(pi->hw, node->parent, 1, &teid); 1189 if (!status) 1190 ice_free_sched_node(pi, node); 1191 } 1192 } 1193 1194 /** 1195 * ice_sched_rm_dflt_nodes - free the default nodes in the tree 1196 * @pi: port information structure 1197 * 1198 * This function frees all the nodes except root and TC that were created by 1199 * the FW during initialization 1200 */ 1201 static void ice_sched_rm_dflt_nodes(struct ice_port_info *pi) 1202 { 1203 struct ice_sched_node *node; 1204 1205 ice_rm_dflt_leaf_node(pi); 1206 1207 /* remove the default nodes except TC and root nodes */ 1208 node = pi->root; 1209 while (node) { 1210 if (node->tx_sched_layer >= pi->hw->sw_entry_point_layer && 1211 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_TC && 1212 node->info.data.elem_type != ICE_AQC_ELEM_TYPE_ROOT_PORT) { 1213 ice_free_sched_node(pi, node); 1214 break; 1215 } 1216 1217 if (!node->num_children) 1218 break; 1219 node = node->children[0]; 1220 } 1221 } 1222 1223 /** 1224 * ice_sched_init_port - Initialize scheduler by querying information from FW 1225 * @pi: port info structure for the tree to cleanup 1226 * 1227 * This function is the initial call to find the total number of Tx scheduler 1228 * resources, default topology created by firmware and storing the information 1229 * in SW DB. 1230 */ 1231 enum ice_status ice_sched_init_port(struct ice_port_info *pi) 1232 { 1233 struct ice_aqc_get_topo_elem *buf; 1234 enum ice_status status; 1235 struct ice_hw *hw; 1236 u8 num_branches; 1237 u16 num_elems; 1238 u8 i, j; 1239 1240 if (!pi) 1241 return ICE_ERR_PARAM; 1242 hw = pi->hw; 1243 1244 /* Query the Default Topology from FW */ 1245 buf = (struct ice_aqc_get_topo_elem *)ice_malloc(hw, 1246 ICE_AQ_MAX_BUF_LEN); 1247 if (!buf) 1248 return ICE_ERR_NO_MEMORY; 1249 1250 /* Query default scheduling tree topology */ 1251 status = ice_aq_get_dflt_topo(hw, pi->lport, buf, ICE_AQ_MAX_BUF_LEN, 1252 &num_branches, NULL); 1253 if (status) 1254 goto err_init_port; 1255 1256 /* num_branches should be between 1-8 */ 1257 if (num_branches < 1 || num_branches > ICE_TXSCHED_MAX_BRANCHES) { 1258 ice_debug(hw, ICE_DBG_SCHED, "num_branches unexpected %d\n", 1259 num_branches); 1260 status = ICE_ERR_PARAM; 1261 goto err_init_port; 1262 } 1263 1264 /* get the number of elements on the default/first branch */ 1265 num_elems = LE16_TO_CPU(buf[0].hdr.num_elems); 1266 1267 /* num_elems should always be between 1-9 */ 1268 if (num_elems < 1 || num_elems > ICE_AQC_TOPO_MAX_LEVEL_NUM) { 1269 ice_debug(hw, ICE_DBG_SCHED, "num_elems unexpected %d\n", 1270 num_elems); 1271 status = ICE_ERR_PARAM; 1272 goto err_init_port; 1273 } 1274 1275 /* If the last node is a leaf node then the index of the queue group 1276 * layer is two less than the number of elements. 1277 */ 1278 if (num_elems > 2 && buf[0].generic[num_elems - 1].data.elem_type == 1279 ICE_AQC_ELEM_TYPE_LEAF) 1280 pi->last_node_teid = 1281 LE32_TO_CPU(buf[0].generic[num_elems - 2].node_teid); 1282 else 1283 pi->last_node_teid = 1284 LE32_TO_CPU(buf[0].generic[num_elems - 1].node_teid); 1285 1286 /* Insert the Tx Sched root node */ 1287 status = ice_sched_add_root_node(pi, &buf[0].generic[0]); 1288 if (status) 1289 goto err_init_port; 1290 1291 /* Parse the default tree and cache the information */ 1292 for (i = 0; i < num_branches; i++) { 1293 num_elems = LE16_TO_CPU(buf[i].hdr.num_elems); 1294 1295 /* Skip root element as already inserted */ 1296 for (j = 1; j < num_elems; j++) { 1297 /* update the sw entry point */ 1298 if (buf[0].generic[j].data.elem_type == 1299 ICE_AQC_ELEM_TYPE_ENTRY_POINT) 1300 hw->sw_entry_point_layer = j; 1301 1302 status = ice_sched_add_node(pi, j, &buf[i].generic[j]); 1303 if (status) 1304 goto err_init_port; 1305 } 1306 } 1307 1308 /* Remove the default nodes. */ 1309 if (pi->root) 1310 ice_sched_rm_dflt_nodes(pi); 1311 1312 /* initialize the port for handling the scheduler tree */ 1313 pi->port_state = ICE_SCHED_PORT_STATE_READY; 1314 ice_init_lock(&pi->sched_lock); 1315 for (i = 0; i < ICE_AQC_TOPO_MAX_LEVEL_NUM; i++) 1316 INIT_LIST_HEAD(&hw->rl_prof_list[i]); 1317 1318 err_init_port: 1319 if (status && pi->root) { 1320 ice_free_sched_node(pi, pi->root); 1321 pi->root = NULL; 1322 } 1323 1324 ice_free(hw, buf); 1325 return status; 1326 } 1327 1328 /** 1329 * ice_sched_get_node - Get the struct ice_sched_node for given TEID 1330 * @pi: port information structure 1331 * @teid: Scheduler node TEID 1332 * 1333 * This function retrieves the ice_sched_node struct for given TEID from 1334 * the SW DB and returns it to the caller. 1335 */ 1336 struct ice_sched_node *ice_sched_get_node(struct ice_port_info *pi, u32 teid) 1337 { 1338 struct ice_sched_node *node; 1339 1340 if (!pi) 1341 return NULL; 1342 1343 /* Find the node starting from root */ 1344 ice_acquire_lock(&pi->sched_lock); 1345 node = ice_sched_find_node_by_teid(pi->root, teid); 1346 ice_release_lock(&pi->sched_lock); 1347 1348 if (!node) 1349 ice_debug(pi->hw, ICE_DBG_SCHED, "Node not found for teid=0x%x\n", teid); 1350 1351 return node; 1352 } 1353 1354 /** 1355 * ice_sched_query_res_alloc - query the FW for num of logical sched layers 1356 * @hw: pointer to the HW struct 1357 * 1358 * query FW for allocated scheduler resources and store in HW struct 1359 */ 1360 enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw) 1361 { 1362 struct ice_aqc_query_txsched_res_resp *buf; 1363 enum ice_status status = ICE_SUCCESS; 1364 __le16 max_sibl; 1365 u8 i; 1366 1367 if (hw->layer_info) 1368 return status; 1369 1370 buf = (struct ice_aqc_query_txsched_res_resp *) 1371 ice_malloc(hw, sizeof(*buf)); 1372 if (!buf) 1373 return ICE_ERR_NO_MEMORY; 1374 1375 status = ice_aq_query_sched_res(hw, sizeof(*buf), buf, NULL); 1376 if (status) 1377 goto sched_query_out; 1378 1379 hw->num_tx_sched_layers = LE16_TO_CPU(buf->sched_props.logical_levels); 1380 hw->num_tx_sched_phys_layers = 1381 LE16_TO_CPU(buf->sched_props.phys_levels); 1382 hw->flattened_layers = buf->sched_props.flattening_bitmap; 1383 hw->max_cgds = buf->sched_props.max_pf_cgds; 1384 1385 /* max sibling group size of current layer refers to the max children 1386 * of the below layer node. 1387 * layer 1 node max children will be layer 2 max sibling group size 1388 * layer 2 node max children will be layer 3 max sibling group size 1389 * and so on. This array will be populated from root (index 0) to 1390 * qgroup layer 7. Leaf node has no children. 1391 */ 1392 for (i = 0; i < hw->num_tx_sched_layers - 1; i++) { 1393 max_sibl = buf->layer_props[i + 1].max_sibl_grp_sz; 1394 hw->max_children[i] = LE16_TO_CPU(max_sibl); 1395 } 1396 1397 hw->layer_info = (struct ice_aqc_layer_props *) 1398 ice_memdup(hw, buf->layer_props, 1399 (hw->num_tx_sched_layers * 1400 sizeof(*hw->layer_info)), 1401 ICE_NONDMA_TO_NONDMA); 1402 if (!hw->layer_info) { 1403 status = ICE_ERR_NO_MEMORY; 1404 goto sched_query_out; 1405 } 1406 1407 sched_query_out: 1408 ice_free(hw, buf); 1409 return status; 1410 } 1411 1412 /** 1413 * ice_sched_get_psm_clk_freq - determine the PSM clock frequency 1414 * @hw: pointer to the HW struct 1415 * 1416 * Determine the PSM clock frequency and store in HW struct 1417 */ 1418 void ice_sched_get_psm_clk_freq(struct ice_hw *hw) 1419 { 1420 u32 val, clk_src; 1421 1422 val = rd32(hw, GLGEN_CLKSTAT_SRC); 1423 clk_src = (val & GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M) >> 1424 GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_S; 1425 1426 #define PSM_CLK_SRC_367_MHZ 0x0 1427 #define PSM_CLK_SRC_416_MHZ 0x1 1428 #define PSM_CLK_SRC_446_MHZ 0x2 1429 #define PSM_CLK_SRC_390_MHZ 0x3 1430 1431 switch (clk_src) { 1432 case PSM_CLK_SRC_367_MHZ: 1433 hw->psm_clk_freq = ICE_PSM_CLK_367MHZ_IN_HZ; 1434 break; 1435 case PSM_CLK_SRC_416_MHZ: 1436 hw->psm_clk_freq = ICE_PSM_CLK_416MHZ_IN_HZ; 1437 break; 1438 case PSM_CLK_SRC_446_MHZ: 1439 hw->psm_clk_freq = ICE_PSM_CLK_446MHZ_IN_HZ; 1440 break; 1441 case PSM_CLK_SRC_390_MHZ: 1442 hw->psm_clk_freq = ICE_PSM_CLK_390MHZ_IN_HZ; 1443 break; 1444 default: 1445 ice_debug(hw, ICE_DBG_SCHED, "PSM clk_src unexpected %u\n", 1446 clk_src); 1447 /* fall back to a safe default */ 1448 hw->psm_clk_freq = ICE_PSM_CLK_446MHZ_IN_HZ; 1449 } 1450 } 1451 1452 /** 1453 * ice_sched_find_node_in_subtree - Find node in part of base node subtree 1454 * @hw: pointer to the HW struct 1455 * @base: pointer to the base node 1456 * @node: pointer to the node to search 1457 * 1458 * This function checks whether a given node is part of the base node 1459 * subtree or not 1460 */ 1461 bool 1462 ice_sched_find_node_in_subtree(struct ice_hw *hw, struct ice_sched_node *base, 1463 struct ice_sched_node *node) 1464 { 1465 u8 i; 1466 1467 for (i = 0; i < base->num_children; i++) { 1468 struct ice_sched_node *child = base->children[i]; 1469 1470 if (node == child) 1471 return true; 1472 1473 if (child->tx_sched_layer > node->tx_sched_layer) 1474 return false; 1475 1476 /* this recursion is intentional, and wouldn't 1477 * go more than 8 calls 1478 */ 1479 if (ice_sched_find_node_in_subtree(hw, child, node)) 1480 return true; 1481 } 1482 return false; 1483 } 1484 1485 /** 1486 * ice_sched_get_free_qgrp - Scan all queue group siblings and find a free node 1487 * @pi: port information structure 1488 * @vsi_node: software VSI handle 1489 * @qgrp_node: first queue group node identified for scanning 1490 * @owner: LAN or RDMA 1491 * 1492 * This function retrieves a free LAN or RDMA queue group node by scanning 1493 * qgrp_node and its siblings for the queue group with the fewest number 1494 * of queues currently assigned. 1495 */ 1496 static struct ice_sched_node * 1497 ice_sched_get_free_qgrp(struct ice_port_info *pi, 1498 struct ice_sched_node *vsi_node, 1499 struct ice_sched_node *qgrp_node, u8 owner) 1500 { 1501 struct ice_sched_node *min_qgrp; 1502 u8 min_children; 1503 1504 if (!qgrp_node) 1505 return qgrp_node; 1506 min_children = qgrp_node->num_children; 1507 if (!min_children) 1508 return qgrp_node; 1509 min_qgrp = qgrp_node; 1510 /* scan all queue groups until find a node which has less than the 1511 * minimum number of children. This way all queue group nodes get 1512 * equal number of shares and active. The bandwidth will be equally 1513 * distributed across all queues. 1514 */ 1515 while (qgrp_node) { 1516 /* make sure the qgroup node is part of the VSI subtree */ 1517 if (ice_sched_find_node_in_subtree(pi->hw, vsi_node, qgrp_node)) 1518 if (qgrp_node->num_children < min_children && 1519 qgrp_node->owner == owner) { 1520 /* replace the new min queue group node */ 1521 min_qgrp = qgrp_node; 1522 min_children = min_qgrp->num_children; 1523 /* break if it has no children, */ 1524 if (!min_children) 1525 break; 1526 } 1527 qgrp_node = qgrp_node->sibling; 1528 } 1529 return min_qgrp; 1530 } 1531 1532 /** 1533 * ice_sched_get_free_qparent - Get a free LAN or RDMA queue group node 1534 * @pi: port information structure 1535 * @vsi_handle: software VSI handle 1536 * @tc: branch number 1537 * @owner: LAN or RDMA 1538 * 1539 * This function retrieves a free LAN or RDMA queue group node 1540 */ 1541 struct ice_sched_node * 1542 ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 1543 u8 owner) 1544 { 1545 struct ice_sched_node *vsi_node, *qgrp_node; 1546 struct ice_vsi_ctx *vsi_ctx; 1547 u16 max_children; 1548 u8 qgrp_layer; 1549 1550 qgrp_layer = ice_sched_get_qgrp_layer(pi->hw); 1551 max_children = pi->hw->max_children[qgrp_layer]; 1552 1553 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 1554 if (!vsi_ctx) 1555 return NULL; 1556 vsi_node = vsi_ctx->sched.vsi_node[tc]; 1557 /* validate invalid VSI ID */ 1558 if (!vsi_node) 1559 return NULL; 1560 1561 /* get the first queue group node from VSI sub-tree */ 1562 qgrp_node = ice_sched_get_first_node(pi, vsi_node, qgrp_layer); 1563 while (qgrp_node) { 1564 /* make sure the qgroup node is part of the VSI subtree */ 1565 if (ice_sched_find_node_in_subtree(pi->hw, vsi_node, qgrp_node)) 1566 if (qgrp_node->num_children < max_children && 1567 qgrp_node->owner == owner) 1568 break; 1569 qgrp_node = qgrp_node->sibling; 1570 } 1571 1572 /* Select the best queue group */ 1573 return ice_sched_get_free_qgrp(pi, vsi_node, qgrp_node, owner); 1574 } 1575 1576 /** 1577 * ice_sched_get_vsi_node - Get a VSI node based on VSI ID 1578 * @pi: pointer to the port information structure 1579 * @tc_node: pointer to the TC node 1580 * @vsi_handle: software VSI handle 1581 * 1582 * This function retrieves a VSI node for a given VSI ID from a given 1583 * TC branch 1584 */ 1585 struct ice_sched_node * 1586 ice_sched_get_vsi_node(struct ice_port_info *pi, struct ice_sched_node *tc_node, 1587 u16 vsi_handle) 1588 { 1589 struct ice_sched_node *node; 1590 u8 vsi_layer; 1591 1592 vsi_layer = ice_sched_get_vsi_layer(pi->hw); 1593 node = ice_sched_get_first_node(pi, tc_node, vsi_layer); 1594 1595 /* Check whether it already exists */ 1596 while (node) { 1597 if (node->vsi_handle == vsi_handle) 1598 return node; 1599 node = node->sibling; 1600 } 1601 1602 return node; 1603 } 1604 1605 /** 1606 * ice_sched_get_agg_node - Get an aggregator node based on aggregator ID 1607 * @pi: pointer to the port information structure 1608 * @tc_node: pointer to the TC node 1609 * @agg_id: aggregator ID 1610 * 1611 * This function retrieves an aggregator node for a given aggregator ID from 1612 * a given TC branch 1613 */ 1614 static struct ice_sched_node * 1615 ice_sched_get_agg_node(struct ice_port_info *pi, struct ice_sched_node *tc_node, 1616 u32 agg_id) 1617 { 1618 struct ice_sched_node *node; 1619 struct ice_hw *hw = pi->hw; 1620 u8 agg_layer; 1621 1622 if (!hw) 1623 return NULL; 1624 agg_layer = ice_sched_get_agg_layer(hw); 1625 node = ice_sched_get_first_node(pi, tc_node, agg_layer); 1626 1627 /* Check whether it already exists */ 1628 while (node) { 1629 if (node->agg_id == agg_id) 1630 return node; 1631 node = node->sibling; 1632 } 1633 1634 return node; 1635 } 1636 1637 /** 1638 * ice_sched_check_node - Compare node parameters between SW DB and HW DB 1639 * @hw: pointer to the HW struct 1640 * @node: pointer to the ice_sched_node struct 1641 * 1642 * This function queries and compares the HW element with SW DB node parameters 1643 */ 1644 static bool ice_sched_check_node(struct ice_hw *hw, struct ice_sched_node *node) 1645 { 1646 struct ice_aqc_txsched_elem_data buf; 1647 enum ice_status status; 1648 u32 node_teid; 1649 1650 node_teid = LE32_TO_CPU(node->info.node_teid); 1651 status = ice_sched_query_elem(hw, node_teid, &buf); 1652 if (status != ICE_SUCCESS) 1653 return false; 1654 1655 if (memcmp(&buf, &node->info, sizeof(buf))) { 1656 ice_debug(hw, ICE_DBG_SCHED, "Node mismatch for teid=0x%x\n", 1657 node_teid); 1658 return false; 1659 } 1660 1661 return true; 1662 } 1663 1664 /** 1665 * ice_sched_calc_vsi_child_nodes - calculate number of VSI child nodes 1666 * @hw: pointer to the HW struct 1667 * @num_qs: number of queues 1668 * @num_nodes: num nodes array 1669 * 1670 * This function calculates the number of VSI child nodes based on the 1671 * number of queues. 1672 */ 1673 static void 1674 ice_sched_calc_vsi_child_nodes(struct ice_hw *hw, u16 num_qs, u16 *num_nodes) 1675 { 1676 u16 num = num_qs; 1677 u8 i, qgl, vsil; 1678 1679 qgl = ice_sched_get_qgrp_layer(hw); 1680 vsil = ice_sched_get_vsi_layer(hw); 1681 1682 /* calculate num nodes from queue group to VSI layer */ 1683 for (i = qgl; i > vsil; i--) { 1684 /* round to the next integer if there is a remainder */ 1685 num = DIVIDE_AND_ROUND_UP(num, hw->max_children[i]); 1686 1687 /* need at least one node */ 1688 num_nodes[i] = num ? num : 1; 1689 } 1690 } 1691 1692 /** 1693 * ice_sched_add_vsi_child_nodes - add VSI child nodes to tree 1694 * @pi: port information structure 1695 * @vsi_handle: software VSI handle 1696 * @tc_node: pointer to the TC node 1697 * @num_nodes: pointer to the num nodes that needs to be added per layer 1698 * @owner: node owner (LAN or RDMA) 1699 * 1700 * This function adds the VSI child nodes to tree. It gets called for 1701 * LAN and RDMA separately. 1702 */ 1703 static enum ice_status 1704 ice_sched_add_vsi_child_nodes(struct ice_port_info *pi, u16 vsi_handle, 1705 struct ice_sched_node *tc_node, u16 *num_nodes, 1706 u8 owner) 1707 { 1708 struct ice_sched_node *parent, *node; 1709 struct ice_hw *hw = pi->hw; 1710 enum ice_status status; 1711 u32 first_node_teid; 1712 u16 num_added = 0; 1713 u8 i, qgl, vsil; 1714 1715 qgl = ice_sched_get_qgrp_layer(hw); 1716 vsil = ice_sched_get_vsi_layer(hw); 1717 parent = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 1718 for (i = vsil + 1; i <= qgl; i++) { 1719 if (!parent) 1720 return ICE_ERR_CFG; 1721 1722 status = ice_sched_add_nodes_to_layer(pi, tc_node, parent, i, 1723 num_nodes[i], 1724 &first_node_teid, 1725 &num_added); 1726 if (status != ICE_SUCCESS || num_nodes[i] != num_added) 1727 return ICE_ERR_CFG; 1728 1729 /* The newly added node can be a new parent for the next 1730 * layer nodes 1731 */ 1732 if (num_added) { 1733 parent = ice_sched_find_node_by_teid(tc_node, 1734 first_node_teid); 1735 node = parent; 1736 while (node) { 1737 node->owner = owner; 1738 node = node->sibling; 1739 } 1740 } else { 1741 parent = parent->children[0]; 1742 } 1743 } 1744 1745 return ICE_SUCCESS; 1746 } 1747 1748 /** 1749 * ice_sched_calc_vsi_support_nodes - calculate number of VSI support nodes 1750 * @pi: pointer to the port info structure 1751 * @tc_node: pointer to TC node 1752 * @num_nodes: pointer to num nodes array 1753 * 1754 * This function calculates the number of supported nodes needed to add this 1755 * VSI into Tx tree including the VSI, parent and intermediate nodes in below 1756 * layers 1757 */ 1758 static void 1759 ice_sched_calc_vsi_support_nodes(struct ice_port_info *pi, 1760 struct ice_sched_node *tc_node, u16 *num_nodes) 1761 { 1762 struct ice_sched_node *node; 1763 u8 vsil; 1764 int i; 1765 1766 vsil = ice_sched_get_vsi_layer(pi->hw); 1767 for (i = vsil; i >= pi->hw->sw_entry_point_layer; i--) 1768 /* Add intermediate nodes if TC has no children and 1769 * need at least one node for VSI 1770 */ 1771 if (!tc_node->num_children || i == vsil) { 1772 num_nodes[i]++; 1773 } else { 1774 /* If intermediate nodes are reached max children 1775 * then add a new one. 1776 */ 1777 node = ice_sched_get_first_node(pi, tc_node, (u8)i); 1778 /* scan all the siblings */ 1779 while (node) { 1780 if (node->num_children < 1781 pi->hw->max_children[i]) 1782 break; 1783 node = node->sibling; 1784 } 1785 1786 /* tree has one intermediate node to add this new VSI. 1787 * So no need to calculate supported nodes for below 1788 * layers. 1789 */ 1790 if (node) 1791 break; 1792 /* all the nodes are full, allocate a new one */ 1793 num_nodes[i]++; 1794 } 1795 } 1796 1797 /** 1798 * ice_sched_add_vsi_support_nodes - add VSI supported nodes into Tx tree 1799 * @pi: port information structure 1800 * @vsi_handle: software VSI handle 1801 * @tc_node: pointer to TC node 1802 * @num_nodes: pointer to num nodes array 1803 * 1804 * This function adds the VSI supported nodes into Tx tree including the 1805 * VSI, its parent and intermediate nodes in below layers 1806 */ 1807 static enum ice_status 1808 ice_sched_add_vsi_support_nodes(struct ice_port_info *pi, u16 vsi_handle, 1809 struct ice_sched_node *tc_node, u16 *num_nodes) 1810 { 1811 struct ice_sched_node *parent = tc_node; 1812 enum ice_status status; 1813 u32 first_node_teid; 1814 u16 num_added = 0; 1815 u8 i, vsil; 1816 1817 if (!pi) 1818 return ICE_ERR_PARAM; 1819 1820 vsil = ice_sched_get_vsi_layer(pi->hw); 1821 for (i = pi->hw->sw_entry_point_layer; i <= vsil; i++) { 1822 status = ice_sched_add_nodes_to_layer(pi, tc_node, parent, 1823 i, num_nodes[i], 1824 &first_node_teid, 1825 &num_added); 1826 if (status != ICE_SUCCESS || num_nodes[i] != num_added) 1827 return ICE_ERR_CFG; 1828 1829 /* The newly added node can be a new parent for the next 1830 * layer nodes 1831 */ 1832 if (num_added) 1833 parent = ice_sched_find_node_by_teid(tc_node, 1834 first_node_teid); 1835 else 1836 parent = parent->children[0]; 1837 1838 if (!parent) 1839 return ICE_ERR_CFG; 1840 1841 if (i == vsil) 1842 parent->vsi_handle = vsi_handle; 1843 } 1844 1845 return ICE_SUCCESS; 1846 } 1847 1848 /** 1849 * ice_sched_add_vsi_to_topo - add a new VSI into tree 1850 * @pi: port information structure 1851 * @vsi_handle: software VSI handle 1852 * @tc: TC number 1853 * 1854 * This function adds a new VSI into scheduler tree 1855 */ 1856 static enum ice_status 1857 ice_sched_add_vsi_to_topo(struct ice_port_info *pi, u16 vsi_handle, u8 tc) 1858 { 1859 u16 num_nodes[ICE_AQC_TOPO_MAX_LEVEL_NUM] = { 0 }; 1860 struct ice_sched_node *tc_node; 1861 1862 tc_node = ice_sched_get_tc_node(pi, tc); 1863 if (!tc_node) 1864 return ICE_ERR_PARAM; 1865 1866 /* calculate number of supported nodes needed for this VSI */ 1867 ice_sched_calc_vsi_support_nodes(pi, tc_node, num_nodes); 1868 1869 /* add VSI supported nodes to TC subtree */ 1870 return ice_sched_add_vsi_support_nodes(pi, vsi_handle, tc_node, 1871 num_nodes); 1872 } 1873 1874 /** 1875 * ice_sched_update_vsi_child_nodes - update VSI child nodes 1876 * @pi: port information structure 1877 * @vsi_handle: software VSI handle 1878 * @tc: TC number 1879 * @new_numqs: new number of max queues 1880 * @owner: owner of this subtree 1881 * 1882 * This function updates the VSI child nodes based on the number of queues 1883 */ 1884 static enum ice_status 1885 ice_sched_update_vsi_child_nodes(struct ice_port_info *pi, u16 vsi_handle, 1886 u8 tc, u16 new_numqs, u8 owner) 1887 { 1888 u16 new_num_nodes[ICE_AQC_TOPO_MAX_LEVEL_NUM] = { 0 }; 1889 struct ice_sched_node *vsi_node; 1890 struct ice_sched_node *tc_node; 1891 struct ice_vsi_ctx *vsi_ctx; 1892 enum ice_status status = ICE_SUCCESS; 1893 struct ice_hw *hw = pi->hw; 1894 u16 prev_numqs; 1895 1896 tc_node = ice_sched_get_tc_node(pi, tc); 1897 if (!tc_node) 1898 return ICE_ERR_CFG; 1899 1900 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 1901 if (!vsi_node) 1902 return ICE_ERR_CFG; 1903 1904 vsi_ctx = ice_get_vsi_ctx(hw, vsi_handle); 1905 if (!vsi_ctx) 1906 return ICE_ERR_PARAM; 1907 1908 prev_numqs = vsi_ctx->sched.max_lanq[tc]; 1909 /* num queues are not changed or less than the previous number */ 1910 if (new_numqs <= prev_numqs) 1911 return status; 1912 status = ice_alloc_lan_q_ctx(hw, vsi_handle, tc, new_numqs); 1913 if (status) 1914 return status; 1915 1916 if (new_numqs) 1917 ice_sched_calc_vsi_child_nodes(hw, new_numqs, new_num_nodes); 1918 /* Keep the max number of queue configuration all the time. Update the 1919 * tree only if number of queues > previous number of queues. This may 1920 * leave some extra nodes in the tree if number of queues < previous 1921 * number but that wouldn't harm anything. Removing those extra nodes 1922 * may complicate the code if those nodes are part of SRL or 1923 * individually rate limited. 1924 */ 1925 status = ice_sched_add_vsi_child_nodes(pi, vsi_handle, tc_node, 1926 new_num_nodes, owner); 1927 if (status) 1928 return status; 1929 vsi_ctx->sched.max_lanq[tc] = new_numqs; 1930 1931 return ICE_SUCCESS; 1932 } 1933 1934 /** 1935 * ice_sched_cfg_vsi - configure the new/existing VSI 1936 * @pi: port information structure 1937 * @vsi_handle: software VSI handle 1938 * @tc: TC number 1939 * @maxqs: max number of queues 1940 * @owner: LAN or RDMA 1941 * @enable: TC enabled or disabled 1942 * 1943 * This function adds/updates VSI nodes based on the number of queues. If TC is 1944 * enabled and VSI is in suspended state then resume the VSI back. If TC is 1945 * disabled then suspend the VSI if it is not already. 1946 */ 1947 enum ice_status 1948 ice_sched_cfg_vsi(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 maxqs, 1949 u8 owner, bool enable) 1950 { 1951 struct ice_sched_node *vsi_node, *tc_node; 1952 struct ice_vsi_ctx *vsi_ctx; 1953 enum ice_status status = ICE_SUCCESS; 1954 struct ice_hw *hw = pi->hw; 1955 1956 ice_debug(pi->hw, ICE_DBG_SCHED, "add/config VSI %d\n", vsi_handle); 1957 tc_node = ice_sched_get_tc_node(pi, tc); 1958 if (!tc_node) 1959 return ICE_ERR_PARAM; 1960 vsi_ctx = ice_get_vsi_ctx(hw, vsi_handle); 1961 if (!vsi_ctx) 1962 return ICE_ERR_PARAM; 1963 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 1964 1965 /* suspend the VSI if TC is not enabled */ 1966 if (!enable) { 1967 if (vsi_node && vsi_node->in_use) { 1968 u32 teid = LE32_TO_CPU(vsi_node->info.node_teid); 1969 1970 status = ice_sched_suspend_resume_elems(hw, 1, &teid, 1971 true); 1972 if (!status) 1973 vsi_node->in_use = false; 1974 } 1975 return status; 1976 } 1977 1978 /* TC is enabled, if it is a new VSI then add it to the tree */ 1979 if (!vsi_node) { 1980 status = ice_sched_add_vsi_to_topo(pi, vsi_handle, tc); 1981 if (status) 1982 return status; 1983 1984 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 1985 if (!vsi_node) 1986 return ICE_ERR_CFG; 1987 1988 vsi_ctx->sched.vsi_node[tc] = vsi_node; 1989 vsi_node->in_use = true; 1990 /* invalidate the max queues whenever VSI gets added first time 1991 * into the scheduler tree (boot or after reset). We need to 1992 * recreate the child nodes all the time in these cases. 1993 */ 1994 vsi_ctx->sched.max_lanq[tc] = 0; 1995 } 1996 1997 /* update the VSI child nodes */ 1998 status = ice_sched_update_vsi_child_nodes(pi, vsi_handle, tc, maxqs, 1999 owner); 2000 if (status) 2001 return status; 2002 2003 /* TC is enabled, resume the VSI if it is in the suspend state */ 2004 if (!vsi_node->in_use) { 2005 u32 teid = LE32_TO_CPU(vsi_node->info.node_teid); 2006 2007 status = ice_sched_suspend_resume_elems(hw, 1, &teid, false); 2008 if (!status) 2009 vsi_node->in_use = true; 2010 } 2011 2012 return status; 2013 } 2014 2015 /** 2016 * ice_sched_rm_agg_vsi_entry - remove aggregator related VSI info entry 2017 * @pi: port information structure 2018 * @vsi_handle: software VSI handle 2019 * 2020 * This function removes single aggregator VSI info entry from 2021 * aggregator list. 2022 */ 2023 static void ice_sched_rm_agg_vsi_info(struct ice_port_info *pi, u16 vsi_handle) 2024 { 2025 struct ice_sched_agg_info *agg_info; 2026 struct ice_sched_agg_info *atmp; 2027 2028 LIST_FOR_EACH_ENTRY_SAFE(agg_info, atmp, &pi->hw->agg_list, 2029 ice_sched_agg_info, 2030 list_entry) { 2031 struct ice_sched_agg_vsi_info *agg_vsi_info; 2032 struct ice_sched_agg_vsi_info *vtmp; 2033 2034 LIST_FOR_EACH_ENTRY_SAFE(agg_vsi_info, vtmp, 2035 &agg_info->agg_vsi_list, 2036 ice_sched_agg_vsi_info, list_entry) 2037 if (agg_vsi_info->vsi_handle == vsi_handle) { 2038 LIST_DEL(&agg_vsi_info->list_entry); 2039 ice_free(pi->hw, agg_vsi_info); 2040 return; 2041 } 2042 } 2043 } 2044 2045 /** 2046 * ice_sched_is_leaf_node_present - check for a leaf node in the sub-tree 2047 * @node: pointer to the sub-tree node 2048 * 2049 * This function checks for a leaf node presence in a given sub-tree node. 2050 */ 2051 static bool ice_sched_is_leaf_node_present(struct ice_sched_node *node) 2052 { 2053 u8 i; 2054 2055 for (i = 0; i < node->num_children; i++) 2056 if (ice_sched_is_leaf_node_present(node->children[i])) 2057 return true; 2058 /* check for a leaf node */ 2059 return (node->info.data.elem_type == ICE_AQC_ELEM_TYPE_LEAF); 2060 } 2061 2062 /** 2063 * ice_sched_rm_vsi_cfg - remove the VSI and its children nodes 2064 * @pi: port information structure 2065 * @vsi_handle: software VSI handle 2066 * @owner: LAN or RDMA 2067 * 2068 * This function removes the VSI and its LAN or RDMA children nodes from the 2069 * scheduler tree. 2070 */ 2071 static enum ice_status 2072 ice_sched_rm_vsi_cfg(struct ice_port_info *pi, u16 vsi_handle, u8 owner) 2073 { 2074 enum ice_status status = ICE_ERR_PARAM; 2075 struct ice_vsi_ctx *vsi_ctx; 2076 u8 i; 2077 2078 ice_debug(pi->hw, ICE_DBG_SCHED, "removing VSI %d\n", vsi_handle); 2079 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 2080 return status; 2081 ice_acquire_lock(&pi->sched_lock); 2082 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 2083 if (!vsi_ctx) 2084 goto exit_sched_rm_vsi_cfg; 2085 2086 ice_for_each_traffic_class(i) { 2087 struct ice_sched_node *vsi_node, *tc_node; 2088 u8 j = 0; 2089 2090 tc_node = ice_sched_get_tc_node(pi, i); 2091 if (!tc_node) 2092 continue; 2093 2094 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 2095 if (!vsi_node) 2096 continue; 2097 2098 if (ice_sched_is_leaf_node_present(vsi_node)) { 2099 ice_debug(pi->hw, ICE_DBG_SCHED, "VSI has leaf nodes in TC %d\n", i); 2100 status = ICE_ERR_IN_USE; 2101 goto exit_sched_rm_vsi_cfg; 2102 } 2103 while (j < vsi_node->num_children) { 2104 if (vsi_node->children[j]->owner == owner) { 2105 ice_free_sched_node(pi, vsi_node->children[j]); 2106 2107 /* reset the counter again since the num 2108 * children will be updated after node removal 2109 */ 2110 j = 0; 2111 } else { 2112 j++; 2113 } 2114 } 2115 /* remove the VSI if it has no children */ 2116 if (!vsi_node->num_children) { 2117 ice_free_sched_node(pi, vsi_node); 2118 vsi_ctx->sched.vsi_node[i] = NULL; 2119 2120 /* clean up aggregator related VSI info if any */ 2121 ice_sched_rm_agg_vsi_info(pi, vsi_handle); 2122 } 2123 if (owner == ICE_SCHED_NODE_OWNER_LAN) 2124 vsi_ctx->sched.max_lanq[i] = 0; 2125 } 2126 status = ICE_SUCCESS; 2127 2128 exit_sched_rm_vsi_cfg: 2129 ice_release_lock(&pi->sched_lock); 2130 return status; 2131 } 2132 2133 /** 2134 * ice_rm_vsi_lan_cfg - remove VSI and its LAN children nodes 2135 * @pi: port information structure 2136 * @vsi_handle: software VSI handle 2137 * 2138 * This function clears the VSI and its LAN children nodes from scheduler tree 2139 * for all TCs. 2140 */ 2141 enum ice_status ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle) 2142 { 2143 return ice_sched_rm_vsi_cfg(pi, vsi_handle, ICE_SCHED_NODE_OWNER_LAN); 2144 } 2145 2146 /** 2147 * ice_sched_is_tree_balanced - Check tree nodes are identical or not 2148 * @hw: pointer to the HW struct 2149 * @node: pointer to the ice_sched_node struct 2150 * 2151 * This function compares all the nodes for a given tree against HW DB nodes 2152 * This function needs to be called with the port_info->sched_lock held 2153 */ 2154 bool ice_sched_is_tree_balanced(struct ice_hw *hw, struct ice_sched_node *node) 2155 { 2156 u8 i; 2157 2158 /* start from the leaf node */ 2159 for (i = 0; i < node->num_children; i++) 2160 /* Fail if node doesn't match with the SW DB 2161 * this recursion is intentional, and wouldn't 2162 * go more than 9 calls 2163 */ 2164 if (!ice_sched_is_tree_balanced(hw, node->children[i])) 2165 return false; 2166 2167 return ice_sched_check_node(hw, node); 2168 } 2169 2170 /** 2171 * ice_aq_query_node_to_root - retrieve the tree topology for a given node TEID 2172 * @hw: pointer to the HW struct 2173 * @node_teid: node TEID 2174 * @buf: pointer to buffer 2175 * @buf_size: buffer size in bytes 2176 * @cd: pointer to command details structure or NULL 2177 * 2178 * This function retrieves the tree topology from the firmware for a given 2179 * node TEID to the root node. 2180 */ 2181 enum ice_status 2182 ice_aq_query_node_to_root(struct ice_hw *hw, u32 node_teid, 2183 struct ice_aqc_txsched_elem_data *buf, u16 buf_size, 2184 struct ice_sq_cd *cd) 2185 { 2186 struct ice_aqc_query_node_to_root *cmd; 2187 struct ice_aq_desc desc; 2188 2189 cmd = &desc.params.query_node_to_root; 2190 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_query_node_to_root); 2191 cmd->teid = CPU_TO_LE32(node_teid); 2192 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 2193 } 2194 2195 /** 2196 * ice_get_agg_info - get the aggregator ID 2197 * @hw: pointer to the hardware structure 2198 * @agg_id: aggregator ID 2199 * 2200 * This function validates aggregator ID. The function returns info if 2201 * aggregator ID is present in list otherwise it returns null. 2202 */ 2203 static struct ice_sched_agg_info * 2204 ice_get_agg_info(struct ice_hw *hw, u32 agg_id) 2205 { 2206 struct ice_sched_agg_info *agg_info; 2207 2208 LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info, 2209 list_entry) 2210 if (agg_info->agg_id == agg_id) 2211 return agg_info; 2212 2213 return NULL; 2214 } 2215 2216 /** 2217 * ice_sched_get_free_vsi_parent - Find a free parent node in aggregator subtree 2218 * @hw: pointer to the HW struct 2219 * @node: pointer to a child node 2220 * @num_nodes: num nodes count array 2221 * 2222 * This function walks through the aggregator subtree to find a free parent 2223 * node 2224 */ 2225 static struct ice_sched_node * 2226 ice_sched_get_free_vsi_parent(struct ice_hw *hw, struct ice_sched_node *node, 2227 u16 *num_nodes) 2228 { 2229 u8 l = node->tx_sched_layer; 2230 u8 vsil, i; 2231 2232 vsil = ice_sched_get_vsi_layer(hw); 2233 2234 /* Is it VSI parent layer ? */ 2235 if (l == vsil - 1) 2236 return (node->num_children < hw->max_children[l]) ? node : NULL; 2237 2238 /* We have intermediate nodes. Let's walk through the subtree. If the 2239 * intermediate node has space to add a new node then clear the count 2240 */ 2241 if (node->num_children < hw->max_children[l]) 2242 num_nodes[l] = 0; 2243 /* The below recursive call is intentional and wouldn't go more than 2244 * 2 or 3 iterations. 2245 */ 2246 2247 for (i = 0; i < node->num_children; i++) { 2248 struct ice_sched_node *parent; 2249 2250 parent = ice_sched_get_free_vsi_parent(hw, node->children[i], 2251 num_nodes); 2252 if (parent) 2253 return parent; 2254 } 2255 2256 return NULL; 2257 } 2258 2259 /** 2260 * ice_sched_update_parent - update the new parent in SW DB 2261 * @new_parent: pointer to a new parent node 2262 * @node: pointer to a child node 2263 * 2264 * This function removes the child from the old parent and adds it to a new 2265 * parent 2266 */ 2267 static void 2268 ice_sched_update_parent(struct ice_sched_node *new_parent, 2269 struct ice_sched_node *node) 2270 { 2271 struct ice_sched_node *old_parent; 2272 u8 i, j; 2273 2274 old_parent = node->parent; 2275 2276 /* update the old parent children */ 2277 for (i = 0; i < old_parent->num_children; i++) 2278 if (old_parent->children[i] == node) { 2279 for (j = i + 1; j < old_parent->num_children; j++) 2280 old_parent->children[j - 1] = 2281 old_parent->children[j]; 2282 old_parent->num_children--; 2283 break; 2284 } 2285 2286 /* now move the node to a new parent */ 2287 new_parent->children[new_parent->num_children++] = node; 2288 node->parent = new_parent; 2289 node->info.parent_teid = new_parent->info.node_teid; 2290 } 2291 2292 /** 2293 * ice_sched_move_nodes - move child nodes to a given parent 2294 * @pi: port information structure 2295 * @parent: pointer to parent node 2296 * @num_items: number of child nodes to be moved 2297 * @list: pointer to child node teids 2298 * 2299 * This function move the child nodes to a given parent. 2300 */ 2301 static enum ice_status 2302 ice_sched_move_nodes(struct ice_port_info *pi, struct ice_sched_node *parent, 2303 u16 num_items, u32 *list) 2304 { 2305 struct ice_aqc_move_elem *buf; 2306 struct ice_sched_node *node; 2307 enum ice_status status = ICE_SUCCESS; 2308 u16 i, grps_movd = 0; 2309 struct ice_hw *hw; 2310 u16 buf_len; 2311 2312 hw = pi->hw; 2313 2314 if (!parent || !num_items) 2315 return ICE_ERR_PARAM; 2316 2317 /* Does parent have enough space */ 2318 if (parent->num_children + num_items > 2319 hw->max_children[parent->tx_sched_layer]) 2320 return ICE_ERR_AQ_FULL; 2321 2322 buf_len = ice_struct_size(buf, teid, 1); 2323 buf = (struct ice_aqc_move_elem *)ice_malloc(hw, buf_len); 2324 if (!buf) 2325 return ICE_ERR_NO_MEMORY; 2326 2327 for (i = 0; i < num_items; i++) { 2328 node = ice_sched_find_node_by_teid(pi->root, list[i]); 2329 if (!node) { 2330 status = ICE_ERR_PARAM; 2331 goto move_err_exit; 2332 } 2333 2334 buf->hdr.src_parent_teid = node->info.parent_teid; 2335 buf->hdr.dest_parent_teid = parent->info.node_teid; 2336 buf->teid[0] = node->info.node_teid; 2337 buf->hdr.num_elems = CPU_TO_LE16(1); 2338 status = ice_aq_move_sched_elems(hw, 1, buf, buf_len, 2339 &grps_movd, NULL); 2340 if (status && grps_movd != 1) { 2341 status = ICE_ERR_CFG; 2342 goto move_err_exit; 2343 } 2344 2345 /* update the SW DB */ 2346 ice_sched_update_parent(parent, node); 2347 } 2348 2349 move_err_exit: 2350 ice_free(hw, buf); 2351 return status; 2352 } 2353 2354 /** 2355 * ice_sched_move_vsi_to_agg - move VSI to aggregator node 2356 * @pi: port information structure 2357 * @vsi_handle: software VSI handle 2358 * @agg_id: aggregator ID 2359 * @tc: TC number 2360 * 2361 * This function moves a VSI to an aggregator node or its subtree. 2362 * Intermediate nodes may be created if required. 2363 */ 2364 static enum ice_status 2365 ice_sched_move_vsi_to_agg(struct ice_port_info *pi, u16 vsi_handle, u32 agg_id, 2366 u8 tc) 2367 { 2368 struct ice_sched_node *vsi_node, *agg_node, *tc_node, *parent; 2369 u16 num_nodes[ICE_AQC_TOPO_MAX_LEVEL_NUM] = { 0 }; 2370 u32 first_node_teid, vsi_teid; 2371 enum ice_status status; 2372 u16 num_nodes_added; 2373 u8 aggl, vsil, i; 2374 2375 tc_node = ice_sched_get_tc_node(pi, tc); 2376 if (!tc_node) 2377 return ICE_ERR_CFG; 2378 2379 agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); 2380 if (!agg_node) 2381 return ICE_ERR_DOES_NOT_EXIST; 2382 2383 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 2384 if (!vsi_node) 2385 return ICE_ERR_DOES_NOT_EXIST; 2386 2387 /* Is this VSI already part of given aggregator? */ 2388 if (ice_sched_find_node_in_subtree(pi->hw, agg_node, vsi_node)) 2389 return ICE_SUCCESS; 2390 2391 aggl = ice_sched_get_agg_layer(pi->hw); 2392 vsil = ice_sched_get_vsi_layer(pi->hw); 2393 2394 /* set intermediate node count to 1 between aggregator and VSI layers */ 2395 for (i = aggl + 1; i < vsil; i++) 2396 num_nodes[i] = 1; 2397 2398 /* Check if the aggregator subtree has any free node to add the VSI */ 2399 for (i = 0; i < agg_node->num_children; i++) { 2400 parent = ice_sched_get_free_vsi_parent(pi->hw, 2401 agg_node->children[i], 2402 num_nodes); 2403 if (parent) 2404 goto move_nodes; 2405 } 2406 2407 /* add new nodes */ 2408 parent = agg_node; 2409 for (i = aggl + 1; i < vsil; i++) { 2410 status = ice_sched_add_nodes_to_layer(pi, tc_node, parent, i, 2411 num_nodes[i], 2412 &first_node_teid, 2413 &num_nodes_added); 2414 if (status != ICE_SUCCESS || num_nodes[i] != num_nodes_added) 2415 return ICE_ERR_CFG; 2416 2417 /* The newly added node can be a new parent for the next 2418 * layer nodes 2419 */ 2420 if (num_nodes_added) 2421 parent = ice_sched_find_node_by_teid(tc_node, 2422 first_node_teid); 2423 else 2424 parent = parent->children[0]; 2425 2426 if (!parent) 2427 return ICE_ERR_CFG; 2428 } 2429 2430 move_nodes: 2431 vsi_teid = LE32_TO_CPU(vsi_node->info.node_teid); 2432 return ice_sched_move_nodes(pi, parent, 1, &vsi_teid); 2433 } 2434 2435 /** 2436 * ice_move_all_vsi_to_dflt_agg - move all VSI(s) to default aggregator 2437 * @pi: port information structure 2438 * @agg_info: aggregator info 2439 * @tc: traffic class number 2440 * @rm_vsi_info: true or false 2441 * 2442 * This function move all the VSI(s) to the default aggregator and delete 2443 * aggregator VSI info based on passed in boolean parameter rm_vsi_info. The 2444 * caller holds the scheduler lock. 2445 */ 2446 static enum ice_status 2447 ice_move_all_vsi_to_dflt_agg(struct ice_port_info *pi, 2448 struct ice_sched_agg_info *agg_info, u8 tc, 2449 bool rm_vsi_info) 2450 { 2451 struct ice_sched_agg_vsi_info *agg_vsi_info; 2452 struct ice_sched_agg_vsi_info *tmp; 2453 enum ice_status status = ICE_SUCCESS; 2454 2455 LIST_FOR_EACH_ENTRY_SAFE(agg_vsi_info, tmp, &agg_info->agg_vsi_list, 2456 ice_sched_agg_vsi_info, list_entry) { 2457 u16 vsi_handle = agg_vsi_info->vsi_handle; 2458 2459 /* Move VSI to default aggregator */ 2460 if (!ice_is_tc_ena(agg_vsi_info->tc_bitmap[0], tc)) 2461 continue; 2462 2463 status = ice_sched_move_vsi_to_agg(pi, vsi_handle, 2464 ICE_DFLT_AGG_ID, tc); 2465 if (status) 2466 break; 2467 2468 ice_clear_bit(tc, agg_vsi_info->tc_bitmap); 2469 if (rm_vsi_info && !agg_vsi_info->tc_bitmap[0]) { 2470 LIST_DEL(&agg_vsi_info->list_entry); 2471 ice_free(pi->hw, agg_vsi_info); 2472 } 2473 } 2474 2475 return status; 2476 } 2477 2478 /** 2479 * ice_sched_is_agg_inuse - check whether the aggregator is in use or not 2480 * @pi: port information structure 2481 * @node: node pointer 2482 * 2483 * This function checks whether the aggregator is attached with any VSI or not. 2484 */ 2485 static bool 2486 ice_sched_is_agg_inuse(struct ice_port_info *pi, struct ice_sched_node *node) 2487 { 2488 u8 vsil, i; 2489 2490 vsil = ice_sched_get_vsi_layer(pi->hw); 2491 if (node->tx_sched_layer < vsil - 1) { 2492 for (i = 0; i < node->num_children; i++) 2493 if (ice_sched_is_agg_inuse(pi, node->children[i])) 2494 return true; 2495 return false; 2496 } else { 2497 return node->num_children ? true : false; 2498 } 2499 } 2500 2501 /** 2502 * ice_sched_rm_agg_cfg - remove the aggregator node 2503 * @pi: port information structure 2504 * @agg_id: aggregator ID 2505 * @tc: TC number 2506 * 2507 * This function removes the aggregator node and intermediate nodes if any 2508 * from the given TC 2509 */ 2510 static enum ice_status 2511 ice_sched_rm_agg_cfg(struct ice_port_info *pi, u32 agg_id, u8 tc) 2512 { 2513 struct ice_sched_node *tc_node, *agg_node; 2514 struct ice_hw *hw = pi->hw; 2515 2516 tc_node = ice_sched_get_tc_node(pi, tc); 2517 if (!tc_node) 2518 return ICE_ERR_CFG; 2519 2520 agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); 2521 if (!agg_node) 2522 return ICE_ERR_DOES_NOT_EXIST; 2523 2524 /* Can't remove the aggregator node if it has children */ 2525 if (ice_sched_is_agg_inuse(pi, agg_node)) 2526 return ICE_ERR_IN_USE; 2527 2528 /* need to remove the whole subtree if aggregator node is the 2529 * only child. 2530 */ 2531 while (agg_node->tx_sched_layer > hw->sw_entry_point_layer) { 2532 struct ice_sched_node *parent = agg_node->parent; 2533 2534 if (!parent) 2535 return ICE_ERR_CFG; 2536 2537 if (parent->num_children > 1) 2538 break; 2539 2540 agg_node = parent; 2541 } 2542 2543 ice_free_sched_node(pi, agg_node); 2544 return ICE_SUCCESS; 2545 } 2546 2547 /** 2548 * ice_rm_agg_cfg_tc - remove aggregator configuration for TC 2549 * @pi: port information structure 2550 * @agg_info: aggregator ID 2551 * @tc: TC number 2552 * @rm_vsi_info: bool value true or false 2553 * 2554 * This function removes aggregator reference to VSI of given TC. It removes 2555 * the aggregator configuration completely for requested TC. The caller needs 2556 * to hold the scheduler lock. 2557 */ 2558 static enum ice_status 2559 ice_rm_agg_cfg_tc(struct ice_port_info *pi, struct ice_sched_agg_info *agg_info, 2560 u8 tc, bool rm_vsi_info) 2561 { 2562 enum ice_status status = ICE_SUCCESS; 2563 2564 /* If nothing to remove - return success */ 2565 if (!ice_is_tc_ena(agg_info->tc_bitmap[0], tc)) 2566 goto exit_rm_agg_cfg_tc; 2567 2568 status = ice_move_all_vsi_to_dflt_agg(pi, agg_info, tc, rm_vsi_info); 2569 if (status) 2570 goto exit_rm_agg_cfg_tc; 2571 2572 /* Delete aggregator node(s) */ 2573 status = ice_sched_rm_agg_cfg(pi, agg_info->agg_id, tc); 2574 if (status) 2575 goto exit_rm_agg_cfg_tc; 2576 2577 ice_clear_bit(tc, agg_info->tc_bitmap); 2578 exit_rm_agg_cfg_tc: 2579 return status; 2580 } 2581 2582 /** 2583 * ice_save_agg_tc_bitmap - save aggregator TC bitmap 2584 * @pi: port information structure 2585 * @agg_id: aggregator ID 2586 * @tc_bitmap: 8 bits TC bitmap 2587 * 2588 * Save aggregator TC bitmap. This function needs to be called with scheduler 2589 * lock held. 2590 */ 2591 static enum ice_status 2592 ice_save_agg_tc_bitmap(struct ice_port_info *pi, u32 agg_id, 2593 ice_bitmap_t *tc_bitmap) 2594 { 2595 struct ice_sched_agg_info *agg_info; 2596 2597 agg_info = ice_get_agg_info(pi->hw, agg_id); 2598 if (!agg_info) 2599 return ICE_ERR_PARAM; 2600 ice_cp_bitmap(agg_info->replay_tc_bitmap, tc_bitmap, 2601 ICE_MAX_TRAFFIC_CLASS); 2602 return ICE_SUCCESS; 2603 } 2604 2605 /** 2606 * ice_sched_add_agg_cfg - create an aggregator node 2607 * @pi: port information structure 2608 * @agg_id: aggregator ID 2609 * @tc: TC number 2610 * 2611 * This function creates an aggregator node and intermediate nodes if required 2612 * for the given TC 2613 */ 2614 static enum ice_status 2615 ice_sched_add_agg_cfg(struct ice_port_info *pi, u32 agg_id, u8 tc) 2616 { 2617 struct ice_sched_node *parent, *agg_node, *tc_node; 2618 u16 num_nodes[ICE_AQC_TOPO_MAX_LEVEL_NUM] = { 0 }; 2619 enum ice_status status = ICE_SUCCESS; 2620 struct ice_hw *hw = pi->hw; 2621 u32 first_node_teid; 2622 u16 num_nodes_added; 2623 u8 i, aggl; 2624 2625 tc_node = ice_sched_get_tc_node(pi, tc); 2626 if (!tc_node) 2627 return ICE_ERR_CFG; 2628 2629 agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); 2630 /* Does Agg node already exist ? */ 2631 if (agg_node) 2632 return status; 2633 2634 aggl = ice_sched_get_agg_layer(hw); 2635 2636 /* need one node in Agg layer */ 2637 num_nodes[aggl] = 1; 2638 2639 /* Check whether the intermediate nodes have space to add the 2640 * new aggregator. If they are full, then SW needs to allocate a new 2641 * intermediate node on those layers 2642 */ 2643 for (i = hw->sw_entry_point_layer; i < aggl; i++) { 2644 parent = ice_sched_get_first_node(pi, tc_node, i); 2645 2646 /* scan all the siblings */ 2647 while (parent) { 2648 if (parent->num_children < hw->max_children[i]) 2649 break; 2650 parent = parent->sibling; 2651 } 2652 2653 /* all the nodes are full, reserve one for this layer */ 2654 if (!parent) 2655 num_nodes[i]++; 2656 } 2657 2658 /* add the aggregator node */ 2659 parent = tc_node; 2660 for (i = hw->sw_entry_point_layer; i <= aggl; i++) { 2661 if (!parent) 2662 return ICE_ERR_CFG; 2663 2664 status = ice_sched_add_nodes_to_layer(pi, tc_node, parent, i, 2665 num_nodes[i], 2666 &first_node_teid, 2667 &num_nodes_added); 2668 if (status != ICE_SUCCESS || num_nodes[i] != num_nodes_added) 2669 return ICE_ERR_CFG; 2670 2671 /* The newly added node can be a new parent for the next 2672 * layer nodes 2673 */ 2674 if (num_nodes_added) { 2675 parent = ice_sched_find_node_by_teid(tc_node, 2676 first_node_teid); 2677 /* register aggregator ID with the aggregator node */ 2678 if (parent && i == aggl) 2679 parent->agg_id = agg_id; 2680 } else { 2681 parent = parent->children[0]; 2682 } 2683 } 2684 2685 return ICE_SUCCESS; 2686 } 2687 2688 /** 2689 * ice_sched_cfg_agg - configure aggregator node 2690 * @pi: port information structure 2691 * @agg_id: aggregator ID 2692 * @agg_type: aggregator type queue, VSI, or aggregator group 2693 * @tc_bitmap: bits TC bitmap 2694 * 2695 * It registers a unique aggregator node into scheduler services. It 2696 * allows a user to register with a unique ID to track it's resources. 2697 * The aggregator type determines if this is a queue group, VSI group 2698 * or aggregator group. It then creates the aggregator node(s) for requested 2699 * TC(s) or removes an existing aggregator node including its configuration 2700 * if indicated via tc_bitmap. Call ice_rm_agg_cfg to release aggregator 2701 * resources and remove aggregator ID. 2702 * This function needs to be called with scheduler lock held. 2703 */ 2704 static enum ice_status 2705 ice_sched_cfg_agg(struct ice_port_info *pi, u32 agg_id, 2706 enum ice_agg_type agg_type, ice_bitmap_t *tc_bitmap) 2707 { 2708 struct ice_sched_agg_info *agg_info; 2709 enum ice_status status = ICE_SUCCESS; 2710 struct ice_hw *hw = pi->hw; 2711 u8 tc; 2712 2713 agg_info = ice_get_agg_info(hw, agg_id); 2714 if (!agg_info) { 2715 /* Create new entry for new aggregator ID */ 2716 agg_info = (struct ice_sched_agg_info *) 2717 ice_malloc(hw, sizeof(*agg_info)); 2718 if (!agg_info) 2719 return ICE_ERR_NO_MEMORY; 2720 2721 agg_info->agg_id = agg_id; 2722 agg_info->agg_type = agg_type; 2723 agg_info->tc_bitmap[0] = 0; 2724 2725 /* Initialize the aggregator VSI list head */ 2726 INIT_LIST_HEAD(&agg_info->agg_vsi_list); 2727 2728 /* Add new entry in aggregator list */ 2729 LIST_ADD(&agg_info->list_entry, &hw->agg_list); 2730 } 2731 /* Create aggregator node(s) for requested TC(s) */ 2732 ice_for_each_traffic_class(tc) { 2733 if (!ice_is_tc_ena(*tc_bitmap, tc)) { 2734 /* Delete aggregator cfg TC if it exists previously */ 2735 status = ice_rm_agg_cfg_tc(pi, agg_info, tc, false); 2736 if (status) 2737 break; 2738 continue; 2739 } 2740 2741 /* Check if aggregator node for TC already exists */ 2742 if (ice_is_tc_ena(agg_info->tc_bitmap[0], tc)) 2743 continue; 2744 2745 /* Create new aggregator node for TC */ 2746 status = ice_sched_add_agg_cfg(pi, agg_id, tc); 2747 if (status) 2748 break; 2749 2750 /* Save aggregator node's TC information */ 2751 ice_set_bit(tc, agg_info->tc_bitmap); 2752 } 2753 2754 return status; 2755 } 2756 2757 /** 2758 * ice_cfg_agg - config aggregator node 2759 * @pi: port information structure 2760 * @agg_id: aggregator ID 2761 * @agg_type: aggregator type queue, VSI, or aggregator group 2762 * @tc_bitmap: bits TC bitmap 2763 * 2764 * This function configures aggregator node(s). 2765 */ 2766 enum ice_status 2767 ice_cfg_agg(struct ice_port_info *pi, u32 agg_id, enum ice_agg_type agg_type, 2768 u8 tc_bitmap) 2769 { 2770 ice_bitmap_t bitmap = tc_bitmap; 2771 enum ice_status status; 2772 2773 ice_acquire_lock(&pi->sched_lock); 2774 status = ice_sched_cfg_agg(pi, agg_id, agg_type, 2775 (ice_bitmap_t *)&bitmap); 2776 if (!status) 2777 status = ice_save_agg_tc_bitmap(pi, agg_id, 2778 (ice_bitmap_t *)&bitmap); 2779 ice_release_lock(&pi->sched_lock); 2780 return status; 2781 } 2782 2783 /** 2784 * ice_get_agg_vsi_info - get the aggregator ID 2785 * @agg_info: aggregator info 2786 * @vsi_handle: software VSI handle 2787 * 2788 * The function returns aggregator VSI info based on VSI handle. This function 2789 * needs to be called with scheduler lock held. 2790 */ 2791 static struct ice_sched_agg_vsi_info * 2792 ice_get_agg_vsi_info(struct ice_sched_agg_info *agg_info, u16 vsi_handle) 2793 { 2794 struct ice_sched_agg_vsi_info *agg_vsi_info; 2795 2796 LIST_FOR_EACH_ENTRY(agg_vsi_info, &agg_info->agg_vsi_list, 2797 ice_sched_agg_vsi_info, list_entry) 2798 if (agg_vsi_info->vsi_handle == vsi_handle) 2799 return agg_vsi_info; 2800 2801 return NULL; 2802 } 2803 2804 /** 2805 * ice_get_vsi_agg_info - get the aggregator info of VSI 2806 * @hw: pointer to the hardware structure 2807 * @vsi_handle: Sw VSI handle 2808 * 2809 * The function returns aggregator info of VSI represented via vsi_handle. The 2810 * VSI has in this case a different aggregator than the default one. This 2811 * function needs to be called with scheduler lock held. 2812 */ 2813 static struct ice_sched_agg_info * 2814 ice_get_vsi_agg_info(struct ice_hw *hw, u16 vsi_handle) 2815 { 2816 struct ice_sched_agg_info *agg_info; 2817 2818 LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info, 2819 list_entry) { 2820 struct ice_sched_agg_vsi_info *agg_vsi_info; 2821 2822 agg_vsi_info = ice_get_agg_vsi_info(agg_info, vsi_handle); 2823 if (agg_vsi_info) 2824 return agg_info; 2825 } 2826 return NULL; 2827 } 2828 2829 /** 2830 * ice_save_agg_vsi_tc_bitmap - save aggregator VSI TC bitmap 2831 * @pi: port information structure 2832 * @agg_id: aggregator ID 2833 * @vsi_handle: software VSI handle 2834 * @tc_bitmap: TC bitmap of enabled TC(s) 2835 * 2836 * Save VSI to aggregator TC bitmap. This function needs to call with scheduler 2837 * lock held. 2838 */ 2839 static enum ice_status 2840 ice_save_agg_vsi_tc_bitmap(struct ice_port_info *pi, u32 agg_id, u16 vsi_handle, 2841 ice_bitmap_t *tc_bitmap) 2842 { 2843 struct ice_sched_agg_vsi_info *agg_vsi_info; 2844 struct ice_sched_agg_info *agg_info; 2845 2846 agg_info = ice_get_agg_info(pi->hw, agg_id); 2847 if (!agg_info) 2848 return ICE_ERR_PARAM; 2849 /* check if entry already exist */ 2850 agg_vsi_info = ice_get_agg_vsi_info(agg_info, vsi_handle); 2851 if (!agg_vsi_info) 2852 return ICE_ERR_PARAM; 2853 ice_cp_bitmap(agg_vsi_info->replay_tc_bitmap, tc_bitmap, 2854 ICE_MAX_TRAFFIC_CLASS); 2855 return ICE_SUCCESS; 2856 } 2857 2858 /** 2859 * ice_sched_assoc_vsi_to_agg - associate/move VSI to new/default aggregator 2860 * @pi: port information structure 2861 * @agg_id: aggregator ID 2862 * @vsi_handle: software VSI handle 2863 * @tc_bitmap: TC bitmap of enabled TC(s) 2864 * 2865 * This function moves VSI to a new or default aggregator node. If VSI is 2866 * already associated to the aggregator node then no operation is performed on 2867 * the tree. This function needs to be called with scheduler lock held. 2868 */ 2869 static enum ice_status 2870 ice_sched_assoc_vsi_to_agg(struct ice_port_info *pi, u32 agg_id, 2871 u16 vsi_handle, ice_bitmap_t *tc_bitmap) 2872 { 2873 struct ice_sched_agg_vsi_info *agg_vsi_info; 2874 struct ice_sched_agg_info *agg_info; 2875 enum ice_status status = ICE_SUCCESS; 2876 struct ice_hw *hw = pi->hw; 2877 u8 tc; 2878 2879 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 2880 return ICE_ERR_PARAM; 2881 agg_info = ice_get_agg_info(hw, agg_id); 2882 if (!agg_info) 2883 return ICE_ERR_PARAM; 2884 /* check if entry already exist */ 2885 agg_vsi_info = ice_get_agg_vsi_info(agg_info, vsi_handle); 2886 if (!agg_vsi_info) { 2887 /* Create new entry for VSI under aggregator list */ 2888 agg_vsi_info = (struct ice_sched_agg_vsi_info *) 2889 ice_malloc(hw, sizeof(*agg_vsi_info)); 2890 if (!agg_vsi_info) 2891 return ICE_ERR_PARAM; 2892 2893 /* add VSI ID into the aggregator list */ 2894 agg_vsi_info->vsi_handle = vsi_handle; 2895 LIST_ADD(&agg_vsi_info->list_entry, &agg_info->agg_vsi_list); 2896 } 2897 /* Move VSI node to new aggregator node for requested TC(s) */ 2898 ice_for_each_traffic_class(tc) { 2899 if (!ice_is_tc_ena(*tc_bitmap, tc)) 2900 continue; 2901 2902 /* Move VSI to new aggregator */ 2903 status = ice_sched_move_vsi_to_agg(pi, vsi_handle, agg_id, tc); 2904 if (status) 2905 break; 2906 2907 ice_set_bit(tc, agg_vsi_info->tc_bitmap); 2908 } 2909 return status; 2910 } 2911 2912 /** 2913 * ice_sched_rm_unused_rl_prof - remove unused RL profile 2914 * @hw: pointer to the hardware structure 2915 * 2916 * This function removes unused rate limit profiles from the HW and 2917 * SW DB. The caller needs to hold scheduler lock. 2918 */ 2919 static void ice_sched_rm_unused_rl_prof(struct ice_hw *hw) 2920 { 2921 u16 ln; 2922 2923 for (ln = 0; ln < hw->num_tx_sched_layers; ln++) { 2924 struct ice_aqc_rl_profile_info *rl_prof_elem; 2925 struct ice_aqc_rl_profile_info *rl_prof_tmp; 2926 2927 LIST_FOR_EACH_ENTRY_SAFE(rl_prof_elem, rl_prof_tmp, 2928 &hw->rl_prof_list[ln], 2929 ice_aqc_rl_profile_info, list_entry) { 2930 if (!ice_sched_del_rl_profile(hw, rl_prof_elem)) 2931 ice_debug(hw, ICE_DBG_SCHED, "Removed rl profile\n"); 2932 } 2933 } 2934 } 2935 2936 /** 2937 * ice_sched_update_elem - update element 2938 * @hw: pointer to the HW struct 2939 * @node: pointer to node 2940 * @info: node info to update 2941 * 2942 * Update the HW DB, and local SW DB of node. Update the scheduling 2943 * parameters of node from argument info data buffer (Info->data buf) and 2944 * returns success or error on config sched element failure. The caller 2945 * needs to hold scheduler lock. 2946 */ 2947 static enum ice_status 2948 ice_sched_update_elem(struct ice_hw *hw, struct ice_sched_node *node, 2949 struct ice_aqc_txsched_elem_data *info) 2950 { 2951 struct ice_aqc_txsched_elem_data buf; 2952 enum ice_status status; 2953 u16 elem_cfgd = 0; 2954 u16 num_elems = 1; 2955 2956 buf = *info; 2957 /* Parent TEID is reserved field in this aq call */ 2958 buf.parent_teid = 0; 2959 /* Element type is reserved field in this aq call */ 2960 buf.data.elem_type = 0; 2961 /* Flags is reserved field in this aq call */ 2962 buf.data.flags = 0; 2963 2964 /* Update HW DB */ 2965 /* Configure element node */ 2966 status = ice_aq_cfg_sched_elems(hw, num_elems, &buf, sizeof(buf), 2967 &elem_cfgd, NULL); 2968 if (status || elem_cfgd != num_elems) { 2969 ice_debug(hw, ICE_DBG_SCHED, "Config sched elem error\n"); 2970 return ICE_ERR_CFG; 2971 } 2972 2973 /* Config success case */ 2974 /* Now update local SW DB */ 2975 /* Only copy the data portion of info buffer */ 2976 node->info.data = info->data; 2977 return status; 2978 } 2979 2980 /** 2981 * ice_sched_cfg_node_bw_alloc - configure node BW weight/alloc params 2982 * @hw: pointer to the HW struct 2983 * @node: sched node to configure 2984 * @rl_type: rate limit type CIR, EIR, or shared 2985 * @bw_alloc: BW weight/allocation 2986 * 2987 * This function configures node element's BW allocation. 2988 */ 2989 static enum ice_status 2990 ice_sched_cfg_node_bw_alloc(struct ice_hw *hw, struct ice_sched_node *node, 2991 enum ice_rl_type rl_type, u16 bw_alloc) 2992 { 2993 struct ice_aqc_txsched_elem_data buf; 2994 struct ice_aqc_txsched_elem *data; 2995 enum ice_status status; 2996 2997 buf = node->info; 2998 data = &buf.data; 2999 if (rl_type == ICE_MIN_BW) { 3000 data->valid_sections |= ICE_AQC_ELEM_VALID_CIR; 3001 data->cir_bw.bw_alloc = CPU_TO_LE16(bw_alloc); 3002 } else if (rl_type == ICE_MAX_BW) { 3003 data->valid_sections |= ICE_AQC_ELEM_VALID_EIR; 3004 data->eir_bw.bw_alloc = CPU_TO_LE16(bw_alloc); 3005 } else { 3006 return ICE_ERR_PARAM; 3007 } 3008 3009 /* Configure element */ 3010 status = ice_sched_update_elem(hw, node, &buf); 3011 return status; 3012 } 3013 3014 /** 3015 * ice_move_vsi_to_agg - moves VSI to new or default aggregator 3016 * @pi: port information structure 3017 * @agg_id: aggregator ID 3018 * @vsi_handle: software VSI handle 3019 * @tc_bitmap: TC bitmap of enabled TC(s) 3020 * 3021 * Move or associate VSI to a new or default aggregator node. 3022 */ 3023 enum ice_status 3024 ice_move_vsi_to_agg(struct ice_port_info *pi, u32 agg_id, u16 vsi_handle, 3025 u8 tc_bitmap) 3026 { 3027 ice_bitmap_t bitmap = tc_bitmap; 3028 enum ice_status status; 3029 3030 ice_acquire_lock(&pi->sched_lock); 3031 status = ice_sched_assoc_vsi_to_agg(pi, agg_id, vsi_handle, 3032 (ice_bitmap_t *)&bitmap); 3033 if (!status) 3034 status = ice_save_agg_vsi_tc_bitmap(pi, agg_id, vsi_handle, 3035 (ice_bitmap_t *)&bitmap); 3036 ice_release_lock(&pi->sched_lock); 3037 return status; 3038 } 3039 3040 /** 3041 * ice_rm_agg_cfg - remove aggregator configuration 3042 * @pi: port information structure 3043 * @agg_id: aggregator ID 3044 * 3045 * This function removes aggregator reference to VSI and delete aggregator ID 3046 * info. It removes the aggregator configuration completely. 3047 */ 3048 enum ice_status ice_rm_agg_cfg(struct ice_port_info *pi, u32 agg_id) 3049 { 3050 struct ice_sched_agg_info *agg_info; 3051 enum ice_status status = ICE_SUCCESS; 3052 u8 tc; 3053 3054 ice_acquire_lock(&pi->sched_lock); 3055 agg_info = ice_get_agg_info(pi->hw, agg_id); 3056 if (!agg_info) { 3057 status = ICE_ERR_DOES_NOT_EXIST; 3058 goto exit_ice_rm_agg_cfg; 3059 } 3060 3061 ice_for_each_traffic_class(tc) { 3062 status = ice_rm_agg_cfg_tc(pi, agg_info, tc, true); 3063 if (status) 3064 goto exit_ice_rm_agg_cfg; 3065 } 3066 3067 if (ice_is_any_bit_set(agg_info->tc_bitmap, ICE_MAX_TRAFFIC_CLASS)) { 3068 status = ICE_ERR_IN_USE; 3069 goto exit_ice_rm_agg_cfg; 3070 } 3071 3072 /* Safe to delete entry now */ 3073 LIST_DEL(&agg_info->list_entry); 3074 ice_free(pi->hw, agg_info); 3075 3076 /* Remove unused RL profile IDs from HW and SW DB */ 3077 ice_sched_rm_unused_rl_prof(pi->hw); 3078 3079 exit_ice_rm_agg_cfg: 3080 ice_release_lock(&pi->sched_lock); 3081 return status; 3082 } 3083 3084 /** 3085 * ice_set_clear_cir_bw_alloc - set or clear CIR BW alloc information 3086 * @bw_t_info: bandwidth type information structure 3087 * @bw_alloc: Bandwidth allocation information 3088 * 3089 * Save or clear CIR BW alloc information (bw_alloc) in the passed param 3090 * bw_t_info. 3091 */ 3092 static void 3093 ice_set_clear_cir_bw_alloc(struct ice_bw_type_info *bw_t_info, u16 bw_alloc) 3094 { 3095 bw_t_info->cir_bw.bw_alloc = bw_alloc; 3096 if (bw_t_info->cir_bw.bw_alloc) 3097 ice_set_bit(ICE_BW_TYPE_CIR_WT, bw_t_info->bw_t_bitmap); 3098 else 3099 ice_clear_bit(ICE_BW_TYPE_CIR_WT, bw_t_info->bw_t_bitmap); 3100 } 3101 3102 /** 3103 * ice_set_clear_eir_bw_alloc - set or clear EIR BW alloc information 3104 * @bw_t_info: bandwidth type information structure 3105 * @bw_alloc: Bandwidth allocation information 3106 * 3107 * Save or clear EIR BW alloc information (bw_alloc) in the passed param 3108 * bw_t_info. 3109 */ 3110 static void 3111 ice_set_clear_eir_bw_alloc(struct ice_bw_type_info *bw_t_info, u16 bw_alloc) 3112 { 3113 bw_t_info->eir_bw.bw_alloc = bw_alloc; 3114 if (bw_t_info->eir_bw.bw_alloc) 3115 ice_set_bit(ICE_BW_TYPE_EIR_WT, bw_t_info->bw_t_bitmap); 3116 else 3117 ice_clear_bit(ICE_BW_TYPE_EIR_WT, bw_t_info->bw_t_bitmap); 3118 } 3119 3120 /** 3121 * ice_sched_save_vsi_bw_alloc - save VSI node's BW alloc information 3122 * @pi: port information structure 3123 * @vsi_handle: sw VSI handle 3124 * @tc: traffic class 3125 * @rl_type: rate limit type min or max 3126 * @bw_alloc: Bandwidth allocation information 3127 * 3128 * Save BW alloc information of VSI type node for post replay use. 3129 */ 3130 static enum ice_status 3131 ice_sched_save_vsi_bw_alloc(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 3132 enum ice_rl_type rl_type, u16 bw_alloc) 3133 { 3134 struct ice_vsi_ctx *vsi_ctx; 3135 3136 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 3137 return ICE_ERR_PARAM; 3138 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 3139 if (!vsi_ctx) 3140 return ICE_ERR_PARAM; 3141 switch (rl_type) { 3142 case ICE_MIN_BW: 3143 ice_set_clear_cir_bw_alloc(&vsi_ctx->sched.bw_t_info[tc], 3144 bw_alloc); 3145 break; 3146 case ICE_MAX_BW: 3147 ice_set_clear_eir_bw_alloc(&vsi_ctx->sched.bw_t_info[tc], 3148 bw_alloc); 3149 break; 3150 default: 3151 return ICE_ERR_PARAM; 3152 } 3153 return ICE_SUCCESS; 3154 } 3155 3156 /** 3157 * ice_set_clear_cir_bw - set or clear CIR BW 3158 * @bw_t_info: bandwidth type information structure 3159 * @bw: bandwidth in Kbps - Kilo bits per sec 3160 * 3161 * Save or clear CIR bandwidth (BW) in the passed param bw_t_info. 3162 */ 3163 static void ice_set_clear_cir_bw(struct ice_bw_type_info *bw_t_info, u32 bw) 3164 { 3165 if (bw == ICE_SCHED_DFLT_BW) { 3166 ice_clear_bit(ICE_BW_TYPE_CIR, bw_t_info->bw_t_bitmap); 3167 bw_t_info->cir_bw.bw = 0; 3168 } else { 3169 /* Save type of BW information */ 3170 ice_set_bit(ICE_BW_TYPE_CIR, bw_t_info->bw_t_bitmap); 3171 bw_t_info->cir_bw.bw = bw; 3172 } 3173 } 3174 3175 /** 3176 * ice_set_clear_eir_bw - set or clear EIR BW 3177 * @bw_t_info: bandwidth type information structure 3178 * @bw: bandwidth in Kbps - Kilo bits per sec 3179 * 3180 * Save or clear EIR bandwidth (BW) in the passed param bw_t_info. 3181 */ 3182 static void ice_set_clear_eir_bw(struct ice_bw_type_info *bw_t_info, u32 bw) 3183 { 3184 if (bw == ICE_SCHED_DFLT_BW) { 3185 ice_clear_bit(ICE_BW_TYPE_EIR, bw_t_info->bw_t_bitmap); 3186 bw_t_info->eir_bw.bw = 0; 3187 } else { 3188 /* save EIR BW information */ 3189 ice_set_bit(ICE_BW_TYPE_EIR, bw_t_info->bw_t_bitmap); 3190 bw_t_info->eir_bw.bw = bw; 3191 } 3192 } 3193 3194 /** 3195 * ice_set_clear_shared_bw - set or clear shared BW 3196 * @bw_t_info: bandwidth type information structure 3197 * @bw: bandwidth in Kbps - Kilo bits per sec 3198 * 3199 * Save or clear shared bandwidth (BW) in the passed param bw_t_info. 3200 */ 3201 static void ice_set_clear_shared_bw(struct ice_bw_type_info *bw_t_info, u32 bw) 3202 { 3203 if (bw == ICE_SCHED_DFLT_BW) { 3204 ice_clear_bit(ICE_BW_TYPE_SHARED, bw_t_info->bw_t_bitmap); 3205 bw_t_info->shared_bw = 0; 3206 } else { 3207 /* save shared BW information */ 3208 ice_set_bit(ICE_BW_TYPE_SHARED, bw_t_info->bw_t_bitmap); 3209 bw_t_info->shared_bw = bw; 3210 } 3211 } 3212 3213 /** 3214 * ice_sched_save_vsi_bw - save VSI node's BW information 3215 * @pi: port information structure 3216 * @vsi_handle: sw VSI handle 3217 * @tc: traffic class 3218 * @rl_type: rate limit type min, max, or shared 3219 * @bw: bandwidth in Kbps - Kilo bits per sec 3220 * 3221 * Save BW information of VSI type node for post replay use. 3222 */ 3223 static enum ice_status 3224 ice_sched_save_vsi_bw(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 3225 enum ice_rl_type rl_type, u32 bw) 3226 { 3227 struct ice_vsi_ctx *vsi_ctx; 3228 3229 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 3230 return ICE_ERR_PARAM; 3231 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 3232 if (!vsi_ctx) 3233 return ICE_ERR_PARAM; 3234 switch (rl_type) { 3235 case ICE_MIN_BW: 3236 ice_set_clear_cir_bw(&vsi_ctx->sched.bw_t_info[tc], bw); 3237 break; 3238 case ICE_MAX_BW: 3239 ice_set_clear_eir_bw(&vsi_ctx->sched.bw_t_info[tc], bw); 3240 break; 3241 case ICE_SHARED_BW: 3242 ice_set_clear_shared_bw(&vsi_ctx->sched.bw_t_info[tc], bw); 3243 break; 3244 default: 3245 return ICE_ERR_PARAM; 3246 } 3247 return ICE_SUCCESS; 3248 } 3249 3250 /** 3251 * ice_set_clear_prio - set or clear priority information 3252 * @bw_t_info: bandwidth type information structure 3253 * @prio: priority to save 3254 * 3255 * Save or clear priority (prio) in the passed param bw_t_info. 3256 */ 3257 static void ice_set_clear_prio(struct ice_bw_type_info *bw_t_info, u8 prio) 3258 { 3259 bw_t_info->generic = prio; 3260 if (bw_t_info->generic) 3261 ice_set_bit(ICE_BW_TYPE_PRIO, bw_t_info->bw_t_bitmap); 3262 else 3263 ice_clear_bit(ICE_BW_TYPE_PRIO, bw_t_info->bw_t_bitmap); 3264 } 3265 3266 /** 3267 * ice_sched_save_vsi_prio - save VSI node's priority information 3268 * @pi: port information structure 3269 * @vsi_handle: Software VSI handle 3270 * @tc: traffic class 3271 * @prio: priority to save 3272 * 3273 * Save priority information of VSI type node for post replay use. 3274 */ 3275 static enum ice_status 3276 ice_sched_save_vsi_prio(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 3277 u8 prio) 3278 { 3279 struct ice_vsi_ctx *vsi_ctx; 3280 3281 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 3282 return ICE_ERR_PARAM; 3283 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 3284 if (!vsi_ctx) 3285 return ICE_ERR_PARAM; 3286 if (tc >= ICE_MAX_TRAFFIC_CLASS) 3287 return ICE_ERR_PARAM; 3288 ice_set_clear_prio(&vsi_ctx->sched.bw_t_info[tc], prio); 3289 return ICE_SUCCESS; 3290 } 3291 3292 /** 3293 * ice_sched_save_agg_bw_alloc - save aggregator node's BW alloc information 3294 * @pi: port information structure 3295 * @agg_id: node aggregator ID 3296 * @tc: traffic class 3297 * @rl_type: rate limit type min or max 3298 * @bw_alloc: bandwidth alloc information 3299 * 3300 * Save BW alloc information of AGG type node for post replay use. 3301 */ 3302 static enum ice_status 3303 ice_sched_save_agg_bw_alloc(struct ice_port_info *pi, u32 agg_id, u8 tc, 3304 enum ice_rl_type rl_type, u16 bw_alloc) 3305 { 3306 struct ice_sched_agg_info *agg_info; 3307 3308 agg_info = ice_get_agg_info(pi->hw, agg_id); 3309 if (!agg_info) 3310 return ICE_ERR_PARAM; 3311 if (!ice_is_tc_ena(agg_info->tc_bitmap[0], tc)) 3312 return ICE_ERR_PARAM; 3313 switch (rl_type) { 3314 case ICE_MIN_BW: 3315 ice_set_clear_cir_bw_alloc(&agg_info->bw_t_info[tc], bw_alloc); 3316 break; 3317 case ICE_MAX_BW: 3318 ice_set_clear_eir_bw_alloc(&agg_info->bw_t_info[tc], bw_alloc); 3319 break; 3320 default: 3321 return ICE_ERR_PARAM; 3322 } 3323 return ICE_SUCCESS; 3324 } 3325 3326 /** 3327 * ice_sched_save_agg_bw - save aggregator node's BW information 3328 * @pi: port information structure 3329 * @agg_id: node aggregator ID 3330 * @tc: traffic class 3331 * @rl_type: rate limit type min, max, or shared 3332 * @bw: bandwidth in Kbps - Kilo bits per sec 3333 * 3334 * Save BW information of AGG type node for post replay use. 3335 */ 3336 static enum ice_status 3337 ice_sched_save_agg_bw(struct ice_port_info *pi, u32 agg_id, u8 tc, 3338 enum ice_rl_type rl_type, u32 bw) 3339 { 3340 struct ice_sched_agg_info *agg_info; 3341 3342 agg_info = ice_get_agg_info(pi->hw, agg_id); 3343 if (!agg_info) 3344 return ICE_ERR_PARAM; 3345 if (!ice_is_tc_ena(agg_info->tc_bitmap[0], tc)) 3346 return ICE_ERR_PARAM; 3347 switch (rl_type) { 3348 case ICE_MIN_BW: 3349 ice_set_clear_cir_bw(&agg_info->bw_t_info[tc], bw); 3350 break; 3351 case ICE_MAX_BW: 3352 ice_set_clear_eir_bw(&agg_info->bw_t_info[tc], bw); 3353 break; 3354 case ICE_SHARED_BW: 3355 ice_set_clear_shared_bw(&agg_info->bw_t_info[tc], bw); 3356 break; 3357 default: 3358 return ICE_ERR_PARAM; 3359 } 3360 return ICE_SUCCESS; 3361 } 3362 3363 /** 3364 * ice_cfg_vsi_bw_lmt_per_tc - configure VSI BW limit per TC 3365 * @pi: port information structure 3366 * @vsi_handle: software VSI handle 3367 * @tc: traffic class 3368 * @rl_type: min or max 3369 * @bw: bandwidth in Kbps 3370 * 3371 * This function configures BW limit of VSI scheduling node based on TC 3372 * information. 3373 */ 3374 enum ice_status 3375 ice_cfg_vsi_bw_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 3376 enum ice_rl_type rl_type, u32 bw) 3377 { 3378 enum ice_status status; 3379 3380 status = ice_sched_set_node_bw_lmt_per_tc(pi, vsi_handle, 3381 ICE_AGG_TYPE_VSI, 3382 tc, rl_type, bw); 3383 if (!status) { 3384 ice_acquire_lock(&pi->sched_lock); 3385 status = ice_sched_save_vsi_bw(pi, vsi_handle, tc, rl_type, bw); 3386 ice_release_lock(&pi->sched_lock); 3387 } 3388 return status; 3389 } 3390 3391 /** 3392 * ice_cfg_dflt_vsi_bw_lmt_per_tc - configure default VSI BW limit per TC 3393 * @pi: port information structure 3394 * @vsi_handle: software VSI handle 3395 * @tc: traffic class 3396 * @rl_type: min or max 3397 * 3398 * This function configures default BW limit of VSI scheduling node based on TC 3399 * information. 3400 */ 3401 enum ice_status 3402 ice_cfg_vsi_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 3403 enum ice_rl_type rl_type) 3404 { 3405 enum ice_status status; 3406 3407 status = ice_sched_set_node_bw_lmt_per_tc(pi, vsi_handle, 3408 ICE_AGG_TYPE_VSI, 3409 tc, rl_type, 3410 ICE_SCHED_DFLT_BW); 3411 if (!status) { 3412 ice_acquire_lock(&pi->sched_lock); 3413 status = ice_sched_save_vsi_bw(pi, vsi_handle, tc, rl_type, 3414 ICE_SCHED_DFLT_BW); 3415 ice_release_lock(&pi->sched_lock); 3416 } 3417 return status; 3418 } 3419 3420 /** 3421 * ice_cfg_agg_bw_lmt_per_tc - configure aggregator BW limit per TC 3422 * @pi: port information structure 3423 * @agg_id: aggregator ID 3424 * @tc: traffic class 3425 * @rl_type: min or max 3426 * @bw: bandwidth in Kbps 3427 * 3428 * This function applies BW limit to aggregator scheduling node based on TC 3429 * information. 3430 */ 3431 enum ice_status 3432 ice_cfg_agg_bw_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc, 3433 enum ice_rl_type rl_type, u32 bw) 3434 { 3435 enum ice_status status; 3436 3437 status = ice_sched_set_node_bw_lmt_per_tc(pi, agg_id, ICE_AGG_TYPE_AGG, 3438 tc, rl_type, bw); 3439 if (!status) { 3440 ice_acquire_lock(&pi->sched_lock); 3441 status = ice_sched_save_agg_bw(pi, agg_id, tc, rl_type, bw); 3442 ice_release_lock(&pi->sched_lock); 3443 } 3444 return status; 3445 } 3446 3447 /** 3448 * ice_cfg_agg_bw_dflt_lmt_per_tc - configure aggregator BW default limit per TC 3449 * @pi: port information structure 3450 * @agg_id: aggregator ID 3451 * @tc: traffic class 3452 * @rl_type: min or max 3453 * 3454 * This function applies default BW limit to aggregator scheduling node based 3455 * on TC information. 3456 */ 3457 enum ice_status 3458 ice_cfg_agg_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc, 3459 enum ice_rl_type rl_type) 3460 { 3461 enum ice_status status; 3462 3463 status = ice_sched_set_node_bw_lmt_per_tc(pi, agg_id, ICE_AGG_TYPE_AGG, 3464 tc, rl_type, 3465 ICE_SCHED_DFLT_BW); 3466 if (!status) { 3467 ice_acquire_lock(&pi->sched_lock); 3468 status = ice_sched_save_agg_bw(pi, agg_id, tc, rl_type, 3469 ICE_SCHED_DFLT_BW); 3470 ice_release_lock(&pi->sched_lock); 3471 } 3472 return status; 3473 } 3474 3475 /** 3476 * ice_cfg_vsi_bw_shared_lmt - configure VSI BW shared limit 3477 * @pi: port information structure 3478 * @vsi_handle: software VSI handle 3479 * @min_bw: minimum bandwidth in Kbps 3480 * @max_bw: maximum bandwidth in Kbps 3481 * @shared_bw: shared bandwidth in Kbps 3482 * 3483 * Configure shared rate limiter(SRL) of all VSI type nodes across all traffic 3484 * classes for VSI matching handle. 3485 */ 3486 enum ice_status 3487 ice_cfg_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle, u32 min_bw, 3488 u32 max_bw, u32 shared_bw) 3489 { 3490 return ice_sched_set_vsi_bw_shared_lmt(pi, vsi_handle, min_bw, max_bw, 3491 shared_bw); 3492 } 3493 3494 /** 3495 * ice_cfg_vsi_bw_no_shared_lmt - configure VSI BW for no shared limiter 3496 * @pi: port information structure 3497 * @vsi_handle: software VSI handle 3498 * 3499 * This function removes the shared rate limiter(SRL) of all VSI type nodes 3500 * across all traffic classes for VSI matching handle. 3501 */ 3502 enum ice_status 3503 ice_cfg_vsi_bw_no_shared_lmt(struct ice_port_info *pi, u16 vsi_handle) 3504 { 3505 return ice_sched_set_vsi_bw_shared_lmt(pi, vsi_handle, 3506 ICE_SCHED_DFLT_BW, 3507 ICE_SCHED_DFLT_BW, 3508 ICE_SCHED_DFLT_BW); 3509 } 3510 3511 /** 3512 * ice_cfg_agg_bw_shared_lmt - configure aggregator BW shared limit 3513 * @pi: port information structure 3514 * @agg_id: aggregator ID 3515 * @min_bw: minimum bandwidth in Kbps 3516 * @max_bw: maximum bandwidth in Kbps 3517 * @shared_bw: shared bandwidth in Kbps 3518 * 3519 * This function configures the shared rate limiter(SRL) of all aggregator type 3520 * nodes across all traffic classes for aggregator matching agg_id. 3521 */ 3522 enum ice_status 3523 ice_cfg_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, u32 min_bw, 3524 u32 max_bw, u32 shared_bw) 3525 { 3526 return ice_sched_set_agg_bw_shared_lmt(pi, agg_id, min_bw, max_bw, 3527 shared_bw); 3528 } 3529 3530 /** 3531 * ice_cfg_agg_bw_no_shared_lmt - configure aggregator BW for no shared limiter 3532 * @pi: port information structure 3533 * @agg_id: aggregator ID 3534 * 3535 * This function removes the shared rate limiter(SRL) of all aggregator type 3536 * nodes across all traffic classes for aggregator matching agg_id. 3537 */ 3538 enum ice_status 3539 ice_cfg_agg_bw_no_shared_lmt(struct ice_port_info *pi, u32 agg_id) 3540 { 3541 return ice_sched_set_agg_bw_shared_lmt(pi, agg_id, ICE_SCHED_DFLT_BW, 3542 ICE_SCHED_DFLT_BW, 3543 ICE_SCHED_DFLT_BW); 3544 } 3545 3546 /** 3547 * ice_cfg_agg_bw_shared_lmt_per_tc - configure aggregator BW shared limit per tc 3548 * @pi: port information structure 3549 * @agg_id: aggregator ID 3550 * @tc: traffic class 3551 * @min_bw: minimum bandwidth in Kbps 3552 * @max_bw: maximum bandwidth in Kbps 3553 * @shared_bw: shared bandwidth in Kbps 3554 * 3555 * This function configures the shared rate limiter(SRL) of all aggregator type 3556 * nodes across all traffic classes for aggregator matching agg_id. 3557 */ 3558 enum ice_status 3559 ice_cfg_agg_bw_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc, 3560 u32 min_bw, u32 max_bw, u32 shared_bw) 3561 { 3562 return ice_sched_set_agg_bw_shared_lmt_per_tc(pi, agg_id, tc, min_bw, 3563 max_bw, shared_bw); 3564 } 3565 3566 /** 3567 * ice_cfg_agg_bw_shared_lmt_per_tc - configure aggregator BW shared limit per tc 3568 * @pi: port information structure 3569 * @agg_id: aggregator ID 3570 * @tc: traffic class 3571 * 3572 * This function configures the shared rate limiter(SRL) of all aggregator type 3573 * nodes across all traffic classes for aggregator matching agg_id. 3574 */ 3575 enum ice_status 3576 ice_cfg_agg_bw_no_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc) 3577 { 3578 return ice_sched_set_agg_bw_shared_lmt_per_tc(pi, agg_id, tc, 3579 ICE_SCHED_DFLT_BW, 3580 ICE_SCHED_DFLT_BW, 3581 ICE_SCHED_DFLT_BW); 3582 } 3583 3584 /** 3585 * ice_config_vsi_queue_priority - config VSI queue priority of node 3586 * @pi: port information structure 3587 * @num_qs: number of VSI queues 3588 * @q_ids: queue IDs array 3589 * @q_prio: queue priority array 3590 * 3591 * This function configures the queue node priority (Sibling Priority) of the 3592 * passed in VSI's queue(s) for a given traffic class (TC). 3593 */ 3594 enum ice_status 3595 ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 num_qs, u32 *q_ids, 3596 u8 *q_prio) 3597 { 3598 enum ice_status status = ICE_ERR_PARAM; 3599 u16 i; 3600 3601 ice_acquire_lock(&pi->sched_lock); 3602 3603 for (i = 0; i < num_qs; i++) { 3604 struct ice_sched_node *node; 3605 3606 node = ice_sched_find_node_by_teid(pi->root, q_ids[i]); 3607 if (!node || node->info.data.elem_type != 3608 ICE_AQC_ELEM_TYPE_LEAF) { 3609 status = ICE_ERR_PARAM; 3610 break; 3611 } 3612 /* Configure Priority */ 3613 status = ice_sched_cfg_sibl_node_prio(pi, node, q_prio[i]); 3614 if (status) 3615 break; 3616 } 3617 3618 ice_release_lock(&pi->sched_lock); 3619 return status; 3620 } 3621 3622 /** 3623 * ice_cfg_agg_vsi_priority_per_tc - config aggregator's VSI priority per TC 3624 * @pi: port information structure 3625 * @agg_id: Aggregator ID 3626 * @num_vsis: number of VSI(s) 3627 * @vsi_handle_arr: array of software VSI handles 3628 * @node_prio: pointer to node priority 3629 * @tc: traffic class 3630 * 3631 * This function configures the node priority (Sibling Priority) of the 3632 * passed in VSI's for a given traffic class (TC) of an Aggregator ID. 3633 */ 3634 enum ice_status 3635 ice_cfg_agg_vsi_priority_per_tc(struct ice_port_info *pi, u32 agg_id, 3636 u16 num_vsis, u16 *vsi_handle_arr, 3637 u8 *node_prio, u8 tc) 3638 { 3639 struct ice_sched_agg_vsi_info *agg_vsi_info; 3640 struct ice_sched_node *tc_node, *agg_node; 3641 enum ice_status status = ICE_ERR_PARAM; 3642 struct ice_sched_agg_info *agg_info; 3643 bool agg_id_present = false; 3644 struct ice_hw *hw = pi->hw; 3645 u16 i; 3646 3647 ice_acquire_lock(&pi->sched_lock); 3648 LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info, 3649 list_entry) 3650 if (agg_info->agg_id == agg_id) { 3651 agg_id_present = true; 3652 break; 3653 } 3654 if (!agg_id_present) 3655 goto exit_agg_priority_per_tc; 3656 3657 tc_node = ice_sched_get_tc_node(pi, tc); 3658 if (!tc_node) 3659 goto exit_agg_priority_per_tc; 3660 3661 agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); 3662 if (!agg_node) 3663 goto exit_agg_priority_per_tc; 3664 3665 if (num_vsis > hw->max_children[agg_node->tx_sched_layer]) 3666 goto exit_agg_priority_per_tc; 3667 3668 for (i = 0; i < num_vsis; i++) { 3669 struct ice_sched_node *vsi_node; 3670 bool vsi_handle_valid = false; 3671 u16 vsi_handle; 3672 3673 status = ICE_ERR_PARAM; 3674 vsi_handle = vsi_handle_arr[i]; 3675 if (!ice_is_vsi_valid(hw, vsi_handle)) 3676 goto exit_agg_priority_per_tc; 3677 /* Verify child nodes before applying settings */ 3678 LIST_FOR_EACH_ENTRY(agg_vsi_info, &agg_info->agg_vsi_list, 3679 ice_sched_agg_vsi_info, list_entry) 3680 if (agg_vsi_info->vsi_handle == vsi_handle) { 3681 /* cppcheck-suppress unreadVariable */ 3682 vsi_handle_valid = true; 3683 break; 3684 } 3685 3686 if (!vsi_handle_valid) 3687 goto exit_agg_priority_per_tc; 3688 3689 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 3690 if (!vsi_node) 3691 goto exit_agg_priority_per_tc; 3692 3693 if (ice_sched_find_node_in_subtree(hw, agg_node, vsi_node)) { 3694 /* Configure Priority */ 3695 status = ice_sched_cfg_sibl_node_prio(pi, vsi_node, 3696 node_prio[i]); 3697 if (status) 3698 break; 3699 status = ice_sched_save_vsi_prio(pi, vsi_handle, tc, 3700 node_prio[i]); 3701 if (status) 3702 break; 3703 } 3704 } 3705 3706 exit_agg_priority_per_tc: 3707 ice_release_lock(&pi->sched_lock); 3708 return status; 3709 } 3710 3711 /** 3712 * ice_cfg_vsi_bw_alloc - config VSI BW alloc per TC 3713 * @pi: port information structure 3714 * @vsi_handle: software VSI handle 3715 * @ena_tcmap: enabled TC map 3716 * @rl_type: Rate limit type CIR/EIR 3717 * @bw_alloc: Array of BW alloc 3718 * 3719 * This function configures the BW allocation of the passed in VSI's 3720 * node(s) for enabled traffic class. 3721 */ 3722 enum ice_status 3723 ice_cfg_vsi_bw_alloc(struct ice_port_info *pi, u16 vsi_handle, u8 ena_tcmap, 3724 enum ice_rl_type rl_type, u8 *bw_alloc) 3725 { 3726 enum ice_status status = ICE_SUCCESS; 3727 u8 tc; 3728 3729 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 3730 return ICE_ERR_PARAM; 3731 3732 ice_acquire_lock(&pi->sched_lock); 3733 3734 /* Return success if no nodes are present across TC */ 3735 ice_for_each_traffic_class(tc) { 3736 struct ice_sched_node *tc_node, *vsi_node; 3737 3738 if (!ice_is_tc_ena(ena_tcmap, tc)) 3739 continue; 3740 3741 tc_node = ice_sched_get_tc_node(pi, tc); 3742 if (!tc_node) 3743 continue; 3744 3745 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 3746 if (!vsi_node) 3747 continue; 3748 3749 status = ice_sched_cfg_node_bw_alloc(pi->hw, vsi_node, rl_type, 3750 bw_alloc[tc]); 3751 if (status) 3752 break; 3753 status = ice_sched_save_vsi_bw_alloc(pi, vsi_handle, tc, 3754 rl_type, bw_alloc[tc]); 3755 if (status) 3756 break; 3757 } 3758 3759 ice_release_lock(&pi->sched_lock); 3760 return status; 3761 } 3762 3763 /** 3764 * ice_cfg_agg_bw_alloc - config aggregator BW alloc 3765 * @pi: port information structure 3766 * @agg_id: aggregator ID 3767 * @ena_tcmap: enabled TC map 3768 * @rl_type: rate limit type CIR/EIR 3769 * @bw_alloc: array of BW alloc 3770 * 3771 * This function configures the BW allocation of passed in aggregator for 3772 * enabled traffic class(s). 3773 */ 3774 enum ice_status 3775 ice_cfg_agg_bw_alloc(struct ice_port_info *pi, u32 agg_id, u8 ena_tcmap, 3776 enum ice_rl_type rl_type, u8 *bw_alloc) 3777 { 3778 struct ice_sched_agg_info *agg_info; 3779 bool agg_id_present = false; 3780 enum ice_status status = ICE_SUCCESS; 3781 struct ice_hw *hw = pi->hw; 3782 u8 tc; 3783 3784 ice_acquire_lock(&pi->sched_lock); 3785 LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info, 3786 list_entry) 3787 if (agg_info->agg_id == agg_id) { 3788 agg_id_present = true; 3789 break; 3790 } 3791 if (!agg_id_present) { 3792 status = ICE_ERR_PARAM; 3793 goto exit_cfg_agg_bw_alloc; 3794 } 3795 3796 /* Return success if no nodes are present across TC */ 3797 ice_for_each_traffic_class(tc) { 3798 struct ice_sched_node *tc_node, *agg_node; 3799 3800 if (!ice_is_tc_ena(ena_tcmap, tc)) 3801 continue; 3802 3803 tc_node = ice_sched_get_tc_node(pi, tc); 3804 if (!tc_node) 3805 continue; 3806 3807 agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); 3808 if (!agg_node) 3809 continue; 3810 3811 status = ice_sched_cfg_node_bw_alloc(hw, agg_node, rl_type, 3812 bw_alloc[tc]); 3813 if (status) 3814 break; 3815 status = ice_sched_save_agg_bw_alloc(pi, agg_id, tc, rl_type, 3816 bw_alloc[tc]); 3817 if (status) 3818 break; 3819 } 3820 3821 exit_cfg_agg_bw_alloc: 3822 ice_release_lock(&pi->sched_lock); 3823 return status; 3824 } 3825 3826 /** 3827 * ice_sched_calc_wakeup - calculate RL profile wakeup parameter 3828 * @hw: pointer to the HW struct 3829 * @bw: bandwidth in Kbps 3830 * 3831 * This function calculates the wakeup parameter of RL profile. 3832 */ 3833 static u16 ice_sched_calc_wakeup(struct ice_hw *hw, s32 bw) 3834 { 3835 s64 bytes_per_sec, wakeup_int, wakeup_a, wakeup_b, wakeup_f; 3836 s32 wakeup_f_int; 3837 u16 wakeup = 0; 3838 3839 /* Get the wakeup integer value */ 3840 bytes_per_sec = DIV_64BIT(((s64)bw * 1000), BITS_PER_BYTE); 3841 wakeup_int = DIV_64BIT(hw->psm_clk_freq, bytes_per_sec); 3842 if (wakeup_int > 63) { 3843 wakeup = (u16)((1 << 15) | wakeup_int); 3844 } else { 3845 /* Calculate fraction value up to 4 decimals 3846 * Convert Integer value to a constant multiplier 3847 */ 3848 wakeup_b = (s64)ICE_RL_PROF_MULTIPLIER * wakeup_int; 3849 wakeup_a = DIV_64BIT((s64)ICE_RL_PROF_MULTIPLIER * 3850 hw->psm_clk_freq, bytes_per_sec); 3851 3852 /* Get Fraction value */ 3853 wakeup_f = wakeup_a - wakeup_b; 3854 3855 /* Round up the Fractional value via Ceil(Fractional value) */ 3856 if (wakeup_f > DIV_64BIT(ICE_RL_PROF_MULTIPLIER, 2)) 3857 wakeup_f += 1; 3858 3859 wakeup_f_int = (s32)DIV_64BIT(wakeup_f * ICE_RL_PROF_FRACTION, 3860 ICE_RL_PROF_MULTIPLIER); 3861 wakeup |= (u16)(wakeup_int << 9); 3862 wakeup |= (u16)(0x1ff & wakeup_f_int); 3863 } 3864 3865 return wakeup; 3866 } 3867 3868 /** 3869 * ice_sched_bw_to_rl_profile - convert BW to profile parameters 3870 * @hw: pointer to the HW struct 3871 * @bw: bandwidth in Kbps 3872 * @profile: profile parameters to return 3873 * 3874 * This function converts the BW to profile structure format. 3875 */ 3876 static enum ice_status 3877 ice_sched_bw_to_rl_profile(struct ice_hw *hw, u32 bw, 3878 struct ice_aqc_rl_profile_elem *profile) 3879 { 3880 enum ice_status status = ICE_ERR_PARAM; 3881 s64 bytes_per_sec, ts_rate, mv_tmp; 3882 bool found = false; 3883 s32 encode = 0; 3884 s64 mv = 0; 3885 s32 i; 3886 3887 /* Bw settings range is from 0.5Mb/sec to 100Gb/sec */ 3888 if (bw < ICE_SCHED_MIN_BW || bw > ICE_SCHED_MAX_BW) 3889 return status; 3890 3891 /* Bytes per second from Kbps */ 3892 bytes_per_sec = DIV_64BIT(((s64)bw * 1000), BITS_PER_BYTE); 3893 3894 /* encode is 6 bits but really useful are 5 bits */ 3895 for (i = 0; i < 64; i++) { 3896 u64 pow_result = BIT_ULL(i); 3897 3898 ts_rate = DIV_64BIT((s64)hw->psm_clk_freq, 3899 pow_result * ICE_RL_PROF_TS_MULTIPLIER); 3900 if (ts_rate <= 0) 3901 continue; 3902 3903 /* Multiplier value */ 3904 mv_tmp = DIV_64BIT(bytes_per_sec * ICE_RL_PROF_MULTIPLIER, 3905 ts_rate); 3906 3907 /* Round to the nearest ICE_RL_PROF_MULTIPLIER */ 3908 mv = round_up_64bit(mv_tmp, ICE_RL_PROF_MULTIPLIER); 3909 3910 /* First multiplier value greater than the given 3911 * accuracy bytes 3912 */ 3913 if (mv > ICE_RL_PROF_ACCURACY_BYTES) { 3914 encode = i; 3915 found = true; 3916 break; 3917 } 3918 } 3919 if (found) { 3920 u16 wm; 3921 3922 wm = ice_sched_calc_wakeup(hw, bw); 3923 profile->rl_multiply = CPU_TO_LE16(mv); 3924 profile->wake_up_calc = CPU_TO_LE16(wm); 3925 profile->rl_encode = CPU_TO_LE16(encode); 3926 status = ICE_SUCCESS; 3927 } else { 3928 status = ICE_ERR_DOES_NOT_EXIST; 3929 } 3930 3931 return status; 3932 } 3933 3934 /** 3935 * ice_sched_add_rl_profile - add RL profile 3936 * @hw: pointer to the hardware structure 3937 * @rl_type: type of rate limit BW - min, max, or shared 3938 * @bw: bandwidth in Kbps - Kilo bits per sec 3939 * @layer_num: specifies in which layer to create profile 3940 * 3941 * This function first checks the existing list for corresponding BW 3942 * parameter. If it exists, it returns the associated profile otherwise 3943 * it creates a new rate limit profile for requested BW, and adds it to 3944 * the HW DB and local list. It returns the new profile or null on error. 3945 * The caller needs to hold the scheduler lock. 3946 */ 3947 static struct ice_aqc_rl_profile_info * 3948 ice_sched_add_rl_profile(struct ice_hw *hw, enum ice_rl_type rl_type, 3949 u32 bw, u8 layer_num) 3950 { 3951 struct ice_aqc_rl_profile_info *rl_prof_elem; 3952 u16 profiles_added = 0, num_profiles = 1; 3953 struct ice_aqc_rl_profile_elem *buf; 3954 enum ice_status status; 3955 u8 profile_type; 3956 3957 if (layer_num >= ICE_AQC_TOPO_MAX_LEVEL_NUM) 3958 return NULL; 3959 switch (rl_type) { 3960 case ICE_MIN_BW: 3961 profile_type = ICE_AQC_RL_PROFILE_TYPE_CIR; 3962 break; 3963 case ICE_MAX_BW: 3964 profile_type = ICE_AQC_RL_PROFILE_TYPE_EIR; 3965 break; 3966 case ICE_SHARED_BW: 3967 profile_type = ICE_AQC_RL_PROFILE_TYPE_SRL; 3968 break; 3969 default: 3970 return NULL; 3971 } 3972 3973 if (!hw) 3974 return NULL; 3975 LIST_FOR_EACH_ENTRY(rl_prof_elem, &hw->rl_prof_list[layer_num], 3976 ice_aqc_rl_profile_info, list_entry) 3977 if ((rl_prof_elem->profile.flags & ICE_AQC_RL_PROFILE_TYPE_M) == 3978 profile_type && rl_prof_elem->bw == bw) 3979 /* Return existing profile ID info */ 3980 return rl_prof_elem; 3981 3982 /* Create new profile ID */ 3983 rl_prof_elem = (struct ice_aqc_rl_profile_info *) 3984 ice_malloc(hw, sizeof(*rl_prof_elem)); 3985 3986 if (!rl_prof_elem) 3987 return NULL; 3988 3989 status = ice_sched_bw_to_rl_profile(hw, bw, &rl_prof_elem->profile); 3990 if (status != ICE_SUCCESS) 3991 goto exit_add_rl_prof; 3992 3993 rl_prof_elem->bw = bw; 3994 /* layer_num is zero relative, and fw expects level from 1 to 9 */ 3995 rl_prof_elem->profile.level = layer_num + 1; 3996 rl_prof_elem->profile.flags = profile_type; 3997 rl_prof_elem->profile.max_burst_size = CPU_TO_LE16(hw->max_burst_size); 3998 3999 /* Create new entry in HW DB */ 4000 buf = &rl_prof_elem->profile; 4001 status = ice_aq_add_rl_profile(hw, num_profiles, buf, sizeof(*buf), 4002 &profiles_added, NULL); 4003 if (status || profiles_added != num_profiles) 4004 goto exit_add_rl_prof; 4005 4006 /* Good entry - add in the list */ 4007 rl_prof_elem->prof_id_ref = 0; 4008 LIST_ADD(&rl_prof_elem->list_entry, &hw->rl_prof_list[layer_num]); 4009 return rl_prof_elem; 4010 4011 exit_add_rl_prof: 4012 ice_free(hw, rl_prof_elem); 4013 return NULL; 4014 } 4015 4016 /** 4017 * ice_sched_cfg_node_bw_lmt - configure node sched params 4018 * @hw: pointer to the HW struct 4019 * @node: sched node to configure 4020 * @rl_type: rate limit type CIR, EIR, or shared 4021 * @rl_prof_id: rate limit profile ID 4022 * 4023 * This function configures node element's BW limit. 4024 */ 4025 static enum ice_status 4026 ice_sched_cfg_node_bw_lmt(struct ice_hw *hw, struct ice_sched_node *node, 4027 enum ice_rl_type rl_type, u16 rl_prof_id) 4028 { 4029 struct ice_aqc_txsched_elem_data buf; 4030 struct ice_aqc_txsched_elem *data; 4031 4032 buf = node->info; 4033 data = &buf.data; 4034 switch (rl_type) { 4035 case ICE_MIN_BW: 4036 data->valid_sections |= ICE_AQC_ELEM_VALID_CIR; 4037 data->cir_bw.bw_profile_idx = CPU_TO_LE16(rl_prof_id); 4038 break; 4039 case ICE_MAX_BW: 4040 data->valid_sections |= ICE_AQC_ELEM_VALID_EIR; 4041 data->eir_bw.bw_profile_idx = CPU_TO_LE16(rl_prof_id); 4042 break; 4043 case ICE_SHARED_BW: 4044 data->valid_sections |= ICE_AQC_ELEM_VALID_SHARED; 4045 data->srl_id = CPU_TO_LE16(rl_prof_id); 4046 break; 4047 default: 4048 /* Unknown rate limit type */ 4049 return ICE_ERR_PARAM; 4050 } 4051 4052 /* Configure element */ 4053 return ice_sched_update_elem(hw, node, &buf); 4054 } 4055 4056 /** 4057 * ice_sched_get_node_rl_prof_id - get node's rate limit profile ID 4058 * @node: sched node 4059 * @rl_type: rate limit type 4060 * 4061 * If existing profile matches, it returns the corresponding rate 4062 * limit profile ID, otherwise it returns an invalid ID as error. 4063 */ 4064 static u16 4065 ice_sched_get_node_rl_prof_id(struct ice_sched_node *node, 4066 enum ice_rl_type rl_type) 4067 { 4068 u16 rl_prof_id = ICE_SCHED_INVAL_PROF_ID; 4069 struct ice_aqc_txsched_elem *data; 4070 4071 data = &node->info.data; 4072 switch (rl_type) { 4073 case ICE_MIN_BW: 4074 if (data->valid_sections & ICE_AQC_ELEM_VALID_CIR) 4075 rl_prof_id = LE16_TO_CPU(data->cir_bw.bw_profile_idx); 4076 break; 4077 case ICE_MAX_BW: 4078 if (data->valid_sections & ICE_AQC_ELEM_VALID_EIR) 4079 rl_prof_id = LE16_TO_CPU(data->eir_bw.bw_profile_idx); 4080 break; 4081 case ICE_SHARED_BW: 4082 if (data->valid_sections & ICE_AQC_ELEM_VALID_SHARED) 4083 rl_prof_id = LE16_TO_CPU(data->srl_id); 4084 break; 4085 default: 4086 break; 4087 } 4088 4089 return rl_prof_id; 4090 } 4091 4092 /** 4093 * ice_sched_get_rl_prof_layer - selects rate limit profile creation layer 4094 * @pi: port information structure 4095 * @rl_type: type of rate limit BW - min, max, or shared 4096 * @layer_index: layer index 4097 * 4098 * This function returns requested profile creation layer. 4099 */ 4100 static u8 4101 ice_sched_get_rl_prof_layer(struct ice_port_info *pi, enum ice_rl_type rl_type, 4102 u8 layer_index) 4103 { 4104 struct ice_hw *hw = pi->hw; 4105 4106 if (layer_index >= hw->num_tx_sched_layers) 4107 return ICE_SCHED_INVAL_LAYER_NUM; 4108 switch (rl_type) { 4109 case ICE_MIN_BW: 4110 if (hw->layer_info[layer_index].max_cir_rl_profiles) 4111 return layer_index; 4112 break; 4113 case ICE_MAX_BW: 4114 if (hw->layer_info[layer_index].max_eir_rl_profiles) 4115 return layer_index; 4116 break; 4117 case ICE_SHARED_BW: 4118 /* if current layer doesn't support SRL profile creation 4119 * then try a layer up or down. 4120 */ 4121 if (hw->layer_info[layer_index].max_srl_profiles) 4122 return layer_index; 4123 else if (layer_index < hw->num_tx_sched_layers - 1 && 4124 hw->layer_info[layer_index + 1].max_srl_profiles) 4125 return layer_index + 1; 4126 else if (layer_index > 0 && 4127 hw->layer_info[layer_index - 1].max_srl_profiles) 4128 return layer_index - 1; 4129 break; 4130 default: 4131 break; 4132 } 4133 return ICE_SCHED_INVAL_LAYER_NUM; 4134 } 4135 4136 /** 4137 * ice_sched_get_srl_node - get shared rate limit node 4138 * @node: tree node 4139 * @srl_layer: shared rate limit layer 4140 * 4141 * This function returns SRL node to be used for shared rate limit purpose. 4142 * The caller needs to hold scheduler lock. 4143 */ 4144 static struct ice_sched_node * 4145 ice_sched_get_srl_node(struct ice_sched_node *node, u8 srl_layer) 4146 { 4147 if (srl_layer > node->tx_sched_layer) 4148 return node->children[0]; 4149 else if (srl_layer < node->tx_sched_layer) 4150 /* Node can't be created without a parent. It will always 4151 * have a valid parent except root node. 4152 */ 4153 return node->parent; 4154 else 4155 return node; 4156 } 4157 4158 /** 4159 * ice_sched_rm_rl_profile - remove RL profile ID 4160 * @hw: pointer to the hardware structure 4161 * @layer_num: layer number where profiles are saved 4162 * @profile_type: profile type like EIR, CIR, or SRL 4163 * @profile_id: profile ID to remove 4164 * 4165 * This function removes rate limit profile from layer 'layer_num' of type 4166 * 'profile_type' and profile ID as 'profile_id'. The caller needs to hold 4167 * scheduler lock. 4168 */ 4169 static enum ice_status 4170 ice_sched_rm_rl_profile(struct ice_hw *hw, u8 layer_num, u8 profile_type, 4171 u16 profile_id) 4172 { 4173 struct ice_aqc_rl_profile_info *rl_prof_elem; 4174 enum ice_status status = ICE_SUCCESS; 4175 4176 if (layer_num >= ICE_AQC_TOPO_MAX_LEVEL_NUM) 4177 return ICE_ERR_PARAM; 4178 /* Check the existing list for RL profile */ 4179 LIST_FOR_EACH_ENTRY(rl_prof_elem, &hw->rl_prof_list[layer_num], 4180 ice_aqc_rl_profile_info, list_entry) 4181 if ((rl_prof_elem->profile.flags & ICE_AQC_RL_PROFILE_TYPE_M) == 4182 profile_type && 4183 LE16_TO_CPU(rl_prof_elem->profile.profile_id) == 4184 profile_id) { 4185 if (rl_prof_elem->prof_id_ref) 4186 rl_prof_elem->prof_id_ref--; 4187 4188 /* Remove old profile ID from database */ 4189 status = ice_sched_del_rl_profile(hw, rl_prof_elem); 4190 if (status && status != ICE_ERR_IN_USE) 4191 ice_debug(hw, ICE_DBG_SCHED, "Remove rl profile failed\n"); 4192 break; 4193 } 4194 if (status == ICE_ERR_IN_USE) 4195 status = ICE_SUCCESS; 4196 return status; 4197 } 4198 4199 /** 4200 * ice_sched_set_node_bw_dflt - set node's bandwidth limit to default 4201 * @pi: port information structure 4202 * @node: pointer to node structure 4203 * @rl_type: rate limit type min, max, or shared 4204 * @layer_num: layer number where RL profiles are saved 4205 * 4206 * This function configures node element's BW rate limit profile ID of 4207 * type CIR, EIR, or SRL to default. This function needs to be called 4208 * with the scheduler lock held. 4209 */ 4210 static enum ice_status 4211 ice_sched_set_node_bw_dflt(struct ice_port_info *pi, 4212 struct ice_sched_node *node, 4213 enum ice_rl_type rl_type, u8 layer_num) 4214 { 4215 enum ice_status status; 4216 struct ice_hw *hw; 4217 u8 profile_type; 4218 u16 rl_prof_id; 4219 u16 old_id; 4220 4221 hw = pi->hw; 4222 switch (rl_type) { 4223 case ICE_MIN_BW: 4224 profile_type = ICE_AQC_RL_PROFILE_TYPE_CIR; 4225 rl_prof_id = ICE_SCHED_DFLT_RL_PROF_ID; 4226 break; 4227 case ICE_MAX_BW: 4228 profile_type = ICE_AQC_RL_PROFILE_TYPE_EIR; 4229 rl_prof_id = ICE_SCHED_DFLT_RL_PROF_ID; 4230 break; 4231 case ICE_SHARED_BW: 4232 profile_type = ICE_AQC_RL_PROFILE_TYPE_SRL; 4233 /* No SRL is configured for default case */ 4234 rl_prof_id = ICE_SCHED_NO_SHARED_RL_PROF_ID; 4235 break; 4236 default: 4237 return ICE_ERR_PARAM; 4238 } 4239 /* Save existing RL prof ID for later clean up */ 4240 old_id = ice_sched_get_node_rl_prof_id(node, rl_type); 4241 /* Configure BW scheduling parameters */ 4242 status = ice_sched_cfg_node_bw_lmt(hw, node, rl_type, rl_prof_id); 4243 if (status) 4244 return status; 4245 4246 /* Remove stale RL profile ID */ 4247 if (old_id == ICE_SCHED_DFLT_RL_PROF_ID || 4248 old_id == ICE_SCHED_INVAL_PROF_ID) 4249 return ICE_SUCCESS; 4250 4251 return ice_sched_rm_rl_profile(hw, layer_num, profile_type, old_id); 4252 } 4253 4254 /** 4255 * ice_sched_set_node_bw - set node's bandwidth 4256 * @pi: port information structure 4257 * @node: tree node 4258 * @rl_type: rate limit type min, max, or shared 4259 * @bw: bandwidth in Kbps - Kilo bits per sec 4260 * @layer_num: layer number 4261 * 4262 * This function adds new profile corresponding to requested BW, configures 4263 * node's RL profile ID of type CIR, EIR, or SRL, and removes old profile 4264 * ID from local database. The caller needs to hold scheduler lock. 4265 */ 4266 static enum ice_status 4267 ice_sched_set_node_bw(struct ice_port_info *pi, struct ice_sched_node *node, 4268 enum ice_rl_type rl_type, u32 bw, u8 layer_num) 4269 { 4270 struct ice_aqc_rl_profile_info *rl_prof_info; 4271 enum ice_status status = ICE_ERR_PARAM; 4272 struct ice_hw *hw = pi->hw; 4273 u16 old_id, rl_prof_id; 4274 4275 rl_prof_info = ice_sched_add_rl_profile(hw, rl_type, bw, layer_num); 4276 if (!rl_prof_info) 4277 return status; 4278 4279 rl_prof_id = LE16_TO_CPU(rl_prof_info->profile.profile_id); 4280 4281 /* Save existing RL prof ID for later clean up */ 4282 old_id = ice_sched_get_node_rl_prof_id(node, rl_type); 4283 /* Configure BW scheduling parameters */ 4284 status = ice_sched_cfg_node_bw_lmt(hw, node, rl_type, rl_prof_id); 4285 if (status) 4286 return status; 4287 4288 /* New changes has been applied */ 4289 /* Increment the profile ID reference count */ 4290 rl_prof_info->prof_id_ref++; 4291 4292 /* Check for old ID removal */ 4293 if ((old_id == ICE_SCHED_DFLT_RL_PROF_ID && rl_type != ICE_SHARED_BW) || 4294 old_id == ICE_SCHED_INVAL_PROF_ID || old_id == rl_prof_id) 4295 return ICE_SUCCESS; 4296 4297 return ice_sched_rm_rl_profile(hw, layer_num, 4298 rl_prof_info->profile.flags & 4299 ICE_AQC_RL_PROFILE_TYPE_M, old_id); 4300 } 4301 4302 /** 4303 * ice_sched_set_node_bw_lmt - set node's BW limit 4304 * @pi: port information structure 4305 * @node: tree node 4306 * @rl_type: rate limit type min, max, or shared 4307 * @bw: bandwidth in Kbps - Kilo bits per sec 4308 * 4309 * It updates node's BW limit parameters like BW RL profile ID of type CIR, 4310 * EIR, or SRL. The caller needs to hold scheduler lock. 4311 * 4312 * NOTE: Caller provides the correct SRL node in case of shared profile 4313 * settings. 4314 */ 4315 static enum ice_status 4316 ice_sched_set_node_bw_lmt(struct ice_port_info *pi, struct ice_sched_node *node, 4317 enum ice_rl_type rl_type, u32 bw) 4318 { 4319 struct ice_hw *hw; 4320 u8 layer_num; 4321 4322 if (!pi) 4323 return ICE_ERR_PARAM; 4324 hw = pi->hw; 4325 /* Remove unused RL profile IDs from HW and SW DB */ 4326 ice_sched_rm_unused_rl_prof(hw); 4327 4328 layer_num = ice_sched_get_rl_prof_layer(pi, rl_type, 4329 node->tx_sched_layer); 4330 if (layer_num >= hw->num_tx_sched_layers) 4331 return ICE_ERR_PARAM; 4332 4333 if (bw == ICE_SCHED_DFLT_BW) 4334 return ice_sched_set_node_bw_dflt(pi, node, rl_type, layer_num); 4335 return ice_sched_set_node_bw(pi, node, rl_type, bw, layer_num); 4336 } 4337 4338 /** 4339 * ice_sched_set_node_bw_dflt_lmt - set node's BW limit to default 4340 * @pi: port information structure 4341 * @node: pointer to node structure 4342 * @rl_type: rate limit type min, max, or shared 4343 * 4344 * This function configures node element's BW rate limit profile ID of 4345 * type CIR, EIR, or SRL to default. This function needs to be called 4346 * with the scheduler lock held. 4347 */ 4348 static enum ice_status 4349 ice_sched_set_node_bw_dflt_lmt(struct ice_port_info *pi, 4350 struct ice_sched_node *node, 4351 enum ice_rl_type rl_type) 4352 { 4353 return ice_sched_set_node_bw_lmt(pi, node, rl_type, 4354 ICE_SCHED_DFLT_BW); 4355 } 4356 4357 /** 4358 * ice_sched_validate_srl_node - Check node for SRL applicability 4359 * @node: sched node to configure 4360 * @sel_layer: selected SRL layer 4361 * 4362 * This function checks if the SRL can be applied to a selceted layer node on 4363 * behalf of the requested node (first argument). This function needs to be 4364 * called with scheduler lock held. 4365 */ 4366 static enum ice_status 4367 ice_sched_validate_srl_node(struct ice_sched_node *node, u8 sel_layer) 4368 { 4369 /* SRL profiles are not available on all layers. Check if the 4370 * SRL profile can be applied to a node above or below the 4371 * requested node. SRL configuration is possible only if the 4372 * selected layer's node has single child. 4373 */ 4374 if (sel_layer == node->tx_sched_layer || 4375 ((sel_layer == node->tx_sched_layer + 1) && 4376 node->num_children == 1) || 4377 ((sel_layer == node->tx_sched_layer - 1) && 4378 (node->parent && node->parent->num_children == 1))) 4379 return ICE_SUCCESS; 4380 4381 return ICE_ERR_CFG; 4382 } 4383 4384 /** 4385 * ice_sched_save_q_bw - save queue node's BW information 4386 * @q_ctx: queue context structure 4387 * @rl_type: rate limit type min, max, or shared 4388 * @bw: bandwidth in Kbps - Kilo bits per sec 4389 * 4390 * Save BW information of queue type node for post replay use. 4391 */ 4392 static enum ice_status 4393 ice_sched_save_q_bw(struct ice_q_ctx *q_ctx, enum ice_rl_type rl_type, u32 bw) 4394 { 4395 switch (rl_type) { 4396 case ICE_MIN_BW: 4397 ice_set_clear_cir_bw(&q_ctx->bw_t_info, bw); 4398 break; 4399 case ICE_MAX_BW: 4400 ice_set_clear_eir_bw(&q_ctx->bw_t_info, bw); 4401 break; 4402 case ICE_SHARED_BW: 4403 ice_set_clear_shared_bw(&q_ctx->bw_t_info, bw); 4404 break; 4405 default: 4406 return ICE_ERR_PARAM; 4407 } 4408 return ICE_SUCCESS; 4409 } 4410 4411 /** 4412 * ice_sched_set_q_bw_lmt - sets queue BW limit 4413 * @pi: port information structure 4414 * @vsi_handle: sw VSI handle 4415 * @tc: traffic class 4416 * @q_handle: software queue handle 4417 * @rl_type: min, max, or shared 4418 * @bw: bandwidth in Kbps 4419 * 4420 * This function sets BW limit of queue scheduling node. 4421 */ 4422 static enum ice_status 4423 ice_sched_set_q_bw_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 4424 u16 q_handle, enum ice_rl_type rl_type, u32 bw) 4425 { 4426 enum ice_status status = ICE_ERR_PARAM; 4427 struct ice_sched_node *node; 4428 struct ice_q_ctx *q_ctx; 4429 4430 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4431 return ICE_ERR_PARAM; 4432 ice_acquire_lock(&pi->sched_lock); 4433 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handle); 4434 if (!q_ctx) 4435 goto exit_q_bw_lmt; 4436 node = ice_sched_find_node_by_teid(pi->root, q_ctx->q_teid); 4437 if (!node) { 4438 ice_debug(pi->hw, ICE_DBG_SCHED, "Wrong q_teid\n"); 4439 goto exit_q_bw_lmt; 4440 } 4441 4442 /* Return error if it is not a leaf node */ 4443 if (node->info.data.elem_type != ICE_AQC_ELEM_TYPE_LEAF) 4444 goto exit_q_bw_lmt; 4445 4446 /* SRL bandwidth layer selection */ 4447 if (rl_type == ICE_SHARED_BW) { 4448 u8 sel_layer; /* selected layer */ 4449 4450 sel_layer = ice_sched_get_rl_prof_layer(pi, rl_type, 4451 node->tx_sched_layer); 4452 if (sel_layer >= pi->hw->num_tx_sched_layers) { 4453 status = ICE_ERR_PARAM; 4454 goto exit_q_bw_lmt; 4455 } 4456 status = ice_sched_validate_srl_node(node, sel_layer); 4457 if (status) 4458 goto exit_q_bw_lmt; 4459 } 4460 4461 if (bw == ICE_SCHED_DFLT_BW) 4462 status = ice_sched_set_node_bw_dflt_lmt(pi, node, rl_type); 4463 else 4464 status = ice_sched_set_node_bw_lmt(pi, node, rl_type, bw); 4465 4466 if (!status) 4467 status = ice_sched_save_q_bw(q_ctx, rl_type, bw); 4468 4469 exit_q_bw_lmt: 4470 ice_release_lock(&pi->sched_lock); 4471 return status; 4472 } 4473 4474 /** 4475 * ice_cfg_q_bw_lmt - configure queue BW limit 4476 * @pi: port information structure 4477 * @vsi_handle: sw VSI handle 4478 * @tc: traffic class 4479 * @q_handle: software queue handle 4480 * @rl_type: min, max, or shared 4481 * @bw: bandwidth in Kbps 4482 * 4483 * This function configures BW limit of queue scheduling node. 4484 */ 4485 enum ice_status 4486 ice_cfg_q_bw_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 4487 u16 q_handle, enum ice_rl_type rl_type, u32 bw) 4488 { 4489 return ice_sched_set_q_bw_lmt(pi, vsi_handle, tc, q_handle, rl_type, 4490 bw); 4491 } 4492 4493 /** 4494 * ice_cfg_q_bw_dflt_lmt - configure queue BW default limit 4495 * @pi: port information structure 4496 * @vsi_handle: sw VSI handle 4497 * @tc: traffic class 4498 * @q_handle: software queue handle 4499 * @rl_type: min, max, or shared 4500 * 4501 * This function configures BW default limit of queue scheduling node. 4502 */ 4503 enum ice_status 4504 ice_cfg_q_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 4505 u16 q_handle, enum ice_rl_type rl_type) 4506 { 4507 return ice_sched_set_q_bw_lmt(pi, vsi_handle, tc, q_handle, rl_type, 4508 ICE_SCHED_DFLT_BW); 4509 } 4510 4511 /** 4512 * ice_sched_save_tc_node_bw - save TC node BW limit 4513 * @pi: port information structure 4514 * @tc: TC number 4515 * @rl_type: min or max 4516 * @bw: bandwidth in Kbps 4517 * 4518 * This function saves the modified values of bandwidth settings for later 4519 * replay purpose (restore) after reset. 4520 */ 4521 static enum ice_status 4522 ice_sched_save_tc_node_bw(struct ice_port_info *pi, u8 tc, 4523 enum ice_rl_type rl_type, u32 bw) 4524 { 4525 if (tc >= ICE_MAX_TRAFFIC_CLASS) 4526 return ICE_ERR_PARAM; 4527 switch (rl_type) { 4528 case ICE_MIN_BW: 4529 ice_set_clear_cir_bw(&pi->tc_node_bw_t_info[tc], bw); 4530 break; 4531 case ICE_MAX_BW: 4532 ice_set_clear_eir_bw(&pi->tc_node_bw_t_info[tc], bw); 4533 break; 4534 case ICE_SHARED_BW: 4535 ice_set_clear_shared_bw(&pi->tc_node_bw_t_info[tc], bw); 4536 break; 4537 default: 4538 return ICE_ERR_PARAM; 4539 } 4540 return ICE_SUCCESS; 4541 } 4542 4543 /** 4544 * ice_sched_set_tc_node_bw_lmt - sets TC node BW limit 4545 * @pi: port information structure 4546 * @tc: TC number 4547 * @rl_type: min or max 4548 * @bw: bandwidth in Kbps 4549 * 4550 * This function configures bandwidth limit of TC node. 4551 */ 4552 static enum ice_status 4553 ice_sched_set_tc_node_bw_lmt(struct ice_port_info *pi, u8 tc, 4554 enum ice_rl_type rl_type, u32 bw) 4555 { 4556 enum ice_status status = ICE_ERR_PARAM; 4557 struct ice_sched_node *tc_node; 4558 4559 if (tc >= ICE_MAX_TRAFFIC_CLASS) 4560 return status; 4561 ice_acquire_lock(&pi->sched_lock); 4562 tc_node = ice_sched_get_tc_node(pi, tc); 4563 if (!tc_node) 4564 goto exit_set_tc_node_bw; 4565 if (bw == ICE_SCHED_DFLT_BW) 4566 status = ice_sched_set_node_bw_dflt_lmt(pi, tc_node, rl_type); 4567 else 4568 status = ice_sched_set_node_bw_lmt(pi, tc_node, rl_type, bw); 4569 if (!status) 4570 status = ice_sched_save_tc_node_bw(pi, tc, rl_type, bw); 4571 4572 exit_set_tc_node_bw: 4573 ice_release_lock(&pi->sched_lock); 4574 return status; 4575 } 4576 4577 /** 4578 * ice_cfg_tc_node_bw_lmt - configure TC node BW limit 4579 * @pi: port information structure 4580 * @tc: TC number 4581 * @rl_type: min or max 4582 * @bw: bandwidth in Kbps 4583 * 4584 * This function configures BW limit of TC node. 4585 * Note: The minimum guaranteed reservation is done via DCBX. 4586 */ 4587 enum ice_status 4588 ice_cfg_tc_node_bw_lmt(struct ice_port_info *pi, u8 tc, 4589 enum ice_rl_type rl_type, u32 bw) 4590 { 4591 return ice_sched_set_tc_node_bw_lmt(pi, tc, rl_type, bw); 4592 } 4593 4594 /** 4595 * ice_cfg_tc_node_bw_dflt_lmt - configure TC node BW default limit 4596 * @pi: port information structure 4597 * @tc: TC number 4598 * @rl_type: min or max 4599 * 4600 * This function configures BW default limit of TC node. 4601 */ 4602 enum ice_status 4603 ice_cfg_tc_node_bw_dflt_lmt(struct ice_port_info *pi, u8 tc, 4604 enum ice_rl_type rl_type) 4605 { 4606 return ice_sched_set_tc_node_bw_lmt(pi, tc, rl_type, ICE_SCHED_DFLT_BW); 4607 } 4608 4609 /** 4610 * ice_sched_save_tc_node_bw_alloc - save TC node's BW alloc information 4611 * @pi: port information structure 4612 * @tc: traffic class 4613 * @rl_type: rate limit type min or max 4614 * @bw_alloc: Bandwidth allocation information 4615 * 4616 * Save BW alloc information of VSI type node for post replay use. 4617 */ 4618 static enum ice_status 4619 ice_sched_save_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc, 4620 enum ice_rl_type rl_type, u16 bw_alloc) 4621 { 4622 if (tc >= ICE_MAX_TRAFFIC_CLASS) 4623 return ICE_ERR_PARAM; 4624 switch (rl_type) { 4625 case ICE_MIN_BW: 4626 ice_set_clear_cir_bw_alloc(&pi->tc_node_bw_t_info[tc], 4627 bw_alloc); 4628 break; 4629 case ICE_MAX_BW: 4630 ice_set_clear_eir_bw_alloc(&pi->tc_node_bw_t_info[tc], 4631 bw_alloc); 4632 break; 4633 default: 4634 return ICE_ERR_PARAM; 4635 } 4636 return ICE_SUCCESS; 4637 } 4638 4639 /** 4640 * ice_sched_set_tc_node_bw_alloc - set TC node BW alloc 4641 * @pi: port information structure 4642 * @tc: TC number 4643 * @rl_type: min or max 4644 * @bw_alloc: bandwidth alloc 4645 * 4646 * This function configures bandwidth alloc of TC node, also saves the 4647 * changed settings for replay purpose, and return success if it succeeds 4648 * in modifying bandwidth alloc setting. 4649 */ 4650 static enum ice_status 4651 ice_sched_set_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc, 4652 enum ice_rl_type rl_type, u8 bw_alloc) 4653 { 4654 enum ice_status status = ICE_ERR_PARAM; 4655 struct ice_sched_node *tc_node; 4656 4657 if (tc >= ICE_MAX_TRAFFIC_CLASS) 4658 return status; 4659 ice_acquire_lock(&pi->sched_lock); 4660 tc_node = ice_sched_get_tc_node(pi, tc); 4661 if (!tc_node) 4662 goto exit_set_tc_node_bw_alloc; 4663 status = ice_sched_cfg_node_bw_alloc(pi->hw, tc_node, rl_type, 4664 bw_alloc); 4665 if (status) 4666 goto exit_set_tc_node_bw_alloc; 4667 status = ice_sched_save_tc_node_bw_alloc(pi, tc, rl_type, bw_alloc); 4668 4669 exit_set_tc_node_bw_alloc: 4670 ice_release_lock(&pi->sched_lock); 4671 return status; 4672 } 4673 4674 /** 4675 * ice_cfg_tc_node_bw_alloc - configure TC node BW alloc 4676 * @pi: port information structure 4677 * @tc: TC number 4678 * @rl_type: min or max 4679 * @bw_alloc: bandwidth alloc 4680 * 4681 * This function configures BW limit of TC node. 4682 * Note: The minimum guaranteed reservation is done via DCBX. 4683 */ 4684 enum ice_status 4685 ice_cfg_tc_node_bw_alloc(struct ice_port_info *pi, u8 tc, 4686 enum ice_rl_type rl_type, u8 bw_alloc) 4687 { 4688 return ice_sched_set_tc_node_bw_alloc(pi, tc, rl_type, bw_alloc); 4689 } 4690 4691 /** 4692 * ice_sched_set_agg_bw_dflt_lmt - set aggregator node's BW limit to default 4693 * @pi: port information structure 4694 * @vsi_handle: software VSI handle 4695 * 4696 * This function retrieves the aggregator ID based on VSI ID and TC, 4697 * and sets node's BW limit to default. This function needs to be 4698 * called with the scheduler lock held. 4699 */ 4700 enum ice_status 4701 ice_sched_set_agg_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle) 4702 { 4703 struct ice_vsi_ctx *vsi_ctx; 4704 enum ice_status status = ICE_SUCCESS; 4705 u8 tc; 4706 4707 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4708 return ICE_ERR_PARAM; 4709 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 4710 if (!vsi_ctx) 4711 return ICE_ERR_PARAM; 4712 4713 ice_for_each_traffic_class(tc) { 4714 struct ice_sched_node *node; 4715 4716 node = vsi_ctx->sched.ag_node[tc]; 4717 if (!node) 4718 continue; 4719 4720 /* Set min profile to default */ 4721 status = ice_sched_set_node_bw_dflt_lmt(pi, node, ICE_MIN_BW); 4722 if (status) 4723 break; 4724 4725 /* Set max profile to default */ 4726 status = ice_sched_set_node_bw_dflt_lmt(pi, node, ICE_MAX_BW); 4727 if (status) 4728 break; 4729 4730 /* Remove shared profile, if there is one */ 4731 status = ice_sched_set_node_bw_dflt_lmt(pi, node, 4732 ICE_SHARED_BW); 4733 if (status) 4734 break; 4735 } 4736 4737 return status; 4738 } 4739 4740 /** 4741 * ice_sched_get_node_by_id_type - get node from ID type 4742 * @pi: port information structure 4743 * @id: identifier 4744 * @agg_type: type of aggregator 4745 * @tc: traffic class 4746 * 4747 * This function returns node identified by ID of type aggregator, and 4748 * based on traffic class (TC). This function needs to be called with 4749 * the scheduler lock held. 4750 */ 4751 static struct ice_sched_node * 4752 ice_sched_get_node_by_id_type(struct ice_port_info *pi, u32 id, 4753 enum ice_agg_type agg_type, u8 tc) 4754 { 4755 struct ice_sched_node *node = NULL; 4756 struct ice_sched_node *child_node; 4757 4758 switch (agg_type) { 4759 case ICE_AGG_TYPE_VSI: { 4760 struct ice_vsi_ctx *vsi_ctx; 4761 u16 vsi_handle = (u16)id; 4762 4763 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4764 break; 4765 /* Get sched_vsi_info */ 4766 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 4767 if (!vsi_ctx) 4768 break; 4769 node = vsi_ctx->sched.vsi_node[tc]; 4770 break; 4771 } 4772 4773 case ICE_AGG_TYPE_AGG: { 4774 struct ice_sched_node *tc_node; 4775 4776 tc_node = ice_sched_get_tc_node(pi, tc); 4777 if (tc_node) 4778 node = ice_sched_get_agg_node(pi, tc_node, id); 4779 break; 4780 } 4781 4782 case ICE_AGG_TYPE_Q: 4783 /* The current implementation allows single queue to modify */ 4784 node = ice_sched_get_node(pi, id); 4785 break; 4786 4787 case ICE_AGG_TYPE_QG: 4788 /* The current implementation allows single qg to modify */ 4789 child_node = ice_sched_get_node(pi, id); 4790 if (!child_node) 4791 break; 4792 node = child_node->parent; 4793 break; 4794 4795 default: 4796 break; 4797 } 4798 4799 return node; 4800 } 4801 4802 /** 4803 * ice_sched_set_node_bw_lmt_per_tc - set node BW limit per TC 4804 * @pi: port information structure 4805 * @id: ID (software VSI handle or AGG ID) 4806 * @agg_type: aggregator type (VSI or AGG type node) 4807 * @tc: traffic class 4808 * @rl_type: min or max 4809 * @bw: bandwidth in Kbps 4810 * 4811 * This function sets BW limit of VSI or Aggregator scheduling node 4812 * based on TC information from passed in argument BW. 4813 */ 4814 enum ice_status 4815 ice_sched_set_node_bw_lmt_per_tc(struct ice_port_info *pi, u32 id, 4816 enum ice_agg_type agg_type, u8 tc, 4817 enum ice_rl_type rl_type, u32 bw) 4818 { 4819 enum ice_status status = ICE_ERR_PARAM; 4820 struct ice_sched_node *node; 4821 4822 if (!pi) 4823 return status; 4824 4825 if (rl_type == ICE_UNKNOWN_BW) 4826 return status; 4827 4828 ice_acquire_lock(&pi->sched_lock); 4829 node = ice_sched_get_node_by_id_type(pi, id, agg_type, tc); 4830 if (!node) { 4831 ice_debug(pi->hw, ICE_DBG_SCHED, "Wrong id, agg type, or tc\n"); 4832 goto exit_set_node_bw_lmt_per_tc; 4833 } 4834 if (bw == ICE_SCHED_DFLT_BW) 4835 status = ice_sched_set_node_bw_dflt_lmt(pi, node, rl_type); 4836 else 4837 status = ice_sched_set_node_bw_lmt(pi, node, rl_type, bw); 4838 4839 exit_set_node_bw_lmt_per_tc: 4840 ice_release_lock(&pi->sched_lock); 4841 return status; 4842 } 4843 4844 /** 4845 * ice_sched_validate_vsi_srl_node - validate VSI SRL node 4846 * @pi: port information structure 4847 * @vsi_handle: software VSI handle 4848 * 4849 * This function validates SRL node of the VSI node if available SRL layer is 4850 * different than the VSI node layer on all TC(s).This function needs to be 4851 * called with scheduler lock held. 4852 */ 4853 static enum ice_status 4854 ice_sched_validate_vsi_srl_node(struct ice_port_info *pi, u16 vsi_handle) 4855 { 4856 u8 sel_layer = ICE_SCHED_INVAL_LAYER_NUM; 4857 u8 tc; 4858 4859 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 4860 return ICE_ERR_PARAM; 4861 4862 /* Return success if no nodes are present across TC */ 4863 ice_for_each_traffic_class(tc) { 4864 struct ice_sched_node *tc_node, *vsi_node; 4865 enum ice_rl_type rl_type = ICE_SHARED_BW; 4866 enum ice_status status; 4867 4868 tc_node = ice_sched_get_tc_node(pi, tc); 4869 if (!tc_node) 4870 continue; 4871 4872 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 4873 if (!vsi_node) 4874 continue; 4875 4876 /* SRL bandwidth layer selection */ 4877 if (sel_layer == ICE_SCHED_INVAL_LAYER_NUM) { 4878 u8 node_layer = vsi_node->tx_sched_layer; 4879 u8 layer_num; 4880 4881 layer_num = ice_sched_get_rl_prof_layer(pi, rl_type, 4882 node_layer); 4883 if (layer_num >= pi->hw->num_tx_sched_layers) 4884 return ICE_ERR_PARAM; 4885 sel_layer = layer_num; 4886 } 4887 4888 status = ice_sched_validate_srl_node(vsi_node, sel_layer); 4889 if (status) 4890 return status; 4891 } 4892 return ICE_SUCCESS; 4893 } 4894 4895 /** 4896 * ice_sched_set_save_vsi_srl_node_bw - set VSI shared limit values 4897 * @pi: port information structure 4898 * @vsi_handle: software VSI handle 4899 * @tc: traffic class 4900 * @srl_node: sched node to configure 4901 * @rl_type: rate limit type minimum, maximum, or shared 4902 * @bw: minimum, maximum, or shared bandwidth in Kbps 4903 * 4904 * Configure shared rate limiter(SRL) of VSI type nodes across given traffic 4905 * class, and saves those value for later use for replaying purposes. The 4906 * caller holds the scheduler lock. 4907 */ 4908 static enum ice_status 4909 ice_sched_set_save_vsi_srl_node_bw(struct ice_port_info *pi, u16 vsi_handle, 4910 u8 tc, struct ice_sched_node *srl_node, 4911 enum ice_rl_type rl_type, u32 bw) 4912 { 4913 enum ice_status status; 4914 4915 if (bw == ICE_SCHED_DFLT_BW) { 4916 status = ice_sched_set_node_bw_dflt_lmt(pi, srl_node, rl_type); 4917 } else { 4918 status = ice_sched_set_node_bw_lmt(pi, srl_node, rl_type, bw); 4919 if (status) 4920 return status; 4921 status = ice_sched_save_vsi_bw(pi, vsi_handle, tc, rl_type, bw); 4922 } 4923 return status; 4924 } 4925 4926 /** 4927 * ice_sched_set_vsi_node_srl_per_tc - set VSI node BW shared limit for tc 4928 * @pi: port information structure 4929 * @vsi_handle: software VSI handle 4930 * @tc: traffic class 4931 * @min_bw: minimum bandwidth in Kbps 4932 * @max_bw: maximum bandwidth in Kbps 4933 * @shared_bw: shared bandwidth in Kbps 4934 * 4935 * Configure shared rate limiter(SRL) of VSI type nodes across requested 4936 * traffic class for VSI matching handle. When BW value of ICE_SCHED_DFLT_BW 4937 * is passed, it removes the corresponding bw from the node. The caller 4938 * holds scheduler lock. 4939 */ 4940 static enum ice_status 4941 ice_sched_set_vsi_node_srl_per_tc(struct ice_port_info *pi, u16 vsi_handle, 4942 u8 tc, u32 min_bw, u32 max_bw, u32 shared_bw) 4943 { 4944 struct ice_sched_node *tc_node, *vsi_node, *cfg_node; 4945 enum ice_status status; 4946 u8 layer_num; 4947 4948 tc_node = ice_sched_get_tc_node(pi, tc); 4949 if (!tc_node) 4950 return ICE_ERR_CFG; 4951 4952 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 4953 if (!vsi_node) 4954 return ICE_ERR_CFG; 4955 4956 layer_num = ice_sched_get_rl_prof_layer(pi, ICE_SHARED_BW, 4957 vsi_node->tx_sched_layer); 4958 if (layer_num >= pi->hw->num_tx_sched_layers) 4959 return ICE_ERR_PARAM; 4960 4961 /* SRL node may be different */ 4962 cfg_node = ice_sched_get_srl_node(vsi_node, layer_num); 4963 if (!cfg_node) 4964 return ICE_ERR_CFG; 4965 4966 status = ice_sched_set_save_vsi_srl_node_bw(pi, vsi_handle, tc, 4967 cfg_node, ICE_MIN_BW, 4968 min_bw); 4969 if (status) 4970 return status; 4971 4972 status = ice_sched_set_save_vsi_srl_node_bw(pi, vsi_handle, tc, 4973 cfg_node, ICE_MAX_BW, 4974 max_bw); 4975 if (status) 4976 return status; 4977 4978 return ice_sched_set_save_vsi_srl_node_bw(pi, vsi_handle, tc, cfg_node, 4979 ICE_SHARED_BW, shared_bw); 4980 } 4981 4982 /** 4983 * ice_sched_set_vsi_bw_shared_lmt - set VSI BW shared limit 4984 * @pi: port information structure 4985 * @vsi_handle: software VSI handle 4986 * @min_bw: minimum bandwidth in Kbps 4987 * @max_bw: maximum bandwidth in Kbps 4988 * @shared_bw: shared bandwidth in Kbps 4989 * 4990 * Configure shared rate limiter(SRL) of all VSI type nodes across all traffic 4991 * classes for VSI matching handle. When BW value of ICE_SCHED_DFLT_BW is 4992 * passed, it removes those value(s) from the node. 4993 */ 4994 enum ice_status 4995 ice_sched_set_vsi_bw_shared_lmt(struct ice_port_info *pi, u16 vsi_handle, 4996 u32 min_bw, u32 max_bw, u32 shared_bw) 4997 { 4998 enum ice_status status = ICE_SUCCESS; 4999 u8 tc; 5000 5001 if (!pi) 5002 return ICE_ERR_PARAM; 5003 5004 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 5005 return ICE_ERR_PARAM; 5006 5007 ice_acquire_lock(&pi->sched_lock); 5008 status = ice_sched_validate_vsi_srl_node(pi, vsi_handle); 5009 if (status) 5010 goto exit_set_vsi_bw_shared_lmt; 5011 /* Return success if no nodes are present across TC */ 5012 ice_for_each_traffic_class(tc) { 5013 struct ice_sched_node *tc_node, *vsi_node; 5014 5015 tc_node = ice_sched_get_tc_node(pi, tc); 5016 if (!tc_node) 5017 continue; 5018 5019 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 5020 if (!vsi_node) 5021 continue; 5022 5023 status = ice_sched_set_vsi_node_srl_per_tc(pi, vsi_handle, tc, 5024 min_bw, max_bw, 5025 shared_bw); 5026 if (status) 5027 break; 5028 } 5029 5030 exit_set_vsi_bw_shared_lmt: 5031 ice_release_lock(&pi->sched_lock); 5032 return status; 5033 } 5034 5035 /** 5036 * ice_sched_validate_agg_srl_node - validate AGG SRL node 5037 * @pi: port information structure 5038 * @agg_id: aggregator ID 5039 * 5040 * This function validates SRL node of the AGG node if available SRL layer is 5041 * different than the AGG node layer on all TC(s).This function needs to be 5042 * called with scheduler lock held. 5043 */ 5044 static enum ice_status 5045 ice_sched_validate_agg_srl_node(struct ice_port_info *pi, u32 agg_id) 5046 { 5047 u8 sel_layer = ICE_SCHED_INVAL_LAYER_NUM; 5048 struct ice_sched_agg_info *agg_info; 5049 bool agg_id_present = false; 5050 enum ice_status status = ICE_SUCCESS; 5051 u8 tc; 5052 5053 LIST_FOR_EACH_ENTRY(agg_info, &pi->hw->agg_list, ice_sched_agg_info, 5054 list_entry) 5055 if (agg_info->agg_id == agg_id) { 5056 agg_id_present = true; 5057 break; 5058 } 5059 if (!agg_id_present) 5060 return ICE_ERR_PARAM; 5061 /* Return success if no nodes are present across TC */ 5062 ice_for_each_traffic_class(tc) { 5063 struct ice_sched_node *tc_node, *agg_node; 5064 enum ice_rl_type rl_type = ICE_SHARED_BW; 5065 5066 tc_node = ice_sched_get_tc_node(pi, tc); 5067 if (!tc_node) 5068 continue; 5069 5070 agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); 5071 if (!agg_node) 5072 continue; 5073 /* SRL bandwidth layer selection */ 5074 if (sel_layer == ICE_SCHED_INVAL_LAYER_NUM) { 5075 u8 node_layer = agg_node->tx_sched_layer; 5076 u8 layer_num; 5077 5078 layer_num = ice_sched_get_rl_prof_layer(pi, rl_type, 5079 node_layer); 5080 if (layer_num >= pi->hw->num_tx_sched_layers) 5081 return ICE_ERR_PARAM; 5082 sel_layer = layer_num; 5083 } 5084 5085 status = ice_sched_validate_srl_node(agg_node, sel_layer); 5086 if (status) 5087 break; 5088 } 5089 return status; 5090 } 5091 5092 /** 5093 * ice_sched_validate_agg_id - Validate aggregator id 5094 * @pi: port information structure 5095 * @agg_id: aggregator ID 5096 * 5097 * This function validates aggregator id. Caller holds the scheduler lock. 5098 */ 5099 static enum ice_status 5100 ice_sched_validate_agg_id(struct ice_port_info *pi, u32 agg_id) 5101 { 5102 struct ice_sched_agg_info *agg_info; 5103 struct ice_sched_agg_info *tmp; 5104 bool agg_id_present = false; 5105 enum ice_status status; 5106 5107 status = ice_sched_validate_agg_srl_node(pi, agg_id); 5108 if (status) 5109 return status; 5110 5111 LIST_FOR_EACH_ENTRY_SAFE(agg_info, tmp, &pi->hw->agg_list, 5112 ice_sched_agg_info, list_entry) 5113 if (agg_info->agg_id == agg_id) { 5114 agg_id_present = true; 5115 break; 5116 } 5117 5118 if (!agg_id_present) 5119 return ICE_ERR_PARAM; 5120 5121 return ICE_SUCCESS; 5122 } 5123 5124 /** 5125 * ice_sched_set_save_agg_srl_node_bw - set aggregator shared limit values 5126 * @pi: port information structure 5127 * @agg_id: aggregator ID 5128 * @tc: traffic class 5129 * @srl_node: sched node to configure 5130 * @rl_type: rate limit type minimum, maximum, or shared 5131 * @bw: minimum, maximum, or shared bandwidth in Kbps 5132 * 5133 * Configure shared rate limiter(SRL) of aggregator type nodes across 5134 * requested traffic class, and saves those value for later use for 5135 * replaying purposes. The caller holds the scheduler lock. 5136 */ 5137 static enum ice_status 5138 ice_sched_set_save_agg_srl_node_bw(struct ice_port_info *pi, u32 agg_id, u8 tc, 5139 struct ice_sched_node *srl_node, 5140 enum ice_rl_type rl_type, u32 bw) 5141 { 5142 enum ice_status status; 5143 5144 if (bw == ICE_SCHED_DFLT_BW) { 5145 status = ice_sched_set_node_bw_dflt_lmt(pi, srl_node, rl_type); 5146 } else { 5147 status = ice_sched_set_node_bw_lmt(pi, srl_node, rl_type, bw); 5148 if (status) 5149 return status; 5150 status = ice_sched_save_agg_bw(pi, agg_id, tc, rl_type, bw); 5151 } 5152 return status; 5153 } 5154 5155 /** 5156 * ice_sched_set_agg_node_srl_per_tc - set aggregator SRL per tc 5157 * @pi: port information structure 5158 * @agg_id: aggregator ID 5159 * @tc: traffic class 5160 * @min_bw: minimum bandwidth in Kbps 5161 * @max_bw: maximum bandwidth in Kbps 5162 * @shared_bw: shared bandwidth in Kbps 5163 * 5164 * This function configures the shared rate limiter(SRL) of aggregator type 5165 * node for a given traffic class for aggregator matching agg_id. When BW 5166 * value of ICE_SCHED_DFLT_BW is passed, it removes SRL from the node. Caller 5167 * holds the scheduler lock. 5168 */ 5169 static enum ice_status 5170 ice_sched_set_agg_node_srl_per_tc(struct ice_port_info *pi, u32 agg_id, 5171 u8 tc, u32 min_bw, u32 max_bw, u32 shared_bw) 5172 { 5173 struct ice_sched_node *tc_node, *agg_node, *cfg_node; 5174 enum ice_rl_type rl_type = ICE_SHARED_BW; 5175 enum ice_status status = ICE_ERR_CFG; 5176 u8 layer_num; 5177 5178 tc_node = ice_sched_get_tc_node(pi, tc); 5179 if (!tc_node) 5180 return ICE_ERR_CFG; 5181 5182 agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); 5183 if (!agg_node) 5184 return ICE_ERR_CFG; 5185 5186 layer_num = ice_sched_get_rl_prof_layer(pi, rl_type, 5187 agg_node->tx_sched_layer); 5188 if (layer_num >= pi->hw->num_tx_sched_layers) 5189 return ICE_ERR_PARAM; 5190 5191 /* SRL node may be different */ 5192 cfg_node = ice_sched_get_srl_node(agg_node, layer_num); 5193 if (!cfg_node) 5194 return ICE_ERR_CFG; 5195 5196 status = ice_sched_set_save_agg_srl_node_bw(pi, agg_id, tc, cfg_node, 5197 ICE_MIN_BW, min_bw); 5198 if (status) 5199 return status; 5200 5201 status = ice_sched_set_save_agg_srl_node_bw(pi, agg_id, tc, cfg_node, 5202 ICE_MAX_BW, max_bw); 5203 if (status) 5204 return status; 5205 5206 status = ice_sched_set_save_agg_srl_node_bw(pi, agg_id, tc, cfg_node, 5207 ICE_SHARED_BW, shared_bw); 5208 return status; 5209 } 5210 5211 /** 5212 * ice_sched_set_agg_bw_shared_lmt - set aggregator BW shared limit 5213 * @pi: port information structure 5214 * @agg_id: aggregator ID 5215 * @min_bw: minimum bandwidth in Kbps 5216 * @max_bw: maximum bandwidth in Kbps 5217 * @shared_bw: shared bandwidth in Kbps 5218 * 5219 * This function configures the shared rate limiter(SRL) of all aggregator type 5220 * nodes across all traffic classes for aggregator matching agg_id. When 5221 * BW value of ICE_SCHED_DFLT_BW is passed, it removes SRL from the 5222 * node(s). 5223 */ 5224 enum ice_status 5225 ice_sched_set_agg_bw_shared_lmt(struct ice_port_info *pi, u32 agg_id, 5226 u32 min_bw, u32 max_bw, u32 shared_bw) 5227 { 5228 enum ice_status status; 5229 u8 tc; 5230 5231 if (!pi) 5232 return ICE_ERR_PARAM; 5233 5234 ice_acquire_lock(&pi->sched_lock); 5235 status = ice_sched_validate_agg_id(pi, agg_id); 5236 if (status) 5237 goto exit_agg_bw_shared_lmt; 5238 5239 /* Return success if no nodes are present across TC */ 5240 ice_for_each_traffic_class(tc) { 5241 struct ice_sched_node *tc_node, *agg_node; 5242 5243 tc_node = ice_sched_get_tc_node(pi, tc); 5244 if (!tc_node) 5245 continue; 5246 5247 agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); 5248 if (!agg_node) 5249 continue; 5250 5251 status = ice_sched_set_agg_node_srl_per_tc(pi, agg_id, tc, 5252 min_bw, max_bw, 5253 shared_bw); 5254 if (status) 5255 break; 5256 } 5257 5258 exit_agg_bw_shared_lmt: 5259 ice_release_lock(&pi->sched_lock); 5260 return status; 5261 } 5262 5263 /** 5264 * ice_sched_set_agg_bw_shared_lmt_per_tc - set aggregator BW shared lmt per tc 5265 * @pi: port information structure 5266 * @agg_id: aggregator ID 5267 * @tc: traffic class 5268 * @min_bw: minimum bandwidth in Kbps 5269 * @max_bw: maximum bandwidth in Kbps 5270 * @shared_bw: shared bandwidth in Kbps 5271 * 5272 * This function configures the shared rate limiter(SRL) of aggregator type 5273 * node for a given traffic class for aggregator matching agg_id. When BW 5274 * value of ICE_SCHED_DFLT_BW is passed, it removes SRL from the node. 5275 */ 5276 enum ice_status 5277 ice_sched_set_agg_bw_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, 5278 u8 tc, u32 min_bw, u32 max_bw, 5279 u32 shared_bw) 5280 { 5281 enum ice_status status; 5282 5283 if (!pi) 5284 return ICE_ERR_PARAM; 5285 ice_acquire_lock(&pi->sched_lock); 5286 status = ice_sched_validate_agg_id(pi, agg_id); 5287 if (status) 5288 goto exit_agg_bw_shared_lmt_per_tc; 5289 5290 status = ice_sched_set_agg_node_srl_per_tc(pi, agg_id, tc, min_bw, 5291 max_bw, shared_bw); 5292 5293 exit_agg_bw_shared_lmt_per_tc: 5294 ice_release_lock(&pi->sched_lock); 5295 return status; 5296 } 5297 5298 /** 5299 * ice_sched_cfg_sibl_node_prio - configure node sibling priority 5300 * @pi: port information structure 5301 * @node: sched node to configure 5302 * @priority: sibling priority 5303 * 5304 * This function configures node element's sibling priority only. This 5305 * function needs to be called with scheduler lock held. 5306 */ 5307 enum ice_status 5308 ice_sched_cfg_sibl_node_prio(struct ice_port_info *pi, 5309 struct ice_sched_node *node, u8 priority) 5310 { 5311 struct ice_aqc_txsched_elem_data buf; 5312 struct ice_aqc_txsched_elem *data; 5313 struct ice_hw *hw = pi->hw; 5314 enum ice_status status; 5315 5316 if (!hw) 5317 return ICE_ERR_PARAM; 5318 buf = node->info; 5319 data = &buf.data; 5320 data->valid_sections |= ICE_AQC_ELEM_VALID_GENERIC; 5321 priority = (priority << ICE_AQC_ELEM_GENERIC_PRIO_S) & 5322 ICE_AQC_ELEM_GENERIC_PRIO_M; 5323 data->generic &= ~ICE_AQC_ELEM_GENERIC_PRIO_M; 5324 data->generic |= priority; 5325 5326 /* Configure element */ 5327 status = ice_sched_update_elem(hw, node, &buf); 5328 return status; 5329 } 5330 5331 /** 5332 * ice_cfg_rl_burst_size - Set burst size value 5333 * @hw: pointer to the HW struct 5334 * @bytes: burst size in bytes 5335 * 5336 * This function configures/set the burst size to requested new value. The new 5337 * burst size value is used for future rate limit calls. It doesn't change the 5338 * existing or previously created RL profiles. 5339 */ 5340 enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes) 5341 { 5342 u16 burst_size_to_prog; 5343 5344 if (bytes < ICE_MIN_BURST_SIZE_ALLOWED || 5345 bytes > ICE_MAX_BURST_SIZE_ALLOWED) 5346 return ICE_ERR_PARAM; 5347 if (ice_round_to_num(bytes, 64) <= 5348 ICE_MAX_BURST_SIZE_64_BYTE_GRANULARITY) { 5349 /* 64 byte granularity case */ 5350 /* Disable MSB granularity bit */ 5351 burst_size_to_prog = ICE_64_BYTE_GRANULARITY; 5352 /* round number to nearest 64 byte granularity */ 5353 bytes = ice_round_to_num(bytes, 64); 5354 /* The value is in 64 byte chunks */ 5355 burst_size_to_prog |= (u16)(bytes / 64); 5356 } else { 5357 /* k bytes granularity case */ 5358 /* Enable MSB granularity bit */ 5359 burst_size_to_prog = ICE_KBYTE_GRANULARITY; 5360 /* round number to nearest 1024 granularity */ 5361 bytes = ice_round_to_num(bytes, 1024); 5362 /* check rounding doesn't go beyond allowed */ 5363 if (bytes > ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY) 5364 bytes = ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY; 5365 /* The value is in k bytes */ 5366 burst_size_to_prog |= (u16)(bytes / 1024); 5367 } 5368 hw->max_burst_size = burst_size_to_prog; 5369 return ICE_SUCCESS; 5370 } 5371 5372 /** 5373 * ice_sched_replay_node_prio - re-configure node priority 5374 * @hw: pointer to the HW struct 5375 * @node: sched node to configure 5376 * @priority: priority value 5377 * 5378 * This function configures node element's priority value. It 5379 * needs to be called with scheduler lock held. 5380 */ 5381 static enum ice_status 5382 ice_sched_replay_node_prio(struct ice_hw *hw, struct ice_sched_node *node, 5383 u8 priority) 5384 { 5385 struct ice_aqc_txsched_elem_data buf; 5386 struct ice_aqc_txsched_elem *data; 5387 enum ice_status status; 5388 5389 buf = node->info; 5390 data = &buf.data; 5391 data->valid_sections |= ICE_AQC_ELEM_VALID_GENERIC; 5392 data->generic = priority; 5393 5394 /* Configure element */ 5395 status = ice_sched_update_elem(hw, node, &buf); 5396 return status; 5397 } 5398 5399 /** 5400 * ice_sched_replay_node_bw - replay node(s) BW 5401 * @hw: pointer to the HW struct 5402 * @node: sched node to configure 5403 * @bw_t_info: BW type information 5404 * 5405 * This function restores node's BW from bw_t_info. The caller needs 5406 * to hold the scheduler lock. 5407 */ 5408 static enum ice_status 5409 ice_sched_replay_node_bw(struct ice_hw *hw, struct ice_sched_node *node, 5410 struct ice_bw_type_info *bw_t_info) 5411 { 5412 struct ice_port_info *pi = hw->port_info; 5413 enum ice_status status = ICE_ERR_PARAM; 5414 u16 bw_alloc; 5415 5416 if (!node) 5417 return status; 5418 if (!ice_is_any_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_CNT)) 5419 return ICE_SUCCESS; 5420 if (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_PRIO)) { 5421 status = ice_sched_replay_node_prio(hw, node, 5422 bw_t_info->generic); 5423 if (status) 5424 return status; 5425 } 5426 if (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_CIR)) { 5427 status = ice_sched_set_node_bw_lmt(pi, node, ICE_MIN_BW, 5428 bw_t_info->cir_bw.bw); 5429 if (status) 5430 return status; 5431 } 5432 if (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_CIR_WT)) { 5433 bw_alloc = bw_t_info->cir_bw.bw_alloc; 5434 status = ice_sched_cfg_node_bw_alloc(hw, node, ICE_MIN_BW, 5435 bw_alloc); 5436 if (status) 5437 return status; 5438 } 5439 if (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_EIR)) { 5440 status = ice_sched_set_node_bw_lmt(pi, node, ICE_MAX_BW, 5441 bw_t_info->eir_bw.bw); 5442 if (status) 5443 return status; 5444 } 5445 if (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_EIR_WT)) { 5446 bw_alloc = bw_t_info->eir_bw.bw_alloc; 5447 status = ice_sched_cfg_node_bw_alloc(hw, node, ICE_MAX_BW, 5448 bw_alloc); 5449 if (status) 5450 return status; 5451 } 5452 if (ice_is_bit_set(bw_t_info->bw_t_bitmap, ICE_BW_TYPE_SHARED)) 5453 status = ice_sched_set_node_bw_lmt(pi, node, ICE_SHARED_BW, 5454 bw_t_info->shared_bw); 5455 return status; 5456 } 5457 5458 /** 5459 * ice_sched_replay_agg_bw - replay aggregator node(s) BW 5460 * @hw: pointer to the HW struct 5461 * @agg_info: aggregator data structure 5462 * 5463 * This function re-creates aggregator type nodes. The caller needs to hold 5464 * the scheduler lock. 5465 */ 5466 static enum ice_status 5467 ice_sched_replay_agg_bw(struct ice_hw *hw, struct ice_sched_agg_info *agg_info) 5468 { 5469 struct ice_sched_node *tc_node, *agg_node; 5470 enum ice_status status = ICE_SUCCESS; 5471 u8 tc; 5472 5473 if (!agg_info) 5474 return ICE_ERR_PARAM; 5475 ice_for_each_traffic_class(tc) { 5476 if (!ice_is_any_bit_set(agg_info->bw_t_info[tc].bw_t_bitmap, 5477 ICE_BW_TYPE_CNT)) 5478 continue; 5479 tc_node = ice_sched_get_tc_node(hw->port_info, tc); 5480 if (!tc_node) { 5481 status = ICE_ERR_PARAM; 5482 break; 5483 } 5484 agg_node = ice_sched_get_agg_node(hw->port_info, tc_node, 5485 agg_info->agg_id); 5486 if (!agg_node) { 5487 status = ICE_ERR_PARAM; 5488 break; 5489 } 5490 status = ice_sched_replay_node_bw(hw, agg_node, 5491 &agg_info->bw_t_info[tc]); 5492 if (status) 5493 break; 5494 } 5495 return status; 5496 } 5497 5498 /** 5499 * ice_sched_get_ena_tc_bitmap - get enabled TC bitmap 5500 * @pi: port info struct 5501 * @tc_bitmap: 8 bits TC bitmap to check 5502 * @ena_tc_bitmap: 8 bits enabled TC bitmap to return 5503 * 5504 * This function returns enabled TC bitmap in variable ena_tc_bitmap. Some TCs 5505 * may be missing, it returns enabled TCs. This function needs to be called with 5506 * scheduler lock held. 5507 */ 5508 static void 5509 ice_sched_get_ena_tc_bitmap(struct ice_port_info *pi, ice_bitmap_t *tc_bitmap, 5510 ice_bitmap_t *ena_tc_bitmap) 5511 { 5512 u8 tc; 5513 5514 /* Some TC(s) may be missing after reset, adjust for replay */ 5515 ice_for_each_traffic_class(tc) 5516 if (ice_is_tc_ena(*tc_bitmap, tc) && 5517 (ice_sched_get_tc_node(pi, tc))) 5518 ice_set_bit(tc, ena_tc_bitmap); 5519 } 5520 5521 /** 5522 * ice_sched_replay_agg - recreate aggregator node(s) 5523 * @hw: pointer to the HW struct 5524 * 5525 * This function recreate aggregator type nodes which are not replayed earlier. 5526 * It also replay aggregator BW information. These aggregator nodes are not 5527 * associated with VSI type node yet. 5528 */ 5529 void ice_sched_replay_agg(struct ice_hw *hw) 5530 { 5531 struct ice_port_info *pi = hw->port_info; 5532 struct ice_sched_agg_info *agg_info; 5533 5534 ice_acquire_lock(&pi->sched_lock); 5535 LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info, 5536 list_entry) 5537 /* replay aggregator (re-create aggregator node) */ 5538 if (!ice_cmp_bitmap(agg_info->tc_bitmap, 5539 agg_info->replay_tc_bitmap, 5540 ICE_MAX_TRAFFIC_CLASS)) { 5541 ice_declare_bitmap(replay_bitmap, 5542 ICE_MAX_TRAFFIC_CLASS); 5543 enum ice_status status; 5544 5545 ice_zero_bitmap(replay_bitmap, ICE_MAX_TRAFFIC_CLASS); 5546 ice_sched_get_ena_tc_bitmap(pi, 5547 agg_info->replay_tc_bitmap, 5548 replay_bitmap); 5549 status = ice_sched_cfg_agg(hw->port_info, 5550 agg_info->agg_id, 5551 ICE_AGG_TYPE_AGG, 5552 replay_bitmap); 5553 if (status) { 5554 ice_info(hw, "Replay agg id[%d] failed\n", 5555 agg_info->agg_id); 5556 /* Move on to next one */ 5557 continue; 5558 } 5559 /* Replay aggregator node BW (restore aggregator BW) */ 5560 status = ice_sched_replay_agg_bw(hw, agg_info); 5561 if (status) 5562 ice_info(hw, "Replay agg bw [id=%d] failed\n", 5563 agg_info->agg_id); 5564 } 5565 ice_release_lock(&pi->sched_lock); 5566 } 5567 5568 /** 5569 * ice_sched_replay_agg_vsi_preinit - Agg/VSI replay pre initialization 5570 * @hw: pointer to the HW struct 5571 * 5572 * This function initialize aggregator(s) TC bitmap to zero. A required 5573 * preinit step for replaying aggregators. 5574 */ 5575 void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw) 5576 { 5577 struct ice_port_info *pi = hw->port_info; 5578 struct ice_sched_agg_info *agg_info; 5579 5580 ice_acquire_lock(&pi->sched_lock); 5581 LIST_FOR_EACH_ENTRY(agg_info, &hw->agg_list, ice_sched_agg_info, 5582 list_entry) { 5583 struct ice_sched_agg_vsi_info *agg_vsi_info; 5584 5585 agg_info->tc_bitmap[0] = 0; 5586 LIST_FOR_EACH_ENTRY(agg_vsi_info, &agg_info->agg_vsi_list, 5587 ice_sched_agg_vsi_info, list_entry) 5588 agg_vsi_info->tc_bitmap[0] = 0; 5589 } 5590 ice_release_lock(&pi->sched_lock); 5591 } 5592 5593 /** 5594 * ice_sched_replay_root_node_bw - replay root node BW 5595 * @pi: port information structure 5596 * 5597 * Replay root node BW settings. 5598 */ 5599 enum ice_status ice_sched_replay_root_node_bw(struct ice_port_info *pi) 5600 { 5601 enum ice_status status = ICE_SUCCESS; 5602 5603 if (!pi->hw) 5604 return ICE_ERR_PARAM; 5605 ice_acquire_lock(&pi->sched_lock); 5606 5607 status = ice_sched_replay_node_bw(pi->hw, pi->root, 5608 &pi->root_node_bw_t_info); 5609 ice_release_lock(&pi->sched_lock); 5610 return status; 5611 } 5612 5613 /** 5614 * ice_sched_replay_tc_node_bw - replay TC node(s) BW 5615 * @pi: port information structure 5616 * 5617 * This function replay TC nodes. 5618 */ 5619 enum ice_status ice_sched_replay_tc_node_bw(struct ice_port_info *pi) 5620 { 5621 enum ice_status status = ICE_SUCCESS; 5622 u8 tc; 5623 5624 if (!pi->hw) 5625 return ICE_ERR_PARAM; 5626 ice_acquire_lock(&pi->sched_lock); 5627 ice_for_each_traffic_class(tc) { 5628 struct ice_sched_node *tc_node; 5629 5630 tc_node = ice_sched_get_tc_node(pi, tc); 5631 if (!tc_node) 5632 continue; /* TC not present */ 5633 status = ice_sched_replay_node_bw(pi->hw, tc_node, 5634 &pi->tc_node_bw_t_info[tc]); 5635 if (status) 5636 break; 5637 } 5638 ice_release_lock(&pi->sched_lock); 5639 return status; 5640 } 5641 5642 /** 5643 * ice_sched_replay_vsi_bw - replay VSI type node(s) BW 5644 * @hw: pointer to the HW struct 5645 * @vsi_handle: software VSI handle 5646 * @tc_bitmap: 8 bits TC bitmap 5647 * 5648 * This function replays VSI type nodes bandwidth. This function needs to be 5649 * called with scheduler lock held. 5650 */ 5651 static enum ice_status 5652 ice_sched_replay_vsi_bw(struct ice_hw *hw, u16 vsi_handle, 5653 ice_bitmap_t *tc_bitmap) 5654 { 5655 struct ice_sched_node *vsi_node, *tc_node; 5656 struct ice_port_info *pi = hw->port_info; 5657 struct ice_bw_type_info *bw_t_info; 5658 struct ice_vsi_ctx *vsi_ctx; 5659 enum ice_status status = ICE_SUCCESS; 5660 u8 tc; 5661 5662 vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle); 5663 if (!vsi_ctx) 5664 return ICE_ERR_PARAM; 5665 ice_for_each_traffic_class(tc) { 5666 if (!ice_is_tc_ena(*tc_bitmap, tc)) 5667 continue; 5668 tc_node = ice_sched_get_tc_node(pi, tc); 5669 if (!tc_node) 5670 continue; 5671 vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); 5672 if (!vsi_node) 5673 continue; 5674 bw_t_info = &vsi_ctx->sched.bw_t_info[tc]; 5675 status = ice_sched_replay_node_bw(hw, vsi_node, bw_t_info); 5676 if (status) 5677 break; 5678 } 5679 return status; 5680 } 5681 5682 /** 5683 * ice_sched_replay_vsi_agg - replay aggregator & VSI to aggregator node(s) 5684 * @hw: pointer to the HW struct 5685 * @vsi_handle: software VSI handle 5686 * 5687 * This function replays aggregator node, VSI to aggregator type nodes, and 5688 * their node bandwidth information. This function needs to be called with 5689 * scheduler lock held. 5690 */ 5691 static enum ice_status 5692 ice_sched_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle) 5693 { 5694 ice_declare_bitmap(replay_bitmap, ICE_MAX_TRAFFIC_CLASS); 5695 struct ice_sched_agg_vsi_info *agg_vsi_info; 5696 struct ice_port_info *pi = hw->port_info; 5697 struct ice_sched_agg_info *agg_info; 5698 enum ice_status status; 5699 5700 ice_zero_bitmap(replay_bitmap, ICE_MAX_TRAFFIC_CLASS); 5701 if (!ice_is_vsi_valid(hw, vsi_handle)) 5702 return ICE_ERR_PARAM; 5703 agg_info = ice_get_vsi_agg_info(hw, vsi_handle); 5704 if (!agg_info) 5705 return ICE_SUCCESS; /* Not present in list - default Agg case */ 5706 agg_vsi_info = ice_get_agg_vsi_info(agg_info, vsi_handle); 5707 if (!agg_vsi_info) 5708 return ICE_SUCCESS; /* Not present in list - default Agg case */ 5709 ice_sched_get_ena_tc_bitmap(pi, agg_info->replay_tc_bitmap, 5710 replay_bitmap); 5711 /* Replay aggregator node associated to vsi_handle */ 5712 status = ice_sched_cfg_agg(hw->port_info, agg_info->agg_id, 5713 ICE_AGG_TYPE_AGG, replay_bitmap); 5714 if (status) 5715 return status; 5716 /* Replay aggregator node BW (restore aggregator BW) */ 5717 status = ice_sched_replay_agg_bw(hw, agg_info); 5718 if (status) 5719 return status; 5720 5721 ice_zero_bitmap(replay_bitmap, ICE_MAX_TRAFFIC_CLASS); 5722 ice_sched_get_ena_tc_bitmap(pi, agg_vsi_info->replay_tc_bitmap, 5723 replay_bitmap); 5724 /* Move this VSI (vsi_handle) to above aggregator */ 5725 status = ice_sched_assoc_vsi_to_agg(pi, agg_info->agg_id, vsi_handle, 5726 replay_bitmap); 5727 if (status) 5728 return status; 5729 /* Replay VSI BW (restore VSI BW) */ 5730 return ice_sched_replay_vsi_bw(hw, vsi_handle, 5731 agg_vsi_info->tc_bitmap); 5732 } 5733 5734 /** 5735 * ice_replay_vsi_agg - replay VSI to aggregator node 5736 * @hw: pointer to the HW struct 5737 * @vsi_handle: software VSI handle 5738 * 5739 * This function replays association of VSI to aggregator type nodes, and 5740 * node bandwidth information. 5741 */ 5742 enum ice_status ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle) 5743 { 5744 struct ice_port_info *pi = hw->port_info; 5745 enum ice_status status; 5746 5747 ice_acquire_lock(&pi->sched_lock); 5748 status = ice_sched_replay_vsi_agg(hw, vsi_handle); 5749 ice_release_lock(&pi->sched_lock); 5750 return status; 5751 } 5752 5753 /** 5754 * ice_sched_replay_q_bw - replay queue type node BW 5755 * @pi: port information structure 5756 * @q_ctx: queue context structure 5757 * 5758 * This function replays queue type node bandwidth. This function needs to be 5759 * called with scheduler lock held. 5760 */ 5761 enum ice_status 5762 ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx) 5763 { 5764 struct ice_sched_node *q_node; 5765 5766 /* Following also checks the presence of node in tree */ 5767 q_node = ice_sched_find_node_by_teid(pi->root, q_ctx->q_teid); 5768 if (!q_node) 5769 return ICE_ERR_PARAM; 5770 return ice_sched_replay_node_bw(pi->hw, q_node, &q_ctx->bw_t_info); 5771 } 5772