1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2024, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _ICE_SBQ_CMD_H_ 33 #define _ICE_SBQ_CMD_H_ 34 35 /* This header file defines the Sideband Queue commands, error codes and 36 * descriptor format. It is shared between Firmware and Software. 37 */ 38 39 /* Sideband Queue command structure and opcodes */ 40 enum ice_sbq_opc { 41 /* Sideband Queue commands */ 42 ice_sbq_opc_neigh_dev_req = 0x0C00, 43 ice_sbq_opc_neigh_dev_ev = 0x0C01 44 }; 45 46 /* Sideband Queue descriptor. Indirect command 47 * and non posted 48 */ 49 struct ice_sbq_cmd_desc { 50 __le16 flags; 51 __le16 opcode; 52 __le16 datalen; 53 __le16 cmd_retval; 54 55 /* Opaque message data */ 56 __le32 cookie_high; 57 __le32 cookie_low; 58 59 union { 60 __le16 cmd_len; 61 __le16 cmpl_len; 62 } param0; 63 64 u8 reserved[6]; 65 __le32 addr_high; 66 __le32 addr_low; 67 }; 68 69 struct ice_sbq_evt_desc { 70 __le16 flags; 71 __le16 opcode; 72 __le16 datalen; 73 __le16 cmd_retval; 74 u8 data[24]; 75 }; 76 77 enum ice_sbq_msg_dev { 78 rmn_0 = 0x02, 79 rmn_1 = 0x03, 80 rmn_2 = 0x04, 81 cgu = 0x06 82 }; 83 84 enum ice_sbq_msg_opcode { 85 ice_sbq_msg_rd = 0x00, 86 ice_sbq_msg_wr = 0x01 87 }; 88 89 #define ICE_SBQ_MSG_FLAGS 0x40 90 #define ICE_SBQ_MSG_SBE_FBE 0x0F 91 92 struct ice_sbq_msg_req { 93 u8 dest_dev; 94 u8 src_dev; 95 u8 opcode; 96 u8 flags; 97 u8 sbe_fbe; 98 u8 func_id; 99 __le16 msg_addr_low; 100 __le32 msg_addr_high; 101 __le32 data; 102 }; 103 104 struct ice_sbq_msg_cmpl { 105 u8 dest_dev; 106 u8 src_dev; 107 u8 opcode; 108 u8 flags; 109 __le32 data; 110 }; 111 112 /* Internal struct */ 113 struct ice_sbq_msg_input { 114 u8 dest_dev; 115 u8 opcode; 116 u16 msg_addr_low; 117 u32 msg_addr_high; 118 u32 data; 119 }; 120 #endif /* _ICE_SBQ_CMD_H_ */ 121