xref: /freebsd/sys/dev/ice/ice_controlq.h (revision c66ec88fed842fbaad62c30d510644ceb7bd2d71)
1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /*  Copyright (c) 2020, Intel Corporation
3  *  All rights reserved.
4  *
5  *  Redistribution and use in source and binary forms, with or without
6  *  modification, are permitted provided that the following conditions are met:
7  *
8  *   1. Redistributions of source code must retain the above copyright notice,
9  *      this list of conditions and the following disclaimer.
10  *
11  *   2. Redistributions in binary form must reproduce the above copyright
12  *      notice, this list of conditions and the following disclaimer in the
13  *      documentation and/or other materials provided with the distribution.
14  *
15  *   3. Neither the name of the Intel Corporation nor the names of its
16  *      contributors may be used to endorse or promote products derived from
17  *      this software without specific prior written permission.
18  *
19  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  *  POSSIBILITY OF SUCH DAMAGE.
30  */
31 /*$FreeBSD$*/
32 
33 #ifndef _ICE_CONTROLQ_H_
34 #define _ICE_CONTROLQ_H_
35 
36 #include "ice_adminq_cmd.h"
37 
38 /* Maximum buffer lengths for all control queue types */
39 #define ICE_AQ_MAX_BUF_LEN 4096
40 #define ICE_MBXQ_MAX_BUF_LEN 4096
41 
42 #define ICE_CTL_Q_DESC(R, i) \
43 	(&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))
44 
45 #define ICE_CTL_Q_DESC_UNUSED(R) \
46 	(u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
47 	      (R)->next_to_clean - (R)->next_to_use - 1)
48 
49 /* Defines that help manage the driver vs FW API checks.
50  * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage.
51  */
52 #define EXP_FW_API_VER_BRANCH		0x00
53 #define EXP_FW_API_VER_MAJOR		0x01
54 #define EXP_FW_API_VER_MINOR		0x05
55 
56 /* Different control queue types: These are mainly for SW consumption. */
57 enum ice_ctl_q {
58 	ICE_CTL_Q_UNKNOWN = 0,
59 	ICE_CTL_Q_ADMIN,
60 	ICE_CTL_Q_MAILBOX,
61 };
62 
63 /* Control Queue timeout settings - max delay 250ms */
64 #define ICE_CTL_Q_SQ_CMD_TIMEOUT	2500  /* Count 2500 times */
65 #define ICE_CTL_Q_SQ_CMD_USEC		100   /* Check every 100usec */
66 #define ICE_CTL_Q_ADMIN_INIT_TIMEOUT	10    /* Count 10 times */
67 #define ICE_CTL_Q_ADMIN_INIT_MSEC	100   /* Check every 100msec */
68 
69 struct ice_ctl_q_ring {
70 	void *dma_head;			/* Virtual address to DMA head */
71 	struct ice_dma_mem desc_buf;	/* descriptor ring memory */
72 	void *cmd_buf;			/* command buffer memory */
73 
74 	union {
75 		struct ice_dma_mem *sq_bi;
76 		struct ice_dma_mem *rq_bi;
77 	} r;
78 
79 	u16 count;		/* Number of descriptors */
80 
81 	/* used for interrupt processing */
82 	u16 next_to_use;
83 	u16 next_to_clean;
84 
85 	/* used for queue tracking */
86 	u32 head;
87 	u32 tail;
88 	u32 len;
89 	u32 bah;
90 	u32 bal;
91 	u32 len_mask;
92 	u32 len_ena_mask;
93 	u32 len_crit_mask;
94 	u32 head_mask;
95 };
96 
97 /* sq transaction details */
98 struct ice_sq_cd {
99 	struct ice_aq_desc *wb_desc;
100 };
101 
102 #define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i]))
103 
104 /* rq event information */
105 struct ice_rq_event_info {
106 	struct ice_aq_desc desc;
107 	u16 msg_len;
108 	u16 buf_len;
109 	u8 *msg_buf;
110 };
111 
112 /* Control Queue information */
113 struct ice_ctl_q_info {
114 	enum ice_ctl_q qtype;
115 	enum ice_aq_err rq_last_status;	/* last status on receive queue */
116 	struct ice_ctl_q_ring rq;	/* receive queue */
117 	struct ice_ctl_q_ring sq;	/* send queue */
118 	u32 sq_cmd_timeout;		/* send queue cmd write back timeout */
119 	u16 num_rq_entries;		/* receive queue depth */
120 	u16 num_sq_entries;		/* send queue depth */
121 	u16 rq_buf_size;		/* receive queue buffer size */
122 	u16 sq_buf_size;		/* send queue buffer size */
123 	enum ice_aq_err sq_last_status;	/* last status on send queue */
124 	struct ice_lock sq_lock;		/* Send queue lock */
125 	struct ice_lock rq_lock;		/* Receive queue lock */
126 };
127 
128 #endif /* _ICE_CONTROLQ_H_ */
129