1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2021, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*$FreeBSD$*/ 32 33 #ifndef _ICE_COMMON_H_ 34 #define _ICE_COMMON_H_ 35 36 #include "ice_type.h" 37 #include "ice_nvm.h" 38 #include "ice_flex_pipe.h" 39 #include "virtchnl.h" 40 #include "ice_switch.h" 41 42 enum ice_fw_modes { 43 ICE_FW_MODE_NORMAL, 44 ICE_FW_MODE_DBG, 45 ICE_FW_MODE_REC, 46 ICE_FW_MODE_ROLLBACK 47 }; 48 49 void ice_idle_aq(struct ice_hw *hw, struct ice_ctl_q_info *cq); 50 bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq); 51 52 enum ice_status ice_init_hw(struct ice_hw *hw); 53 void ice_deinit_hw(struct ice_hw *hw); 54 enum ice_status ice_check_reset(struct ice_hw *hw); 55 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req); 56 57 enum ice_status ice_create_all_ctrlq(struct ice_hw *hw); 58 enum ice_status ice_init_all_ctrlq(struct ice_hw *hw); 59 void ice_shutdown_all_ctrlq(struct ice_hw *hw); 60 void ice_destroy_all_ctrlq(struct ice_hw *hw); 61 enum ice_status 62 ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq, 63 struct ice_rq_event_info *e, u16 *pending); 64 enum ice_status 65 ice_get_link_status(struct ice_port_info *pi, bool *link_up); 66 enum ice_status ice_update_link_info(struct ice_port_info *pi); 67 enum ice_status 68 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 69 enum ice_aq_res_access_type access, u32 timeout); 70 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res); 71 enum ice_status 72 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res); 73 enum ice_status 74 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res); 75 enum ice_status 76 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 77 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 78 enum ice_adminq_opc opc, struct ice_sq_cd *cd); 79 enum ice_status 80 ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, 81 struct ice_aq_desc *desc, void *buf, u16 buf_size, 82 struct ice_sq_cd *cd); 83 void ice_clear_pxe_mode(struct ice_hw *hw); 84 85 enum ice_status ice_get_caps(struct ice_hw *hw); 86 87 void ice_set_safe_mode_caps(struct ice_hw *hw); 88 89 enum ice_status ice_set_mac_type(struct ice_hw *hw); 90 91 /* Define a macro that will align a pointer to point to the next memory address 92 * that falls on the given power of 2 (i.e., 2, 4, 8, 16, 32, 64...). For 93 * example, given the variable pointer = 0x1006, then after the following call: 94 * 95 * pointer = ICE_ALIGN(pointer, 4) 96 * 97 * ... the value of pointer would equal 0x1008, since 0x1008 is the next 98 * address after 0x1006 which is divisible by 4. 99 */ 100 #define ICE_ALIGN(ptr, align) (((ptr) + ((align) - 1)) & ~((align) - 1)) 101 102 enum ice_status 103 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 104 u32 rxq_index); 105 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index); 106 enum ice_status 107 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index); 108 enum ice_status 109 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw, 110 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx, 111 u32 tx_cmpltnq_index); 112 enum ice_status 113 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index); 114 enum ice_status 115 ice_write_tx_drbell_q_ctx(struct ice_hw *hw, 116 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx, 117 u32 tx_drbell_q_index); 118 119 enum ice_status 120 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params); 121 enum ice_status 122 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params); 123 enum ice_status 124 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 125 struct ice_aqc_get_set_rss_keys *keys); 126 enum ice_status 127 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 128 struct ice_aqc_get_set_rss_keys *keys); 129 enum ice_status 130 ice_aq_add_lan_txq(struct ice_hw *hw, u8 count, 131 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 132 struct ice_sq_cd *cd); 133 enum ice_status 134 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move, 135 bool is_tc_change, bool subseq_call, bool flush_pipe, 136 u8 timeout, u32 *blocked_cgds, 137 struct ice_aqc_move_txqs_data *buf, u16 buf_size, 138 u8 *txqs_moved, struct ice_sq_cd *cd); 139 140 bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq); 141 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading); 142 void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode); 143 extern const struct ice_ctx_ele ice_tlan_ctx_info[]; 144 enum ice_status 145 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 146 const struct ice_ctx_ele *ce_info); 147 148 enum ice_status 149 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, 150 void *buf, u16 buf_size, struct ice_sq_cd *cd); 151 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd); 152 153 enum ice_status 154 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 155 struct ice_sq_cd *cd); 156 enum ice_status 157 ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi, 158 bool save_bad_pac, bool pad_short_pac, bool double_vlan, 159 struct ice_sq_cd *cd); 160 enum ice_status 161 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 162 struct ice_aqc_get_phy_caps_data *caps, 163 struct ice_sq_cd *cd); 164 void 165 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 166 u16 link_speeds_bitmap); 167 enum ice_status 168 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 169 struct ice_sq_cd *cd); 170 enum ice_status 171 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 172 struct ice_sq_cd *cd); 173 174 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw); 175 enum ice_status 176 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 177 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd); 178 bool ice_fw_supports_link_override(struct ice_hw *hw); 179 enum ice_status 180 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 181 struct ice_port_info *pi); 182 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps); 183 184 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps); 185 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options); 186 enum ice_status 187 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, 188 bool ena_auto_link_update); 189 bool 190 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps, 191 struct ice_aqc_set_phy_cfg_data *cfg); 192 void 193 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 194 struct ice_aqc_get_phy_caps_data *caps, 195 struct ice_aqc_set_phy_cfg_data *cfg); 196 enum ice_status 197 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 198 enum ice_fec_mode fec); 199 enum ice_status 200 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 201 struct ice_sq_cd *cd); 202 enum ice_status 203 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd); 204 enum ice_status 205 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 206 struct ice_link_status *link, struct ice_sq_cd *cd); 207 enum ice_status 208 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 209 struct ice_sq_cd *cd); 210 enum ice_status 211 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd); 212 213 enum ice_status 214 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 215 struct ice_sq_cd *cd); 216 enum ice_status 217 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 218 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 219 bool write, struct ice_sq_cd *cd); 220 221 enum ice_status 222 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info); 223 enum ice_status 224 __ice_write_sr_word(struct ice_hw *hw, u32 offset, const u16 *data); 225 enum ice_status 226 __ice_write_sr_buf(struct ice_hw *hw, u32 offset, u16 words, const u16 *data); 227 enum ice_status 228 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 229 u16 *q_handle, u16 *q_ids, u32 *q_teids, 230 enum ice_disq_rst_src rst_src, u16 vmvf_num, 231 struct ice_sq_cd *cd); 232 enum ice_status 233 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 234 u16 *max_lanqs); 235 enum ice_status 236 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 237 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 238 struct ice_sq_cd *cd); 239 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle); 240 void ice_replay_post(struct ice_hw *hw); 241 struct ice_q_ctx * 242 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle); 243 void 244 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 245 u64 *prev_stat, u64 *cur_stat); 246 void 247 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 248 u64 *prev_stat, u64 *cur_stat); 249 void 250 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded, 251 struct ice_eth_stats *cur_stats); 252 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw); 253 void ice_print_rollback_msg(struct ice_hw *hw); 254 enum ice_status 255 ice_aq_alternate_write(struct ice_hw *hw, u32 reg_addr0, u32 reg_val0, 256 u32 reg_addr1, u32 reg_val1); 257 enum ice_status 258 ice_aq_alternate_read(struct ice_hw *hw, u32 reg_addr0, u32 *reg_val0, 259 u32 reg_addr1, u32 *reg_val1); 260 enum ice_status 261 ice_aq_alternate_write_done(struct ice_hw *hw, u8 bios_mode, 262 bool *reset_needed); 263 enum ice_status ice_aq_alternate_clear(struct ice_hw *hw); 264 enum ice_status 265 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 266 struct ice_aqc_txsched_elem_data *buf); 267 enum ice_status 268 ice_get_cur_lldp_persist_status(struct ice_hw *hw, u32 *lldp_status); 269 enum ice_status 270 ice_get_dflt_lldp_persist_status(struct ice_hw *hw, u32 *lldp_status); 271 enum ice_status ice_get_netlist_ver_info(struct ice_hw *hw, struct ice_netlist_info *netlist); 272 enum ice_status 273 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 274 struct ice_sq_cd *cd); 275 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw); 276 enum ice_status 277 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add); 278 #endif /* _ICE_COMMON_H_ */ 279