1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2024, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _ICE_COMMON_H_ 33 #define _ICE_COMMON_H_ 34 35 #include "ice_type.h" 36 #include "ice_nvm.h" 37 #include "ice_flex_pipe.h" 38 #include "virtchnl.h" 39 #include "ice_switch.h" 40 41 #define ICE_SQ_SEND_DELAY_TIME_MS 10 42 #define ICE_SQ_SEND_MAX_EXECUTE 3 43 44 #define LOOPBACK_MODE_NO 0 45 #define LOOPBACK_MODE_HIGH 2 46 47 enum ice_fw_modes { 48 ICE_FW_MODE_NORMAL, 49 ICE_FW_MODE_DBG, 50 ICE_FW_MODE_REC, 51 ICE_FW_MODE_ROLLBACK 52 }; 53 54 void ice_idle_aq(struct ice_hw *hw, struct ice_ctl_q_info *cq); 55 bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq); 56 57 int ice_init_fltr_mgmt_struct(struct ice_hw *hw); 58 void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw); 59 void ice_set_umac_shared(struct ice_hw *hw); 60 int ice_init_hw(struct ice_hw *hw); 61 void ice_deinit_hw(struct ice_hw *hw); 62 int ice_check_reset(struct ice_hw *hw); 63 int ice_reset(struct ice_hw *hw, enum ice_reset_req req); 64 int ice_create_all_ctrlq(struct ice_hw *hw); 65 int ice_init_all_ctrlq(struct ice_hw *hw); 66 void ice_shutdown_all_ctrlq(struct ice_hw *hw, bool unloading); 67 void ice_destroy_all_ctrlq(struct ice_hw *hw); 68 int 69 ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq, 70 struct ice_rq_event_info *e, u16 *pending); 71 int 72 ice_get_link_status(struct ice_port_info *pi, bool *link_up); 73 int ice_update_link_info(struct ice_port_info *pi); 74 int 75 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 76 enum ice_aq_res_access_type access, u32 timeout); 77 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res); 78 int 79 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res); 80 int 81 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res); 82 int 83 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 84 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 85 enum ice_adminq_opc opc, struct ice_sq_cd *cd); 86 int 87 ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq, 88 struct ice_aq_desc *desc, void *buf, u16 buf_size, 89 struct ice_sq_cd *cd); 90 int 91 ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, 92 struct ice_aq_desc *desc, void *buf, u16 buf_size, 93 struct ice_sq_cd *cd); 94 void ice_clear_pxe_mode(struct ice_hw *hw); 95 int ice_get_caps(struct ice_hw *hw); 96 97 void ice_set_safe_mode_caps(struct ice_hw *hw); 98 99 int 100 ice_aq_get_internal_data(struct ice_hw *hw, u16 cluster_id, u16 table_id, 101 u32 start, void *buf, u16 buf_size, u16 *ret_buf_size, 102 u16 *ret_next_cluster, u16 *ret_next_table, 103 u32 *ret_next_index, struct ice_sq_cd *cd); 104 105 int ice_set_mac_type(struct ice_hw *hw); 106 107 /* Define a macro that will align a pointer to point to the next memory address 108 * that falls on the given power of 2 (i.e., 2, 4, 8, 16, 32, 64...). For 109 * example, given the variable pointer = 0x1006, then after the following call: 110 * 111 * pointer = ICE_ALIGN(pointer, 4) 112 * 113 * ... the value of pointer would equal 0x1008, since 0x1008 is the next 114 * address after 0x1006 which is divisible by 4. 115 */ 116 #define ICE_ALIGN(ptr, align) (((ptr) + ((align) - 1)) & ~((align) - 1)) 117 118 #define ice_arr_elem_idx(idx, val) [(idx)] = (val) 119 120 int 121 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 122 u32 rxq_index); 123 int 124 ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 125 u32 rxq_index); 126 int ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index); 127 int 128 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index); 129 int 130 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw, 131 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx, 132 u32 tx_cmpltnq_index); 133 int 134 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index); 135 int 136 ice_write_tx_drbell_q_ctx(struct ice_hw *hw, 137 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx, 138 u32 tx_drbell_q_index); 139 140 int ice_lut_size_to_type(int lut_size); 141 int 142 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params); 143 int 144 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params); 145 int 146 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 147 struct ice_aqc_get_set_rss_keys *keys); 148 int 149 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 150 struct ice_aqc_get_set_rss_keys *keys); 151 int 152 ice_aq_add_lan_txq(struct ice_hw *hw, u8 count, 153 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 154 struct ice_sq_cd *cd); 155 int 156 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move, 157 bool is_tc_change, bool subseq_call, bool flush_pipe, 158 u8 timeout, u32 *blocked_cgds, 159 struct ice_aqc_move_txqs_data *buf, u16 buf_size, 160 u8 *txqs_moved, struct ice_sq_cd *cd); 161 162 int 163 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 164 struct ice_aqc_add_rdma_qset_data *qset_list, 165 u16 buf_size, struct ice_sq_cd *cd); 166 167 bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq); 168 int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading); 169 void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode); 170 extern const struct ice_ctx_ele ice_tlan_ctx_info[]; 171 int 172 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 173 const struct ice_ctx_ele *ce_info); 174 int 175 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info); 176 177 int 178 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, 179 void *buf, u16 buf_size, struct ice_sq_cd *cd); 180 int ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd); 181 182 int 183 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 184 struct ice_sq_cd *cd); 185 int 186 ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi, 187 bool save_bad_pac, bool pad_short_pac, bool double_vlan, 188 struct ice_sq_cd *cd); 189 int 190 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 191 struct ice_aqc_get_phy_caps_data *caps, 192 struct ice_sq_cd *cd); 193 int 194 ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, 195 u8 *node_part_number, u16 *node_handle); 196 int 197 ice_find_netlist_node(struct ice_hw *hw, u8 node_type_ctx, u8 node_part_number, 198 u16 *node_handle); 199 void 200 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 201 u16 link_speeds_bitmap); 202 int 203 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 204 struct ice_sq_cd *cd); 205 int 206 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 207 struct ice_sq_cd *cd); 208 209 int ice_clear_pf_cfg(struct ice_hw *hw); 210 int 211 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 212 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd); 213 bool ice_fw_supports_link_override(struct ice_hw *hw); 214 bool ice_fw_supports_fec_dis_auto(struct ice_hw *hw); 215 int 216 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 217 struct ice_port_info *pi); 218 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps); 219 int ice_aq_get_phy_equalization(struct ice_hw *hw, u16 data_in, u16 op_code, 220 u8 serdes_num, int *output); 221 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps); 222 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options); 223 int 224 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, 225 bool ena_auto_link_update); 226 bool 227 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps, 228 struct ice_aqc_set_phy_cfg_data *cfg); 229 void 230 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 231 struct ice_aqc_get_phy_caps_data *caps, 232 struct ice_aqc_set_phy_cfg_data *cfg); 233 int 234 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 235 enum ice_fec_mode fec); 236 int 237 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 238 struct ice_sq_cd *cd); 239 int 240 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, bool auto_drop, 241 struct ice_sq_cd *cd); 242 int 243 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 244 struct ice_link_status *link, struct ice_sq_cd *cd); 245 int 246 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 247 struct ice_sq_cd *cd); 248 int 249 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd); 250 251 int 252 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 253 struct ice_sq_cd *cd); 254 int 255 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 256 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 257 bool write, struct ice_sq_cd *cd); 258 u32 ice_get_link_speed(u16 index); 259 260 int 261 ice_aq_prog_topo_dev_nvm(struct ice_hw *hw, 262 struct ice_aqc_link_topo_params *topo_params, 263 struct ice_sq_cd *cd); 264 int 265 ice_aq_read_topo_dev_nvm(struct ice_hw *hw, 266 struct ice_aqc_link_topo_params *topo_params, 267 u32 start_address, u8 *buf, u8 buf_size, 268 struct ice_sq_cd *cd); 269 270 int 271 ice_aq_get_port_options(struct ice_hw *hw, 272 struct ice_aqc_get_port_options_elem *options, 273 u8 *option_count, u8 lport, bool lport_valid, 274 u8 *active_option_idx, bool *active_option_valid, 275 u8 *pending_option_idx, bool *pending_option_valid); 276 int 277 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 278 u8 new_option); 279 int 280 __ice_write_sr_word(struct ice_hw *hw, u32 offset, const u16 *data); 281 int 282 __ice_write_sr_buf(struct ice_hw *hw, u32 offset, u16 words, const u16 *data); 283 int 284 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 285 u16 *max_rdmaqs); 286 int 287 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 288 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid); 289 int 290 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 291 u16 *q_id); 292 int 293 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 294 u16 *q_handle, u16 *q_ids, u32 *q_teids, 295 enum ice_disq_rst_src rst_src, u16 vmvf_num, 296 struct ice_sq_cd *cd); 297 int 298 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 299 u16 *max_lanqs); 300 int 301 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 302 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 303 struct ice_sq_cd *cd); 304 int 305 ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw); 306 int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle); 307 void ice_replay_post(struct ice_hw *hw); 308 struct ice_q_ctx * 309 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle); 310 int ice_sbq_rw_reg_lp(struct ice_hw *hw, struct ice_sbq_msg_input *in, 311 u16 flag, bool lock); 312 void ice_sbq_lock(struct ice_hw *hw); 313 void ice_sbq_unlock(struct ice_hw *hw); 314 int ice_sbq_rw_reg(struct ice_hw *hw, struct ice_sbq_msg_input *in, u16 flag); 315 int 316 ice_aq_get_sensor_reading(struct ice_hw *hw, u8 sensor, u8 format, 317 struct ice_aqc_get_sensor_reading_resp *data, 318 struct ice_sq_cd *cd); 319 void 320 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 321 u64 *prev_stat, u64 *cur_stat); 322 void 323 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 324 u64 *prev_stat, u64 *cur_stat); 325 void 326 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded, 327 struct ice_eth_stats *cur_stats); 328 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw); 329 void ice_print_rollback_msg(struct ice_hw *hw); 330 bool ice_is_generic_mac(struct ice_hw *hw); 331 bool ice_is_e810(struct ice_hw *hw); 332 bool ice_is_e810t(struct ice_hw *hw); 333 bool ice_is_e830(struct ice_hw *hw); 334 bool ice_is_e825c(struct ice_hw *hw); 335 bool ice_is_e823(struct ice_hw *hw); 336 int 337 ice_aq_alternate_write(struct ice_hw *hw, u32 reg_addr0, u32 reg_val0, 338 u32 reg_addr1, u32 reg_val1); 339 int 340 ice_aq_alternate_read(struct ice_hw *hw, u32 reg_addr0, u32 *reg_val0, 341 u32 reg_addr1, u32 *reg_val1); 342 int 343 ice_aq_alternate_write_done(struct ice_hw *hw, u8 bios_mode, 344 bool *reset_needed); 345 int ice_aq_alternate_clear(struct ice_hw *hw); 346 int 347 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 348 struct ice_aqc_txsched_elem_data *buf); 349 int 350 ice_get_cur_lldp_persist_status(struct ice_hw *hw, u32 *lldp_status); 351 int 352 ice_get_dflt_lldp_persist_status(struct ice_hw *hw, u32 *lldp_status); 353 int 354 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 355 struct ice_sq_cd *cd); 356 int 357 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 358 bool *value, struct ice_sq_cd *cd); 359 bool ice_is_100m_speed_supported(struct ice_hw *hw); 360 int ice_get_netlist_ver_info(struct ice_hw *hw, struct ice_netlist_info *netlist); 361 int 362 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 363 struct ice_sq_cd *cd); 364 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw); 365 int 366 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add); 367 int ice_lldp_execute_pending_mib(struct ice_hw *hw); 368 int 369 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 370 u16 bus_addr, __le16 addr, u8 params, u8 *data, 371 struct ice_sq_cd *cd); 372 int 373 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 374 u16 bus_addr, __le16 addr, u8 params, const u8 *data, 375 struct ice_sq_cd *cd); 376 int 377 ice_aq_set_health_status_config(struct ice_hw *hw, u8 event_source, 378 struct ice_sq_cd *cd); 379 bool ice_is_fw_health_report_supported(struct ice_hw *hw); 380 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw); 381 /* AQ API version for FW auto drop reports */ 382 bool ice_is_fw_auto_drop_supported(struct ice_hw *hw); 383 #endif /* _ICE_COMMON_H_ */ 384