1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2020, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*$FreeBSD$*/ 32 33 #ifndef _ICE_COMMON_H_ 34 #define _ICE_COMMON_H_ 35 36 #include "ice_type.h" 37 #include "ice_nvm.h" 38 #include "ice_flex_pipe.h" 39 #include "virtchnl.h" 40 #include "ice_switch.h" 41 42 enum ice_fw_modes { 43 ICE_FW_MODE_NORMAL, 44 ICE_FW_MODE_DBG, 45 ICE_FW_MODE_REC, 46 ICE_FW_MODE_ROLLBACK 47 }; 48 49 /* prototype for functions used for SW locks */ 50 void ice_free_list(struct LIST_HEAD_TYPE *list); 51 void ice_init_lock(struct ice_lock *lock); 52 void ice_acquire_lock(struct ice_lock *lock); 53 void ice_release_lock(struct ice_lock *lock); 54 void ice_destroy_lock(struct ice_lock *lock); 55 56 void *ice_alloc_dma_mem(struct ice_hw *hw, struct ice_dma_mem *m, u64 size); 57 void ice_free_dma_mem(struct ice_hw *hw, struct ice_dma_mem *m); 58 59 void ice_idle_aq(struct ice_hw *hw, struct ice_ctl_q_info *cq); 60 bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq); 61 62 enum ice_status ice_update_sr_checksum(struct ice_hw *hw); 63 enum ice_status ice_validate_sr_checksum(struct ice_hw *hw, u16 *checksum); 64 enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw); 65 enum ice_status ice_init_hw(struct ice_hw *hw); 66 void ice_deinit_hw(struct ice_hw *hw); 67 enum ice_status ice_check_reset(struct ice_hw *hw); 68 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req); 69 70 enum ice_status ice_create_all_ctrlq(struct ice_hw *hw); 71 enum ice_status ice_init_all_ctrlq(struct ice_hw *hw); 72 void ice_shutdown_all_ctrlq(struct ice_hw *hw); 73 void ice_destroy_all_ctrlq(struct ice_hw *hw); 74 enum ice_status 75 ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq, 76 struct ice_rq_event_info *e, u16 *pending); 77 enum ice_status 78 ice_get_link_status(struct ice_port_info *pi, bool *link_up); 79 enum ice_status ice_update_link_info(struct ice_port_info *pi); 80 enum ice_status 81 ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access); 82 void ice_release_nvm(struct ice_hw *hw); 83 enum ice_status 84 ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length, 85 void *data, bool last_command, bool read_shadow_ram, 86 struct ice_sq_cd *cd); 87 enum ice_status 88 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 89 enum ice_aq_res_access_type access, u32 timeout); 90 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res); 91 enum ice_status 92 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res); 93 enum ice_status 94 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res); 95 enum ice_status 96 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 97 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 98 enum ice_adminq_opc opc, struct ice_sq_cd *cd); 99 enum ice_status 100 ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, 101 struct ice_aq_desc *desc, void *buf, u16 buf_size, 102 struct ice_sq_cd *cd); 103 void ice_clear_pxe_mode(struct ice_hw *hw); 104 105 enum ice_status ice_get_caps(struct ice_hw *hw); 106 107 void ice_set_safe_mode_caps(struct ice_hw *hw); 108 109 enum ice_status ice_set_mac_type(struct ice_hw *hw); 110 111 /* Define a macro that will align a pointer to point to the next memory address 112 * that falls on the given power of 2 (i.e., 2, 4, 8, 16, 32, 64...). For 113 * example, given the variable pointer = 0x1006, then after the following call: 114 * 115 * pointer = ICE_ALIGN(pointer, 4) 116 * 117 * ... the value of pointer would equal 0x1008, since 0x1008 is the next 118 * address after 0x1006 which is divisible by 4. 119 */ 120 #define ICE_ALIGN(ptr, align) (((ptr) + ((align) - 1)) & ~((align) - 1)) 121 122 enum ice_status 123 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 124 u32 rxq_index); 125 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index); 126 enum ice_status 127 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index); 128 enum ice_status 129 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw, 130 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx, 131 u32 tx_cmpltnq_index); 132 enum ice_status 133 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index); 134 enum ice_status 135 ice_write_tx_drbell_q_ctx(struct ice_hw *hw, 136 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx, 137 u32 tx_drbell_q_index); 138 139 enum ice_status 140 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, u8 *lut, 141 u16 lut_size); 142 enum ice_status 143 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, u8 *lut, 144 u16 lut_size); 145 enum ice_status 146 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 147 struct ice_aqc_get_set_rss_keys *keys); 148 enum ice_status 149 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 150 struct ice_aqc_get_set_rss_keys *keys); 151 enum ice_status 152 ice_aq_add_lan_txq(struct ice_hw *hw, u8 count, 153 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 154 struct ice_sq_cd *cd); 155 enum ice_status 156 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move, 157 bool is_tc_change, bool subseq_call, bool flush_pipe, 158 u8 timeout, u32 *blocked_cgds, 159 struct ice_aqc_move_txqs_data *buf, u16 buf_size, 160 u8 *txqs_moved, struct ice_sq_cd *cd); 161 162 bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq); 163 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading); 164 void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode); 165 extern const struct ice_ctx_ele ice_tlan_ctx_info[]; 166 enum ice_status 167 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info); 168 169 enum ice_status 170 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, 171 void *buf, u16 buf_size, struct ice_sq_cd *cd); 172 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd); 173 174 enum ice_status 175 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 176 struct ice_sq_cd *cd); 177 enum ice_status 178 ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi, 179 bool save_bad_pac, bool pad_short_pac, bool double_vlan, 180 struct ice_sq_cd *cd); 181 enum ice_status 182 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 183 struct ice_aqc_get_phy_caps_data *caps, 184 struct ice_sq_cd *cd); 185 enum ice_status 186 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 187 enum ice_adminq_opc opc, struct ice_sq_cd *cd); 188 void 189 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 190 u16 link_speeds_bitmap); 191 enum ice_status 192 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 193 struct ice_sq_cd *cd); 194 enum ice_status 195 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 196 struct ice_sq_cd *cd); 197 198 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw); 199 enum ice_status 200 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 201 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd); 202 bool ice_fw_supports_link_override(struct ice_hw *hw); 203 enum ice_status 204 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 205 struct ice_port_info *pi); 206 207 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps); 208 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options); 209 enum ice_status 210 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, 211 bool ena_auto_link_update); 212 bool 213 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps, 214 struct ice_aqc_set_phy_cfg_data *cfg); 215 void 216 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 217 struct ice_aqc_get_phy_caps_data *caps, 218 struct ice_aqc_set_phy_cfg_data *cfg); 219 enum ice_status 220 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 221 enum ice_fec_mode fec); 222 enum ice_status 223 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 224 struct ice_sq_cd *cd); 225 enum ice_status 226 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd); 227 enum ice_status 228 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 229 struct ice_link_status *link, struct ice_sq_cd *cd); 230 enum ice_status 231 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 232 struct ice_sq_cd *cd); 233 enum ice_status 234 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd); 235 236 enum ice_status 237 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 238 struct ice_sq_cd *cd); 239 enum ice_status 240 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 241 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 242 bool write, struct ice_sq_cd *cd); 243 244 enum ice_status 245 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info); 246 enum ice_status 247 __ice_write_sr_word(struct ice_hw *hw, u32 offset, const u16 *data); 248 enum ice_status 249 __ice_write_sr_buf(struct ice_hw *hw, u32 offset, u16 words, const u16 *data); 250 enum ice_status 251 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 252 u16 *q_handle, u16 *q_ids, u32 *q_teids, 253 enum ice_disq_rst_src rst_src, u16 vmvf_num, 254 struct ice_sq_cd *cd); 255 enum ice_status 256 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 257 u16 *max_lanqs); 258 enum ice_status 259 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 260 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 261 struct ice_sq_cd *cd); 262 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle); 263 void ice_replay_post(struct ice_hw *hw); 264 void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw); 265 void ice_sched_replay_agg(struct ice_hw *hw); 266 enum ice_status ice_sched_replay_tc_node_bw(struct ice_port_info *pi); 267 enum ice_status ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle); 268 enum ice_status 269 ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx); 270 struct ice_q_ctx * 271 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle); 272 void 273 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 274 u64 *prev_stat, u64 *cur_stat); 275 void 276 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 277 u64 *prev_stat, u64 *cur_stat); 278 void 279 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded, 280 struct ice_eth_stats *cur_stats); 281 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw); 282 void ice_print_rollback_msg(struct ice_hw *hw); 283 bool ice_is_generic_mac(struct ice_hw *hw); 284 enum ice_status 285 ice_aq_alternate_write(struct ice_hw *hw, u32 reg_addr0, u32 reg_val0, 286 u32 reg_addr1, u32 reg_val1); 287 enum ice_status 288 ice_aq_alternate_read(struct ice_hw *hw, u32 reg_addr0, u32 *reg_val0, 289 u32 reg_addr1, u32 *reg_val1); 290 enum ice_status 291 ice_aq_alternate_write_done(struct ice_hw *hw, u8 bios_mode, 292 bool *reset_needed); 293 enum ice_status ice_aq_alternate_clear(struct ice_hw *hw); 294 enum ice_status 295 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 296 struct ice_aqc_get_elem *buf); 297 enum ice_status 298 ice_get_cur_lldp_persist_status(struct ice_hw *hw, u32 *lldp_status); 299 enum ice_status 300 ice_get_dflt_lldp_persist_status(struct ice_hw *hw, u32 *lldp_status); 301 enum ice_status ice_get_netlist_ver_info(struct ice_hw *hw); 302 #endif /* _ICE_COMMON_H_ */ 303