1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2023, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*$FreeBSD$*/ 32 33 #ifndef _ICE_COMMON_H_ 34 #define _ICE_COMMON_H_ 35 36 #include "ice_type.h" 37 #include "ice_nvm.h" 38 #include "ice_flex_pipe.h" 39 #include "virtchnl.h" 40 #include "ice_switch.h" 41 42 #define ICE_SQ_SEND_DELAY_TIME_MS 10 43 #define ICE_SQ_SEND_MAX_EXECUTE 3 44 45 enum ice_fw_modes { 46 ICE_FW_MODE_NORMAL, 47 ICE_FW_MODE_DBG, 48 ICE_FW_MODE_REC, 49 ICE_FW_MODE_ROLLBACK 50 }; 51 52 void ice_idle_aq(struct ice_hw *hw, struct ice_ctl_q_info *cq); 53 bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq); 54 55 void ice_set_umac_shared(struct ice_hw *hw); 56 enum ice_status ice_init_hw(struct ice_hw *hw); 57 void ice_deinit_hw(struct ice_hw *hw); 58 enum ice_status ice_check_reset(struct ice_hw *hw); 59 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req); 60 enum ice_status ice_create_all_ctrlq(struct ice_hw *hw); 61 enum ice_status ice_init_all_ctrlq(struct ice_hw *hw); 62 void ice_shutdown_all_ctrlq(struct ice_hw *hw, bool unloading); 63 void ice_destroy_all_ctrlq(struct ice_hw *hw); 64 enum ice_status 65 ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq, 66 struct ice_rq_event_info *e, u16 *pending); 67 enum ice_status 68 ice_get_link_status(struct ice_port_info *pi, bool *link_up); 69 enum ice_status ice_update_link_info(struct ice_port_info *pi); 70 enum ice_status 71 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 72 enum ice_aq_res_access_type access, u32 timeout); 73 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res); 74 enum ice_status 75 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res); 76 enum ice_status 77 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res); 78 enum ice_status 79 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 80 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 81 enum ice_adminq_opc opc, struct ice_sq_cd *cd); 82 enum ice_status 83 ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, 84 struct ice_aq_desc *desc, void *buf, u16 buf_size, 85 struct ice_sq_cd *cd); 86 void ice_clear_pxe_mode(struct ice_hw *hw); 87 enum ice_status ice_get_caps(struct ice_hw *hw); 88 89 void ice_set_safe_mode_caps(struct ice_hw *hw); 90 91 enum ice_status 92 ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id, 93 u32 start, void *buf, u16 buf_size, u16 *ret_buf_size, 94 u16 *ret_next_table, u32 *ret_next_index, 95 struct ice_sq_cd *cd); 96 97 enum ice_status ice_set_mac_type(struct ice_hw *hw); 98 99 /* Define a macro that will align a pointer to point to the next memory address 100 * that falls on the given power of 2 (i.e., 2, 4, 8, 16, 32, 64...). For 101 * example, given the variable pointer = 0x1006, then after the following call: 102 * 103 * pointer = ICE_ALIGN(pointer, 4) 104 * 105 * ... the value of pointer would equal 0x1008, since 0x1008 is the next 106 * address after 0x1006 which is divisible by 4. 107 */ 108 #define ICE_ALIGN(ptr, align) (((ptr) + ((align) - 1)) & ~((align) - 1)) 109 110 #define ice_arr_elem_idx(idx, val) [(idx)] = (val) 111 112 enum ice_status 113 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 114 u32 rxq_index); 115 enum ice_status 116 ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 117 u32 rxq_index); 118 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index); 119 enum ice_status 120 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index); 121 enum ice_status 122 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw, 123 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx, 124 u32 tx_cmpltnq_index); 125 enum ice_status 126 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index); 127 enum ice_status 128 ice_write_tx_drbell_q_ctx(struct ice_hw *hw, 129 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx, 130 u32 tx_drbell_q_index); 131 132 enum ice_status 133 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params); 134 enum ice_status 135 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params); 136 enum ice_status 137 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 138 struct ice_aqc_get_set_rss_keys *keys); 139 enum ice_status 140 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 141 struct ice_aqc_get_set_rss_keys *keys); 142 enum ice_status 143 ice_aq_add_lan_txq(struct ice_hw *hw, u8 count, 144 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 145 struct ice_sq_cd *cd); 146 enum ice_status 147 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move, 148 bool is_tc_change, bool subseq_call, bool flush_pipe, 149 u8 timeout, u32 *blocked_cgds, 150 struct ice_aqc_move_txqs_data *buf, u16 buf_size, 151 u8 *txqs_moved, struct ice_sq_cd *cd); 152 153 enum ice_status 154 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 155 struct ice_aqc_add_rdma_qset_data *qset_list, 156 u16 buf_size, struct ice_sq_cd *cd); 157 158 bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq); 159 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading); 160 void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode); 161 extern const struct ice_ctx_ele ice_tlan_ctx_info[]; 162 enum ice_status 163 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 164 const struct ice_ctx_ele *ce_info); 165 enum ice_status 166 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info); 167 168 enum ice_status 169 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, 170 void *buf, u16 buf_size, struct ice_sq_cd *cd); 171 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd); 172 173 enum ice_status 174 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 175 struct ice_sq_cd *cd); 176 enum ice_status 177 ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi, 178 bool save_bad_pac, bool pad_short_pac, bool double_vlan, 179 struct ice_sq_cd *cd); 180 enum ice_status 181 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 182 struct ice_aqc_get_phy_caps_data *caps, 183 struct ice_sq_cd *cd); 184 enum ice_status 185 ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, 186 u8 *node_part_number, u16 *node_handle); 187 enum ice_status 188 ice_find_netlist_node(struct ice_hw *hw, u8 node_type_ctx, u8 node_part_number, 189 u16 *node_handle); 190 void 191 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 192 u16 link_speeds_bitmap); 193 enum ice_status 194 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 195 struct ice_sq_cd *cd); 196 enum ice_status 197 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 198 struct ice_sq_cd *cd); 199 200 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw); 201 enum ice_status 202 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 203 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd); 204 bool ice_fw_supports_link_override(struct ice_hw *hw); 205 bool ice_fw_supports_fec_dis_auto(struct ice_hw *hw); 206 enum ice_status 207 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 208 struct ice_port_info *pi); 209 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps); 210 211 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps); 212 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options); 213 enum ice_status 214 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, 215 bool ena_auto_link_update); 216 bool 217 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps, 218 struct ice_aqc_set_phy_cfg_data *cfg); 219 void 220 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 221 struct ice_aqc_get_phy_caps_data *caps, 222 struct ice_aqc_set_phy_cfg_data *cfg); 223 enum ice_status 224 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 225 enum ice_fec_mode fec); 226 enum ice_status 227 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 228 struct ice_sq_cd *cd); 229 enum ice_status 230 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, bool auto_drop, 231 struct ice_sq_cd *cd); 232 enum ice_status 233 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 234 struct ice_link_status *link, struct ice_sq_cd *cd); 235 enum ice_status 236 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 237 struct ice_sq_cd *cd); 238 enum ice_status 239 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd); 240 241 enum ice_status 242 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 243 struct ice_sq_cd *cd); 244 enum ice_status 245 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 246 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 247 bool write, struct ice_sq_cd *cd); 248 u32 ice_get_link_speed(u16 index); 249 250 enum ice_status 251 ice_aq_prog_topo_dev_nvm(struct ice_hw *hw, 252 struct ice_aqc_link_topo_params *topo_params, 253 struct ice_sq_cd *cd); 254 enum ice_status 255 ice_aq_read_topo_dev_nvm(struct ice_hw *hw, 256 struct ice_aqc_link_topo_params *topo_params, 257 u32 start_address, u8 *buf, u8 buf_size, 258 struct ice_sq_cd *cd); 259 260 enum ice_status 261 ice_aq_get_port_options(struct ice_hw *hw, 262 struct ice_aqc_get_port_options_elem *options, 263 u8 *option_count, u8 lport, bool lport_valid, 264 u8 *active_option_idx, bool *active_option_valid, 265 u8 *pending_option_idx, bool *pending_option_valid); 266 enum ice_status 267 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 268 u8 new_option); 269 enum ice_status 270 __ice_write_sr_word(struct ice_hw *hw, u32 offset, const u16 *data); 271 enum ice_status 272 __ice_write_sr_buf(struct ice_hw *hw, u32 offset, u16 words, const u16 *data); 273 enum ice_status 274 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 275 u16 *max_rdmaqs); 276 enum ice_status 277 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 278 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid); 279 enum ice_status 280 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 281 u16 *q_id); 282 enum ice_status 283 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 284 u16 *q_handle, u16 *q_ids, u32 *q_teids, 285 enum ice_disq_rst_src rst_src, u16 vmvf_num, 286 struct ice_sq_cd *cd); 287 enum ice_status 288 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 289 u16 *max_lanqs); 290 enum ice_status 291 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 292 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 293 struct ice_sq_cd *cd); 294 enum ice_status 295 ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw); 296 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle); 297 void ice_replay_post(struct ice_hw *hw); 298 struct ice_q_ctx * 299 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle); 300 void 301 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 302 u64 *prev_stat, u64 *cur_stat); 303 void 304 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 305 u64 *prev_stat, u64 *cur_stat); 306 void 307 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded, 308 struct ice_eth_stats *cur_stats); 309 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw); 310 void ice_print_rollback_msg(struct ice_hw *hw); 311 bool ice_is_e810(struct ice_hw *hw); 312 bool ice_is_e810t(struct ice_hw *hw); 313 bool ice_is_e823(struct ice_hw *hw); 314 enum ice_status 315 ice_aq_alternate_write(struct ice_hw *hw, u32 reg_addr0, u32 reg_val0, 316 u32 reg_addr1, u32 reg_val1); 317 enum ice_status 318 ice_aq_alternate_read(struct ice_hw *hw, u32 reg_addr0, u32 *reg_val0, 319 u32 reg_addr1, u32 *reg_val1); 320 enum ice_status 321 ice_aq_alternate_write_done(struct ice_hw *hw, u8 bios_mode, 322 bool *reset_needed); 323 enum ice_status ice_aq_alternate_clear(struct ice_hw *hw); 324 enum ice_status 325 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 326 struct ice_aqc_txsched_elem_data *buf); 327 enum ice_status 328 ice_get_cur_lldp_persist_status(struct ice_hw *hw, u32 *lldp_status); 329 enum ice_status 330 ice_get_dflt_lldp_persist_status(struct ice_hw *hw, u32 *lldp_status); 331 enum ice_status 332 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 333 struct ice_sq_cd *cd); 334 enum ice_status 335 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 336 bool *value, struct ice_sq_cd *cd); 337 bool ice_is_100m_speed_supported(struct ice_hw *hw); 338 enum ice_status ice_get_netlist_ver_info(struct ice_hw *hw, struct ice_netlist_info *netlist); 339 enum ice_status 340 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 341 struct ice_sq_cd *cd); 342 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw); 343 enum ice_status 344 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add); 345 enum ice_status ice_lldp_execute_pending_mib(struct ice_hw *hw); 346 enum ice_status 347 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 348 u16 bus_addr, __le16 addr, u8 params, u8 *data, 349 struct ice_sq_cd *cd); 350 enum ice_status 351 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 352 u16 bus_addr, __le16 addr, u8 params, u8 *data, 353 struct ice_sq_cd *cd); 354 enum ice_status 355 ice_aq_set_health_status_config(struct ice_hw *hw, u8 event_source, 356 struct ice_sq_cd *cd); 357 bool ice_is_fw_health_report_supported(struct ice_hw *hw); 358 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw); 359 /* AQ API version for FW auto drop reports */ 360 bool ice_is_fw_auto_drop_supported(struct ice_hw *hw); 361 #endif /* _ICE_COMMON_H_ */ 362