1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2023, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _ICE_COMMON_H_ 33 #define _ICE_COMMON_H_ 34 35 #include "ice_type.h" 36 #include "ice_nvm.h" 37 #include "ice_flex_pipe.h" 38 #include "virtchnl.h" 39 #include "ice_switch.h" 40 41 #define ICE_SQ_SEND_DELAY_TIME_MS 10 42 #define ICE_SQ_SEND_MAX_EXECUTE 3 43 44 enum ice_fw_modes { 45 ICE_FW_MODE_NORMAL, 46 ICE_FW_MODE_DBG, 47 ICE_FW_MODE_REC, 48 ICE_FW_MODE_ROLLBACK 49 }; 50 51 void ice_idle_aq(struct ice_hw *hw, struct ice_ctl_q_info *cq); 52 bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq); 53 54 void ice_set_umac_shared(struct ice_hw *hw); 55 enum ice_status ice_init_hw(struct ice_hw *hw); 56 void ice_deinit_hw(struct ice_hw *hw); 57 enum ice_status ice_check_reset(struct ice_hw *hw); 58 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req); 59 enum ice_status ice_create_all_ctrlq(struct ice_hw *hw); 60 enum ice_status ice_init_all_ctrlq(struct ice_hw *hw); 61 void ice_shutdown_all_ctrlq(struct ice_hw *hw, bool unloading); 62 void ice_destroy_all_ctrlq(struct ice_hw *hw); 63 enum ice_status 64 ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq, 65 struct ice_rq_event_info *e, u16 *pending); 66 enum ice_status 67 ice_get_link_status(struct ice_port_info *pi, bool *link_up); 68 enum ice_status ice_update_link_info(struct ice_port_info *pi); 69 enum ice_status 70 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 71 enum ice_aq_res_access_type access, u32 timeout); 72 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res); 73 enum ice_status 74 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res); 75 enum ice_status 76 ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res); 77 enum ice_status 78 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 79 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 80 enum ice_adminq_opc opc, struct ice_sq_cd *cd); 81 enum ice_status 82 ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq, 83 struct ice_aq_desc *desc, void *buf, u16 buf_size, 84 struct ice_sq_cd *cd); 85 void ice_clear_pxe_mode(struct ice_hw *hw); 86 enum ice_status ice_get_caps(struct ice_hw *hw); 87 88 void ice_set_safe_mode_caps(struct ice_hw *hw); 89 90 enum ice_status 91 ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id, 92 u32 start, void *buf, u16 buf_size, u16 *ret_buf_size, 93 u16 *ret_next_table, u32 *ret_next_index, 94 struct ice_sq_cd *cd); 95 96 enum ice_status ice_set_mac_type(struct ice_hw *hw); 97 98 /* Define a macro that will align a pointer to point to the next memory address 99 * that falls on the given power of 2 (i.e., 2, 4, 8, 16, 32, 64...). For 100 * example, given the variable pointer = 0x1006, then after the following call: 101 * 102 * pointer = ICE_ALIGN(pointer, 4) 103 * 104 * ... the value of pointer would equal 0x1008, since 0x1008 is the next 105 * address after 0x1006 which is divisible by 4. 106 */ 107 #define ICE_ALIGN(ptr, align) (((ptr) + ((align) - 1)) & ~((align) - 1)) 108 109 #define ice_arr_elem_idx(idx, val) [(idx)] = (val) 110 111 enum ice_status 112 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 113 u32 rxq_index); 114 enum ice_status 115 ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 116 u32 rxq_index); 117 enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index); 118 enum ice_status 119 ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index); 120 enum ice_status 121 ice_write_tx_cmpltnq_ctx(struct ice_hw *hw, 122 struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx, 123 u32 tx_cmpltnq_index); 124 enum ice_status 125 ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index); 126 enum ice_status 127 ice_write_tx_drbell_q_ctx(struct ice_hw *hw, 128 struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx, 129 u32 tx_drbell_q_index); 130 131 int ice_lut_size_to_type(int lut_size); 132 enum ice_status 133 ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params); 134 enum ice_status 135 ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params); 136 enum ice_status 137 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 138 struct ice_aqc_get_set_rss_keys *keys); 139 enum ice_status 140 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 141 struct ice_aqc_get_set_rss_keys *keys); 142 enum ice_status 143 ice_aq_add_lan_txq(struct ice_hw *hw, u8 count, 144 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 145 struct ice_sq_cd *cd); 146 enum ice_status 147 ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move, 148 bool is_tc_change, bool subseq_call, bool flush_pipe, 149 u8 timeout, u32 *blocked_cgds, 150 struct ice_aqc_move_txqs_data *buf, u16 buf_size, 151 u8 *txqs_moved, struct ice_sq_cd *cd); 152 153 enum ice_status 154 ice_aq_add_rdma_qsets(struct ice_hw *hw, u8 num_qset_grps, 155 struct ice_aqc_add_rdma_qset_data *qset_list, 156 u16 buf_size, struct ice_sq_cd *cd); 157 158 bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq); 159 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading); 160 void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode); 161 extern const struct ice_ctx_ele ice_tlan_ctx_info[]; 162 enum ice_status 163 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 164 const struct ice_ctx_ele *ce_info); 165 enum ice_status 166 ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info); 167 168 enum ice_status 169 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, 170 void *buf, u16 buf_size, struct ice_sq_cd *cd); 171 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd); 172 173 enum ice_status 174 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 175 struct ice_sq_cd *cd); 176 enum ice_status 177 ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi, 178 bool save_bad_pac, bool pad_short_pac, bool double_vlan, 179 struct ice_sq_cd *cd); 180 enum ice_status 181 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 182 struct ice_aqc_get_phy_caps_data *caps, 183 struct ice_sq_cd *cd); 184 enum ice_status 185 ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, 186 u8 *node_part_number, u16 *node_handle); 187 enum ice_status 188 ice_find_netlist_node(struct ice_hw *hw, u8 node_type_ctx, u8 node_part_number, 189 u16 *node_handle); 190 void 191 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 192 u16 link_speeds_bitmap); 193 enum ice_status 194 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 195 struct ice_sq_cd *cd); 196 enum ice_status 197 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 198 struct ice_sq_cd *cd); 199 200 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw); 201 enum ice_status 202 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 203 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd); 204 bool ice_fw_supports_link_override(struct ice_hw *hw); 205 bool ice_fw_supports_fec_dis_auto(struct ice_hw *hw); 206 enum ice_status 207 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 208 struct ice_port_info *pi); 209 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps); 210 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps); 211 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options); 212 enum ice_status 213 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, 214 bool ena_auto_link_update); 215 bool 216 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps, 217 struct ice_aqc_set_phy_cfg_data *cfg); 218 void 219 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 220 struct ice_aqc_get_phy_caps_data *caps, 221 struct ice_aqc_set_phy_cfg_data *cfg); 222 enum ice_status 223 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 224 enum ice_fec_mode fec); 225 enum ice_status 226 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 227 struct ice_sq_cd *cd); 228 enum ice_status 229 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, bool auto_drop, 230 struct ice_sq_cd *cd); 231 enum ice_status 232 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 233 struct ice_link_status *link, struct ice_sq_cd *cd); 234 enum ice_status 235 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 236 struct ice_sq_cd *cd); 237 enum ice_status 238 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd); 239 240 enum ice_status 241 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 242 struct ice_sq_cd *cd); 243 enum ice_status 244 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 245 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 246 bool write, struct ice_sq_cd *cd); 247 u32 ice_get_link_speed(u16 index); 248 249 enum ice_status 250 ice_aq_prog_topo_dev_nvm(struct ice_hw *hw, 251 struct ice_aqc_link_topo_params *topo_params, 252 struct ice_sq_cd *cd); 253 enum ice_status 254 ice_aq_read_topo_dev_nvm(struct ice_hw *hw, 255 struct ice_aqc_link_topo_params *topo_params, 256 u32 start_address, u8 *buf, u8 buf_size, 257 struct ice_sq_cd *cd); 258 259 enum ice_status 260 ice_aq_get_port_options(struct ice_hw *hw, 261 struct ice_aqc_get_port_options_elem *options, 262 u8 *option_count, u8 lport, bool lport_valid, 263 u8 *active_option_idx, bool *active_option_valid, 264 u8 *pending_option_idx, bool *pending_option_valid); 265 enum ice_status 266 ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid, 267 u8 new_option); 268 enum ice_status 269 __ice_write_sr_word(struct ice_hw *hw, u32 offset, const u16 *data); 270 enum ice_status 271 __ice_write_sr_buf(struct ice_hw *hw, u32 offset, u16 words, const u16 *data); 272 enum ice_status 273 ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 274 u16 *max_rdmaqs); 275 enum ice_status 276 ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 277 u16 *rdma_qset, u16 num_qsets, u32 *qset_teid); 278 enum ice_status 279 ice_dis_vsi_rdma_qset(struct ice_port_info *pi, u16 count, u32 *qset_teid, 280 u16 *q_id); 281 enum ice_status 282 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 283 u16 *q_handle, u16 *q_ids, u32 *q_teids, 284 enum ice_disq_rst_src rst_src, u16 vmvf_num, 285 struct ice_sq_cd *cd); 286 enum ice_status 287 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 288 u16 *max_lanqs); 289 enum ice_status 290 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 291 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 292 struct ice_sq_cd *cd); 293 enum ice_status 294 ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw); 295 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle); 296 void ice_replay_post(struct ice_hw *hw); 297 struct ice_q_ctx * 298 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle); 299 enum ice_status 300 ice_aq_get_sensor_reading(struct ice_hw *hw, u8 sensor, u8 format, 301 struct ice_aqc_get_sensor_reading_resp *data, 302 struct ice_sq_cd *cd); 303 void 304 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 305 u64 *prev_stat, u64 *cur_stat); 306 void 307 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 308 u64 *prev_stat, u64 *cur_stat); 309 void 310 ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded, 311 struct ice_eth_stats *cur_stats); 312 enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw); 313 void ice_print_rollback_msg(struct ice_hw *hw); 314 bool ice_is_e810(struct ice_hw *hw); 315 bool ice_is_e810t(struct ice_hw *hw); 316 bool ice_is_e823(struct ice_hw *hw); 317 enum ice_status 318 ice_aq_alternate_write(struct ice_hw *hw, u32 reg_addr0, u32 reg_val0, 319 u32 reg_addr1, u32 reg_val1); 320 enum ice_status 321 ice_aq_alternate_read(struct ice_hw *hw, u32 reg_addr0, u32 *reg_val0, 322 u32 reg_addr1, u32 *reg_val1); 323 enum ice_status 324 ice_aq_alternate_write_done(struct ice_hw *hw, u8 bios_mode, 325 bool *reset_needed); 326 enum ice_status ice_aq_alternate_clear(struct ice_hw *hw); 327 enum ice_status 328 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 329 struct ice_aqc_txsched_elem_data *buf); 330 enum ice_status 331 ice_get_cur_lldp_persist_status(struct ice_hw *hw, u32 *lldp_status); 332 enum ice_status 333 ice_get_dflt_lldp_persist_status(struct ice_hw *hw, u32 *lldp_status); 334 enum ice_status 335 ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value, 336 struct ice_sq_cd *cd); 337 enum ice_status 338 ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, 339 bool *value, struct ice_sq_cd *cd); 340 bool ice_is_100m_speed_supported(struct ice_hw *hw); 341 enum ice_status ice_get_netlist_ver_info(struct ice_hw *hw, struct ice_netlist_info *netlist); 342 enum ice_status 343 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 344 struct ice_sq_cd *cd); 345 bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw); 346 enum ice_status 347 ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add); 348 enum ice_status ice_lldp_execute_pending_mib(struct ice_hw *hw); 349 enum ice_status 350 ice_aq_read_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 351 u16 bus_addr, __le16 addr, u8 params, u8 *data, 352 struct ice_sq_cd *cd); 353 enum ice_status 354 ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr, 355 u16 bus_addr, __le16 addr, u8 params, u8 *data, 356 struct ice_sq_cd *cd); 357 enum ice_status 358 ice_aq_set_health_status_config(struct ice_hw *hw, u8 event_source, 359 struct ice_sq_cd *cd); 360 bool ice_is_fw_health_report_supported(struct ice_hw *hw); 361 bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw); 362 /* AQ API version for FW auto drop reports */ 363 bool ice_is_fw_auto_drop_supported(struct ice_hw *hw); 364 #endif /* _ICE_COMMON_H_ */ 365