171d10453SEric Joyner /* SPDX-License-Identifier: BSD-3-Clause */ 2d08b8680SEric Joyner /* Copyright (c) 2021, Intel Corporation 371d10453SEric Joyner * All rights reserved. 471d10453SEric Joyner * 571d10453SEric Joyner * Redistribution and use in source and binary forms, with or without 671d10453SEric Joyner * modification, are permitted provided that the following conditions are met: 771d10453SEric Joyner * 871d10453SEric Joyner * 1. Redistributions of source code must retain the above copyright notice, 971d10453SEric Joyner * this list of conditions and the following disclaimer. 1071d10453SEric Joyner * 1171d10453SEric Joyner * 2. Redistributions in binary form must reproduce the above copyright 1271d10453SEric Joyner * notice, this list of conditions and the following disclaimer in the 1371d10453SEric Joyner * documentation and/or other materials provided with the distribution. 1471d10453SEric Joyner * 1571d10453SEric Joyner * 3. Neither the name of the Intel Corporation nor the names of its 1671d10453SEric Joyner * contributors may be used to endorse or promote products derived from 1771d10453SEric Joyner * this software without specific prior written permission. 1871d10453SEric Joyner * 1971d10453SEric Joyner * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2071d10453SEric Joyner * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2171d10453SEric Joyner * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2271d10453SEric Joyner * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 2371d10453SEric Joyner * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2471d10453SEric Joyner * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2571d10453SEric Joyner * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2671d10453SEric Joyner * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2771d10453SEric Joyner * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2871d10453SEric Joyner * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 2971d10453SEric Joyner * POSSIBILITY OF SUCH DAMAGE. 3071d10453SEric Joyner */ 3171d10453SEric Joyner /*$FreeBSD$*/ 3271d10453SEric Joyner 3371d10453SEric Joyner #include "ice_common.h" 3471d10453SEric Joyner #include "ice_sched.h" 3571d10453SEric Joyner #include "ice_adminq_cmd.h" 3671d10453SEric Joyner 3771d10453SEric Joyner #include "ice_flow.h" 3871d10453SEric Joyner #include "ice_switch.h" 3971d10453SEric Joyner 4071d10453SEric Joyner #define ICE_PF_RESET_WAIT_COUNT 300 4171d10453SEric Joyner 4271d10453SEric Joyner /** 4371d10453SEric Joyner * ice_set_mac_type - Sets MAC type 4471d10453SEric Joyner * @hw: pointer to the HW structure 4571d10453SEric Joyner * 4671d10453SEric Joyner * This function sets the MAC type of the adapter based on the 4771d10453SEric Joyner * vendor ID and device ID stored in the HW structure. 4871d10453SEric Joyner */ 4971d10453SEric Joyner enum ice_status ice_set_mac_type(struct ice_hw *hw) 5071d10453SEric Joyner { 5171d10453SEric Joyner ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 5271d10453SEric Joyner 5371d10453SEric Joyner if (hw->vendor_id != ICE_INTEL_VENDOR_ID) 5471d10453SEric Joyner return ICE_ERR_DEVICE_NOT_SUPPORTED; 5571d10453SEric Joyner 5671d10453SEric Joyner switch (hw->device_id) { 5771d10453SEric Joyner case ICE_DEV_ID_E810C_BACKPLANE: 5871d10453SEric Joyner case ICE_DEV_ID_E810C_QSFP: 5971d10453SEric Joyner case ICE_DEV_ID_E810C_SFP: 6071d10453SEric Joyner case ICE_DEV_ID_E810_XXV_BACKPLANE: 6171d10453SEric Joyner case ICE_DEV_ID_E810_XXV_QSFP: 6271d10453SEric Joyner case ICE_DEV_ID_E810_XXV_SFP: 6371d10453SEric Joyner hw->mac_type = ICE_MAC_E810; 6471d10453SEric Joyner break; 6571d10453SEric Joyner case ICE_DEV_ID_E822C_10G_BASE_T: 6671d10453SEric Joyner case ICE_DEV_ID_E822C_BACKPLANE: 6771d10453SEric Joyner case ICE_DEV_ID_E822C_QSFP: 6871d10453SEric Joyner case ICE_DEV_ID_E822C_SFP: 6971d10453SEric Joyner case ICE_DEV_ID_E822C_SGMII: 7071d10453SEric Joyner case ICE_DEV_ID_E822L_10G_BASE_T: 7171d10453SEric Joyner case ICE_DEV_ID_E822L_BACKPLANE: 7271d10453SEric Joyner case ICE_DEV_ID_E822L_SFP: 7371d10453SEric Joyner case ICE_DEV_ID_E822L_SGMII: 7471d10453SEric Joyner case ICE_DEV_ID_E823L_10G_BASE_T: 7571d10453SEric Joyner case ICE_DEV_ID_E823L_1GBE: 7671d10453SEric Joyner case ICE_DEV_ID_E823L_BACKPLANE: 7771d10453SEric Joyner case ICE_DEV_ID_E823L_QSFP: 7871d10453SEric Joyner case ICE_DEV_ID_E823L_SFP: 7971d10453SEric Joyner hw->mac_type = ICE_MAC_GENERIC; 8071d10453SEric Joyner break; 8171d10453SEric Joyner default: 8271d10453SEric Joyner hw->mac_type = ICE_MAC_UNKNOWN; 8371d10453SEric Joyner break; 8471d10453SEric Joyner } 8571d10453SEric Joyner 8671d10453SEric Joyner ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); 8771d10453SEric Joyner return ICE_SUCCESS; 8871d10453SEric Joyner } 8971d10453SEric Joyner 9071d10453SEric Joyner /** 9171d10453SEric Joyner * ice_clear_pf_cfg - Clear PF configuration 9271d10453SEric Joyner * @hw: pointer to the hardware structure 9371d10453SEric Joyner * 9471d10453SEric Joyner * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port 9571d10453SEric Joyner * configuration, flow director filters, etc.). 9671d10453SEric Joyner */ 9771d10453SEric Joyner enum ice_status ice_clear_pf_cfg(struct ice_hw *hw) 9871d10453SEric Joyner { 9971d10453SEric Joyner struct ice_aq_desc desc; 10071d10453SEric Joyner 10171d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg); 10271d10453SEric Joyner 10371d10453SEric Joyner return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 10471d10453SEric Joyner } 10571d10453SEric Joyner 10671d10453SEric Joyner /** 10771d10453SEric Joyner * ice_aq_manage_mac_read - manage MAC address read command 10871d10453SEric Joyner * @hw: pointer to the HW struct 10971d10453SEric Joyner * @buf: a virtual buffer to hold the manage MAC read response 11071d10453SEric Joyner * @buf_size: Size of the virtual buffer 11171d10453SEric Joyner * @cd: pointer to command details structure or NULL 11271d10453SEric Joyner * 11371d10453SEric Joyner * This function is used to return per PF station MAC address (0x0107). 11471d10453SEric Joyner * NOTE: Upon successful completion of this command, MAC address information 11571d10453SEric Joyner * is returned in user specified buffer. Please interpret user specified 11671d10453SEric Joyner * buffer as "manage_mac_read" response. 11771d10453SEric Joyner * Response such as various MAC addresses are stored in HW struct (port.mac) 1187d7af7f8SEric Joyner * ice_discover_dev_caps is expected to be called before this function is 1197d7af7f8SEric Joyner * called. 12071d10453SEric Joyner */ 12171d10453SEric Joyner enum ice_status 12271d10453SEric Joyner ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size, 12371d10453SEric Joyner struct ice_sq_cd *cd) 12471d10453SEric Joyner { 12571d10453SEric Joyner struct ice_aqc_manage_mac_read_resp *resp; 12671d10453SEric Joyner struct ice_aqc_manage_mac_read *cmd; 12771d10453SEric Joyner struct ice_aq_desc desc; 12871d10453SEric Joyner enum ice_status status; 12971d10453SEric Joyner u16 flags; 13071d10453SEric Joyner u8 i; 13171d10453SEric Joyner 13271d10453SEric Joyner cmd = &desc.params.mac_read; 13371d10453SEric Joyner 13471d10453SEric Joyner if (buf_size < sizeof(*resp)) 13571d10453SEric Joyner return ICE_ERR_BUF_TOO_SHORT; 13671d10453SEric Joyner 13771d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read); 13871d10453SEric Joyner 13971d10453SEric Joyner status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 14071d10453SEric Joyner if (status) 14171d10453SEric Joyner return status; 14271d10453SEric Joyner 14371d10453SEric Joyner resp = (struct ice_aqc_manage_mac_read_resp *)buf; 14471d10453SEric Joyner flags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; 14571d10453SEric Joyner 14671d10453SEric Joyner if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) { 14771d10453SEric Joyner ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n"); 14871d10453SEric Joyner return ICE_ERR_CFG; 14971d10453SEric Joyner } 15071d10453SEric Joyner 15171d10453SEric Joyner /* A single port can report up to two (LAN and WoL) addresses */ 15271d10453SEric Joyner for (i = 0; i < cmd->num_addr; i++) 15371d10453SEric Joyner if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) { 15471d10453SEric Joyner ice_memcpy(hw->port_info->mac.lan_addr, 15571d10453SEric Joyner resp[i].mac_addr, ETH_ALEN, 15671d10453SEric Joyner ICE_DMA_TO_NONDMA); 15771d10453SEric Joyner ice_memcpy(hw->port_info->mac.perm_addr, 15871d10453SEric Joyner resp[i].mac_addr, 15971d10453SEric Joyner ETH_ALEN, ICE_DMA_TO_NONDMA); 16071d10453SEric Joyner break; 16171d10453SEric Joyner } 16271d10453SEric Joyner return ICE_SUCCESS; 16371d10453SEric Joyner } 16471d10453SEric Joyner 16571d10453SEric Joyner /** 16671d10453SEric Joyner * ice_aq_get_phy_caps - returns PHY capabilities 16771d10453SEric Joyner * @pi: port information structure 16871d10453SEric Joyner * @qual_mods: report qualified modules 16971d10453SEric Joyner * @report_mode: report mode capabilities 17071d10453SEric Joyner * @pcaps: structure for PHY capabilities to be filled 17171d10453SEric Joyner * @cd: pointer to command details structure or NULL 17271d10453SEric Joyner * 17371d10453SEric Joyner * Returns the various PHY capabilities supported on the Port (0x0600) 17471d10453SEric Joyner */ 17571d10453SEric Joyner enum ice_status 17671d10453SEric Joyner ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, 17771d10453SEric Joyner struct ice_aqc_get_phy_caps_data *pcaps, 17871d10453SEric Joyner struct ice_sq_cd *cd) 17971d10453SEric Joyner { 18071d10453SEric Joyner struct ice_aqc_get_phy_caps *cmd; 18171d10453SEric Joyner u16 pcaps_size = sizeof(*pcaps); 18271d10453SEric Joyner struct ice_aq_desc desc; 18371d10453SEric Joyner enum ice_status status; 1847d7af7f8SEric Joyner struct ice_hw *hw; 18571d10453SEric Joyner 18671d10453SEric Joyner cmd = &desc.params.get_phy; 18771d10453SEric Joyner 18871d10453SEric Joyner if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi) 18971d10453SEric Joyner return ICE_ERR_PARAM; 1907d7af7f8SEric Joyner hw = pi->hw; 19171d10453SEric Joyner 192*9cf1841cSEric Joyner if (report_mode == ICE_AQC_REPORT_DFLT_CFG && 193*9cf1841cSEric Joyner !ice_fw_supports_report_dflt_cfg(hw)) 194*9cf1841cSEric Joyner return ICE_ERR_PARAM; 195*9cf1841cSEric Joyner 19671d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps); 19771d10453SEric Joyner 19871d10453SEric Joyner if (qual_mods) 19971d10453SEric Joyner cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM); 20071d10453SEric Joyner 20171d10453SEric Joyner cmd->param0 |= CPU_TO_LE16(report_mode); 2027d7af7f8SEric Joyner status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); 2037d7af7f8SEric Joyner 2047d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n", 2057d7af7f8SEric Joyner report_mode); 2067d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 2077d7af7f8SEric Joyner (unsigned long long)LE64_TO_CPU(pcaps->phy_type_low)); 2087d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 2097d7af7f8SEric Joyner (unsigned long long)LE64_TO_CPU(pcaps->phy_type_high)); 2107d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps); 2117d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 2127d7af7f8SEric Joyner pcaps->low_power_ctrl_an); 2137d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap); 2147d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", 2157d7af7f8SEric Joyner pcaps->eeer_value); 2167d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n", 2177d7af7f8SEric Joyner pcaps->link_fec_options); 2187d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n", 2197d7af7f8SEric Joyner pcaps->module_compliance_enforcement); 2207d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n", 2217d7af7f8SEric Joyner pcaps->extended_compliance_code); 2227d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n", 2237d7af7f8SEric Joyner pcaps->module_type[0]); 2247d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n", 2257d7af7f8SEric Joyner pcaps->module_type[1]); 2267d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n", 2277d7af7f8SEric Joyner pcaps->module_type[2]); 22871d10453SEric Joyner 229*9cf1841cSEric Joyner if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { 23071d10453SEric Joyner pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low); 23171d10453SEric Joyner pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high); 2327d7af7f8SEric Joyner ice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type, 2337d7af7f8SEric Joyner sizeof(pi->phy.link_info.module_type), 2347d7af7f8SEric Joyner ICE_NONDMA_TO_NONDMA); 23571d10453SEric Joyner } 23671d10453SEric Joyner 23771d10453SEric Joyner return status; 23871d10453SEric Joyner } 23971d10453SEric Joyner 24071d10453SEric Joyner /** 24171d10453SEric Joyner * ice_aq_get_link_topo_handle - get link topology node return status 24271d10453SEric Joyner * @pi: port information structure 24371d10453SEric Joyner * @node_type: requested node type 24471d10453SEric Joyner * @cd: pointer to command details structure or NULL 24571d10453SEric Joyner * 24671d10453SEric Joyner * Get link topology node return status for specified node type (0x06E0) 24771d10453SEric Joyner * 24871d10453SEric Joyner * Node type cage can be used to determine if cage is present. If AQC 24971d10453SEric Joyner * returns error (ENOENT), then no cage present. If no cage present, then 25071d10453SEric Joyner * connection type is backplane or BASE-T. 25171d10453SEric Joyner */ 25271d10453SEric Joyner static enum ice_status 25371d10453SEric Joyner ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, 25471d10453SEric Joyner struct ice_sq_cd *cd) 25571d10453SEric Joyner { 25671d10453SEric Joyner struct ice_aqc_get_link_topo *cmd; 25771d10453SEric Joyner struct ice_aq_desc desc; 25871d10453SEric Joyner 25971d10453SEric Joyner cmd = &desc.params.get_link_topo; 26071d10453SEric Joyner 26171d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 26271d10453SEric Joyner 26371d10453SEric Joyner cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << 26471d10453SEric Joyner ICE_AQC_LINK_TOPO_NODE_CTX_S); 26571d10453SEric Joyner 26671d10453SEric Joyner /* set node type */ 26771d10453SEric Joyner cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); 26871d10453SEric Joyner 26971d10453SEric Joyner return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 27071d10453SEric Joyner } 27171d10453SEric Joyner 272d08b8680SEric Joyner /** 27371d10453SEric Joyner * ice_is_media_cage_present 27471d10453SEric Joyner * @pi: port information structure 27571d10453SEric Joyner * 27671d10453SEric Joyner * Returns true if media cage is present, else false. If no cage, then 27771d10453SEric Joyner * media type is backplane or BASE-T. 27871d10453SEric Joyner */ 27971d10453SEric Joyner static bool ice_is_media_cage_present(struct ice_port_info *pi) 28071d10453SEric Joyner { 28171d10453SEric Joyner /* Node type cage can be used to determine if cage is present. If AQC 28271d10453SEric Joyner * returns error (ENOENT), then no cage present. If no cage present then 28371d10453SEric Joyner * connection type is backplane or BASE-T. 28471d10453SEric Joyner */ 28571d10453SEric Joyner return !ice_aq_get_link_topo_handle(pi, 28671d10453SEric Joyner ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, 28771d10453SEric Joyner NULL); 28871d10453SEric Joyner } 28971d10453SEric Joyner 29071d10453SEric Joyner /** 29171d10453SEric Joyner * ice_get_media_type - Gets media type 29271d10453SEric Joyner * @pi: port information structure 29371d10453SEric Joyner */ 29471d10453SEric Joyner static enum ice_media_type ice_get_media_type(struct ice_port_info *pi) 29571d10453SEric Joyner { 29671d10453SEric Joyner struct ice_link_status *hw_link_info; 29771d10453SEric Joyner 29871d10453SEric Joyner if (!pi) 29971d10453SEric Joyner return ICE_MEDIA_UNKNOWN; 30071d10453SEric Joyner 30171d10453SEric Joyner hw_link_info = &pi->phy.link_info; 30271d10453SEric Joyner if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) 30371d10453SEric Joyner /* If more than one media type is selected, report unknown */ 30471d10453SEric Joyner return ICE_MEDIA_UNKNOWN; 30571d10453SEric Joyner 30671d10453SEric Joyner if (hw_link_info->phy_type_low) { 3077d7af7f8SEric Joyner /* 1G SGMII is a special case where some DA cable PHYs 3087d7af7f8SEric Joyner * may show this as an option when it really shouldn't 3097d7af7f8SEric Joyner * be since SGMII is meant to be between a MAC and a PHY 3107d7af7f8SEric Joyner * in a backplane. Try to detect this case and handle it 3117d7af7f8SEric Joyner */ 3127d7af7f8SEric Joyner if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && 3137d7af7f8SEric Joyner (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 3147d7af7f8SEric Joyner ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE || 3157d7af7f8SEric Joyner hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == 3167d7af7f8SEric Joyner ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE)) 3177d7af7f8SEric Joyner return ICE_MEDIA_DA; 3187d7af7f8SEric Joyner 31971d10453SEric Joyner switch (hw_link_info->phy_type_low) { 32071d10453SEric Joyner case ICE_PHY_TYPE_LOW_1000BASE_SX: 32171d10453SEric Joyner case ICE_PHY_TYPE_LOW_1000BASE_LX: 32271d10453SEric Joyner case ICE_PHY_TYPE_LOW_10GBASE_SR: 32371d10453SEric Joyner case ICE_PHY_TYPE_LOW_10GBASE_LR: 32471d10453SEric Joyner case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 32571d10453SEric Joyner case ICE_PHY_TYPE_LOW_25GBASE_SR: 32671d10453SEric Joyner case ICE_PHY_TYPE_LOW_25GBASE_LR: 32771d10453SEric Joyner case ICE_PHY_TYPE_LOW_40GBASE_SR4: 32871d10453SEric Joyner case ICE_PHY_TYPE_LOW_40GBASE_LR4: 32971d10453SEric Joyner case ICE_PHY_TYPE_LOW_50GBASE_SR2: 33071d10453SEric Joyner case ICE_PHY_TYPE_LOW_50GBASE_LR2: 33171d10453SEric Joyner case ICE_PHY_TYPE_LOW_50GBASE_SR: 33271d10453SEric Joyner case ICE_PHY_TYPE_LOW_50GBASE_FR: 33371d10453SEric Joyner case ICE_PHY_TYPE_LOW_50GBASE_LR: 33471d10453SEric Joyner case ICE_PHY_TYPE_LOW_100GBASE_SR4: 33571d10453SEric Joyner case ICE_PHY_TYPE_LOW_100GBASE_LR4: 33671d10453SEric Joyner case ICE_PHY_TYPE_LOW_100GBASE_SR2: 33771d10453SEric Joyner case ICE_PHY_TYPE_LOW_100GBASE_DR: 33871d10453SEric Joyner return ICE_MEDIA_FIBER; 3397d7af7f8SEric Joyner case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 3407d7af7f8SEric Joyner case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 3417d7af7f8SEric Joyner case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 3427d7af7f8SEric Joyner case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 3437d7af7f8SEric Joyner case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 3447d7af7f8SEric Joyner case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 3457d7af7f8SEric Joyner case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 3467d7af7f8SEric Joyner case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 3477d7af7f8SEric Joyner return ICE_MEDIA_FIBER; 34871d10453SEric Joyner case ICE_PHY_TYPE_LOW_100BASE_TX: 34971d10453SEric Joyner case ICE_PHY_TYPE_LOW_1000BASE_T: 35071d10453SEric Joyner case ICE_PHY_TYPE_LOW_2500BASE_T: 35171d10453SEric Joyner case ICE_PHY_TYPE_LOW_5GBASE_T: 35271d10453SEric Joyner case ICE_PHY_TYPE_LOW_10GBASE_T: 35371d10453SEric Joyner case ICE_PHY_TYPE_LOW_25GBASE_T: 35471d10453SEric Joyner return ICE_MEDIA_BASET; 35571d10453SEric Joyner case ICE_PHY_TYPE_LOW_10G_SFI_DA: 35671d10453SEric Joyner case ICE_PHY_TYPE_LOW_25GBASE_CR: 35771d10453SEric Joyner case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 35871d10453SEric Joyner case ICE_PHY_TYPE_LOW_25GBASE_CR1: 35971d10453SEric Joyner case ICE_PHY_TYPE_LOW_40GBASE_CR4: 36071d10453SEric Joyner case ICE_PHY_TYPE_LOW_50GBASE_CR2: 36171d10453SEric Joyner case ICE_PHY_TYPE_LOW_50GBASE_CP: 36271d10453SEric Joyner case ICE_PHY_TYPE_LOW_100GBASE_CR4: 36371d10453SEric Joyner case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 36471d10453SEric Joyner case ICE_PHY_TYPE_LOW_100GBASE_CP2: 36571d10453SEric Joyner return ICE_MEDIA_DA; 36671d10453SEric Joyner case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 36771d10453SEric Joyner case ICE_PHY_TYPE_LOW_40G_XLAUI: 36871d10453SEric Joyner case ICE_PHY_TYPE_LOW_50G_LAUI2: 36971d10453SEric Joyner case ICE_PHY_TYPE_LOW_50G_AUI2: 37071d10453SEric Joyner case ICE_PHY_TYPE_LOW_50G_AUI1: 37171d10453SEric Joyner case ICE_PHY_TYPE_LOW_100G_AUI4: 37271d10453SEric Joyner case ICE_PHY_TYPE_LOW_100G_CAUI4: 37371d10453SEric Joyner if (ice_is_media_cage_present(pi)) 3747d7af7f8SEric Joyner return ICE_MEDIA_AUI; 37571d10453SEric Joyner /* fall-through */ 37671d10453SEric Joyner case ICE_PHY_TYPE_LOW_1000BASE_KX: 37771d10453SEric Joyner case ICE_PHY_TYPE_LOW_2500BASE_KX: 37871d10453SEric Joyner case ICE_PHY_TYPE_LOW_2500BASE_X: 37971d10453SEric Joyner case ICE_PHY_TYPE_LOW_5GBASE_KR: 38071d10453SEric Joyner case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 38171d10453SEric Joyner case ICE_PHY_TYPE_LOW_25GBASE_KR: 38271d10453SEric Joyner case ICE_PHY_TYPE_LOW_25GBASE_KR1: 38371d10453SEric Joyner case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 38471d10453SEric Joyner case ICE_PHY_TYPE_LOW_40GBASE_KR4: 38571d10453SEric Joyner case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 38671d10453SEric Joyner case ICE_PHY_TYPE_LOW_50GBASE_KR2: 38771d10453SEric Joyner case ICE_PHY_TYPE_LOW_100GBASE_KR4: 38871d10453SEric Joyner case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 38971d10453SEric Joyner return ICE_MEDIA_BACKPLANE; 39071d10453SEric Joyner } 39171d10453SEric Joyner } else { 39271d10453SEric Joyner switch (hw_link_info->phy_type_high) { 39371d10453SEric Joyner case ICE_PHY_TYPE_HIGH_100G_AUI2: 3947d7af7f8SEric Joyner case ICE_PHY_TYPE_HIGH_100G_CAUI2: 39571d10453SEric Joyner if (ice_is_media_cage_present(pi)) 3967d7af7f8SEric Joyner return ICE_MEDIA_AUI; 39771d10453SEric Joyner /* fall-through */ 39871d10453SEric Joyner case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 39971d10453SEric Joyner return ICE_MEDIA_BACKPLANE; 4007d7af7f8SEric Joyner case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 4017d7af7f8SEric Joyner case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 4027d7af7f8SEric Joyner return ICE_MEDIA_FIBER; 40371d10453SEric Joyner } 40471d10453SEric Joyner } 40571d10453SEric Joyner return ICE_MEDIA_UNKNOWN; 40671d10453SEric Joyner } 40771d10453SEric Joyner 40871d10453SEric Joyner /** 40971d10453SEric Joyner * ice_aq_get_link_info 41071d10453SEric Joyner * @pi: port information structure 41171d10453SEric Joyner * @ena_lse: enable/disable LinkStatusEvent reporting 41271d10453SEric Joyner * @link: pointer to link status structure - optional 41371d10453SEric Joyner * @cd: pointer to command details structure or NULL 41471d10453SEric Joyner * 41571d10453SEric Joyner * Get Link Status (0x607). Returns the link status of the adapter. 41671d10453SEric Joyner */ 41771d10453SEric Joyner enum ice_status 41871d10453SEric Joyner ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, 41971d10453SEric Joyner struct ice_link_status *link, struct ice_sq_cd *cd) 42071d10453SEric Joyner { 42171d10453SEric Joyner struct ice_aqc_get_link_status_data link_data = { 0 }; 42271d10453SEric Joyner struct ice_aqc_get_link_status *resp; 42371d10453SEric Joyner struct ice_link_status *li_old, *li; 42471d10453SEric Joyner enum ice_media_type *hw_media_type; 42571d10453SEric Joyner struct ice_fc_info *hw_fc_info; 42671d10453SEric Joyner bool tx_pause, rx_pause; 42771d10453SEric Joyner struct ice_aq_desc desc; 42871d10453SEric Joyner enum ice_status status; 42971d10453SEric Joyner struct ice_hw *hw; 43071d10453SEric Joyner u16 cmd_flags; 43171d10453SEric Joyner 43271d10453SEric Joyner if (!pi) 43371d10453SEric Joyner return ICE_ERR_PARAM; 43471d10453SEric Joyner hw = pi->hw; 43571d10453SEric Joyner 43671d10453SEric Joyner li_old = &pi->phy.link_info_old; 43771d10453SEric Joyner hw_media_type = &pi->phy.media_type; 43871d10453SEric Joyner li = &pi->phy.link_info; 43971d10453SEric Joyner hw_fc_info = &pi->fc; 44071d10453SEric Joyner 44171d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status); 44271d10453SEric Joyner cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS; 44371d10453SEric Joyner resp = &desc.params.get_link_status; 44471d10453SEric Joyner resp->cmd_flags = CPU_TO_LE16(cmd_flags); 44571d10453SEric Joyner resp->lport_num = pi->lport; 44671d10453SEric Joyner 44771d10453SEric Joyner status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd); 44871d10453SEric Joyner 44971d10453SEric Joyner if (status != ICE_SUCCESS) 45071d10453SEric Joyner return status; 45171d10453SEric Joyner 45271d10453SEric Joyner /* save off old link status information */ 45371d10453SEric Joyner *li_old = *li; 45471d10453SEric Joyner 45571d10453SEric Joyner /* update current link status information */ 45671d10453SEric Joyner li->link_speed = LE16_TO_CPU(link_data.link_speed); 45771d10453SEric Joyner li->phy_type_low = LE64_TO_CPU(link_data.phy_type_low); 45871d10453SEric Joyner li->phy_type_high = LE64_TO_CPU(link_data.phy_type_high); 45971d10453SEric Joyner *hw_media_type = ice_get_media_type(pi); 46071d10453SEric Joyner li->link_info = link_data.link_info; 461*9cf1841cSEric Joyner li->link_cfg_err = link_data.link_cfg_err; 46271d10453SEric Joyner li->an_info = link_data.an_info; 46371d10453SEric Joyner li->ext_info = link_data.ext_info; 46471d10453SEric Joyner li->max_frame_size = LE16_TO_CPU(link_data.max_frame_size); 46571d10453SEric Joyner li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; 46671d10453SEric Joyner li->topo_media_conflict = link_data.topo_media_conflict; 46771d10453SEric Joyner li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | 46871d10453SEric Joyner ICE_AQ_CFG_PACING_TYPE_M); 46971d10453SEric Joyner 47071d10453SEric Joyner /* update fc info */ 47171d10453SEric Joyner tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX); 47271d10453SEric Joyner rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX); 47371d10453SEric Joyner if (tx_pause && rx_pause) 47471d10453SEric Joyner hw_fc_info->current_mode = ICE_FC_FULL; 47571d10453SEric Joyner else if (tx_pause) 47671d10453SEric Joyner hw_fc_info->current_mode = ICE_FC_TX_PAUSE; 47771d10453SEric Joyner else if (rx_pause) 47871d10453SEric Joyner hw_fc_info->current_mode = ICE_FC_RX_PAUSE; 47971d10453SEric Joyner else 48071d10453SEric Joyner hw_fc_info->current_mode = ICE_FC_NONE; 48171d10453SEric Joyner 48271d10453SEric Joyner li->lse_ena = !!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED)); 48371d10453SEric Joyner 4847d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_LINK, "get link info\n"); 48571d10453SEric Joyner ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); 48671d10453SEric Joyner ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 48771d10453SEric Joyner (unsigned long long)li->phy_type_low); 48871d10453SEric Joyner ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 48971d10453SEric Joyner (unsigned long long)li->phy_type_high); 49071d10453SEric Joyner ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); 49171d10453SEric Joyner ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); 49271d10453SEric Joyner ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); 49371d10453SEric Joyner ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); 4947d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); 49571d10453SEric Joyner ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); 4967d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n", 4977d7af7f8SEric Joyner li->max_frame_size); 49871d10453SEric Joyner ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); 49971d10453SEric Joyner 50071d10453SEric Joyner /* save link status information */ 50171d10453SEric Joyner if (link) 50271d10453SEric Joyner *link = *li; 50371d10453SEric Joyner 50471d10453SEric Joyner /* flag cleared so calling functions don't call AQ again */ 50571d10453SEric Joyner pi->phy.get_link_info = false; 50671d10453SEric Joyner 50771d10453SEric Joyner return ICE_SUCCESS; 50871d10453SEric Joyner } 50971d10453SEric Joyner 51071d10453SEric Joyner /** 5117d7af7f8SEric Joyner * ice_fill_tx_timer_and_fc_thresh 51271d10453SEric Joyner * @hw: pointer to the HW struct 5137d7af7f8SEric Joyner * @cmd: pointer to MAC cfg structure 51471d10453SEric Joyner * 5157d7af7f8SEric Joyner * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command 5167d7af7f8SEric Joyner * descriptor 51771d10453SEric Joyner */ 5187d7af7f8SEric Joyner static void 5197d7af7f8SEric Joyner ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, 5207d7af7f8SEric Joyner struct ice_aqc_set_mac_cfg *cmd) 52171d10453SEric Joyner { 5227d7af7f8SEric Joyner u16 fc_thres_val, tx_timer_val; 5237d7af7f8SEric Joyner u32 val; 52471d10453SEric Joyner 52571d10453SEric Joyner /* We read back the transmit timer and fc threshold value of 52671d10453SEric Joyner * LFC. Thus, we will use index = 52771d10453SEric Joyner * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. 52871d10453SEric Joyner * 52971d10453SEric Joyner * Also, because we are opearating on transmit timer and fc 53071d10453SEric Joyner * threshold of LFC, we don't turn on any bit in tx_tmr_priority 53171d10453SEric Joyner */ 53271d10453SEric Joyner #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 53371d10453SEric Joyner 53471d10453SEric Joyner /* Retrieve the transmit timer */ 5357d7af7f8SEric Joyner val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC)); 5367d7af7f8SEric Joyner tx_timer_val = val & 53771d10453SEric Joyner PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M; 53871d10453SEric Joyner cmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val); 53971d10453SEric Joyner 54071d10453SEric Joyner /* Retrieve the fc threshold */ 5417d7af7f8SEric Joyner val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC)); 5427d7af7f8SEric Joyner fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M; 5437d7af7f8SEric Joyner 5447d7af7f8SEric Joyner cmd->fc_refresh_threshold = CPU_TO_LE16(fc_thres_val); 5457d7af7f8SEric Joyner } 5467d7af7f8SEric Joyner 5477d7af7f8SEric Joyner /** 5487d7af7f8SEric Joyner * ice_aq_set_mac_cfg 5497d7af7f8SEric Joyner * @hw: pointer to the HW struct 5507d7af7f8SEric Joyner * @max_frame_size: Maximum Frame Size to be supported 5517d7af7f8SEric Joyner * @cd: pointer to command details structure or NULL 5527d7af7f8SEric Joyner * 5537d7af7f8SEric Joyner * Set MAC configuration (0x0603) 5547d7af7f8SEric Joyner */ 5557d7af7f8SEric Joyner enum ice_status 5567d7af7f8SEric Joyner ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) 5577d7af7f8SEric Joyner { 5587d7af7f8SEric Joyner struct ice_aqc_set_mac_cfg *cmd; 5597d7af7f8SEric Joyner struct ice_aq_desc desc; 5607d7af7f8SEric Joyner 5617d7af7f8SEric Joyner cmd = &desc.params.set_mac_cfg; 5627d7af7f8SEric Joyner 5637d7af7f8SEric Joyner if (max_frame_size == 0) 5647d7af7f8SEric Joyner return ICE_ERR_PARAM; 5657d7af7f8SEric Joyner 5667d7af7f8SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg); 5677d7af7f8SEric Joyner 5687d7af7f8SEric Joyner cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 5697d7af7f8SEric Joyner 5707d7af7f8SEric Joyner ice_fill_tx_timer_and_fc_thresh(hw, cmd); 57171d10453SEric Joyner 57271d10453SEric Joyner return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 57371d10453SEric Joyner } 57471d10453SEric Joyner 57571d10453SEric Joyner /** 57671d10453SEric Joyner * ice_init_fltr_mgmt_struct - initializes filter management list and locks 57771d10453SEric Joyner * @hw: pointer to the HW struct 57871d10453SEric Joyner */ 57971d10453SEric Joyner static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) 58071d10453SEric Joyner { 58171d10453SEric Joyner struct ice_switch_info *sw; 5827d7af7f8SEric Joyner enum ice_status status; 58371d10453SEric Joyner 58471d10453SEric Joyner hw->switch_info = (struct ice_switch_info *) 58571d10453SEric Joyner ice_malloc(hw, sizeof(*hw->switch_info)); 58671d10453SEric Joyner 58771d10453SEric Joyner sw = hw->switch_info; 58871d10453SEric Joyner 58971d10453SEric Joyner if (!sw) 59071d10453SEric Joyner return ICE_ERR_NO_MEMORY; 59171d10453SEric Joyner 59271d10453SEric Joyner INIT_LIST_HEAD(&sw->vsi_list_map_head); 5937d7af7f8SEric Joyner sw->prof_res_bm_init = 0; 59471d10453SEric Joyner 5957d7af7f8SEric Joyner status = ice_init_def_sw_recp(hw, &hw->switch_info->recp_list); 5967d7af7f8SEric Joyner if (status) { 5977d7af7f8SEric Joyner ice_free(hw, hw->switch_info); 5987d7af7f8SEric Joyner return status; 5997d7af7f8SEric Joyner } 6007d7af7f8SEric Joyner return ICE_SUCCESS; 60171d10453SEric Joyner } 60271d10453SEric Joyner 60371d10453SEric Joyner /** 6047d7af7f8SEric Joyner * ice_cleanup_fltr_mgmt_single - clears single filter mngt struct 60571d10453SEric Joyner * @hw: pointer to the HW struct 6067d7af7f8SEric Joyner * @sw: pointer to switch info struct for which function clears filters 60771d10453SEric Joyner */ 6087d7af7f8SEric Joyner static void 6097d7af7f8SEric Joyner ice_cleanup_fltr_mgmt_single(struct ice_hw *hw, struct ice_switch_info *sw) 61071d10453SEric Joyner { 61171d10453SEric Joyner struct ice_vsi_list_map_info *v_pos_map; 61271d10453SEric Joyner struct ice_vsi_list_map_info *v_tmp_map; 61371d10453SEric Joyner struct ice_sw_recipe *recps; 61471d10453SEric Joyner u8 i; 61571d10453SEric Joyner 6167d7af7f8SEric Joyner if (!sw) 6177d7af7f8SEric Joyner return; 6187d7af7f8SEric Joyner 61971d10453SEric Joyner LIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, 62071d10453SEric Joyner ice_vsi_list_map_info, list_entry) { 62171d10453SEric Joyner LIST_DEL(&v_pos_map->list_entry); 62271d10453SEric Joyner ice_free(hw, v_pos_map); 62371d10453SEric Joyner } 6247d7af7f8SEric Joyner recps = sw->recp_list; 62571d10453SEric Joyner for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) { 62671d10453SEric Joyner struct ice_recp_grp_entry *rg_entry, *tmprg_entry; 62771d10453SEric Joyner 62871d10453SEric Joyner recps[i].root_rid = i; 62971d10453SEric Joyner LIST_FOR_EACH_ENTRY_SAFE(rg_entry, tmprg_entry, 63071d10453SEric Joyner &recps[i].rg_list, ice_recp_grp_entry, 63171d10453SEric Joyner l_entry) { 63271d10453SEric Joyner LIST_DEL(&rg_entry->l_entry); 63371d10453SEric Joyner ice_free(hw, rg_entry); 63471d10453SEric Joyner } 63571d10453SEric Joyner 63671d10453SEric Joyner if (recps[i].adv_rule) { 63771d10453SEric Joyner struct ice_adv_fltr_mgmt_list_entry *tmp_entry; 63871d10453SEric Joyner struct ice_adv_fltr_mgmt_list_entry *lst_itr; 63971d10453SEric Joyner 64071d10453SEric Joyner ice_destroy_lock(&recps[i].filt_rule_lock); 64171d10453SEric Joyner LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry, 64271d10453SEric Joyner &recps[i].filt_rules, 64371d10453SEric Joyner ice_adv_fltr_mgmt_list_entry, 64471d10453SEric Joyner list_entry) { 64571d10453SEric Joyner LIST_DEL(&lst_itr->list_entry); 64671d10453SEric Joyner ice_free(hw, lst_itr->lkups); 64771d10453SEric Joyner ice_free(hw, lst_itr); 64871d10453SEric Joyner } 64971d10453SEric Joyner } else { 65071d10453SEric Joyner struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry; 65171d10453SEric Joyner 65271d10453SEric Joyner ice_destroy_lock(&recps[i].filt_rule_lock); 65371d10453SEric Joyner LIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry, 65471d10453SEric Joyner &recps[i].filt_rules, 65571d10453SEric Joyner ice_fltr_mgmt_list_entry, 65671d10453SEric Joyner list_entry) { 65771d10453SEric Joyner LIST_DEL(&lst_itr->list_entry); 65871d10453SEric Joyner ice_free(hw, lst_itr); 65971d10453SEric Joyner } 66071d10453SEric Joyner } 66171d10453SEric Joyner if (recps[i].root_buf) 66271d10453SEric Joyner ice_free(hw, recps[i].root_buf); 66371d10453SEric Joyner } 6647d7af7f8SEric Joyner ice_rm_sw_replay_rule_info(hw, sw); 66571d10453SEric Joyner ice_free(hw, sw->recp_list); 66671d10453SEric Joyner ice_free(hw, sw); 66771d10453SEric Joyner } 66871d10453SEric Joyner 66971d10453SEric Joyner /** 6707d7af7f8SEric Joyner * ice_cleanup_all_fltr_mgmt - cleanup filter management list and locks 6717d7af7f8SEric Joyner * @hw: pointer to the HW struct 6727d7af7f8SEric Joyner */ 6737d7af7f8SEric Joyner static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) 6747d7af7f8SEric Joyner { 6757d7af7f8SEric Joyner ice_cleanup_fltr_mgmt_single(hw, hw->switch_info); 6767d7af7f8SEric Joyner } 6777d7af7f8SEric Joyner 6787d7af7f8SEric Joyner /** 67971d10453SEric Joyner * ice_get_itr_intrl_gran 68071d10453SEric Joyner * @hw: pointer to the HW struct 68171d10453SEric Joyner * 68271d10453SEric Joyner * Determines the ITR/INTRL granularities based on the maximum aggregate 68371d10453SEric Joyner * bandwidth according to the device's configuration during power-on. 68471d10453SEric Joyner */ 68571d10453SEric Joyner static void ice_get_itr_intrl_gran(struct ice_hw *hw) 68671d10453SEric Joyner { 68771d10453SEric Joyner u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) & 68871d10453SEric Joyner GL_PWR_MODE_CTL_CAR_MAX_BW_M) >> 68971d10453SEric Joyner GL_PWR_MODE_CTL_CAR_MAX_BW_S; 69071d10453SEric Joyner 69171d10453SEric Joyner switch (max_agg_bw) { 69271d10453SEric Joyner case ICE_MAX_AGG_BW_200G: 69371d10453SEric Joyner case ICE_MAX_AGG_BW_100G: 69471d10453SEric Joyner case ICE_MAX_AGG_BW_50G: 69571d10453SEric Joyner hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; 69671d10453SEric Joyner hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; 69771d10453SEric Joyner break; 69871d10453SEric Joyner case ICE_MAX_AGG_BW_25G: 69971d10453SEric Joyner hw->itr_gran = ICE_ITR_GRAN_MAX_25; 70071d10453SEric Joyner hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; 70171d10453SEric Joyner break; 70271d10453SEric Joyner } 70371d10453SEric Joyner } 70471d10453SEric Joyner 70571d10453SEric Joyner /** 70671d10453SEric Joyner * ice_print_rollback_msg - print FW rollback message 70771d10453SEric Joyner * @hw: pointer to the hardware structure 70871d10453SEric Joyner */ 70971d10453SEric Joyner void ice_print_rollback_msg(struct ice_hw *hw) 71071d10453SEric Joyner { 71171d10453SEric Joyner char nvm_str[ICE_NVM_VER_LEN] = { 0 }; 71271d10453SEric Joyner struct ice_orom_info *orom; 713d08b8680SEric Joyner struct ice_nvm_info *nvm; 71471d10453SEric Joyner 715d08b8680SEric Joyner orom = &hw->flash.orom; 716d08b8680SEric Joyner nvm = &hw->flash.nvm; 71771d10453SEric Joyner 71871d10453SEric Joyner SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d", 719d08b8680SEric Joyner nvm->major, nvm->minor, nvm->eetrack, orom->major, 72071d10453SEric Joyner orom->build, orom->patch); 72171d10453SEric Joyner ice_warn(hw, 72271d10453SEric Joyner "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode\n", 72371d10453SEric Joyner nvm_str, hw->fw_maj_ver, hw->fw_min_ver); 72471d10453SEric Joyner } 72571d10453SEric Joyner 72671d10453SEric Joyner /** 72771d10453SEric Joyner * ice_init_hw - main hardware initialization routine 72871d10453SEric Joyner * @hw: pointer to the hardware structure 72971d10453SEric Joyner */ 73071d10453SEric Joyner enum ice_status ice_init_hw(struct ice_hw *hw) 73171d10453SEric Joyner { 73271d10453SEric Joyner struct ice_aqc_get_phy_caps_data *pcaps; 73371d10453SEric Joyner enum ice_status status; 73471d10453SEric Joyner u16 mac_buf_len; 73571d10453SEric Joyner void *mac_buf; 73671d10453SEric Joyner 73771d10453SEric Joyner ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 73871d10453SEric Joyner 73971d10453SEric Joyner /* Set MAC type based on DeviceID */ 74071d10453SEric Joyner status = ice_set_mac_type(hw); 74171d10453SEric Joyner if (status) 74271d10453SEric Joyner return status; 74371d10453SEric Joyner 74471d10453SEric Joyner hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & 74571d10453SEric Joyner PF_FUNC_RID_FUNCTION_NUMBER_M) >> 74671d10453SEric Joyner PF_FUNC_RID_FUNCTION_NUMBER_S; 74771d10453SEric Joyner 74871d10453SEric Joyner status = ice_reset(hw, ICE_RESET_PFR); 74971d10453SEric Joyner if (status) 75071d10453SEric Joyner return status; 75171d10453SEric Joyner ice_get_itr_intrl_gran(hw); 75271d10453SEric Joyner 75371d10453SEric Joyner status = ice_create_all_ctrlq(hw); 75471d10453SEric Joyner if (status) 75571d10453SEric Joyner goto err_unroll_cqinit; 75671d10453SEric Joyner 75771d10453SEric Joyner status = ice_init_nvm(hw); 75871d10453SEric Joyner if (status) 75971d10453SEric Joyner goto err_unroll_cqinit; 76071d10453SEric Joyner 76171d10453SEric Joyner if (ice_get_fw_mode(hw) == ICE_FW_MODE_ROLLBACK) 76271d10453SEric Joyner ice_print_rollback_msg(hw); 76371d10453SEric Joyner 76471d10453SEric Joyner status = ice_clear_pf_cfg(hw); 76571d10453SEric Joyner if (status) 76671d10453SEric Joyner goto err_unroll_cqinit; 76771d10453SEric Joyner 76871d10453SEric Joyner ice_clear_pxe_mode(hw); 76971d10453SEric Joyner 77071d10453SEric Joyner status = ice_get_caps(hw); 77171d10453SEric Joyner if (status) 77271d10453SEric Joyner goto err_unroll_cqinit; 77371d10453SEric Joyner 77471d10453SEric Joyner hw->port_info = (struct ice_port_info *) 77571d10453SEric Joyner ice_malloc(hw, sizeof(*hw->port_info)); 77671d10453SEric Joyner if (!hw->port_info) { 77771d10453SEric Joyner status = ICE_ERR_NO_MEMORY; 77871d10453SEric Joyner goto err_unroll_cqinit; 77971d10453SEric Joyner } 78071d10453SEric Joyner 78171d10453SEric Joyner /* set the back pointer to HW */ 78271d10453SEric Joyner hw->port_info->hw = hw; 78371d10453SEric Joyner 78471d10453SEric Joyner /* Initialize port_info struct with switch configuration data */ 78571d10453SEric Joyner status = ice_get_initial_sw_cfg(hw); 78671d10453SEric Joyner if (status) 78771d10453SEric Joyner goto err_unroll_alloc; 78871d10453SEric Joyner 78971d10453SEric Joyner hw->evb_veb = true; 79071d10453SEric Joyner /* Query the allocated resources for Tx scheduler */ 79171d10453SEric Joyner status = ice_sched_query_res_alloc(hw); 79271d10453SEric Joyner if (status) { 7937d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_SCHED, "Failed to get scheduler allocated resources\n"); 79471d10453SEric Joyner goto err_unroll_alloc; 79571d10453SEric Joyner } 79671d10453SEric Joyner ice_sched_get_psm_clk_freq(hw); 79771d10453SEric Joyner 79871d10453SEric Joyner /* Initialize port_info struct with scheduler data */ 79971d10453SEric Joyner status = ice_sched_init_port(hw->port_info); 80071d10453SEric Joyner if (status) 80171d10453SEric Joyner goto err_unroll_sched; 80271d10453SEric Joyner pcaps = (struct ice_aqc_get_phy_caps_data *) 80371d10453SEric Joyner ice_malloc(hw, sizeof(*pcaps)); 80471d10453SEric Joyner if (!pcaps) { 80571d10453SEric Joyner status = ICE_ERR_NO_MEMORY; 80671d10453SEric Joyner goto err_unroll_sched; 80771d10453SEric Joyner } 80871d10453SEric Joyner 80971d10453SEric Joyner /* Initialize port_info struct with PHY capabilities */ 81071d10453SEric Joyner status = ice_aq_get_phy_caps(hw->port_info, false, 811*9cf1841cSEric Joyner ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps, NULL); 81271d10453SEric Joyner ice_free(hw, pcaps); 81371d10453SEric Joyner if (status) 814*9cf1841cSEric Joyner ice_warn(hw, "Get PHY capabilities failed status = %d, continuing anyway\n", 815*9cf1841cSEric Joyner status); 81671d10453SEric Joyner 81771d10453SEric Joyner /* Initialize port_info struct with link information */ 81871d10453SEric Joyner status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); 81971d10453SEric Joyner if (status) 82071d10453SEric Joyner goto err_unroll_sched; 82171d10453SEric Joyner /* need a valid SW entry point to build a Tx tree */ 82271d10453SEric Joyner if (!hw->sw_entry_point_layer) { 82371d10453SEric Joyner ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); 82471d10453SEric Joyner status = ICE_ERR_CFG; 82571d10453SEric Joyner goto err_unroll_sched; 82671d10453SEric Joyner } 82771d10453SEric Joyner INIT_LIST_HEAD(&hw->agg_list); 82871d10453SEric Joyner /* Initialize max burst size */ 82971d10453SEric Joyner if (!hw->max_burst_size) 83071d10453SEric Joyner ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE); 83171d10453SEric Joyner status = ice_init_fltr_mgmt_struct(hw); 83271d10453SEric Joyner if (status) 83371d10453SEric Joyner goto err_unroll_sched; 83471d10453SEric Joyner 83571d10453SEric Joyner /* Get MAC information */ 83671d10453SEric Joyner /* A single port can report up to two (LAN and WoL) addresses */ 83771d10453SEric Joyner mac_buf = ice_calloc(hw, 2, 83871d10453SEric Joyner sizeof(struct ice_aqc_manage_mac_read_resp)); 83971d10453SEric Joyner mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp); 84071d10453SEric Joyner 84171d10453SEric Joyner if (!mac_buf) { 84271d10453SEric Joyner status = ICE_ERR_NO_MEMORY; 84371d10453SEric Joyner goto err_unroll_fltr_mgmt_struct; 84471d10453SEric Joyner } 84571d10453SEric Joyner 84671d10453SEric Joyner status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); 84771d10453SEric Joyner ice_free(hw, mac_buf); 84871d10453SEric Joyner 84971d10453SEric Joyner if (status) 85071d10453SEric Joyner goto err_unroll_fltr_mgmt_struct; 8517d7af7f8SEric Joyner /* enable jumbo frame support at MAC level */ 8527d7af7f8SEric Joyner status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); 8537d7af7f8SEric Joyner if (status) 8547d7af7f8SEric Joyner goto err_unroll_fltr_mgmt_struct; 85571d10453SEric Joyner status = ice_init_hw_tbls(hw); 85671d10453SEric Joyner if (status) 85771d10453SEric Joyner goto err_unroll_fltr_mgmt_struct; 85871d10453SEric Joyner ice_init_lock(&hw->tnl_lock); 859d08b8680SEric Joyner 86071d10453SEric Joyner return ICE_SUCCESS; 86171d10453SEric Joyner 86271d10453SEric Joyner err_unroll_fltr_mgmt_struct: 86371d10453SEric Joyner ice_cleanup_fltr_mgmt_struct(hw); 86471d10453SEric Joyner err_unroll_sched: 86571d10453SEric Joyner ice_sched_cleanup_all(hw); 86671d10453SEric Joyner err_unroll_alloc: 86771d10453SEric Joyner ice_free(hw, hw->port_info); 86871d10453SEric Joyner hw->port_info = NULL; 86971d10453SEric Joyner err_unroll_cqinit: 87071d10453SEric Joyner ice_destroy_all_ctrlq(hw); 87171d10453SEric Joyner return status; 87271d10453SEric Joyner } 87371d10453SEric Joyner 87471d10453SEric Joyner /** 87571d10453SEric Joyner * ice_deinit_hw - unroll initialization operations done by ice_init_hw 87671d10453SEric Joyner * @hw: pointer to the hardware structure 87771d10453SEric Joyner * 87871d10453SEric Joyner * This should be called only during nominal operation, not as a result of 87971d10453SEric Joyner * ice_init_hw() failing since ice_init_hw() will take care of unrolling 88071d10453SEric Joyner * applicable initializations if it fails for any reason. 88171d10453SEric Joyner */ 88271d10453SEric Joyner void ice_deinit_hw(struct ice_hw *hw) 88371d10453SEric Joyner { 88471d10453SEric Joyner ice_cleanup_fltr_mgmt_struct(hw); 88571d10453SEric Joyner 88671d10453SEric Joyner ice_sched_cleanup_all(hw); 88771d10453SEric Joyner ice_sched_clear_agg(hw); 88871d10453SEric Joyner ice_free_seg(hw); 88971d10453SEric Joyner ice_free_hw_tbls(hw); 89071d10453SEric Joyner ice_destroy_lock(&hw->tnl_lock); 89171d10453SEric Joyner 89271d10453SEric Joyner if (hw->port_info) { 89371d10453SEric Joyner ice_free(hw, hw->port_info); 89471d10453SEric Joyner hw->port_info = NULL; 89571d10453SEric Joyner } 89671d10453SEric Joyner 89771d10453SEric Joyner ice_destroy_all_ctrlq(hw); 89871d10453SEric Joyner 89971d10453SEric Joyner /* Clear VSI contexts if not already cleared */ 90071d10453SEric Joyner ice_clear_all_vsi_ctx(hw); 90171d10453SEric Joyner } 90271d10453SEric Joyner 90371d10453SEric Joyner /** 90471d10453SEric Joyner * ice_check_reset - Check to see if a global reset is complete 90571d10453SEric Joyner * @hw: pointer to the hardware structure 90671d10453SEric Joyner */ 90771d10453SEric Joyner enum ice_status ice_check_reset(struct ice_hw *hw) 90871d10453SEric Joyner { 9097d7af7f8SEric Joyner u32 cnt, reg = 0, grst_timeout, uld_mask; 91071d10453SEric Joyner 91171d10453SEric Joyner /* Poll for Device Active state in case a recent CORER, GLOBR, 91271d10453SEric Joyner * or EMPR has occurred. The grst delay value is in 100ms units. 91371d10453SEric Joyner * Add 1sec for outstanding AQ commands that can take a long time. 91471d10453SEric Joyner */ 9157d7af7f8SEric Joyner grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >> 91671d10453SEric Joyner GLGEN_RSTCTL_GRSTDEL_S) + 10; 91771d10453SEric Joyner 9187d7af7f8SEric Joyner for (cnt = 0; cnt < grst_timeout; cnt++) { 91971d10453SEric Joyner ice_msec_delay(100, true); 92071d10453SEric Joyner reg = rd32(hw, GLGEN_RSTAT); 92171d10453SEric Joyner if (!(reg & GLGEN_RSTAT_DEVSTATE_M)) 92271d10453SEric Joyner break; 92371d10453SEric Joyner } 92471d10453SEric Joyner 9257d7af7f8SEric Joyner if (cnt == grst_timeout) { 9267d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "Global reset polling failed to complete.\n"); 92771d10453SEric Joyner return ICE_ERR_RESET_FAILED; 92871d10453SEric Joyner } 92971d10453SEric Joyner 93071d10453SEric Joyner #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\ 93171d10453SEric Joyner GLNVM_ULD_PCIER_DONE_1_M |\ 93271d10453SEric Joyner GLNVM_ULD_CORER_DONE_M |\ 93371d10453SEric Joyner GLNVM_ULD_GLOBR_DONE_M |\ 93471d10453SEric Joyner GLNVM_ULD_POR_DONE_M |\ 93571d10453SEric Joyner GLNVM_ULD_POR_DONE_1_M |\ 93671d10453SEric Joyner GLNVM_ULD_PCIER_DONE_2_M) 93771d10453SEric Joyner 93871d10453SEric Joyner uld_mask = ICE_RESET_DONE_MASK; 93971d10453SEric Joyner 94071d10453SEric Joyner /* Device is Active; check Global Reset processes are done */ 94171d10453SEric Joyner for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) { 94271d10453SEric Joyner reg = rd32(hw, GLNVM_ULD) & uld_mask; 94371d10453SEric Joyner if (reg == uld_mask) { 9447d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "Global reset processes done. %d\n", cnt); 94571d10453SEric Joyner break; 94671d10453SEric Joyner } 94771d10453SEric Joyner ice_msec_delay(10, true); 94871d10453SEric Joyner } 94971d10453SEric Joyner 95071d10453SEric Joyner if (cnt == ICE_PF_RESET_WAIT_COUNT) { 9517d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n", 95271d10453SEric Joyner reg); 95371d10453SEric Joyner return ICE_ERR_RESET_FAILED; 95471d10453SEric Joyner } 95571d10453SEric Joyner 95671d10453SEric Joyner return ICE_SUCCESS; 95771d10453SEric Joyner } 95871d10453SEric Joyner 95971d10453SEric Joyner /** 96071d10453SEric Joyner * ice_pf_reset - Reset the PF 96171d10453SEric Joyner * @hw: pointer to the hardware structure 96271d10453SEric Joyner * 96371d10453SEric Joyner * If a global reset has been triggered, this function checks 96471d10453SEric Joyner * for its completion and then issues the PF reset 96571d10453SEric Joyner */ 96671d10453SEric Joyner static enum ice_status ice_pf_reset(struct ice_hw *hw) 96771d10453SEric Joyner { 96871d10453SEric Joyner u32 cnt, reg; 96971d10453SEric Joyner 97071d10453SEric Joyner /* If at function entry a global reset was already in progress, i.e. 97171d10453SEric Joyner * state is not 'device active' or any of the reset done bits are not 97271d10453SEric Joyner * set in GLNVM_ULD, there is no need for a PF Reset; poll until the 97371d10453SEric Joyner * global reset is done. 97471d10453SEric Joyner */ 97571d10453SEric Joyner if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) || 97671d10453SEric Joyner (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) { 97771d10453SEric Joyner /* poll on global reset currently in progress until done */ 97871d10453SEric Joyner if (ice_check_reset(hw)) 97971d10453SEric Joyner return ICE_ERR_RESET_FAILED; 98071d10453SEric Joyner 98171d10453SEric Joyner return ICE_SUCCESS; 98271d10453SEric Joyner } 98371d10453SEric Joyner 98471d10453SEric Joyner /* Reset the PF */ 98571d10453SEric Joyner reg = rd32(hw, PFGEN_CTRL); 98671d10453SEric Joyner 98771d10453SEric Joyner wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M)); 98871d10453SEric Joyner 9897d7af7f8SEric Joyner /* Wait for the PFR to complete. The wait time is the global config lock 9907d7af7f8SEric Joyner * timeout plus the PFR timeout which will account for a possible reset 9917d7af7f8SEric Joyner * that is occurring during a download package operation. 9927d7af7f8SEric Joyner */ 9937d7af7f8SEric Joyner for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT + 9947d7af7f8SEric Joyner ICE_PF_RESET_WAIT_COUNT; cnt++) { 99571d10453SEric Joyner reg = rd32(hw, PFGEN_CTRL); 99671d10453SEric Joyner if (!(reg & PFGEN_CTRL_PFSWR_M)) 99771d10453SEric Joyner break; 99871d10453SEric Joyner 99971d10453SEric Joyner ice_msec_delay(1, true); 100071d10453SEric Joyner } 100171d10453SEric Joyner 100271d10453SEric Joyner if (cnt == ICE_PF_RESET_WAIT_COUNT) { 10037d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "PF reset polling failed to complete.\n"); 100471d10453SEric Joyner return ICE_ERR_RESET_FAILED; 100571d10453SEric Joyner } 100671d10453SEric Joyner 100771d10453SEric Joyner return ICE_SUCCESS; 100871d10453SEric Joyner } 100971d10453SEric Joyner 101071d10453SEric Joyner /** 101171d10453SEric Joyner * ice_reset - Perform different types of reset 101271d10453SEric Joyner * @hw: pointer to the hardware structure 101371d10453SEric Joyner * @req: reset request 101471d10453SEric Joyner * 101571d10453SEric Joyner * This function triggers a reset as specified by the req parameter. 101671d10453SEric Joyner * 101771d10453SEric Joyner * Note: 101871d10453SEric Joyner * If anything other than a PF reset is triggered, PXE mode is restored. 101971d10453SEric Joyner * This has to be cleared using ice_clear_pxe_mode again, once the AQ 102071d10453SEric Joyner * interface has been restored in the rebuild flow. 102171d10453SEric Joyner */ 102271d10453SEric Joyner enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req) 102371d10453SEric Joyner { 102471d10453SEric Joyner u32 val = 0; 102571d10453SEric Joyner 102671d10453SEric Joyner switch (req) { 102771d10453SEric Joyner case ICE_RESET_PFR: 102871d10453SEric Joyner return ice_pf_reset(hw); 102971d10453SEric Joyner case ICE_RESET_CORER: 103071d10453SEric Joyner ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n"); 103171d10453SEric Joyner val = GLGEN_RTRIG_CORER_M; 103271d10453SEric Joyner break; 103371d10453SEric Joyner case ICE_RESET_GLOBR: 103471d10453SEric Joyner ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n"); 103571d10453SEric Joyner val = GLGEN_RTRIG_GLOBR_M; 103671d10453SEric Joyner break; 103771d10453SEric Joyner default: 103871d10453SEric Joyner return ICE_ERR_PARAM; 103971d10453SEric Joyner } 104071d10453SEric Joyner 104171d10453SEric Joyner val |= rd32(hw, GLGEN_RTRIG); 104271d10453SEric Joyner wr32(hw, GLGEN_RTRIG, val); 104371d10453SEric Joyner ice_flush(hw); 104471d10453SEric Joyner 104571d10453SEric Joyner /* wait for the FW to be ready */ 104671d10453SEric Joyner return ice_check_reset(hw); 104771d10453SEric Joyner } 104871d10453SEric Joyner 104971d10453SEric Joyner /** 105071d10453SEric Joyner * ice_copy_rxq_ctx_to_hw 105171d10453SEric Joyner * @hw: pointer to the hardware structure 105271d10453SEric Joyner * @ice_rxq_ctx: pointer to the rxq context 105371d10453SEric Joyner * @rxq_index: the index of the Rx queue 105471d10453SEric Joyner * 105571d10453SEric Joyner * Copies rxq context from dense structure to HW register space 105671d10453SEric Joyner */ 105771d10453SEric Joyner static enum ice_status 105871d10453SEric Joyner ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) 105971d10453SEric Joyner { 106071d10453SEric Joyner u8 i; 106171d10453SEric Joyner 106271d10453SEric Joyner if (!ice_rxq_ctx) 106371d10453SEric Joyner return ICE_ERR_BAD_PTR; 106471d10453SEric Joyner 106571d10453SEric Joyner if (rxq_index > QRX_CTRL_MAX_INDEX) 106671d10453SEric Joyner return ICE_ERR_PARAM; 106771d10453SEric Joyner 106871d10453SEric Joyner /* Copy each dword separately to HW */ 106971d10453SEric Joyner for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { 107071d10453SEric Joyner wr32(hw, QRX_CONTEXT(i, rxq_index), 107171d10453SEric Joyner *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 107271d10453SEric Joyner 107371d10453SEric Joyner ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, 107471d10453SEric Joyner *((u32 *)(ice_rxq_ctx + (i * sizeof(u32))))); 107571d10453SEric Joyner } 107671d10453SEric Joyner 107771d10453SEric Joyner return ICE_SUCCESS; 107871d10453SEric Joyner } 107971d10453SEric Joyner 108071d10453SEric Joyner /* LAN Rx Queue Context */ 108171d10453SEric Joyner static const struct ice_ctx_ele ice_rlan_ctx_info[] = { 108271d10453SEric Joyner /* Field Width LSB */ 108371d10453SEric Joyner ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0), 108471d10453SEric Joyner ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13), 108571d10453SEric Joyner ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32), 108671d10453SEric Joyner ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89), 108771d10453SEric Joyner ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102), 108871d10453SEric Joyner ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109), 108971d10453SEric Joyner ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114), 109071d10453SEric Joyner ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116), 109171d10453SEric Joyner ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117), 109271d10453SEric Joyner ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119), 109371d10453SEric Joyner ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120), 109471d10453SEric Joyner ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124), 109571d10453SEric Joyner ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127), 109671d10453SEric Joyner ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174), 109771d10453SEric Joyner ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193), 109871d10453SEric Joyner ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194), 109971d10453SEric Joyner ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195), 110071d10453SEric Joyner ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196), 110171d10453SEric Joyner ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198), 110271d10453SEric Joyner ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201), 110371d10453SEric Joyner { 0 } 110471d10453SEric Joyner }; 110571d10453SEric Joyner 110671d10453SEric Joyner /** 110771d10453SEric Joyner * ice_write_rxq_ctx 110871d10453SEric Joyner * @hw: pointer to the hardware structure 110971d10453SEric Joyner * @rlan_ctx: pointer to the rxq context 111071d10453SEric Joyner * @rxq_index: the index of the Rx queue 111171d10453SEric Joyner * 111271d10453SEric Joyner * Converts rxq context from sparse to dense structure and then writes 111371d10453SEric Joyner * it to HW register space and enables the hardware to prefetch descriptors 111471d10453SEric Joyner * instead of only fetching them on demand 111571d10453SEric Joyner */ 111671d10453SEric Joyner enum ice_status 111771d10453SEric Joyner ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, 111871d10453SEric Joyner u32 rxq_index) 111971d10453SEric Joyner { 112071d10453SEric Joyner u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; 112171d10453SEric Joyner 112271d10453SEric Joyner if (!rlan_ctx) 112371d10453SEric Joyner return ICE_ERR_BAD_PTR; 112471d10453SEric Joyner 112571d10453SEric Joyner rlan_ctx->prefena = 1; 112671d10453SEric Joyner 11277d7af7f8SEric Joyner ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info); 112871d10453SEric Joyner return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); 112971d10453SEric Joyner } 113071d10453SEric Joyner 113171d10453SEric Joyner /** 113271d10453SEric Joyner * ice_clear_rxq_ctx 113371d10453SEric Joyner * @hw: pointer to the hardware structure 113471d10453SEric Joyner * @rxq_index: the index of the Rx queue to clear 113571d10453SEric Joyner * 113671d10453SEric Joyner * Clears rxq context in HW register space 113771d10453SEric Joyner */ 113871d10453SEric Joyner enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index) 113971d10453SEric Joyner { 114071d10453SEric Joyner u8 i; 114171d10453SEric Joyner 114271d10453SEric Joyner if (rxq_index > QRX_CTRL_MAX_INDEX) 114371d10453SEric Joyner return ICE_ERR_PARAM; 114471d10453SEric Joyner 114571d10453SEric Joyner /* Clear each dword register separately */ 114671d10453SEric Joyner for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) 114771d10453SEric Joyner wr32(hw, QRX_CONTEXT(i, rxq_index), 0); 114871d10453SEric Joyner 114971d10453SEric Joyner return ICE_SUCCESS; 115071d10453SEric Joyner } 115171d10453SEric Joyner 115271d10453SEric Joyner /* LAN Tx Queue Context */ 115371d10453SEric Joyner const struct ice_ctx_ele ice_tlan_ctx_info[] = { 115471d10453SEric Joyner /* Field Width LSB */ 115571d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0), 115671d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57), 115771d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60), 115871d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65), 115971d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68), 116071d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78), 116171d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80), 116271d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90), 116371d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91), 116471d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92), 116571d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93), 116671d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101), 116771d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102), 116871d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103), 116971d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104), 117071d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105), 117171d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114), 117271d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128), 117371d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129), 117471d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135), 117571d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148), 117671d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152), 117771d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153), 117871d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164), 117971d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165), 118071d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166), 118171d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168), 118271d10453SEric Joyner ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171), 118371d10453SEric Joyner { 0 } 118471d10453SEric Joyner }; 118571d10453SEric Joyner 118671d10453SEric Joyner /** 118771d10453SEric Joyner * ice_copy_tx_cmpltnq_ctx_to_hw 118871d10453SEric Joyner * @hw: pointer to the hardware structure 118971d10453SEric Joyner * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context 119071d10453SEric Joyner * @tx_cmpltnq_index: the index of the completion queue 119171d10453SEric Joyner * 119271d10453SEric Joyner * Copies Tx completion queue context from dense structure to HW register space 119371d10453SEric Joyner */ 119471d10453SEric Joyner static enum ice_status 119571d10453SEric Joyner ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx, 119671d10453SEric Joyner u32 tx_cmpltnq_index) 119771d10453SEric Joyner { 119871d10453SEric Joyner u8 i; 119971d10453SEric Joyner 120071d10453SEric Joyner if (!ice_tx_cmpltnq_ctx) 120171d10453SEric Joyner return ICE_ERR_BAD_PTR; 120271d10453SEric Joyner 120371d10453SEric Joyner if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX) 120471d10453SEric Joyner return ICE_ERR_PARAM; 120571d10453SEric Joyner 120671d10453SEric Joyner /* Copy each dword separately to HW */ 120771d10453SEric Joyner for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) { 120871d10453SEric Joyner wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 120971d10453SEric Joyner *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32))))); 121071d10453SEric Joyner 121171d10453SEric Joyner ice_debug(hw, ICE_DBG_QCTX, "cmpltnqdata[%d]: %08X\n", i, 121271d10453SEric Joyner *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32))))); 121371d10453SEric Joyner } 121471d10453SEric Joyner 121571d10453SEric Joyner return ICE_SUCCESS; 121671d10453SEric Joyner } 121771d10453SEric Joyner 121871d10453SEric Joyner /* LAN Tx Completion Queue Context */ 121971d10453SEric Joyner static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = { 122071d10453SEric Joyner /* Field Width LSB */ 122171d10453SEric Joyner ICE_CTX_STORE(ice_tx_cmpltnq_ctx, base, 57, 0), 122271d10453SEric Joyner ICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len, 18, 64), 122371d10453SEric Joyner ICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation, 1, 96), 122471d10453SEric Joyner ICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr, 22, 97), 122571d10453SEric Joyner ICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num, 3, 128), 122671d10453SEric Joyner ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num, 10, 131), 122771d10453SEric Joyner ICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type, 2, 141), 122871d10453SEric Joyner ICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr, 1, 160), 122971d10453SEric Joyner ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid, 8, 161), 123071d10453SEric Joyner ICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache, 512, 192), 123171d10453SEric Joyner { 0 } 123271d10453SEric Joyner }; 123371d10453SEric Joyner 123471d10453SEric Joyner /** 123571d10453SEric Joyner * ice_write_tx_cmpltnq_ctx 123671d10453SEric Joyner * @hw: pointer to the hardware structure 123771d10453SEric Joyner * @tx_cmpltnq_ctx: pointer to the completion queue context 123871d10453SEric Joyner * @tx_cmpltnq_index: the index of the completion queue 123971d10453SEric Joyner * 124071d10453SEric Joyner * Converts completion queue context from sparse to dense structure and then 124171d10453SEric Joyner * writes it to HW register space 124271d10453SEric Joyner */ 124371d10453SEric Joyner enum ice_status 124471d10453SEric Joyner ice_write_tx_cmpltnq_ctx(struct ice_hw *hw, 124571d10453SEric Joyner struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx, 124671d10453SEric Joyner u32 tx_cmpltnq_index) 124771d10453SEric Joyner { 124871d10453SEric Joyner u8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 }; 124971d10453SEric Joyner 12507d7af7f8SEric Joyner ice_set_ctx(hw, (u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info); 125171d10453SEric Joyner return ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index); 125271d10453SEric Joyner } 125371d10453SEric Joyner 125471d10453SEric Joyner /** 125571d10453SEric Joyner * ice_clear_tx_cmpltnq_ctx 125671d10453SEric Joyner * @hw: pointer to the hardware structure 125771d10453SEric Joyner * @tx_cmpltnq_index: the index of the completion queue to clear 125871d10453SEric Joyner * 125971d10453SEric Joyner * Clears Tx completion queue context in HW register space 126071d10453SEric Joyner */ 126171d10453SEric Joyner enum ice_status 126271d10453SEric Joyner ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index) 126371d10453SEric Joyner { 126471d10453SEric Joyner u8 i; 126571d10453SEric Joyner 126671d10453SEric Joyner if (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX) 126771d10453SEric Joyner return ICE_ERR_PARAM; 126871d10453SEric Joyner 126971d10453SEric Joyner /* Clear each dword register separately */ 127071d10453SEric Joyner for (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) 127171d10453SEric Joyner wr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0); 127271d10453SEric Joyner 127371d10453SEric Joyner return ICE_SUCCESS; 127471d10453SEric Joyner } 127571d10453SEric Joyner 127671d10453SEric Joyner /** 127771d10453SEric Joyner * ice_copy_tx_drbell_q_ctx_to_hw 127871d10453SEric Joyner * @hw: pointer to the hardware structure 127971d10453SEric Joyner * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context 128071d10453SEric Joyner * @tx_drbell_q_index: the index of the doorbell queue 128171d10453SEric Joyner * 128271d10453SEric Joyner * Copies doorbell queue context from dense structure to HW register space 128371d10453SEric Joyner */ 128471d10453SEric Joyner static enum ice_status 128571d10453SEric Joyner ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx, 128671d10453SEric Joyner u32 tx_drbell_q_index) 128771d10453SEric Joyner { 128871d10453SEric Joyner u8 i; 128971d10453SEric Joyner 129071d10453SEric Joyner if (!ice_tx_drbell_q_ctx) 129171d10453SEric Joyner return ICE_ERR_BAD_PTR; 129271d10453SEric Joyner 129371d10453SEric Joyner if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX) 129471d10453SEric Joyner return ICE_ERR_PARAM; 129571d10453SEric Joyner 129671d10453SEric Joyner /* Copy each dword separately to HW */ 129771d10453SEric Joyner for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) { 129871d10453SEric Joyner wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 129971d10453SEric Joyner *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32))))); 130071d10453SEric Joyner 130171d10453SEric Joyner ice_debug(hw, ICE_DBG_QCTX, "tx_drbell_qdata[%d]: %08X\n", i, 130271d10453SEric Joyner *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32))))); 130371d10453SEric Joyner } 130471d10453SEric Joyner 130571d10453SEric Joyner return ICE_SUCCESS; 130671d10453SEric Joyner } 130771d10453SEric Joyner 130871d10453SEric Joyner /* LAN Tx Doorbell Queue Context info */ 130971d10453SEric Joyner static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = { 131071d10453SEric Joyner /* Field Width LSB */ 131171d10453SEric Joyner ICE_CTX_STORE(ice_tx_drbell_q_ctx, base, 57, 0), 131271d10453SEric Joyner ICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len, 13, 64), 131371d10453SEric Joyner ICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num, 3, 80), 131471d10453SEric Joyner ICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num, 8, 84), 131571d10453SEric Joyner ICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type, 2, 94), 131671d10453SEric Joyner ICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid, 8, 96), 131771d10453SEric Joyner ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd, 1, 104), 131871d10453SEric Joyner ICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr, 1, 108), 131971d10453SEric Joyner ICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en, 1, 112), 132071d10453SEric Joyner ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head, 13, 128), 132171d10453SEric Joyner ICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail, 13, 144), 132271d10453SEric Joyner { 0 } 132371d10453SEric Joyner }; 132471d10453SEric Joyner 132571d10453SEric Joyner /** 132671d10453SEric Joyner * ice_write_tx_drbell_q_ctx 132771d10453SEric Joyner * @hw: pointer to the hardware structure 132871d10453SEric Joyner * @tx_drbell_q_ctx: pointer to the doorbell queue context 132971d10453SEric Joyner * @tx_drbell_q_index: the index of the doorbell queue 133071d10453SEric Joyner * 133171d10453SEric Joyner * Converts doorbell queue context from sparse to dense structure and then 133271d10453SEric Joyner * writes it to HW register space 133371d10453SEric Joyner */ 133471d10453SEric Joyner enum ice_status 133571d10453SEric Joyner ice_write_tx_drbell_q_ctx(struct ice_hw *hw, 133671d10453SEric Joyner struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx, 133771d10453SEric Joyner u32 tx_drbell_q_index) 133871d10453SEric Joyner { 133971d10453SEric Joyner u8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 }; 134071d10453SEric Joyner 13417d7af7f8SEric Joyner ice_set_ctx(hw, (u8 *)tx_drbell_q_ctx, ctx_buf, 13427d7af7f8SEric Joyner ice_tx_drbell_q_ctx_info); 134371d10453SEric Joyner return ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index); 134471d10453SEric Joyner } 134571d10453SEric Joyner 134671d10453SEric Joyner /** 134771d10453SEric Joyner * ice_clear_tx_drbell_q_ctx 134871d10453SEric Joyner * @hw: pointer to the hardware structure 134971d10453SEric Joyner * @tx_drbell_q_index: the index of the doorbell queue to clear 135071d10453SEric Joyner * 135171d10453SEric Joyner * Clears doorbell queue context in HW register space 135271d10453SEric Joyner */ 135371d10453SEric Joyner enum ice_status 135471d10453SEric Joyner ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index) 135571d10453SEric Joyner { 135671d10453SEric Joyner u8 i; 135771d10453SEric Joyner 135871d10453SEric Joyner if (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX) 135971d10453SEric Joyner return ICE_ERR_PARAM; 136071d10453SEric Joyner 136171d10453SEric Joyner /* Clear each dword register separately */ 136271d10453SEric Joyner for (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) 136371d10453SEric Joyner wr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0); 136471d10453SEric Joyner 136571d10453SEric Joyner return ICE_SUCCESS; 136671d10453SEric Joyner } 136771d10453SEric Joyner 136871d10453SEric Joyner /* FW Admin Queue command wrappers */ 136971d10453SEric Joyner 137071d10453SEric Joyner /** 1371*9cf1841cSEric Joyner * ice_should_retry_sq_send_cmd 1372*9cf1841cSEric Joyner * @opcode: AQ opcode 1373*9cf1841cSEric Joyner * 1374*9cf1841cSEric Joyner * Decide if we should retry the send command routine for the ATQ, depending 1375*9cf1841cSEric Joyner * on the opcode. 1376*9cf1841cSEric Joyner */ 1377*9cf1841cSEric Joyner static bool ice_should_retry_sq_send_cmd(u16 opcode) 1378*9cf1841cSEric Joyner { 1379*9cf1841cSEric Joyner switch (opcode) { 1380*9cf1841cSEric Joyner case ice_aqc_opc_dnl_get_status: 1381*9cf1841cSEric Joyner case ice_aqc_opc_dnl_run: 1382*9cf1841cSEric Joyner case ice_aqc_opc_dnl_call: 1383*9cf1841cSEric Joyner case ice_aqc_opc_dnl_read_sto: 1384*9cf1841cSEric Joyner case ice_aqc_opc_dnl_write_sto: 1385*9cf1841cSEric Joyner case ice_aqc_opc_dnl_set_breakpoints: 1386*9cf1841cSEric Joyner case ice_aqc_opc_dnl_read_log: 1387*9cf1841cSEric Joyner case ice_aqc_opc_get_link_topo: 1388*9cf1841cSEric Joyner case ice_aqc_opc_done_alt_write: 1389*9cf1841cSEric Joyner case ice_aqc_opc_lldp_stop: 1390*9cf1841cSEric Joyner case ice_aqc_opc_lldp_start: 1391*9cf1841cSEric Joyner case ice_aqc_opc_lldp_filter_ctrl: 1392*9cf1841cSEric Joyner return true; 1393*9cf1841cSEric Joyner } 1394*9cf1841cSEric Joyner 1395*9cf1841cSEric Joyner return false; 1396*9cf1841cSEric Joyner } 1397*9cf1841cSEric Joyner 1398*9cf1841cSEric Joyner /** 1399*9cf1841cSEric Joyner * ice_sq_send_cmd_retry - send command to Control Queue (ATQ) 1400*9cf1841cSEric Joyner * @hw: pointer to the HW struct 1401*9cf1841cSEric Joyner * @cq: pointer to the specific Control queue 1402*9cf1841cSEric Joyner * @desc: prefilled descriptor describing the command 1403*9cf1841cSEric Joyner * @buf: buffer to use for indirect commands (or NULL for direct commands) 1404*9cf1841cSEric Joyner * @buf_size: size of buffer for indirect commands (or 0 for direct commands) 1405*9cf1841cSEric Joyner * @cd: pointer to command details structure 1406*9cf1841cSEric Joyner * 1407*9cf1841cSEric Joyner * Retry sending the FW Admin Queue command, multiple times, to the FW Admin 1408*9cf1841cSEric Joyner * Queue if the EBUSY AQ error is returned. 1409*9cf1841cSEric Joyner */ 1410*9cf1841cSEric Joyner static enum ice_status 1411*9cf1841cSEric Joyner ice_sq_send_cmd_retry(struct ice_hw *hw, struct ice_ctl_q_info *cq, 1412*9cf1841cSEric Joyner struct ice_aq_desc *desc, void *buf, u16 buf_size, 1413*9cf1841cSEric Joyner struct ice_sq_cd *cd) 1414*9cf1841cSEric Joyner { 1415*9cf1841cSEric Joyner struct ice_aq_desc desc_cpy; 1416*9cf1841cSEric Joyner enum ice_status status; 1417*9cf1841cSEric Joyner bool is_cmd_for_retry; 1418*9cf1841cSEric Joyner u8 *buf_cpy = NULL; 1419*9cf1841cSEric Joyner u8 idx = 0; 1420*9cf1841cSEric Joyner u16 opcode; 1421*9cf1841cSEric Joyner 1422*9cf1841cSEric Joyner opcode = LE16_TO_CPU(desc->opcode); 1423*9cf1841cSEric Joyner is_cmd_for_retry = ice_should_retry_sq_send_cmd(opcode); 1424*9cf1841cSEric Joyner ice_memset(&desc_cpy, 0, sizeof(desc_cpy), ICE_NONDMA_MEM); 1425*9cf1841cSEric Joyner 1426*9cf1841cSEric Joyner if (is_cmd_for_retry) { 1427*9cf1841cSEric Joyner if (buf) { 1428*9cf1841cSEric Joyner buf_cpy = (u8 *)ice_malloc(hw, buf_size); 1429*9cf1841cSEric Joyner if (!buf_cpy) 1430*9cf1841cSEric Joyner return ICE_ERR_NO_MEMORY; 1431*9cf1841cSEric Joyner } 1432*9cf1841cSEric Joyner 1433*9cf1841cSEric Joyner ice_memcpy(&desc_cpy, desc, sizeof(desc_cpy), 1434*9cf1841cSEric Joyner ICE_NONDMA_TO_NONDMA); 1435*9cf1841cSEric Joyner } 1436*9cf1841cSEric Joyner 1437*9cf1841cSEric Joyner do { 1438*9cf1841cSEric Joyner status = ice_sq_send_cmd(hw, cq, desc, buf, buf_size, cd); 1439*9cf1841cSEric Joyner 1440*9cf1841cSEric Joyner if (!is_cmd_for_retry || status == ICE_SUCCESS || 1441*9cf1841cSEric Joyner hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY) 1442*9cf1841cSEric Joyner break; 1443*9cf1841cSEric Joyner 1444*9cf1841cSEric Joyner if (buf_cpy) 1445*9cf1841cSEric Joyner ice_memcpy(buf, buf_cpy, buf_size, 1446*9cf1841cSEric Joyner ICE_NONDMA_TO_NONDMA); 1447*9cf1841cSEric Joyner 1448*9cf1841cSEric Joyner ice_memcpy(desc, &desc_cpy, sizeof(desc_cpy), 1449*9cf1841cSEric Joyner ICE_NONDMA_TO_NONDMA); 1450*9cf1841cSEric Joyner 1451*9cf1841cSEric Joyner ice_msec_delay(ICE_SQ_SEND_DELAY_TIME_MS, false); 1452*9cf1841cSEric Joyner 1453*9cf1841cSEric Joyner } while (++idx < ICE_SQ_SEND_MAX_EXECUTE); 1454*9cf1841cSEric Joyner 1455*9cf1841cSEric Joyner if (buf_cpy) 1456*9cf1841cSEric Joyner ice_free(hw, buf_cpy); 1457*9cf1841cSEric Joyner 1458*9cf1841cSEric Joyner return status; 1459*9cf1841cSEric Joyner } 1460*9cf1841cSEric Joyner 1461*9cf1841cSEric Joyner /** 146271d10453SEric Joyner * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue 146371d10453SEric Joyner * @hw: pointer to the HW struct 146471d10453SEric Joyner * @desc: descriptor describing the command 146571d10453SEric Joyner * @buf: buffer to use for indirect commands (NULL for direct commands) 146671d10453SEric Joyner * @buf_size: size of buffer for indirect commands (0 for direct commands) 146771d10453SEric Joyner * @cd: pointer to command details structure 146871d10453SEric Joyner * 146971d10453SEric Joyner * Helper function to send FW Admin Queue commands to the FW Admin Queue. 147071d10453SEric Joyner */ 147171d10453SEric Joyner enum ice_status 147271d10453SEric Joyner ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf, 147371d10453SEric Joyner u16 buf_size, struct ice_sq_cd *cd) 147471d10453SEric Joyner { 1475*9cf1841cSEric Joyner return ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); 147671d10453SEric Joyner } 147771d10453SEric Joyner 147871d10453SEric Joyner /** 147971d10453SEric Joyner * ice_aq_get_fw_ver 148071d10453SEric Joyner * @hw: pointer to the HW struct 148171d10453SEric Joyner * @cd: pointer to command details structure or NULL 148271d10453SEric Joyner * 148371d10453SEric Joyner * Get the firmware version (0x0001) from the admin queue commands 148471d10453SEric Joyner */ 148571d10453SEric Joyner enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd) 148671d10453SEric Joyner { 148771d10453SEric Joyner struct ice_aqc_get_ver *resp; 148871d10453SEric Joyner struct ice_aq_desc desc; 148971d10453SEric Joyner enum ice_status status; 149071d10453SEric Joyner 149171d10453SEric Joyner resp = &desc.params.get_ver; 149271d10453SEric Joyner 149371d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver); 149471d10453SEric Joyner 149571d10453SEric Joyner status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 149671d10453SEric Joyner 149771d10453SEric Joyner if (!status) { 149871d10453SEric Joyner hw->fw_branch = resp->fw_branch; 149971d10453SEric Joyner hw->fw_maj_ver = resp->fw_major; 150071d10453SEric Joyner hw->fw_min_ver = resp->fw_minor; 150171d10453SEric Joyner hw->fw_patch = resp->fw_patch; 150271d10453SEric Joyner hw->fw_build = LE32_TO_CPU(resp->fw_build); 150371d10453SEric Joyner hw->api_branch = resp->api_branch; 150471d10453SEric Joyner hw->api_maj_ver = resp->api_major; 150571d10453SEric Joyner hw->api_min_ver = resp->api_minor; 150671d10453SEric Joyner hw->api_patch = resp->api_patch; 150771d10453SEric Joyner } 150871d10453SEric Joyner 150971d10453SEric Joyner return status; 151071d10453SEric Joyner } 151171d10453SEric Joyner 151271d10453SEric Joyner /** 151371d10453SEric Joyner * ice_aq_send_driver_ver 151471d10453SEric Joyner * @hw: pointer to the HW struct 151571d10453SEric Joyner * @dv: driver's major, minor version 151671d10453SEric Joyner * @cd: pointer to command details structure or NULL 151771d10453SEric Joyner * 151871d10453SEric Joyner * Send the driver version (0x0002) to the firmware 151971d10453SEric Joyner */ 152071d10453SEric Joyner enum ice_status 152171d10453SEric Joyner ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv, 152271d10453SEric Joyner struct ice_sq_cd *cd) 152371d10453SEric Joyner { 152471d10453SEric Joyner struct ice_aqc_driver_ver *cmd; 152571d10453SEric Joyner struct ice_aq_desc desc; 152671d10453SEric Joyner u16 len; 152771d10453SEric Joyner 152871d10453SEric Joyner cmd = &desc.params.driver_ver; 152971d10453SEric Joyner 153071d10453SEric Joyner if (!dv) 153171d10453SEric Joyner return ICE_ERR_PARAM; 153271d10453SEric Joyner 153371d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver); 153471d10453SEric Joyner 153571d10453SEric Joyner desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 153671d10453SEric Joyner cmd->major_ver = dv->major_ver; 153771d10453SEric Joyner cmd->minor_ver = dv->minor_ver; 153871d10453SEric Joyner cmd->build_ver = dv->build_ver; 153971d10453SEric Joyner cmd->subbuild_ver = dv->subbuild_ver; 154071d10453SEric Joyner 154171d10453SEric Joyner len = 0; 154271d10453SEric Joyner while (len < sizeof(dv->driver_string) && 154371d10453SEric Joyner IS_ASCII(dv->driver_string[len]) && dv->driver_string[len]) 154471d10453SEric Joyner len++; 154571d10453SEric Joyner 154671d10453SEric Joyner return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); 154771d10453SEric Joyner } 154871d10453SEric Joyner 154971d10453SEric Joyner /** 155071d10453SEric Joyner * ice_aq_q_shutdown 155171d10453SEric Joyner * @hw: pointer to the HW struct 155271d10453SEric Joyner * @unloading: is the driver unloading itself 155371d10453SEric Joyner * 155471d10453SEric Joyner * Tell the Firmware that we're shutting down the AdminQ and whether 155571d10453SEric Joyner * or not the driver is unloading as well (0x0003). 155671d10453SEric Joyner */ 155771d10453SEric Joyner enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading) 155871d10453SEric Joyner { 155971d10453SEric Joyner struct ice_aqc_q_shutdown *cmd; 156071d10453SEric Joyner struct ice_aq_desc desc; 156171d10453SEric Joyner 156271d10453SEric Joyner cmd = &desc.params.q_shutdown; 156371d10453SEric Joyner 156471d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown); 156571d10453SEric Joyner 156671d10453SEric Joyner if (unloading) 156771d10453SEric Joyner cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; 156871d10453SEric Joyner 156971d10453SEric Joyner return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 157071d10453SEric Joyner } 157171d10453SEric Joyner 157271d10453SEric Joyner /** 157371d10453SEric Joyner * ice_aq_req_res 157471d10453SEric Joyner * @hw: pointer to the HW struct 157571d10453SEric Joyner * @res: resource ID 157671d10453SEric Joyner * @access: access type 157771d10453SEric Joyner * @sdp_number: resource number 157871d10453SEric Joyner * @timeout: the maximum time in ms that the driver may hold the resource 157971d10453SEric Joyner * @cd: pointer to command details structure or NULL 158071d10453SEric Joyner * 158171d10453SEric Joyner * Requests common resource using the admin queue commands (0x0008). 158271d10453SEric Joyner * When attempting to acquire the Global Config Lock, the driver can 158371d10453SEric Joyner * learn of three states: 158471d10453SEric Joyner * 1) ICE_SUCCESS - acquired lock, and can perform download package 158571d10453SEric Joyner * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load 158671d10453SEric Joyner * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has 158771d10453SEric Joyner * successfully downloaded the package; the driver does 158871d10453SEric Joyner * not have to download the package and can continue 158971d10453SEric Joyner * loading 159071d10453SEric Joyner * 159171d10453SEric Joyner * Note that if the caller is in an acquire lock, perform action, release lock 159271d10453SEric Joyner * phase of operation, it is possible that the FW may detect a timeout and issue 159371d10453SEric Joyner * a CORER. In this case, the driver will receive a CORER interrupt and will 159471d10453SEric Joyner * have to determine its cause. The calling thread that is handling this flow 159571d10453SEric Joyner * will likely get an error propagated back to it indicating the Download 159671d10453SEric Joyner * Package, Update Package or the Release Resource AQ commands timed out. 159771d10453SEric Joyner */ 159871d10453SEric Joyner static enum ice_status 159971d10453SEric Joyner ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res, 160071d10453SEric Joyner enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout, 160171d10453SEric Joyner struct ice_sq_cd *cd) 160271d10453SEric Joyner { 160371d10453SEric Joyner struct ice_aqc_req_res *cmd_resp; 160471d10453SEric Joyner struct ice_aq_desc desc; 160571d10453SEric Joyner enum ice_status status; 160671d10453SEric Joyner 160771d10453SEric Joyner ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 160871d10453SEric Joyner 160971d10453SEric Joyner cmd_resp = &desc.params.res_owner; 161071d10453SEric Joyner 161171d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res); 161271d10453SEric Joyner 161371d10453SEric Joyner cmd_resp->res_id = CPU_TO_LE16(res); 161471d10453SEric Joyner cmd_resp->access_type = CPU_TO_LE16(access); 161571d10453SEric Joyner cmd_resp->res_number = CPU_TO_LE32(sdp_number); 161671d10453SEric Joyner cmd_resp->timeout = CPU_TO_LE32(*timeout); 161771d10453SEric Joyner *timeout = 0; 161871d10453SEric Joyner 161971d10453SEric Joyner status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 162071d10453SEric Joyner 162171d10453SEric Joyner /* The completion specifies the maximum time in ms that the driver 162271d10453SEric Joyner * may hold the resource in the Timeout field. 162371d10453SEric Joyner */ 162471d10453SEric Joyner 162571d10453SEric Joyner /* Global config lock response utilizes an additional status field. 162671d10453SEric Joyner * 162771d10453SEric Joyner * If the Global config lock resource is held by some other driver, the 162871d10453SEric Joyner * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field 162971d10453SEric Joyner * and the timeout field indicates the maximum time the current owner 163071d10453SEric Joyner * of the resource has to free it. 163171d10453SEric Joyner */ 163271d10453SEric Joyner if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) { 163371d10453SEric Joyner if (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { 163471d10453SEric Joyner *timeout = LE32_TO_CPU(cmd_resp->timeout); 163571d10453SEric Joyner return ICE_SUCCESS; 163671d10453SEric Joyner } else if (LE16_TO_CPU(cmd_resp->status) == 163771d10453SEric Joyner ICE_AQ_RES_GLBL_IN_PROG) { 163871d10453SEric Joyner *timeout = LE32_TO_CPU(cmd_resp->timeout); 163971d10453SEric Joyner return ICE_ERR_AQ_ERROR; 164071d10453SEric Joyner } else if (LE16_TO_CPU(cmd_resp->status) == 164171d10453SEric Joyner ICE_AQ_RES_GLBL_DONE) { 164271d10453SEric Joyner return ICE_ERR_AQ_NO_WORK; 164371d10453SEric Joyner } 164471d10453SEric Joyner 164571d10453SEric Joyner /* invalid FW response, force a timeout immediately */ 164671d10453SEric Joyner *timeout = 0; 164771d10453SEric Joyner return ICE_ERR_AQ_ERROR; 164871d10453SEric Joyner } 164971d10453SEric Joyner 165071d10453SEric Joyner /* If the resource is held by some other driver, the command completes 165171d10453SEric Joyner * with a busy return value and the timeout field indicates the maximum 165271d10453SEric Joyner * time the current owner of the resource has to free it. 165371d10453SEric Joyner */ 165471d10453SEric Joyner if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) 165571d10453SEric Joyner *timeout = LE32_TO_CPU(cmd_resp->timeout); 165671d10453SEric Joyner 165771d10453SEric Joyner return status; 165871d10453SEric Joyner } 165971d10453SEric Joyner 166071d10453SEric Joyner /** 166171d10453SEric Joyner * ice_aq_release_res 166271d10453SEric Joyner * @hw: pointer to the HW struct 166371d10453SEric Joyner * @res: resource ID 166471d10453SEric Joyner * @sdp_number: resource number 166571d10453SEric Joyner * @cd: pointer to command details structure or NULL 166671d10453SEric Joyner * 166771d10453SEric Joyner * release common resource using the admin queue commands (0x0009) 166871d10453SEric Joyner */ 166971d10453SEric Joyner static enum ice_status 167071d10453SEric Joyner ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number, 167171d10453SEric Joyner struct ice_sq_cd *cd) 167271d10453SEric Joyner { 167371d10453SEric Joyner struct ice_aqc_req_res *cmd; 167471d10453SEric Joyner struct ice_aq_desc desc; 167571d10453SEric Joyner 167671d10453SEric Joyner ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 167771d10453SEric Joyner 167871d10453SEric Joyner cmd = &desc.params.res_owner; 167971d10453SEric Joyner 168071d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res); 168171d10453SEric Joyner 168271d10453SEric Joyner cmd->res_id = CPU_TO_LE16(res); 168371d10453SEric Joyner cmd->res_number = CPU_TO_LE32(sdp_number); 168471d10453SEric Joyner 168571d10453SEric Joyner return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 168671d10453SEric Joyner } 168771d10453SEric Joyner 168871d10453SEric Joyner /** 168971d10453SEric Joyner * ice_acquire_res 169071d10453SEric Joyner * @hw: pointer to the HW structure 169171d10453SEric Joyner * @res: resource ID 169271d10453SEric Joyner * @access: access type (read or write) 169371d10453SEric Joyner * @timeout: timeout in milliseconds 169471d10453SEric Joyner * 169571d10453SEric Joyner * This function will attempt to acquire the ownership of a resource. 169671d10453SEric Joyner */ 169771d10453SEric Joyner enum ice_status 169871d10453SEric Joyner ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res, 169971d10453SEric Joyner enum ice_aq_res_access_type access, u32 timeout) 170071d10453SEric Joyner { 170171d10453SEric Joyner #define ICE_RES_POLLING_DELAY_MS 10 170271d10453SEric Joyner u32 delay = ICE_RES_POLLING_DELAY_MS; 170371d10453SEric Joyner u32 time_left = timeout; 170471d10453SEric Joyner enum ice_status status; 170571d10453SEric Joyner 170671d10453SEric Joyner ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 170771d10453SEric Joyner 170871d10453SEric Joyner status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 170971d10453SEric Joyner 171071d10453SEric Joyner /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has 171171d10453SEric Joyner * previously acquired the resource and performed any necessary updates; 171271d10453SEric Joyner * in this case the caller does not obtain the resource and has no 171371d10453SEric Joyner * further work to do. 171471d10453SEric Joyner */ 171571d10453SEric Joyner if (status == ICE_ERR_AQ_NO_WORK) 171671d10453SEric Joyner goto ice_acquire_res_exit; 171771d10453SEric Joyner 171871d10453SEric Joyner if (status) 17197d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_RES, "resource %d acquire type %d failed.\n", res, access); 172071d10453SEric Joyner 172171d10453SEric Joyner /* If necessary, poll until the current lock owner timeouts */ 172271d10453SEric Joyner timeout = time_left; 172371d10453SEric Joyner while (status && timeout && time_left) { 172471d10453SEric Joyner ice_msec_delay(delay, true); 172571d10453SEric Joyner timeout = (timeout > delay) ? timeout - delay : 0; 172671d10453SEric Joyner status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL); 172771d10453SEric Joyner 172871d10453SEric Joyner if (status == ICE_ERR_AQ_NO_WORK) 172971d10453SEric Joyner /* lock free, but no work to do */ 173071d10453SEric Joyner break; 173171d10453SEric Joyner 173271d10453SEric Joyner if (!status) 173371d10453SEric Joyner /* lock acquired */ 173471d10453SEric Joyner break; 173571d10453SEric Joyner } 173671d10453SEric Joyner if (status && status != ICE_ERR_AQ_NO_WORK) 173771d10453SEric Joyner ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n"); 173871d10453SEric Joyner 173971d10453SEric Joyner ice_acquire_res_exit: 174071d10453SEric Joyner if (status == ICE_ERR_AQ_NO_WORK) { 174171d10453SEric Joyner if (access == ICE_RES_WRITE) 17427d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_RES, "resource indicates no work to do.\n"); 174371d10453SEric Joyner else 17447d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_RES, "Warning: ICE_ERR_AQ_NO_WORK not expected\n"); 174571d10453SEric Joyner } 174671d10453SEric Joyner return status; 174771d10453SEric Joyner } 174871d10453SEric Joyner 174971d10453SEric Joyner /** 175071d10453SEric Joyner * ice_release_res 175171d10453SEric Joyner * @hw: pointer to the HW structure 175271d10453SEric Joyner * @res: resource ID 175371d10453SEric Joyner * 175471d10453SEric Joyner * This function will release a resource using the proper Admin Command. 175571d10453SEric Joyner */ 175671d10453SEric Joyner void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res) 175771d10453SEric Joyner { 175871d10453SEric Joyner enum ice_status status; 175971d10453SEric Joyner u32 total_delay = 0; 176071d10453SEric Joyner 176171d10453SEric Joyner ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 176271d10453SEric Joyner 176371d10453SEric Joyner status = ice_aq_release_res(hw, res, 0, NULL); 176471d10453SEric Joyner 176571d10453SEric Joyner /* there are some rare cases when trying to release the resource 176671d10453SEric Joyner * results in an admin queue timeout, so handle them correctly 176771d10453SEric Joyner */ 176871d10453SEric Joyner while ((status == ICE_ERR_AQ_TIMEOUT) && 176971d10453SEric Joyner (total_delay < hw->adminq.sq_cmd_timeout)) { 177071d10453SEric Joyner ice_msec_delay(1, true); 177171d10453SEric Joyner status = ice_aq_release_res(hw, res, 0, NULL); 177271d10453SEric Joyner total_delay++; 177371d10453SEric Joyner } 177471d10453SEric Joyner } 177571d10453SEric Joyner 177671d10453SEric Joyner /** 177771d10453SEric Joyner * ice_aq_alloc_free_res - command to allocate/free resources 177871d10453SEric Joyner * @hw: pointer to the HW struct 177971d10453SEric Joyner * @num_entries: number of resource entries in buffer 178071d10453SEric Joyner * @buf: Indirect buffer to hold data parameters and response 178171d10453SEric Joyner * @buf_size: size of buffer for indirect commands 178271d10453SEric Joyner * @opc: pass in the command opcode 178371d10453SEric Joyner * @cd: pointer to command details structure or NULL 178471d10453SEric Joyner * 178571d10453SEric Joyner * Helper function to allocate/free resources using the admin queue commands 178671d10453SEric Joyner */ 178771d10453SEric Joyner enum ice_status 178871d10453SEric Joyner ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, 178971d10453SEric Joyner struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size, 179071d10453SEric Joyner enum ice_adminq_opc opc, struct ice_sq_cd *cd) 179171d10453SEric Joyner { 179271d10453SEric Joyner struct ice_aqc_alloc_free_res_cmd *cmd; 179371d10453SEric Joyner struct ice_aq_desc desc; 179471d10453SEric Joyner 179571d10453SEric Joyner ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 179671d10453SEric Joyner 179771d10453SEric Joyner cmd = &desc.params.sw_res_ctrl; 179871d10453SEric Joyner 179971d10453SEric Joyner if (!buf) 180071d10453SEric Joyner return ICE_ERR_PARAM; 180171d10453SEric Joyner 1802d08b8680SEric Joyner if (buf_size < FLEX_ARRAY_SIZE(buf, elem, num_entries)) 180371d10453SEric Joyner return ICE_ERR_PARAM; 180471d10453SEric Joyner 180571d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, opc); 180671d10453SEric Joyner 180771d10453SEric Joyner desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 180871d10453SEric Joyner 180971d10453SEric Joyner cmd->num_entries = CPU_TO_LE16(num_entries); 181071d10453SEric Joyner 181171d10453SEric Joyner return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 181271d10453SEric Joyner } 181371d10453SEric Joyner 181471d10453SEric Joyner /** 181571d10453SEric Joyner * ice_alloc_hw_res - allocate resource 181671d10453SEric Joyner * @hw: pointer to the HW struct 181771d10453SEric Joyner * @type: type of resource 181871d10453SEric Joyner * @num: number of resources to allocate 181971d10453SEric Joyner * @btm: allocate from bottom 182071d10453SEric Joyner * @res: pointer to array that will receive the resources 182171d10453SEric Joyner */ 182271d10453SEric Joyner enum ice_status 182371d10453SEric Joyner ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res) 182471d10453SEric Joyner { 182571d10453SEric Joyner struct ice_aqc_alloc_free_res_elem *buf; 182671d10453SEric Joyner enum ice_status status; 182771d10453SEric Joyner u16 buf_len; 182871d10453SEric Joyner 18297d7af7f8SEric Joyner buf_len = ice_struct_size(buf, elem, num); 18307d7af7f8SEric Joyner buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len); 183171d10453SEric Joyner if (!buf) 183271d10453SEric Joyner return ICE_ERR_NO_MEMORY; 183371d10453SEric Joyner 183471d10453SEric Joyner /* Prepare buffer to allocate resource. */ 183571d10453SEric Joyner buf->num_elems = CPU_TO_LE16(num); 183671d10453SEric Joyner buf->res_type = CPU_TO_LE16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | 183771d10453SEric Joyner ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX); 183871d10453SEric Joyner if (btm) 183971d10453SEric Joyner buf->res_type |= CPU_TO_LE16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); 184071d10453SEric Joyner 184171d10453SEric Joyner status = ice_aq_alloc_free_res(hw, 1, buf, buf_len, 184271d10453SEric Joyner ice_aqc_opc_alloc_res, NULL); 184371d10453SEric Joyner if (status) 184471d10453SEric Joyner goto ice_alloc_res_exit; 184571d10453SEric Joyner 18467d7af7f8SEric Joyner ice_memcpy(res, buf->elem, sizeof(*buf->elem) * num, 184771d10453SEric Joyner ICE_NONDMA_TO_NONDMA); 184871d10453SEric Joyner 184971d10453SEric Joyner ice_alloc_res_exit: 185071d10453SEric Joyner ice_free(hw, buf); 185171d10453SEric Joyner return status; 185271d10453SEric Joyner } 185371d10453SEric Joyner 185471d10453SEric Joyner /** 185571d10453SEric Joyner * ice_free_hw_res - free allocated HW resource 185671d10453SEric Joyner * @hw: pointer to the HW struct 185771d10453SEric Joyner * @type: type of resource to free 185871d10453SEric Joyner * @num: number of resources 185971d10453SEric Joyner * @res: pointer to array that contains the resources to free 186071d10453SEric Joyner */ 18617d7af7f8SEric Joyner enum ice_status ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res) 186271d10453SEric Joyner { 186371d10453SEric Joyner struct ice_aqc_alloc_free_res_elem *buf; 186471d10453SEric Joyner enum ice_status status; 186571d10453SEric Joyner u16 buf_len; 186671d10453SEric Joyner 18677d7af7f8SEric Joyner buf_len = ice_struct_size(buf, elem, num); 186871d10453SEric Joyner buf = (struct ice_aqc_alloc_free_res_elem *)ice_malloc(hw, buf_len); 186971d10453SEric Joyner if (!buf) 187071d10453SEric Joyner return ICE_ERR_NO_MEMORY; 187171d10453SEric Joyner 187271d10453SEric Joyner /* Prepare buffer to free resource. */ 187371d10453SEric Joyner buf->num_elems = CPU_TO_LE16(num); 187471d10453SEric Joyner buf->res_type = CPU_TO_LE16(type); 18757d7af7f8SEric Joyner ice_memcpy(buf->elem, res, sizeof(*buf->elem) * num, 187671d10453SEric Joyner ICE_NONDMA_TO_NONDMA); 187771d10453SEric Joyner 187871d10453SEric Joyner status = ice_aq_alloc_free_res(hw, num, buf, buf_len, 187971d10453SEric Joyner ice_aqc_opc_free_res, NULL); 188071d10453SEric Joyner if (status) 188171d10453SEric Joyner ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); 188271d10453SEric Joyner 188371d10453SEric Joyner ice_free(hw, buf); 188471d10453SEric Joyner return status; 188571d10453SEric Joyner } 188671d10453SEric Joyner 188771d10453SEric Joyner /** 188871d10453SEric Joyner * ice_get_num_per_func - determine number of resources per PF 188971d10453SEric Joyner * @hw: pointer to the HW structure 189071d10453SEric Joyner * @max: value to be evenly split between each PF 189171d10453SEric Joyner * 189271d10453SEric Joyner * Determine the number of valid functions by going through the bitmap returned 189371d10453SEric Joyner * from parsing capabilities and use this to calculate the number of resources 189471d10453SEric Joyner * per PF based on the max value passed in. 189571d10453SEric Joyner */ 189671d10453SEric Joyner static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max) 189771d10453SEric Joyner { 189871d10453SEric Joyner u8 funcs; 189971d10453SEric Joyner 190071d10453SEric Joyner #define ICE_CAPS_VALID_FUNCS_M 0xFF 190171d10453SEric Joyner funcs = ice_hweight8(hw->dev_caps.common_cap.valid_functions & 190271d10453SEric Joyner ICE_CAPS_VALID_FUNCS_M); 190371d10453SEric Joyner 190471d10453SEric Joyner if (!funcs) 190571d10453SEric Joyner return 0; 190671d10453SEric Joyner 190771d10453SEric Joyner return max / funcs; 190871d10453SEric Joyner } 190971d10453SEric Joyner 191071d10453SEric Joyner /** 191171d10453SEric Joyner * ice_print_led_caps - print LED capabilities 191271d10453SEric Joyner * @hw: pointer to the ice_hw instance 191371d10453SEric Joyner * @caps: pointer to common caps instance 191471d10453SEric Joyner * @prefix: string to prefix when printing 1915*9cf1841cSEric Joyner * @dbg: set to indicate debug print 191671d10453SEric Joyner */ 191771d10453SEric Joyner static void 191871d10453SEric Joyner ice_print_led_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 1919*9cf1841cSEric Joyner char const *prefix, bool dbg) 192071d10453SEric Joyner { 192171d10453SEric Joyner u8 i; 192271d10453SEric Joyner 1923*9cf1841cSEric Joyner if (dbg) 192471d10453SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: led_pin_num = %d\n", prefix, 192571d10453SEric Joyner caps->led_pin_num); 192671d10453SEric Joyner else 192771d10453SEric Joyner ice_info(hw, "%s: led_pin_num = %d\n", prefix, 192871d10453SEric Joyner caps->led_pin_num); 192971d10453SEric Joyner 193071d10453SEric Joyner for (i = 0; i < ICE_MAX_SUPPORTED_GPIO_LED; i++) { 193171d10453SEric Joyner if (!caps->led[i]) 193271d10453SEric Joyner continue; 193371d10453SEric Joyner 1934*9cf1841cSEric Joyner if (dbg) 193571d10453SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: led[%d] = %d\n", 193671d10453SEric Joyner prefix, i, caps->led[i]); 193771d10453SEric Joyner else 193871d10453SEric Joyner ice_info(hw, "%s: led[%d] = %d\n", prefix, i, 193971d10453SEric Joyner caps->led[i]); 194071d10453SEric Joyner } 194171d10453SEric Joyner } 194271d10453SEric Joyner 194371d10453SEric Joyner /** 194471d10453SEric Joyner * ice_print_sdp_caps - print SDP capabilities 194571d10453SEric Joyner * @hw: pointer to the ice_hw instance 194671d10453SEric Joyner * @caps: pointer to common caps instance 194771d10453SEric Joyner * @prefix: string to prefix when printing 1948*9cf1841cSEric Joyner * @dbg: set to indicate debug print 194971d10453SEric Joyner */ 195071d10453SEric Joyner static void 195171d10453SEric Joyner ice_print_sdp_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 1952*9cf1841cSEric Joyner char const *prefix, bool dbg) 195371d10453SEric Joyner { 195471d10453SEric Joyner u8 i; 195571d10453SEric Joyner 1956*9cf1841cSEric Joyner if (dbg) 195771d10453SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: sdp_pin_num = %d\n", prefix, 195871d10453SEric Joyner caps->sdp_pin_num); 195971d10453SEric Joyner else 196071d10453SEric Joyner ice_info(hw, "%s: sdp_pin_num = %d\n", prefix, 196171d10453SEric Joyner caps->sdp_pin_num); 196271d10453SEric Joyner 196371d10453SEric Joyner for (i = 0; i < ICE_MAX_SUPPORTED_GPIO_SDP; i++) { 196471d10453SEric Joyner if (!caps->sdp[i]) 196571d10453SEric Joyner continue; 196671d10453SEric Joyner 1967*9cf1841cSEric Joyner if (dbg) 196871d10453SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: sdp[%d] = %d\n", 196971d10453SEric Joyner prefix, i, caps->sdp[i]); 197071d10453SEric Joyner else 197171d10453SEric Joyner ice_info(hw, "%s: sdp[%d] = %d\n", prefix, 197271d10453SEric Joyner i, caps->sdp[i]); 197371d10453SEric Joyner } 197471d10453SEric Joyner } 197571d10453SEric Joyner 197671d10453SEric Joyner /** 19777d7af7f8SEric Joyner * ice_parse_common_caps - parse common device/function capabilities 197871d10453SEric Joyner * @hw: pointer to the HW struct 19797d7af7f8SEric Joyner * @caps: pointer to common capabilities structure 19807d7af7f8SEric Joyner * @elem: the capability element to parse 19817d7af7f8SEric Joyner * @prefix: message prefix for tracing capabilities 198271d10453SEric Joyner * 19837d7af7f8SEric Joyner * Given a capability element, extract relevant details into the common 19847d7af7f8SEric Joyner * capability structure. 19857d7af7f8SEric Joyner * 19867d7af7f8SEric Joyner * Returns: true if the capability matches one of the common capability ids, 19877d7af7f8SEric Joyner * false otherwise. 198871d10453SEric Joyner */ 19897d7af7f8SEric Joyner static bool 19907d7af7f8SEric Joyner ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, 19917d7af7f8SEric Joyner struct ice_aqc_list_caps_elem *elem, const char *prefix) 199271d10453SEric Joyner { 19937d7af7f8SEric Joyner u32 logical_id = LE32_TO_CPU(elem->logical_id); 19947d7af7f8SEric Joyner u32 phys_id = LE32_TO_CPU(elem->phys_id); 19957d7af7f8SEric Joyner u32 number = LE32_TO_CPU(elem->number); 19967d7af7f8SEric Joyner u16 cap = LE16_TO_CPU(elem->cap); 19977d7af7f8SEric Joyner bool found = true; 199871d10453SEric Joyner 199971d10453SEric Joyner switch (cap) { 200071d10453SEric Joyner case ICE_AQC_CAPS_SWITCHING_MODE: 200171d10453SEric Joyner caps->switching_mode = number; 20027d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: switching_mode = %d\n", prefix, 200371d10453SEric Joyner caps->switching_mode); 200471d10453SEric Joyner break; 200571d10453SEric Joyner case ICE_AQC_CAPS_MANAGEABILITY_MODE: 200671d10453SEric Joyner caps->mgmt_mode = number; 200771d10453SEric Joyner caps->mgmt_protocols_mctp = logical_id; 20087d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: mgmt_mode = %d\n", prefix, 200971d10453SEric Joyner caps->mgmt_mode); 20107d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: mgmt_protocols_mctp = %d\n", prefix, 201171d10453SEric Joyner caps->mgmt_protocols_mctp); 201271d10453SEric Joyner break; 201371d10453SEric Joyner case ICE_AQC_CAPS_OS2BMC: 201471d10453SEric Joyner caps->os2bmc = number; 20157d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: os2bmc = %d\n", prefix, caps->os2bmc); 201671d10453SEric Joyner break; 201771d10453SEric Joyner case ICE_AQC_CAPS_VALID_FUNCTIONS: 201871d10453SEric Joyner caps->valid_functions = number; 20197d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: valid_functions (bitmap) = %d\n", prefix, 202071d10453SEric Joyner caps->valid_functions); 202171d10453SEric Joyner break; 202271d10453SEric Joyner case ICE_AQC_CAPS_SRIOV: 202371d10453SEric Joyner caps->sr_iov_1_1 = (number == 1); 20247d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: sr_iov_1_1 = %d\n", prefix, 202571d10453SEric Joyner caps->sr_iov_1_1); 202671d10453SEric Joyner break; 202771d10453SEric Joyner case ICE_AQC_CAPS_802_1QBG: 202871d10453SEric Joyner caps->evb_802_1_qbg = (number == 1); 20297d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: evb_802_1_qbg = %d\n", prefix, number); 203071d10453SEric Joyner break; 203171d10453SEric Joyner case ICE_AQC_CAPS_802_1BR: 203271d10453SEric Joyner caps->evb_802_1_qbh = (number == 1); 20337d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: evb_802_1_qbh = %d\n", prefix, number); 203471d10453SEric Joyner break; 203571d10453SEric Joyner case ICE_AQC_CAPS_DCB: 203671d10453SEric Joyner caps->dcb = (number == 1); 203771d10453SEric Joyner caps->active_tc_bitmap = logical_id; 203871d10453SEric Joyner caps->maxtc = phys_id; 20397d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); 20407d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: active_tc_bitmap = %d\n", prefix, 204171d10453SEric Joyner caps->active_tc_bitmap); 20427d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); 204371d10453SEric Joyner break; 204471d10453SEric Joyner case ICE_AQC_CAPS_ISCSI: 204571d10453SEric Joyner caps->iscsi = (number == 1); 20467d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: iscsi = %d\n", prefix, caps->iscsi); 204771d10453SEric Joyner break; 204871d10453SEric Joyner case ICE_AQC_CAPS_RSS: 204971d10453SEric Joyner caps->rss_table_size = number; 205071d10453SEric Joyner caps->rss_table_entry_width = logical_id; 20517d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_size = %d\n", prefix, 205271d10453SEric Joyner caps->rss_table_size); 20537d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: rss_table_entry_width = %d\n", prefix, 205471d10453SEric Joyner caps->rss_table_entry_width); 205571d10453SEric Joyner break; 205671d10453SEric Joyner case ICE_AQC_CAPS_RXQS: 205771d10453SEric Joyner caps->num_rxq = number; 205871d10453SEric Joyner caps->rxq_first_id = phys_id; 20597d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: num_rxq = %d\n", prefix, 206071d10453SEric Joyner caps->num_rxq); 20617d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: rxq_first_id = %d\n", prefix, 206271d10453SEric Joyner caps->rxq_first_id); 206371d10453SEric Joyner break; 206471d10453SEric Joyner case ICE_AQC_CAPS_TXQS: 206571d10453SEric Joyner caps->num_txq = number; 206671d10453SEric Joyner caps->txq_first_id = phys_id; 20677d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: num_txq = %d\n", prefix, 206871d10453SEric Joyner caps->num_txq); 20697d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: txq_first_id = %d\n", prefix, 207071d10453SEric Joyner caps->txq_first_id); 207171d10453SEric Joyner break; 207271d10453SEric Joyner case ICE_AQC_CAPS_MSIX: 207371d10453SEric Joyner caps->num_msix_vectors = number; 207471d10453SEric Joyner caps->msix_vector_first_id = phys_id; 20757d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, 207671d10453SEric Joyner caps->num_msix_vectors); 20777d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, 207871d10453SEric Joyner caps->msix_vector_first_id); 207971d10453SEric Joyner break; 208071d10453SEric Joyner case ICE_AQC_CAPS_NVM_VER: 208171d10453SEric Joyner break; 208271d10453SEric Joyner case ICE_AQC_CAPS_NVM_MGMT: 2083d08b8680SEric Joyner caps->sec_rev_disabled = 2084d08b8680SEric Joyner (number & ICE_NVM_MGMT_SEC_REV_DISABLED) ? 2085d08b8680SEric Joyner true : false; 2086d08b8680SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: sec_rev_disabled = %d\n", prefix, 2087d08b8680SEric Joyner caps->sec_rev_disabled); 2088d08b8680SEric Joyner caps->update_disabled = 2089d08b8680SEric Joyner (number & ICE_NVM_MGMT_UPDATE_DISABLED) ? 2090d08b8680SEric Joyner true : false; 2091d08b8680SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: update_disabled = %d\n", prefix, 2092d08b8680SEric Joyner caps->update_disabled); 209371d10453SEric Joyner caps->nvm_unified_update = 209471d10453SEric Joyner (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? 209571d10453SEric Joyner true : false; 20967d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, 209771d10453SEric Joyner caps->nvm_unified_update); 209871d10453SEric Joyner break; 209971d10453SEric Joyner case ICE_AQC_CAPS_CEM: 210071d10453SEric Joyner caps->mgmt_cem = (number == 1); 21017d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: mgmt_cem = %d\n", prefix, 210271d10453SEric Joyner caps->mgmt_cem); 210371d10453SEric Joyner break; 210471d10453SEric Joyner case ICE_AQC_CAPS_LED: 210571d10453SEric Joyner if (phys_id < ICE_MAX_SUPPORTED_GPIO_LED) { 210671d10453SEric Joyner caps->led[phys_id] = true; 210771d10453SEric Joyner caps->led_pin_num++; 21087d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: led[%d] = 1\n", prefix, phys_id); 210971d10453SEric Joyner } 211071d10453SEric Joyner break; 211171d10453SEric Joyner case ICE_AQC_CAPS_SDP: 211271d10453SEric Joyner if (phys_id < ICE_MAX_SUPPORTED_GPIO_SDP) { 211371d10453SEric Joyner caps->sdp[phys_id] = true; 211471d10453SEric Joyner caps->sdp_pin_num++; 21157d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: sdp[%d] = 1\n", prefix, phys_id); 211671d10453SEric Joyner } 211771d10453SEric Joyner break; 211871d10453SEric Joyner case ICE_AQC_CAPS_WR_CSR_PROT: 211971d10453SEric Joyner caps->wr_csr_prot = number; 212071d10453SEric Joyner caps->wr_csr_prot |= (u64)logical_id << 32; 21217d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: wr_csr_prot = 0x%llX\n", prefix, 212271d10453SEric Joyner (unsigned long long)caps->wr_csr_prot); 212371d10453SEric Joyner break; 212471d10453SEric Joyner case ICE_AQC_CAPS_WOL_PROXY: 212571d10453SEric Joyner caps->num_wol_proxy_fltr = number; 212671d10453SEric Joyner caps->wol_proxy_vsi_seid = logical_id; 212771d10453SEric Joyner caps->apm_wol_support = !!(phys_id & ICE_WOL_SUPPORT_M); 212871d10453SEric Joyner caps->acpi_prog_mthd = !!(phys_id & 212971d10453SEric Joyner ICE_ACPI_PROG_MTHD_M); 213071d10453SEric Joyner caps->proxy_support = !!(phys_id & ICE_PROXY_SUPPORT_M); 21317d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: num_wol_proxy_fltr = %d\n", prefix, 213271d10453SEric Joyner caps->num_wol_proxy_fltr); 21337d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: wol_proxy_vsi_seid = %d\n", prefix, 213471d10453SEric Joyner caps->wol_proxy_vsi_seid); 213571d10453SEric Joyner break; 213671d10453SEric Joyner case ICE_AQC_CAPS_MAX_MTU: 213771d10453SEric Joyner caps->max_mtu = number; 213871d10453SEric Joyner ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", 213971d10453SEric Joyner prefix, caps->max_mtu); 214071d10453SEric Joyner break; 214171d10453SEric Joyner default: 21427d7af7f8SEric Joyner /* Not one of the recognized common capabilities */ 21437d7af7f8SEric Joyner found = false; 214471d10453SEric Joyner } 214571d10453SEric Joyner 21467d7af7f8SEric Joyner return found; 21477d7af7f8SEric Joyner } 214871d10453SEric Joyner 21497d7af7f8SEric Joyner /** 21507d7af7f8SEric Joyner * ice_recalc_port_limited_caps - Recalculate port limited capabilities 21517d7af7f8SEric Joyner * @hw: pointer to the HW structure 21527d7af7f8SEric Joyner * @caps: pointer to capabilities structure to fix 21537d7af7f8SEric Joyner * 21547d7af7f8SEric Joyner * Re-calculate the capabilities that are dependent on the number of physical 21557d7af7f8SEric Joyner * ports; i.e. some features are not supported or function differently on 21567d7af7f8SEric Joyner * devices with more than 4 ports. 21577d7af7f8SEric Joyner */ 21587d7af7f8SEric Joyner static void 21597d7af7f8SEric Joyner ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps) 21607d7af7f8SEric Joyner { 21617d7af7f8SEric Joyner /* This assumes device capabilities are always scanned before function 21627d7af7f8SEric Joyner * capabilities during the initialization flow. 216371d10453SEric Joyner */ 216471d10453SEric Joyner if (hw->dev_caps.num_funcs > 4) { 216571d10453SEric Joyner /* Max 4 TCs per port */ 216671d10453SEric Joyner caps->maxtc = 4; 21677d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "reducing maxtc to %d (based on #ports)\n", 216871d10453SEric Joyner caps->maxtc); 216971d10453SEric Joyner } 217071d10453SEric Joyner } 217171d10453SEric Joyner 217271d10453SEric Joyner /** 21737d7af7f8SEric Joyner * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps 217471d10453SEric Joyner * @hw: pointer to the HW struct 21757d7af7f8SEric Joyner * @func_p: pointer to function capabilities structure 21767d7af7f8SEric Joyner * @cap: pointer to the capability element to parse 21777d7af7f8SEric Joyner * 21787d7af7f8SEric Joyner * Extract function capabilities for ICE_AQC_CAPS_VF. 21797d7af7f8SEric Joyner */ 21807d7af7f8SEric Joyner static void 21817d7af7f8SEric Joyner ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 21827d7af7f8SEric Joyner struct ice_aqc_list_caps_elem *cap) 21837d7af7f8SEric Joyner { 21847d7af7f8SEric Joyner u32 number = LE32_TO_CPU(cap->number); 21857d7af7f8SEric Joyner u32 logical_id = LE32_TO_CPU(cap->logical_id); 21867d7af7f8SEric Joyner 21877d7af7f8SEric Joyner func_p->num_allocd_vfs = number; 21887d7af7f8SEric Joyner func_p->vf_base_id = logical_id; 21897d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n", 21907d7af7f8SEric Joyner func_p->num_allocd_vfs); 21917d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n", 21927d7af7f8SEric Joyner func_p->vf_base_id); 21937d7af7f8SEric Joyner } 21947d7af7f8SEric Joyner 21957d7af7f8SEric Joyner /** 21967d7af7f8SEric Joyner * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps 21977d7af7f8SEric Joyner * @hw: pointer to the HW struct 21987d7af7f8SEric Joyner * @func_p: pointer to function capabilities structure 21997d7af7f8SEric Joyner * @cap: pointer to the capability element to parse 22007d7af7f8SEric Joyner * 22017d7af7f8SEric Joyner * Extract function capabilities for ICE_AQC_CAPS_VSI. 22027d7af7f8SEric Joyner */ 22037d7af7f8SEric Joyner static void 22047d7af7f8SEric Joyner ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 22057d7af7f8SEric Joyner struct ice_aqc_list_caps_elem *cap) 22067d7af7f8SEric Joyner { 22077d7af7f8SEric Joyner func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); 22087d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n", 22097d7af7f8SEric Joyner LE32_TO_CPU(cap->number)); 22107d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n", 22117d7af7f8SEric Joyner func_p->guar_num_vsi); 22127d7af7f8SEric Joyner } 22137d7af7f8SEric Joyner 22147d7af7f8SEric Joyner /** 22157d7af7f8SEric Joyner * ice_parse_func_caps - Parse function capabilities 22167d7af7f8SEric Joyner * @hw: pointer to the HW struct 22177d7af7f8SEric Joyner * @func_p: pointer to function capabilities structure 22187d7af7f8SEric Joyner * @buf: buffer containing the function capability records 22197d7af7f8SEric Joyner * @cap_count: the number of capabilities 22207d7af7f8SEric Joyner * 22217d7af7f8SEric Joyner * Helper function to parse function (0x000A) capabilities list. For 22227d7af7f8SEric Joyner * capabilities shared between device and function, this relies on 22237d7af7f8SEric Joyner * ice_parse_common_caps. 22247d7af7f8SEric Joyner * 22257d7af7f8SEric Joyner * Loop through the list of provided capabilities and extract the relevant 22267d7af7f8SEric Joyner * data into the function capabilities structured. 22277d7af7f8SEric Joyner */ 22287d7af7f8SEric Joyner static void 22297d7af7f8SEric Joyner ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p, 22307d7af7f8SEric Joyner void *buf, u32 cap_count) 22317d7af7f8SEric Joyner { 22327d7af7f8SEric Joyner struct ice_aqc_list_caps_elem *cap_resp; 22337d7af7f8SEric Joyner u32 i; 22347d7af7f8SEric Joyner 22357d7af7f8SEric Joyner cap_resp = (struct ice_aqc_list_caps_elem *)buf; 22367d7af7f8SEric Joyner 22377d7af7f8SEric Joyner ice_memset(func_p, 0, sizeof(*func_p), ICE_NONDMA_MEM); 22387d7af7f8SEric Joyner 22397d7af7f8SEric Joyner for (i = 0; i < cap_count; i++) { 22407d7af7f8SEric Joyner u16 cap = LE16_TO_CPU(cap_resp[i].cap); 22417d7af7f8SEric Joyner bool found; 22427d7af7f8SEric Joyner 22437d7af7f8SEric Joyner found = ice_parse_common_caps(hw, &func_p->common_cap, 22447d7af7f8SEric Joyner &cap_resp[i], "func caps"); 22457d7af7f8SEric Joyner 22467d7af7f8SEric Joyner switch (cap) { 22477d7af7f8SEric Joyner case ICE_AQC_CAPS_VF: 22487d7af7f8SEric Joyner ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]); 22497d7af7f8SEric Joyner break; 22507d7af7f8SEric Joyner case ICE_AQC_CAPS_VSI: 22517d7af7f8SEric Joyner ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]); 22527d7af7f8SEric Joyner break; 22537d7af7f8SEric Joyner default: 22547d7af7f8SEric Joyner /* Don't list common capabilities as unknown */ 22557d7af7f8SEric Joyner if (!found) 22567d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "func caps: unknown capability[%d]: 0x%x\n", 22577d7af7f8SEric Joyner i, cap); 22587d7af7f8SEric Joyner break; 22597d7af7f8SEric Joyner } 22607d7af7f8SEric Joyner } 22617d7af7f8SEric Joyner 22627d7af7f8SEric Joyner ice_print_led_caps(hw, &func_p->common_cap, "func caps", true); 22637d7af7f8SEric Joyner ice_print_sdp_caps(hw, &func_p->common_cap, "func caps", true); 22647d7af7f8SEric Joyner 22657d7af7f8SEric Joyner ice_recalc_port_limited_caps(hw, &func_p->common_cap); 22667d7af7f8SEric Joyner } 22677d7af7f8SEric Joyner 22687d7af7f8SEric Joyner /** 22697d7af7f8SEric Joyner * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps 22707d7af7f8SEric Joyner * @hw: pointer to the HW struct 22717d7af7f8SEric Joyner * @dev_p: pointer to device capabilities structure 22727d7af7f8SEric Joyner * @cap: capability element to parse 22737d7af7f8SEric Joyner * 22747d7af7f8SEric Joyner * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities. 22757d7af7f8SEric Joyner */ 22767d7af7f8SEric Joyner static void 22777d7af7f8SEric Joyner ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 22787d7af7f8SEric Joyner struct ice_aqc_list_caps_elem *cap) 22797d7af7f8SEric Joyner { 22807d7af7f8SEric Joyner u32 number = LE32_TO_CPU(cap->number); 22817d7af7f8SEric Joyner 22827d7af7f8SEric Joyner dev_p->num_funcs = ice_hweight32(number); 22837d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n", 22847d7af7f8SEric Joyner dev_p->num_funcs); 22857d7af7f8SEric Joyner } 22867d7af7f8SEric Joyner 22877d7af7f8SEric Joyner /** 22887d7af7f8SEric Joyner * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps 22897d7af7f8SEric Joyner * @hw: pointer to the HW struct 22907d7af7f8SEric Joyner * @dev_p: pointer to device capabilities structure 22917d7af7f8SEric Joyner * @cap: capability element to parse 22927d7af7f8SEric Joyner * 22937d7af7f8SEric Joyner * Parse ICE_AQC_CAPS_VF for device capabilities. 22947d7af7f8SEric Joyner */ 22957d7af7f8SEric Joyner static void 22967d7af7f8SEric Joyner ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 22977d7af7f8SEric Joyner struct ice_aqc_list_caps_elem *cap) 22987d7af7f8SEric Joyner { 22997d7af7f8SEric Joyner u32 number = LE32_TO_CPU(cap->number); 23007d7af7f8SEric Joyner 23017d7af7f8SEric Joyner dev_p->num_vfs_exposed = number; 23027d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n", 23037d7af7f8SEric Joyner dev_p->num_vfs_exposed); 23047d7af7f8SEric Joyner } 23057d7af7f8SEric Joyner 23067d7af7f8SEric Joyner /** 23077d7af7f8SEric Joyner * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps 23087d7af7f8SEric Joyner * @hw: pointer to the HW struct 23097d7af7f8SEric Joyner * @dev_p: pointer to device capabilities structure 23107d7af7f8SEric Joyner * @cap: capability element to parse 23117d7af7f8SEric Joyner * 23127d7af7f8SEric Joyner * Parse ICE_AQC_CAPS_VSI for device capabilities. 23137d7af7f8SEric Joyner */ 23147d7af7f8SEric Joyner static void 23157d7af7f8SEric Joyner ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 23167d7af7f8SEric Joyner struct ice_aqc_list_caps_elem *cap) 23177d7af7f8SEric Joyner { 23187d7af7f8SEric Joyner u32 number = LE32_TO_CPU(cap->number); 23197d7af7f8SEric Joyner 23207d7af7f8SEric Joyner dev_p->num_vsi_allocd_to_host = number; 23217d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n", 23227d7af7f8SEric Joyner dev_p->num_vsi_allocd_to_host); 23237d7af7f8SEric Joyner } 23247d7af7f8SEric Joyner 23257d7af7f8SEric Joyner /** 23267d7af7f8SEric Joyner * ice_parse_dev_caps - Parse device capabilities 23277d7af7f8SEric Joyner * @hw: pointer to the HW struct 23287d7af7f8SEric Joyner * @dev_p: pointer to device capabilities structure 23297d7af7f8SEric Joyner * @buf: buffer containing the device capability records 23307d7af7f8SEric Joyner * @cap_count: the number of capabilities 23317d7af7f8SEric Joyner * 23327d7af7f8SEric Joyner * Helper device to parse device (0x000B) capabilities list. For 23337d7af7f8SEric Joyner * capabilities shared between device and function, this relies on 23347d7af7f8SEric Joyner * ice_parse_common_caps. 23357d7af7f8SEric Joyner * 23367d7af7f8SEric Joyner * Loop through the list of provided capabilities and extract the relevant 23377d7af7f8SEric Joyner * data into the device capabilities structured. 23387d7af7f8SEric Joyner */ 23397d7af7f8SEric Joyner static void 23407d7af7f8SEric Joyner ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p, 23417d7af7f8SEric Joyner void *buf, u32 cap_count) 23427d7af7f8SEric Joyner { 23437d7af7f8SEric Joyner struct ice_aqc_list_caps_elem *cap_resp; 23447d7af7f8SEric Joyner u32 i; 23457d7af7f8SEric Joyner 23467d7af7f8SEric Joyner cap_resp = (struct ice_aqc_list_caps_elem *)buf; 23477d7af7f8SEric Joyner 23487d7af7f8SEric Joyner ice_memset(dev_p, 0, sizeof(*dev_p), ICE_NONDMA_MEM); 23497d7af7f8SEric Joyner 23507d7af7f8SEric Joyner for (i = 0; i < cap_count; i++) { 23517d7af7f8SEric Joyner u16 cap = LE16_TO_CPU(cap_resp[i].cap); 23527d7af7f8SEric Joyner bool found; 23537d7af7f8SEric Joyner 23547d7af7f8SEric Joyner found = ice_parse_common_caps(hw, &dev_p->common_cap, 23557d7af7f8SEric Joyner &cap_resp[i], "dev caps"); 23567d7af7f8SEric Joyner 23577d7af7f8SEric Joyner switch (cap) { 23587d7af7f8SEric Joyner case ICE_AQC_CAPS_VALID_FUNCTIONS: 23597d7af7f8SEric Joyner ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]); 23607d7af7f8SEric Joyner break; 23617d7af7f8SEric Joyner case ICE_AQC_CAPS_VF: 23627d7af7f8SEric Joyner ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]); 23637d7af7f8SEric Joyner break; 23647d7af7f8SEric Joyner case ICE_AQC_CAPS_VSI: 23657d7af7f8SEric Joyner ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]); 23667d7af7f8SEric Joyner break; 23677d7af7f8SEric Joyner default: 23687d7af7f8SEric Joyner /* Don't list common capabilities as unknown */ 23697d7af7f8SEric Joyner if (!found) 23707d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "dev caps: unknown capability[%d]: 0x%x\n", 23717d7af7f8SEric Joyner i, cap); 23727d7af7f8SEric Joyner break; 23737d7af7f8SEric Joyner } 23747d7af7f8SEric Joyner } 23757d7af7f8SEric Joyner 23767d7af7f8SEric Joyner ice_print_led_caps(hw, &dev_p->common_cap, "dev caps", true); 23777d7af7f8SEric Joyner ice_print_sdp_caps(hw, &dev_p->common_cap, "dev caps", true); 23787d7af7f8SEric Joyner 23797d7af7f8SEric Joyner ice_recalc_port_limited_caps(hw, &dev_p->common_cap); 23807d7af7f8SEric Joyner } 23817d7af7f8SEric Joyner 23827d7af7f8SEric Joyner /** 23837d7af7f8SEric Joyner * ice_aq_list_caps - query function/device capabilities 23847d7af7f8SEric Joyner * @hw: pointer to the HW struct 23857d7af7f8SEric Joyner * @buf: a buffer to hold the capabilities 23867d7af7f8SEric Joyner * @buf_size: size of the buffer 23877d7af7f8SEric Joyner * @cap_count: if not NULL, set to the number of capabilities reported 23887d7af7f8SEric Joyner * @opc: capabilities type to discover, device or function 238971d10453SEric Joyner * @cd: pointer to command details structure or NULL 239071d10453SEric Joyner * 23917d7af7f8SEric Joyner * Get the function (0x000A) or device (0x000B) capabilities description from 23927d7af7f8SEric Joyner * firmware and store it in the buffer. 23937d7af7f8SEric Joyner * 23947d7af7f8SEric Joyner * If the cap_count pointer is not NULL, then it is set to the number of 23957d7af7f8SEric Joyner * capabilities firmware will report. Note that if the buffer size is too 23967d7af7f8SEric Joyner * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The 23977d7af7f8SEric Joyner * cap_count will still be updated in this case. It is recommended that the 23987d7af7f8SEric Joyner * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that 23997d7af7f8SEric Joyner * firmware could return) to avoid this. 240071d10453SEric Joyner */ 24017d7af7f8SEric Joyner static enum ice_status 24027d7af7f8SEric Joyner ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count, 240371d10453SEric Joyner enum ice_adminq_opc opc, struct ice_sq_cd *cd) 240471d10453SEric Joyner { 240571d10453SEric Joyner struct ice_aqc_list_caps *cmd; 240671d10453SEric Joyner struct ice_aq_desc desc; 240771d10453SEric Joyner enum ice_status status; 240871d10453SEric Joyner 240971d10453SEric Joyner cmd = &desc.params.get_cap; 241071d10453SEric Joyner 241171d10453SEric Joyner if (opc != ice_aqc_opc_list_func_caps && 241271d10453SEric Joyner opc != ice_aqc_opc_list_dev_caps) 241371d10453SEric Joyner return ICE_ERR_PARAM; 241471d10453SEric Joyner 241571d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, opc); 241671d10453SEric Joyner status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 24177d7af7f8SEric Joyner 24187d7af7f8SEric Joyner if (cap_count) 241971d10453SEric Joyner *cap_count = LE32_TO_CPU(cmd->count); 24207d7af7f8SEric Joyner 242171d10453SEric Joyner return status; 242271d10453SEric Joyner } 242371d10453SEric Joyner 242471d10453SEric Joyner /** 24257d7af7f8SEric Joyner * ice_discover_dev_caps - Read and extract device capabilities 242671d10453SEric Joyner * @hw: pointer to the hardware structure 24277d7af7f8SEric Joyner * @dev_caps: pointer to device capabilities structure 24287d7af7f8SEric Joyner * 24297d7af7f8SEric Joyner * Read the device capabilities and extract them into the dev_caps structure 24307d7af7f8SEric Joyner * for later use. 243171d10453SEric Joyner */ 243271d10453SEric Joyner static enum ice_status 24337d7af7f8SEric Joyner ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps) 243471d10453SEric Joyner { 243571d10453SEric Joyner enum ice_status status; 24367d7af7f8SEric Joyner u32 cap_count = 0; 243771d10453SEric Joyner void *cbuf; 243871d10453SEric Joyner 24397d7af7f8SEric Joyner cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN); 244071d10453SEric Joyner if (!cbuf) 244171d10453SEric Joyner return ICE_ERR_NO_MEMORY; 244271d10453SEric Joyner 24437d7af7f8SEric Joyner /* Although the driver doesn't know the number of capabilities the 24447d7af7f8SEric Joyner * device will return, we can simply send a 4KB buffer, the maximum 24457d7af7f8SEric Joyner * possible size that firmware can return. 24467d7af7f8SEric Joyner */ 24477d7af7f8SEric Joyner cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 24487d7af7f8SEric Joyner 24497d7af7f8SEric Joyner status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 24507d7af7f8SEric Joyner ice_aqc_opc_list_dev_caps, NULL); 24517d7af7f8SEric Joyner if (!status) 24527d7af7f8SEric Joyner ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count); 245371d10453SEric Joyner ice_free(hw, cbuf); 245471d10453SEric Joyner 24557d7af7f8SEric Joyner return status; 24567d7af7f8SEric Joyner } 245771d10453SEric Joyner 24587d7af7f8SEric Joyner /** 24597d7af7f8SEric Joyner * ice_discover_func_caps - Read and extract function capabilities 24607d7af7f8SEric Joyner * @hw: pointer to the hardware structure 24617d7af7f8SEric Joyner * @func_caps: pointer to function capabilities structure 24627d7af7f8SEric Joyner * 24637d7af7f8SEric Joyner * Read the function capabilities and extract them into the func_caps structure 24647d7af7f8SEric Joyner * for later use. 24657d7af7f8SEric Joyner */ 24667d7af7f8SEric Joyner static enum ice_status 24677d7af7f8SEric Joyner ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps) 24687d7af7f8SEric Joyner { 24697d7af7f8SEric Joyner enum ice_status status; 24707d7af7f8SEric Joyner u32 cap_count = 0; 24717d7af7f8SEric Joyner void *cbuf; 24727d7af7f8SEric Joyner 24737d7af7f8SEric Joyner cbuf = ice_malloc(hw, ICE_AQ_MAX_BUF_LEN); 24747d7af7f8SEric Joyner if (!cbuf) 24757d7af7f8SEric Joyner return ICE_ERR_NO_MEMORY; 24767d7af7f8SEric Joyner 24777d7af7f8SEric Joyner /* Although the driver doesn't know the number of capabilities the 24787d7af7f8SEric Joyner * device will return, we can simply send a 4KB buffer, the maximum 24797d7af7f8SEric Joyner * possible size that firmware can return. 24807d7af7f8SEric Joyner */ 24817d7af7f8SEric Joyner cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem); 24827d7af7f8SEric Joyner 24837d7af7f8SEric Joyner status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count, 24847d7af7f8SEric Joyner ice_aqc_opc_list_func_caps, NULL); 24857d7af7f8SEric Joyner if (!status) 24867d7af7f8SEric Joyner ice_parse_func_caps(hw, func_caps, cbuf, cap_count); 24877d7af7f8SEric Joyner ice_free(hw, cbuf); 248871d10453SEric Joyner 248971d10453SEric Joyner return status; 249071d10453SEric Joyner } 249171d10453SEric Joyner 249271d10453SEric Joyner /** 249371d10453SEric Joyner * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode 249471d10453SEric Joyner * @hw: pointer to the hardware structure 249571d10453SEric Joyner */ 249671d10453SEric Joyner void ice_set_safe_mode_caps(struct ice_hw *hw) 249771d10453SEric Joyner { 249871d10453SEric Joyner struct ice_hw_func_caps *func_caps = &hw->func_caps; 249971d10453SEric Joyner struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; 2500d08b8680SEric Joyner struct ice_hw_common_caps cached_caps; 250171d10453SEric Joyner u32 num_funcs; 250271d10453SEric Joyner 250371d10453SEric Joyner /* cache some func_caps values that should be restored after memset */ 2504d08b8680SEric Joyner cached_caps = func_caps->common_cap; 250571d10453SEric Joyner 250671d10453SEric Joyner /* unset func capabilities */ 250771d10453SEric Joyner memset(func_caps, 0, sizeof(*func_caps)); 250871d10453SEric Joyner 2509d08b8680SEric Joyner #define ICE_RESTORE_FUNC_CAP(name) \ 2510d08b8680SEric Joyner func_caps->common_cap.name = cached_caps.name 2511d08b8680SEric Joyner 251271d10453SEric Joyner /* restore cached values */ 2513d08b8680SEric Joyner ICE_RESTORE_FUNC_CAP(valid_functions); 2514d08b8680SEric Joyner ICE_RESTORE_FUNC_CAP(txq_first_id); 2515d08b8680SEric Joyner ICE_RESTORE_FUNC_CAP(rxq_first_id); 2516d08b8680SEric Joyner ICE_RESTORE_FUNC_CAP(msix_vector_first_id); 2517d08b8680SEric Joyner ICE_RESTORE_FUNC_CAP(max_mtu); 2518d08b8680SEric Joyner ICE_RESTORE_FUNC_CAP(nvm_unified_update); 251971d10453SEric Joyner 252071d10453SEric Joyner /* one Tx and one Rx queue in safe mode */ 252171d10453SEric Joyner func_caps->common_cap.num_rxq = 1; 252271d10453SEric Joyner func_caps->common_cap.num_txq = 1; 252371d10453SEric Joyner 252471d10453SEric Joyner /* two MSIX vectors, one for traffic and one for misc causes */ 252571d10453SEric Joyner func_caps->common_cap.num_msix_vectors = 2; 252671d10453SEric Joyner func_caps->guar_num_vsi = 1; 252771d10453SEric Joyner 252871d10453SEric Joyner /* cache some dev_caps values that should be restored after memset */ 2529d08b8680SEric Joyner cached_caps = dev_caps->common_cap; 253071d10453SEric Joyner num_funcs = dev_caps->num_funcs; 253171d10453SEric Joyner 253271d10453SEric Joyner /* unset dev capabilities */ 253371d10453SEric Joyner memset(dev_caps, 0, sizeof(*dev_caps)); 253471d10453SEric Joyner 2535d08b8680SEric Joyner #define ICE_RESTORE_DEV_CAP(name) \ 2536d08b8680SEric Joyner dev_caps->common_cap.name = cached_caps.name 2537d08b8680SEric Joyner 253871d10453SEric Joyner /* restore cached values */ 2539d08b8680SEric Joyner ICE_RESTORE_DEV_CAP(valid_functions); 2540d08b8680SEric Joyner ICE_RESTORE_DEV_CAP(txq_first_id); 2541d08b8680SEric Joyner ICE_RESTORE_DEV_CAP(rxq_first_id); 2542d08b8680SEric Joyner ICE_RESTORE_DEV_CAP(msix_vector_first_id); 2543d08b8680SEric Joyner ICE_RESTORE_DEV_CAP(max_mtu); 2544d08b8680SEric Joyner ICE_RESTORE_DEV_CAP(nvm_unified_update); 254571d10453SEric Joyner dev_caps->num_funcs = num_funcs; 254671d10453SEric Joyner 254771d10453SEric Joyner /* one Tx and one Rx queue per function in safe mode */ 254871d10453SEric Joyner dev_caps->common_cap.num_rxq = num_funcs; 254971d10453SEric Joyner dev_caps->common_cap.num_txq = num_funcs; 255071d10453SEric Joyner 255171d10453SEric Joyner /* two MSIX vectors per function */ 255271d10453SEric Joyner dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; 255371d10453SEric Joyner } 255471d10453SEric Joyner 255571d10453SEric Joyner /** 255671d10453SEric Joyner * ice_get_caps - get info about the HW 255771d10453SEric Joyner * @hw: pointer to the hardware structure 255871d10453SEric Joyner */ 255971d10453SEric Joyner enum ice_status ice_get_caps(struct ice_hw *hw) 256071d10453SEric Joyner { 256171d10453SEric Joyner enum ice_status status; 256271d10453SEric Joyner 25637d7af7f8SEric Joyner status = ice_discover_dev_caps(hw, &hw->dev_caps); 25647d7af7f8SEric Joyner if (status) 256571d10453SEric Joyner return status; 25667d7af7f8SEric Joyner 25677d7af7f8SEric Joyner return ice_discover_func_caps(hw, &hw->func_caps); 256871d10453SEric Joyner } 256971d10453SEric Joyner 257071d10453SEric Joyner /** 257171d10453SEric Joyner * ice_aq_manage_mac_write - manage MAC address write command 257271d10453SEric Joyner * @hw: pointer to the HW struct 257371d10453SEric Joyner * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address 257471d10453SEric Joyner * @flags: flags to control write behavior 257571d10453SEric Joyner * @cd: pointer to command details structure or NULL 257671d10453SEric Joyner * 257771d10453SEric Joyner * This function is used to write MAC address to the NVM (0x0108). 257871d10453SEric Joyner */ 257971d10453SEric Joyner enum ice_status 258071d10453SEric Joyner ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags, 258171d10453SEric Joyner struct ice_sq_cd *cd) 258271d10453SEric Joyner { 258371d10453SEric Joyner struct ice_aqc_manage_mac_write *cmd; 258471d10453SEric Joyner struct ice_aq_desc desc; 258571d10453SEric Joyner 258671d10453SEric Joyner cmd = &desc.params.mac_write; 258771d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); 258871d10453SEric Joyner 258971d10453SEric Joyner cmd->flags = flags; 2590d08b8680SEric Joyner ice_memcpy(cmd->mac_addr, mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); 259171d10453SEric Joyner 259271d10453SEric Joyner return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 259371d10453SEric Joyner } 259471d10453SEric Joyner 259571d10453SEric Joyner /** 259671d10453SEric Joyner * ice_aq_clear_pxe_mode 259771d10453SEric Joyner * @hw: pointer to the HW struct 259871d10453SEric Joyner * 259971d10453SEric Joyner * Tell the firmware that the driver is taking over from PXE (0x0110). 260071d10453SEric Joyner */ 260171d10453SEric Joyner static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw) 260271d10453SEric Joyner { 260371d10453SEric Joyner struct ice_aq_desc desc; 260471d10453SEric Joyner 260571d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode); 260671d10453SEric Joyner desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT; 260771d10453SEric Joyner 260871d10453SEric Joyner return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 260971d10453SEric Joyner } 261071d10453SEric Joyner 261171d10453SEric Joyner /** 261271d10453SEric Joyner * ice_clear_pxe_mode - clear pxe operations mode 261371d10453SEric Joyner * @hw: pointer to the HW struct 261471d10453SEric Joyner * 261571d10453SEric Joyner * Make sure all PXE mode settings are cleared, including things 261671d10453SEric Joyner * like descriptor fetch/write-back mode. 261771d10453SEric Joyner */ 261871d10453SEric Joyner void ice_clear_pxe_mode(struct ice_hw *hw) 261971d10453SEric Joyner { 262071d10453SEric Joyner if (ice_check_sq_alive(hw, &hw->adminq)) 262171d10453SEric Joyner ice_aq_clear_pxe_mode(hw); 262271d10453SEric Joyner } 262371d10453SEric Joyner 262471d10453SEric Joyner /** 262571d10453SEric Joyner * ice_aq_set_port_params - set physical port parameters. 262671d10453SEric Joyner * @pi: pointer to the port info struct 262771d10453SEric Joyner * @bad_frame_vsi: defines the VSI to which bad frames are forwarded 262871d10453SEric Joyner * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI 262971d10453SEric Joyner * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded 263071d10453SEric Joyner * @double_vlan: if set double VLAN is enabled 263171d10453SEric Joyner * @cd: pointer to command details structure or NULL 263271d10453SEric Joyner * 263371d10453SEric Joyner * Set Physical port parameters (0x0203) 263471d10453SEric Joyner */ 263571d10453SEric Joyner enum ice_status 263671d10453SEric Joyner ice_aq_set_port_params(struct ice_port_info *pi, u16 bad_frame_vsi, 263771d10453SEric Joyner bool save_bad_pac, bool pad_short_pac, bool double_vlan, 263871d10453SEric Joyner struct ice_sq_cd *cd) 263971d10453SEric Joyner 264071d10453SEric Joyner { 264171d10453SEric Joyner struct ice_aqc_set_port_params *cmd; 264271d10453SEric Joyner struct ice_hw *hw = pi->hw; 264371d10453SEric Joyner struct ice_aq_desc desc; 264471d10453SEric Joyner u16 cmd_flags = 0; 264571d10453SEric Joyner 264671d10453SEric Joyner cmd = &desc.params.set_port_params; 264771d10453SEric Joyner 264871d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_params); 264971d10453SEric Joyner cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi); 265071d10453SEric Joyner if (save_bad_pac) 265171d10453SEric Joyner cmd_flags |= ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS; 265271d10453SEric Joyner if (pad_short_pac) 265371d10453SEric Joyner cmd_flags |= ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS; 265471d10453SEric Joyner if (double_vlan) 265571d10453SEric Joyner cmd_flags |= ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA; 265671d10453SEric Joyner cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 265771d10453SEric Joyner 265871d10453SEric Joyner return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 265971d10453SEric Joyner } 266071d10453SEric Joyner 266171d10453SEric Joyner /** 266271d10453SEric Joyner * ice_get_link_speed_based_on_phy_type - returns link speed 266371d10453SEric Joyner * @phy_type_low: lower part of phy_type 266471d10453SEric Joyner * @phy_type_high: higher part of phy_type 266571d10453SEric Joyner * 266671d10453SEric Joyner * This helper function will convert an entry in PHY type structure 266771d10453SEric Joyner * [phy_type_low, phy_type_high] to its corresponding link speed. 266871d10453SEric Joyner * Note: In the structure of [phy_type_low, phy_type_high], there should 266971d10453SEric Joyner * be one bit set, as this function will convert one PHY type to its 267071d10453SEric Joyner * speed. 267171d10453SEric Joyner * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 267271d10453SEric Joyner * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned 267371d10453SEric Joyner */ 267471d10453SEric Joyner static u16 267571d10453SEric Joyner ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high) 267671d10453SEric Joyner { 267771d10453SEric Joyner u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 267871d10453SEric Joyner u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 267971d10453SEric Joyner 268071d10453SEric Joyner switch (phy_type_low) { 268171d10453SEric Joyner case ICE_PHY_TYPE_LOW_100BASE_TX: 268271d10453SEric Joyner case ICE_PHY_TYPE_LOW_100M_SGMII: 268371d10453SEric Joyner speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB; 268471d10453SEric Joyner break; 268571d10453SEric Joyner case ICE_PHY_TYPE_LOW_1000BASE_T: 268671d10453SEric Joyner case ICE_PHY_TYPE_LOW_1000BASE_SX: 268771d10453SEric Joyner case ICE_PHY_TYPE_LOW_1000BASE_LX: 268871d10453SEric Joyner case ICE_PHY_TYPE_LOW_1000BASE_KX: 268971d10453SEric Joyner case ICE_PHY_TYPE_LOW_1G_SGMII: 269071d10453SEric Joyner speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB; 269171d10453SEric Joyner break; 269271d10453SEric Joyner case ICE_PHY_TYPE_LOW_2500BASE_T: 269371d10453SEric Joyner case ICE_PHY_TYPE_LOW_2500BASE_X: 269471d10453SEric Joyner case ICE_PHY_TYPE_LOW_2500BASE_KX: 269571d10453SEric Joyner speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB; 269671d10453SEric Joyner break; 269771d10453SEric Joyner case ICE_PHY_TYPE_LOW_5GBASE_T: 269871d10453SEric Joyner case ICE_PHY_TYPE_LOW_5GBASE_KR: 269971d10453SEric Joyner speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB; 270071d10453SEric Joyner break; 270171d10453SEric Joyner case ICE_PHY_TYPE_LOW_10GBASE_T: 270271d10453SEric Joyner case ICE_PHY_TYPE_LOW_10G_SFI_DA: 270371d10453SEric Joyner case ICE_PHY_TYPE_LOW_10GBASE_SR: 270471d10453SEric Joyner case ICE_PHY_TYPE_LOW_10GBASE_LR: 270571d10453SEric Joyner case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1: 270671d10453SEric Joyner case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC: 270771d10453SEric Joyner case ICE_PHY_TYPE_LOW_10G_SFI_C2C: 270871d10453SEric Joyner speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB; 270971d10453SEric Joyner break; 271071d10453SEric Joyner case ICE_PHY_TYPE_LOW_25GBASE_T: 271171d10453SEric Joyner case ICE_PHY_TYPE_LOW_25GBASE_CR: 271271d10453SEric Joyner case ICE_PHY_TYPE_LOW_25GBASE_CR_S: 271371d10453SEric Joyner case ICE_PHY_TYPE_LOW_25GBASE_CR1: 271471d10453SEric Joyner case ICE_PHY_TYPE_LOW_25GBASE_SR: 271571d10453SEric Joyner case ICE_PHY_TYPE_LOW_25GBASE_LR: 271671d10453SEric Joyner case ICE_PHY_TYPE_LOW_25GBASE_KR: 271771d10453SEric Joyner case ICE_PHY_TYPE_LOW_25GBASE_KR_S: 271871d10453SEric Joyner case ICE_PHY_TYPE_LOW_25GBASE_KR1: 271971d10453SEric Joyner case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC: 272071d10453SEric Joyner case ICE_PHY_TYPE_LOW_25G_AUI_C2C: 272171d10453SEric Joyner speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB; 272271d10453SEric Joyner break; 272371d10453SEric Joyner case ICE_PHY_TYPE_LOW_40GBASE_CR4: 272471d10453SEric Joyner case ICE_PHY_TYPE_LOW_40GBASE_SR4: 272571d10453SEric Joyner case ICE_PHY_TYPE_LOW_40GBASE_LR4: 272671d10453SEric Joyner case ICE_PHY_TYPE_LOW_40GBASE_KR4: 272771d10453SEric Joyner case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC: 272871d10453SEric Joyner case ICE_PHY_TYPE_LOW_40G_XLAUI: 272971d10453SEric Joyner speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB; 273071d10453SEric Joyner break; 273171d10453SEric Joyner case ICE_PHY_TYPE_LOW_50GBASE_CR2: 273271d10453SEric Joyner case ICE_PHY_TYPE_LOW_50GBASE_SR2: 273371d10453SEric Joyner case ICE_PHY_TYPE_LOW_50GBASE_LR2: 273471d10453SEric Joyner case ICE_PHY_TYPE_LOW_50GBASE_KR2: 273571d10453SEric Joyner case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC: 273671d10453SEric Joyner case ICE_PHY_TYPE_LOW_50G_LAUI2: 273771d10453SEric Joyner case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC: 273871d10453SEric Joyner case ICE_PHY_TYPE_LOW_50G_AUI2: 273971d10453SEric Joyner case ICE_PHY_TYPE_LOW_50GBASE_CP: 274071d10453SEric Joyner case ICE_PHY_TYPE_LOW_50GBASE_SR: 274171d10453SEric Joyner case ICE_PHY_TYPE_LOW_50GBASE_FR: 274271d10453SEric Joyner case ICE_PHY_TYPE_LOW_50GBASE_LR: 274371d10453SEric Joyner case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 274471d10453SEric Joyner case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 274571d10453SEric Joyner case ICE_PHY_TYPE_LOW_50G_AUI1: 274671d10453SEric Joyner speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB; 274771d10453SEric Joyner break; 274871d10453SEric Joyner case ICE_PHY_TYPE_LOW_100GBASE_CR4: 274971d10453SEric Joyner case ICE_PHY_TYPE_LOW_100GBASE_SR4: 275071d10453SEric Joyner case ICE_PHY_TYPE_LOW_100GBASE_LR4: 275171d10453SEric Joyner case ICE_PHY_TYPE_LOW_100GBASE_KR4: 275271d10453SEric Joyner case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC: 275371d10453SEric Joyner case ICE_PHY_TYPE_LOW_100G_CAUI4: 275471d10453SEric Joyner case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC: 275571d10453SEric Joyner case ICE_PHY_TYPE_LOW_100G_AUI4: 275671d10453SEric Joyner case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4: 275771d10453SEric Joyner case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4: 275871d10453SEric Joyner case ICE_PHY_TYPE_LOW_100GBASE_CP2: 275971d10453SEric Joyner case ICE_PHY_TYPE_LOW_100GBASE_SR2: 276071d10453SEric Joyner case ICE_PHY_TYPE_LOW_100GBASE_DR: 276171d10453SEric Joyner speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB; 276271d10453SEric Joyner break; 276371d10453SEric Joyner default: 276471d10453SEric Joyner speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN; 276571d10453SEric Joyner break; 276671d10453SEric Joyner } 276771d10453SEric Joyner 276871d10453SEric Joyner switch (phy_type_high) { 276971d10453SEric Joyner case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4: 277071d10453SEric Joyner case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC: 277171d10453SEric Joyner case ICE_PHY_TYPE_HIGH_100G_CAUI2: 277271d10453SEric Joyner case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC: 277371d10453SEric Joyner case ICE_PHY_TYPE_HIGH_100G_AUI2: 277471d10453SEric Joyner speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB; 277571d10453SEric Joyner break; 277671d10453SEric Joyner default: 277771d10453SEric Joyner speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN; 277871d10453SEric Joyner break; 277971d10453SEric Joyner } 278071d10453SEric Joyner 278171d10453SEric Joyner if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN && 278271d10453SEric Joyner speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 278371d10453SEric Joyner return ICE_AQ_LINK_SPEED_UNKNOWN; 278471d10453SEric Joyner else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 278571d10453SEric Joyner speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN) 278671d10453SEric Joyner return ICE_AQ_LINK_SPEED_UNKNOWN; 278771d10453SEric Joyner else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN && 278871d10453SEric Joyner speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN) 278971d10453SEric Joyner return speed_phy_type_low; 279071d10453SEric Joyner else 279171d10453SEric Joyner return speed_phy_type_high; 279271d10453SEric Joyner } 279371d10453SEric Joyner 279471d10453SEric Joyner /** 279571d10453SEric Joyner * ice_update_phy_type 279671d10453SEric Joyner * @phy_type_low: pointer to the lower part of phy_type 279771d10453SEric Joyner * @phy_type_high: pointer to the higher part of phy_type 279871d10453SEric Joyner * @link_speeds_bitmap: targeted link speeds bitmap 279971d10453SEric Joyner * 280071d10453SEric Joyner * Note: For the link_speeds_bitmap structure, you can check it at 280171d10453SEric Joyner * [ice_aqc_get_link_status->link_speed]. Caller can pass in 280271d10453SEric Joyner * link_speeds_bitmap include multiple speeds. 280371d10453SEric Joyner * 280471d10453SEric Joyner * Each entry in this [phy_type_low, phy_type_high] structure will 280571d10453SEric Joyner * present a certain link speed. This helper function will turn on bits 280671d10453SEric Joyner * in [phy_type_low, phy_type_high] structure based on the value of 280771d10453SEric Joyner * link_speeds_bitmap input parameter. 280871d10453SEric Joyner */ 280971d10453SEric Joyner void 281071d10453SEric Joyner ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high, 281171d10453SEric Joyner u16 link_speeds_bitmap) 281271d10453SEric Joyner { 281371d10453SEric Joyner u64 pt_high; 281471d10453SEric Joyner u64 pt_low; 281571d10453SEric Joyner int index; 281671d10453SEric Joyner u16 speed; 281771d10453SEric Joyner 281871d10453SEric Joyner /* We first check with low part of phy_type */ 281971d10453SEric Joyner for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) { 282071d10453SEric Joyner pt_low = BIT_ULL(index); 282171d10453SEric Joyner speed = ice_get_link_speed_based_on_phy_type(pt_low, 0); 282271d10453SEric Joyner 282371d10453SEric Joyner if (link_speeds_bitmap & speed) 282471d10453SEric Joyner *phy_type_low |= BIT_ULL(index); 282571d10453SEric Joyner } 282671d10453SEric Joyner 282771d10453SEric Joyner /* We then check with high part of phy_type */ 282871d10453SEric Joyner for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) { 282971d10453SEric Joyner pt_high = BIT_ULL(index); 283071d10453SEric Joyner speed = ice_get_link_speed_based_on_phy_type(0, pt_high); 283171d10453SEric Joyner 283271d10453SEric Joyner if (link_speeds_bitmap & speed) 283371d10453SEric Joyner *phy_type_high |= BIT_ULL(index); 283471d10453SEric Joyner } 283571d10453SEric Joyner } 283671d10453SEric Joyner 283771d10453SEric Joyner /** 283871d10453SEric Joyner * ice_aq_set_phy_cfg 283971d10453SEric Joyner * @hw: pointer to the HW struct 284071d10453SEric Joyner * @pi: port info structure of the interested logical port 284171d10453SEric Joyner * @cfg: structure with PHY configuration data to be set 284271d10453SEric Joyner * @cd: pointer to command details structure or NULL 284371d10453SEric Joyner * 284471d10453SEric Joyner * Set the various PHY configuration parameters supported on the Port. 284571d10453SEric Joyner * One or more of the Set PHY config parameters may be ignored in an MFP 284671d10453SEric Joyner * mode as the PF may not have the privilege to set some of the PHY Config 284771d10453SEric Joyner * parameters. This status will be indicated by the command response (0x0601). 284871d10453SEric Joyner */ 284971d10453SEric Joyner enum ice_status 285071d10453SEric Joyner ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi, 285171d10453SEric Joyner struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd) 285271d10453SEric Joyner { 285371d10453SEric Joyner struct ice_aq_desc desc; 285471d10453SEric Joyner enum ice_status status; 285571d10453SEric Joyner 285671d10453SEric Joyner if (!cfg) 285771d10453SEric Joyner return ICE_ERR_PARAM; 285871d10453SEric Joyner 285971d10453SEric Joyner /* Ensure that only valid bits of cfg->caps can be turned on. */ 286071d10453SEric Joyner if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { 28617d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", 286271d10453SEric Joyner cfg->caps); 286371d10453SEric Joyner 286471d10453SEric Joyner cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; 286571d10453SEric Joyner } 286671d10453SEric Joyner 286771d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg); 286871d10453SEric Joyner desc.params.set_phy.lport_num = pi->lport; 286971d10453SEric Joyner desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 287071d10453SEric Joyner 28717d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n"); 287271d10453SEric Joyner ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", 287371d10453SEric Joyner (unsigned long long)LE64_TO_CPU(cfg->phy_type_low)); 287471d10453SEric Joyner ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", 287571d10453SEric Joyner (unsigned long long)LE64_TO_CPU(cfg->phy_type_high)); 287671d10453SEric Joyner ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); 287771d10453SEric Joyner ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", 287871d10453SEric Joyner cfg->low_power_ctrl_an); 287971d10453SEric Joyner ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); 288071d10453SEric Joyner ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); 28817d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n", 28827d7af7f8SEric Joyner cfg->link_fec_opt); 288371d10453SEric Joyner 288471d10453SEric Joyner status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd); 288571d10453SEric Joyner 28867d7af7f8SEric Joyner if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) 28877d7af7f8SEric Joyner status = ICE_SUCCESS; 28887d7af7f8SEric Joyner 288971d10453SEric Joyner if (!status) 289071d10453SEric Joyner pi->phy.curr_user_phy_cfg = *cfg; 289171d10453SEric Joyner 289271d10453SEric Joyner return status; 289371d10453SEric Joyner } 289471d10453SEric Joyner 289571d10453SEric Joyner /** 289671d10453SEric Joyner * ice_update_link_info - update status of the HW network link 289771d10453SEric Joyner * @pi: port info structure of the interested logical port 289871d10453SEric Joyner */ 289971d10453SEric Joyner enum ice_status ice_update_link_info(struct ice_port_info *pi) 290071d10453SEric Joyner { 290171d10453SEric Joyner struct ice_link_status *li; 290271d10453SEric Joyner enum ice_status status; 290371d10453SEric Joyner 290471d10453SEric Joyner if (!pi) 290571d10453SEric Joyner return ICE_ERR_PARAM; 290671d10453SEric Joyner 290771d10453SEric Joyner li = &pi->phy.link_info; 290871d10453SEric Joyner 290971d10453SEric Joyner status = ice_aq_get_link_info(pi, true, NULL, NULL); 291071d10453SEric Joyner if (status) 291171d10453SEric Joyner return status; 291271d10453SEric Joyner 291371d10453SEric Joyner if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { 291471d10453SEric Joyner struct ice_aqc_get_phy_caps_data *pcaps; 291571d10453SEric Joyner struct ice_hw *hw; 291671d10453SEric Joyner 291771d10453SEric Joyner hw = pi->hw; 291871d10453SEric Joyner pcaps = (struct ice_aqc_get_phy_caps_data *) 291971d10453SEric Joyner ice_malloc(hw, sizeof(*pcaps)); 292071d10453SEric Joyner if (!pcaps) 292171d10453SEric Joyner return ICE_ERR_NO_MEMORY; 292271d10453SEric Joyner 2923*9cf1841cSEric Joyner status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 292471d10453SEric Joyner pcaps, NULL); 292571d10453SEric Joyner 2926d08b8680SEric Joyner if (status == ICE_SUCCESS) 2927d08b8680SEric Joyner ice_memcpy(li->module_type, &pcaps->module_type, 2928d08b8680SEric Joyner sizeof(li->module_type), 2929d08b8680SEric Joyner ICE_NONDMA_TO_NONDMA); 2930d08b8680SEric Joyner 293171d10453SEric Joyner ice_free(hw, pcaps); 293271d10453SEric Joyner } 293371d10453SEric Joyner 293471d10453SEric Joyner return status; 293571d10453SEric Joyner } 293671d10453SEric Joyner 293771d10453SEric Joyner /** 293871d10453SEric Joyner * ice_cache_phy_user_req 293971d10453SEric Joyner * @pi: port information structure 294071d10453SEric Joyner * @cache_data: PHY logging data 294171d10453SEric Joyner * @cache_mode: PHY logging mode 294271d10453SEric Joyner * 294371d10453SEric Joyner * Log the user request on (FC, FEC, SPEED) for later user. 294471d10453SEric Joyner */ 294571d10453SEric Joyner static void 294671d10453SEric Joyner ice_cache_phy_user_req(struct ice_port_info *pi, 294771d10453SEric Joyner struct ice_phy_cache_mode_data cache_data, 294871d10453SEric Joyner enum ice_phy_cache_mode cache_mode) 294971d10453SEric Joyner { 295071d10453SEric Joyner if (!pi) 295171d10453SEric Joyner return; 295271d10453SEric Joyner 295371d10453SEric Joyner switch (cache_mode) { 295471d10453SEric Joyner case ICE_FC_MODE: 295571d10453SEric Joyner pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; 295671d10453SEric Joyner break; 295771d10453SEric Joyner case ICE_SPEED_MODE: 295871d10453SEric Joyner pi->phy.curr_user_speed_req = 295971d10453SEric Joyner cache_data.data.curr_user_speed_req; 296071d10453SEric Joyner break; 296171d10453SEric Joyner case ICE_FEC_MODE: 296271d10453SEric Joyner pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; 296371d10453SEric Joyner break; 296471d10453SEric Joyner default: 296571d10453SEric Joyner break; 296671d10453SEric Joyner } 296771d10453SEric Joyner } 296871d10453SEric Joyner 296971d10453SEric Joyner /** 297071d10453SEric Joyner * ice_caps_to_fc_mode 297171d10453SEric Joyner * @caps: PHY capabilities 297271d10453SEric Joyner * 297371d10453SEric Joyner * Convert PHY FC capabilities to ice FC mode 297471d10453SEric Joyner */ 297571d10453SEric Joyner enum ice_fc_mode ice_caps_to_fc_mode(u8 caps) 297671d10453SEric Joyner { 297771d10453SEric Joyner if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE && 297871d10453SEric Joyner caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 297971d10453SEric Joyner return ICE_FC_FULL; 298071d10453SEric Joyner 298171d10453SEric Joyner if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE) 298271d10453SEric Joyner return ICE_FC_TX_PAUSE; 298371d10453SEric Joyner 298471d10453SEric Joyner if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE) 298571d10453SEric Joyner return ICE_FC_RX_PAUSE; 298671d10453SEric Joyner 298771d10453SEric Joyner return ICE_FC_NONE; 298871d10453SEric Joyner } 298971d10453SEric Joyner 299071d10453SEric Joyner /** 299171d10453SEric Joyner * ice_caps_to_fec_mode 299271d10453SEric Joyner * @caps: PHY capabilities 299371d10453SEric Joyner * @fec_options: Link FEC options 299471d10453SEric Joyner * 299571d10453SEric Joyner * Convert PHY FEC capabilities to ice FEC mode 299671d10453SEric Joyner */ 299771d10453SEric Joyner enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options) 299871d10453SEric Joyner { 299971d10453SEric Joyner if (caps & ICE_AQC_PHY_EN_AUTO_FEC) 300071d10453SEric Joyner return ICE_FEC_AUTO; 300171d10453SEric Joyner 300271d10453SEric Joyner if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 300371d10453SEric Joyner ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 300471d10453SEric Joyner ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN | 300571d10453SEric Joyner ICE_AQC_PHY_FEC_25G_KR_REQ)) 300671d10453SEric Joyner return ICE_FEC_BASER; 300771d10453SEric Joyner 300871d10453SEric Joyner if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ | 300971d10453SEric Joyner ICE_AQC_PHY_FEC_25G_RS_544_REQ | 301071d10453SEric Joyner ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN)) 301171d10453SEric Joyner return ICE_FEC_RS; 301271d10453SEric Joyner 301371d10453SEric Joyner return ICE_FEC_NONE; 301471d10453SEric Joyner } 301571d10453SEric Joyner 301671d10453SEric Joyner /** 30177d7af7f8SEric Joyner * ice_cfg_phy_fc - Configure PHY FC data based on FC mode 301871d10453SEric Joyner * @pi: port information structure 30197d7af7f8SEric Joyner * @cfg: PHY configuration data to set FC mode 30207d7af7f8SEric Joyner * @req_mode: FC mode to configure 302171d10453SEric Joyner */ 30227d7af7f8SEric Joyner static enum ice_status 30237d7af7f8SEric Joyner ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 30247d7af7f8SEric Joyner enum ice_fc_mode req_mode) 302571d10453SEric Joyner { 302671d10453SEric Joyner struct ice_phy_cache_mode_data cache_data; 30277d7af7f8SEric Joyner u8 pause_mask = 0x0; 30287d7af7f8SEric Joyner 30297d7af7f8SEric Joyner if (!pi || !cfg) 30307d7af7f8SEric Joyner return ICE_ERR_BAD_PTR; 30317d7af7f8SEric Joyner switch (req_mode) { 30327d7af7f8SEric Joyner case ICE_FC_AUTO: 30337d7af7f8SEric Joyner { 303471d10453SEric Joyner struct ice_aqc_get_phy_caps_data *pcaps; 303571d10453SEric Joyner enum ice_status status; 303671d10453SEric Joyner 303771d10453SEric Joyner pcaps = (struct ice_aqc_get_phy_caps_data *) 30387d7af7f8SEric Joyner ice_malloc(pi->hw, sizeof(*pcaps)); 303971d10453SEric Joyner if (!pcaps) 304071d10453SEric Joyner return ICE_ERR_NO_MEMORY; 304171d10453SEric Joyner /* Query the value of FC that both the NIC and attached media 304271d10453SEric Joyner * can do. 304371d10453SEric Joyner */ 3044*9cf1841cSEric Joyner status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, 304571d10453SEric Joyner pcaps, NULL); 304671d10453SEric Joyner if (status) { 30477d7af7f8SEric Joyner ice_free(pi->hw, pcaps); 30487d7af7f8SEric Joyner return status; 304971d10453SEric Joyner } 305071d10453SEric Joyner 305171d10453SEric Joyner pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE; 305271d10453SEric Joyner pause_mask |= pcaps->caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE; 30537d7af7f8SEric Joyner 30547d7af7f8SEric Joyner ice_free(pi->hw, pcaps); 305571d10453SEric Joyner break; 30567d7af7f8SEric Joyner } 305771d10453SEric Joyner case ICE_FC_FULL: 305871d10453SEric Joyner pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 305971d10453SEric Joyner pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 306071d10453SEric Joyner break; 306171d10453SEric Joyner case ICE_FC_RX_PAUSE: 306271d10453SEric Joyner pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE; 306371d10453SEric Joyner break; 306471d10453SEric Joyner case ICE_FC_TX_PAUSE: 306571d10453SEric Joyner pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE; 306671d10453SEric Joyner break; 306771d10453SEric Joyner default: 306871d10453SEric Joyner break; 306971d10453SEric Joyner } 307071d10453SEric Joyner 30717d7af7f8SEric Joyner /* clear the old pause settings */ 30727d7af7f8SEric Joyner cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | 30737d7af7f8SEric Joyner ICE_AQC_PHY_EN_RX_LINK_PAUSE); 30747d7af7f8SEric Joyner 30757d7af7f8SEric Joyner /* set the new capabilities */ 30767d7af7f8SEric Joyner cfg->caps |= pause_mask; 30777d7af7f8SEric Joyner 30787d7af7f8SEric Joyner /* Cache user FC request */ 30797d7af7f8SEric Joyner cache_data.data.curr_user_fc_req = req_mode; 30807d7af7f8SEric Joyner ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE); 30817d7af7f8SEric Joyner 30827d7af7f8SEric Joyner return ICE_SUCCESS; 30837d7af7f8SEric Joyner } 30847d7af7f8SEric Joyner 30857d7af7f8SEric Joyner /** 30867d7af7f8SEric Joyner * ice_set_fc 30877d7af7f8SEric Joyner * @pi: port information structure 30887d7af7f8SEric Joyner * @aq_failures: pointer to status code, specific to ice_set_fc routine 30897d7af7f8SEric Joyner * @ena_auto_link_update: enable automatic link update 30907d7af7f8SEric Joyner * 30917d7af7f8SEric Joyner * Set the requested flow control mode. 30927d7af7f8SEric Joyner */ 30937d7af7f8SEric Joyner enum ice_status 30947d7af7f8SEric Joyner ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update) 30957d7af7f8SEric Joyner { 30967d7af7f8SEric Joyner struct ice_aqc_set_phy_cfg_data cfg = { 0 }; 30977d7af7f8SEric Joyner struct ice_aqc_get_phy_caps_data *pcaps; 30987d7af7f8SEric Joyner enum ice_status status; 30997d7af7f8SEric Joyner struct ice_hw *hw; 31007d7af7f8SEric Joyner 31017d7af7f8SEric Joyner if (!pi || !aq_failures) 31027d7af7f8SEric Joyner return ICE_ERR_BAD_PTR; 31037d7af7f8SEric Joyner 31047d7af7f8SEric Joyner *aq_failures = 0; 31057d7af7f8SEric Joyner hw = pi->hw; 31067d7af7f8SEric Joyner 31077d7af7f8SEric Joyner pcaps = (struct ice_aqc_get_phy_caps_data *) 31087d7af7f8SEric Joyner ice_malloc(hw, sizeof(*pcaps)); 31097d7af7f8SEric Joyner if (!pcaps) 31107d7af7f8SEric Joyner return ICE_ERR_NO_MEMORY; 31117d7af7f8SEric Joyner 311271d10453SEric Joyner /* Get the current PHY config */ 3113*9cf1841cSEric Joyner status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, 3114*9cf1841cSEric Joyner pcaps, NULL); 3115*9cf1841cSEric Joyner 311671d10453SEric Joyner if (status) { 311771d10453SEric Joyner *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 311871d10453SEric Joyner goto out; 311971d10453SEric Joyner } 312071d10453SEric Joyner 312171d10453SEric Joyner ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg); 312271d10453SEric Joyner 31237d7af7f8SEric Joyner /* Configure the set PHY data */ 31247d7af7f8SEric Joyner status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); 31257d7af7f8SEric Joyner if (status) { 31267d7af7f8SEric Joyner if (status != ICE_ERR_BAD_PTR) 31277d7af7f8SEric Joyner *aq_failures = ICE_SET_FC_AQ_FAIL_GET; 312871d10453SEric Joyner 31297d7af7f8SEric Joyner goto out; 31307d7af7f8SEric Joyner } 313171d10453SEric Joyner 313271d10453SEric Joyner /* If the capabilities have changed, then set the new config */ 313371d10453SEric Joyner if (cfg.caps != pcaps->caps) { 313471d10453SEric Joyner int retry_count, retry_max = 10; 313571d10453SEric Joyner 313671d10453SEric Joyner /* Auto restart link so settings take effect */ 313771d10453SEric Joyner if (ena_auto_link_update) 313871d10453SEric Joyner cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 313971d10453SEric Joyner 314071d10453SEric Joyner status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL); 314171d10453SEric Joyner if (status) { 314271d10453SEric Joyner *aq_failures = ICE_SET_FC_AQ_FAIL_SET; 314371d10453SEric Joyner goto out; 314471d10453SEric Joyner } 314571d10453SEric Joyner 314671d10453SEric Joyner /* Update the link info 314771d10453SEric Joyner * It sometimes takes a really long time for link to 314871d10453SEric Joyner * come back from the atomic reset. Thus, we wait a 314971d10453SEric Joyner * little bit. 315071d10453SEric Joyner */ 315171d10453SEric Joyner for (retry_count = 0; retry_count < retry_max; retry_count++) { 315271d10453SEric Joyner status = ice_update_link_info(pi); 315371d10453SEric Joyner 315471d10453SEric Joyner if (status == ICE_SUCCESS) 315571d10453SEric Joyner break; 315671d10453SEric Joyner 315771d10453SEric Joyner ice_msec_delay(100, true); 315871d10453SEric Joyner } 315971d10453SEric Joyner 316071d10453SEric Joyner if (status) 316171d10453SEric Joyner *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE; 316271d10453SEric Joyner } 316371d10453SEric Joyner 316471d10453SEric Joyner out: 316571d10453SEric Joyner ice_free(hw, pcaps); 316671d10453SEric Joyner return status; 316771d10453SEric Joyner } 316871d10453SEric Joyner 316971d10453SEric Joyner /** 317071d10453SEric Joyner * ice_phy_caps_equals_cfg 317171d10453SEric Joyner * @phy_caps: PHY capabilities 317271d10453SEric Joyner * @phy_cfg: PHY configuration 317371d10453SEric Joyner * 317471d10453SEric Joyner * Helper function to determine if PHY capabilities matches PHY 317571d10453SEric Joyner * configuration 317671d10453SEric Joyner */ 317771d10453SEric Joyner bool 317871d10453SEric Joyner ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps, 317971d10453SEric Joyner struct ice_aqc_set_phy_cfg_data *phy_cfg) 318071d10453SEric Joyner { 318171d10453SEric Joyner u8 caps_mask, cfg_mask; 318271d10453SEric Joyner 318371d10453SEric Joyner if (!phy_caps || !phy_cfg) 318471d10453SEric Joyner return false; 318571d10453SEric Joyner 318671d10453SEric Joyner /* These bits are not common between capabilities and configuration. 318771d10453SEric Joyner * Do not use them to determine equality. 318871d10453SEric Joyner */ 318971d10453SEric Joyner caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE | 319071d10453SEric Joyner ICE_AQC_PHY_EN_MOD_QUAL); 319171d10453SEric Joyner cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT; 319271d10453SEric Joyner 319371d10453SEric Joyner if (phy_caps->phy_type_low != phy_cfg->phy_type_low || 319471d10453SEric Joyner phy_caps->phy_type_high != phy_cfg->phy_type_high || 319571d10453SEric Joyner ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || 319671d10453SEric Joyner phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || 319771d10453SEric Joyner phy_caps->eee_cap != phy_cfg->eee_cap || 319871d10453SEric Joyner phy_caps->eeer_value != phy_cfg->eeer_value || 319971d10453SEric Joyner phy_caps->link_fec_options != phy_cfg->link_fec_opt) 320071d10453SEric Joyner return false; 320171d10453SEric Joyner 320271d10453SEric Joyner return true; 320371d10453SEric Joyner } 320471d10453SEric Joyner 320571d10453SEric Joyner /** 320671d10453SEric Joyner * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data 320771d10453SEric Joyner * @pi: port information structure 320871d10453SEric Joyner * @caps: PHY ability structure to copy date from 320971d10453SEric Joyner * @cfg: PHY configuration structure to copy data to 321071d10453SEric Joyner * 321171d10453SEric Joyner * Helper function to copy AQC PHY get ability data to PHY set configuration 321271d10453SEric Joyner * data structure 321371d10453SEric Joyner */ 321471d10453SEric Joyner void 321571d10453SEric Joyner ice_copy_phy_caps_to_cfg(struct ice_port_info *pi, 321671d10453SEric Joyner struct ice_aqc_get_phy_caps_data *caps, 321771d10453SEric Joyner struct ice_aqc_set_phy_cfg_data *cfg) 321871d10453SEric Joyner { 321971d10453SEric Joyner if (!pi || !caps || !cfg) 322071d10453SEric Joyner return; 322171d10453SEric Joyner 322271d10453SEric Joyner ice_memset(cfg, 0, sizeof(*cfg), ICE_NONDMA_MEM); 322371d10453SEric Joyner cfg->phy_type_low = caps->phy_type_low; 322471d10453SEric Joyner cfg->phy_type_high = caps->phy_type_high; 322571d10453SEric Joyner cfg->caps = caps->caps; 322671d10453SEric Joyner cfg->low_power_ctrl_an = caps->low_power_ctrl_an; 322771d10453SEric Joyner cfg->eee_cap = caps->eee_cap; 322871d10453SEric Joyner cfg->eeer_value = caps->eeer_value; 322971d10453SEric Joyner cfg->link_fec_opt = caps->link_fec_options; 323071d10453SEric Joyner cfg->module_compliance_enforcement = 323171d10453SEric Joyner caps->module_compliance_enforcement; 323271d10453SEric Joyner } 323371d10453SEric Joyner 323471d10453SEric Joyner /** 323571d10453SEric Joyner * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode 323671d10453SEric Joyner * @pi: port information structure 323771d10453SEric Joyner * @cfg: PHY configuration data to set FEC mode 323871d10453SEric Joyner * @fec: FEC mode to configure 323971d10453SEric Joyner */ 324071d10453SEric Joyner enum ice_status 324171d10453SEric Joyner ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg, 324271d10453SEric Joyner enum ice_fec_mode fec) 324371d10453SEric Joyner { 324471d10453SEric Joyner struct ice_aqc_get_phy_caps_data *pcaps; 324571d10453SEric Joyner enum ice_status status = ICE_SUCCESS; 324671d10453SEric Joyner struct ice_hw *hw; 324771d10453SEric Joyner 324871d10453SEric Joyner if (!pi || !cfg) 324971d10453SEric Joyner return ICE_ERR_BAD_PTR; 325071d10453SEric Joyner 325171d10453SEric Joyner hw = pi->hw; 325271d10453SEric Joyner 325371d10453SEric Joyner pcaps = (struct ice_aqc_get_phy_caps_data *) 325471d10453SEric Joyner ice_malloc(hw, sizeof(*pcaps)); 325571d10453SEric Joyner if (!pcaps) 325671d10453SEric Joyner return ICE_ERR_NO_MEMORY; 325771d10453SEric Joyner 3258*9cf1841cSEric Joyner status = ice_aq_get_phy_caps(pi, false, 3259*9cf1841cSEric Joyner (ice_fw_supports_report_dflt_cfg(hw) ? 3260*9cf1841cSEric Joyner ICE_AQC_REPORT_DFLT_CFG : 3261*9cf1841cSEric Joyner ICE_AQC_REPORT_TOPO_CAP_MEDIA), pcaps, NULL); 3262*9cf1841cSEric Joyner 326371d10453SEric Joyner if (status) 326471d10453SEric Joyner goto out; 326571d10453SEric Joyner 32667d7af7f8SEric Joyner cfg->caps |= (pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC); 32677d7af7f8SEric Joyner cfg->link_fec_opt = pcaps->link_fec_options; 32687d7af7f8SEric Joyner 326971d10453SEric Joyner switch (fec) { 327071d10453SEric Joyner case ICE_FEC_BASER: 327171d10453SEric Joyner /* Clear RS bits, and AND BASE-R ability 327271d10453SEric Joyner * bits and OR request bits. 327371d10453SEric Joyner */ 327471d10453SEric Joyner cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | 327571d10453SEric Joyner ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN; 327671d10453SEric Joyner cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | 327771d10453SEric Joyner ICE_AQC_PHY_FEC_25G_KR_REQ; 327871d10453SEric Joyner break; 327971d10453SEric Joyner case ICE_FEC_RS: 328071d10453SEric Joyner /* Clear BASE-R bits, and AND RS ability 328171d10453SEric Joyner * bits and OR request bits. 328271d10453SEric Joyner */ 328371d10453SEric Joyner cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; 328471d10453SEric Joyner cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | 328571d10453SEric Joyner ICE_AQC_PHY_FEC_25G_RS_544_REQ; 328671d10453SEric Joyner break; 328771d10453SEric Joyner case ICE_FEC_NONE: 328871d10453SEric Joyner /* Clear all FEC option bits. */ 328971d10453SEric Joyner cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; 329071d10453SEric Joyner break; 329171d10453SEric Joyner case ICE_FEC_AUTO: 329271d10453SEric Joyner /* AND auto FEC bit, and all caps bits. */ 329371d10453SEric Joyner cfg->caps &= ICE_AQC_PHY_CAPS_MASK; 329471d10453SEric Joyner cfg->link_fec_opt |= pcaps->link_fec_options; 329571d10453SEric Joyner break; 329671d10453SEric Joyner default: 329771d10453SEric Joyner status = ICE_ERR_PARAM; 329871d10453SEric Joyner break; 329971d10453SEric Joyner } 330071d10453SEric Joyner 3301*9cf1841cSEric Joyner if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw) && 3302*9cf1841cSEric Joyner !ice_fw_supports_report_dflt_cfg(pi->hw)) { 330371d10453SEric Joyner struct ice_link_default_override_tlv tlv; 330471d10453SEric Joyner 330571d10453SEric Joyner if (ice_get_link_default_override(&tlv, pi)) 330671d10453SEric Joyner goto out; 330771d10453SEric Joyner 330871d10453SEric Joyner if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) && 330971d10453SEric Joyner (tlv.options & ICE_LINK_OVERRIDE_EN)) 331071d10453SEric Joyner cfg->link_fec_opt = tlv.fec_options; 331171d10453SEric Joyner } 331271d10453SEric Joyner 331371d10453SEric Joyner out: 331471d10453SEric Joyner ice_free(hw, pcaps); 331571d10453SEric Joyner 331671d10453SEric Joyner return status; 331771d10453SEric Joyner } 331871d10453SEric Joyner 331971d10453SEric Joyner /** 332071d10453SEric Joyner * ice_get_link_status - get status of the HW network link 332171d10453SEric Joyner * @pi: port information structure 332271d10453SEric Joyner * @link_up: pointer to bool (true/false = linkup/linkdown) 332371d10453SEric Joyner * 332471d10453SEric Joyner * Variable link_up is true if link is up, false if link is down. 332571d10453SEric Joyner * The variable link_up is invalid if status is non zero. As a 332671d10453SEric Joyner * result of this call, link status reporting becomes enabled 332771d10453SEric Joyner */ 332871d10453SEric Joyner enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up) 332971d10453SEric Joyner { 333071d10453SEric Joyner struct ice_phy_info *phy_info; 333171d10453SEric Joyner enum ice_status status = ICE_SUCCESS; 333271d10453SEric Joyner 333371d10453SEric Joyner if (!pi || !link_up) 333471d10453SEric Joyner return ICE_ERR_PARAM; 333571d10453SEric Joyner 333671d10453SEric Joyner phy_info = &pi->phy; 333771d10453SEric Joyner 333871d10453SEric Joyner if (phy_info->get_link_info) { 333971d10453SEric Joyner status = ice_update_link_info(pi); 334071d10453SEric Joyner 334171d10453SEric Joyner if (status) 33427d7af7f8SEric Joyner ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", 334371d10453SEric Joyner status); 334471d10453SEric Joyner } 334571d10453SEric Joyner 334671d10453SEric Joyner *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; 334771d10453SEric Joyner 334871d10453SEric Joyner return status; 334971d10453SEric Joyner } 335071d10453SEric Joyner 335171d10453SEric Joyner /** 335271d10453SEric Joyner * ice_aq_set_link_restart_an 335371d10453SEric Joyner * @pi: pointer to the port information structure 335471d10453SEric Joyner * @ena_link: if true: enable link, if false: disable link 335571d10453SEric Joyner * @cd: pointer to command details structure or NULL 335671d10453SEric Joyner * 335771d10453SEric Joyner * Sets up the link and restarts the Auto-Negotiation over the link. 335871d10453SEric Joyner */ 335971d10453SEric Joyner enum ice_status 336071d10453SEric Joyner ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link, 336171d10453SEric Joyner struct ice_sq_cd *cd) 336271d10453SEric Joyner { 336371d10453SEric Joyner struct ice_aqc_restart_an *cmd; 336471d10453SEric Joyner struct ice_aq_desc desc; 336571d10453SEric Joyner 336671d10453SEric Joyner cmd = &desc.params.restart_an; 336771d10453SEric Joyner 336871d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an); 336971d10453SEric Joyner 337071d10453SEric Joyner cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; 337171d10453SEric Joyner cmd->lport_num = pi->lport; 337271d10453SEric Joyner if (ena_link) 337371d10453SEric Joyner cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; 337471d10453SEric Joyner else 337571d10453SEric Joyner cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; 337671d10453SEric Joyner 337771d10453SEric Joyner return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); 337871d10453SEric Joyner } 337971d10453SEric Joyner 338071d10453SEric Joyner /** 338171d10453SEric Joyner * ice_aq_set_event_mask 338271d10453SEric Joyner * @hw: pointer to the HW struct 338371d10453SEric Joyner * @port_num: port number of the physical function 338471d10453SEric Joyner * @mask: event mask to be set 338571d10453SEric Joyner * @cd: pointer to command details structure or NULL 338671d10453SEric Joyner * 338771d10453SEric Joyner * Set event mask (0x0613) 338871d10453SEric Joyner */ 338971d10453SEric Joyner enum ice_status 339071d10453SEric Joyner ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask, 339171d10453SEric Joyner struct ice_sq_cd *cd) 339271d10453SEric Joyner { 339371d10453SEric Joyner struct ice_aqc_set_event_mask *cmd; 339471d10453SEric Joyner struct ice_aq_desc desc; 339571d10453SEric Joyner 339671d10453SEric Joyner cmd = &desc.params.set_event_mask; 339771d10453SEric Joyner 339871d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask); 339971d10453SEric Joyner 340071d10453SEric Joyner cmd->lport_num = port_num; 340171d10453SEric Joyner 340271d10453SEric Joyner cmd->event_mask = CPU_TO_LE16(mask); 340371d10453SEric Joyner return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 340471d10453SEric Joyner } 340571d10453SEric Joyner 340671d10453SEric Joyner /** 340771d10453SEric Joyner * ice_aq_set_mac_loopback 340871d10453SEric Joyner * @hw: pointer to the HW struct 340971d10453SEric Joyner * @ena_lpbk: Enable or Disable loopback 341071d10453SEric Joyner * @cd: pointer to command details structure or NULL 341171d10453SEric Joyner * 341271d10453SEric Joyner * Enable/disable loopback on a given port 341371d10453SEric Joyner */ 341471d10453SEric Joyner enum ice_status 341571d10453SEric Joyner ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd) 341671d10453SEric Joyner { 341771d10453SEric Joyner struct ice_aqc_set_mac_lb *cmd; 341871d10453SEric Joyner struct ice_aq_desc desc; 341971d10453SEric Joyner 342071d10453SEric Joyner cmd = &desc.params.set_mac_lb; 342171d10453SEric Joyner 342271d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb); 342371d10453SEric Joyner if (ena_lpbk) 342471d10453SEric Joyner cmd->lb_mode = ICE_AQ_MAC_LB_EN; 342571d10453SEric Joyner 342671d10453SEric Joyner return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 342771d10453SEric Joyner } 342871d10453SEric Joyner 342971d10453SEric Joyner /** 343071d10453SEric Joyner * ice_aq_set_port_id_led 343171d10453SEric Joyner * @pi: pointer to the port information 343271d10453SEric Joyner * @is_orig_mode: is this LED set to original mode (by the net-list) 343371d10453SEric Joyner * @cd: pointer to command details structure or NULL 343471d10453SEric Joyner * 343571d10453SEric Joyner * Set LED value for the given port (0x06e9) 343671d10453SEric Joyner */ 343771d10453SEric Joyner enum ice_status 343871d10453SEric Joyner ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode, 343971d10453SEric Joyner struct ice_sq_cd *cd) 344071d10453SEric Joyner { 344171d10453SEric Joyner struct ice_aqc_set_port_id_led *cmd; 344271d10453SEric Joyner struct ice_hw *hw = pi->hw; 344371d10453SEric Joyner struct ice_aq_desc desc; 344471d10453SEric Joyner 344571d10453SEric Joyner cmd = &desc.params.set_port_id_led; 344671d10453SEric Joyner 344771d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led); 344871d10453SEric Joyner 344971d10453SEric Joyner if (is_orig_mode) 345071d10453SEric Joyner cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; 345171d10453SEric Joyner else 345271d10453SEric Joyner cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; 345371d10453SEric Joyner 345471d10453SEric Joyner return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 345571d10453SEric Joyner } 345671d10453SEric Joyner 345771d10453SEric Joyner /** 345871d10453SEric Joyner * ice_aq_sff_eeprom 345971d10453SEric Joyner * @hw: pointer to the HW struct 346071d10453SEric Joyner * @lport: bits [7:0] = logical port, bit [8] = logical port valid 346171d10453SEric Joyner * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default) 346271d10453SEric Joyner * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding. 346371d10453SEric Joyner * @page: QSFP page 346471d10453SEric Joyner * @set_page: set or ignore the page 346571d10453SEric Joyner * @data: pointer to data buffer to be read/written to the I2C device. 346671d10453SEric Joyner * @length: 1-16 for read, 1 for write. 346771d10453SEric Joyner * @write: 0 read, 1 for write. 346871d10453SEric Joyner * @cd: pointer to command details structure or NULL 346971d10453SEric Joyner * 347071d10453SEric Joyner * Read/Write SFF EEPROM (0x06EE) 347171d10453SEric Joyner */ 347271d10453SEric Joyner enum ice_status 347371d10453SEric Joyner ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, 347471d10453SEric Joyner u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length, 347571d10453SEric Joyner bool write, struct ice_sq_cd *cd) 347671d10453SEric Joyner { 347771d10453SEric Joyner struct ice_aqc_sff_eeprom *cmd; 347871d10453SEric Joyner struct ice_aq_desc desc; 347971d10453SEric Joyner enum ice_status status; 348071d10453SEric Joyner 348171d10453SEric Joyner if (!data || (mem_addr & 0xff00)) 348271d10453SEric Joyner return ICE_ERR_PARAM; 348371d10453SEric Joyner 348471d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); 348571d10453SEric Joyner cmd = &desc.params.read_write_sff_param; 3486d08b8680SEric Joyner desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD); 348771d10453SEric Joyner cmd->lport_num = (u8)(lport & 0xff); 348871d10453SEric Joyner cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); 348971d10453SEric Joyner cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) & 349071d10453SEric Joyner ICE_AQC_SFF_I2CBUS_7BIT_M) | 349171d10453SEric Joyner ((set_page << 349271d10453SEric Joyner ICE_AQC_SFF_SET_EEPROM_PAGE_S) & 349371d10453SEric Joyner ICE_AQC_SFF_SET_EEPROM_PAGE_M)); 349471d10453SEric Joyner cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff); 349571d10453SEric Joyner cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); 349671d10453SEric Joyner if (write) 349771d10453SEric Joyner cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE); 349871d10453SEric Joyner 349971d10453SEric Joyner status = ice_aq_send_cmd(hw, &desc, data, length, cd); 350071d10453SEric Joyner return status; 350171d10453SEric Joyner } 350271d10453SEric Joyner 350371d10453SEric Joyner /** 350471d10453SEric Joyner * __ice_aq_get_set_rss_lut 350571d10453SEric Joyner * @hw: pointer to the hardware structure 3506d08b8680SEric Joyner * @params: RSS LUT parameters 350771d10453SEric Joyner * @set: set true to set the table, false to get the table 350871d10453SEric Joyner * 350971d10453SEric Joyner * Internal function to get (0x0B05) or set (0x0B03) RSS look up table 351071d10453SEric Joyner */ 351171d10453SEric Joyner static enum ice_status 3512d08b8680SEric Joyner __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *params, bool set) 351371d10453SEric Joyner { 3514d08b8680SEric Joyner u16 flags = 0, vsi_id, lut_type, lut_size, glob_lut_idx, vsi_handle; 351571d10453SEric Joyner struct ice_aqc_get_set_rss_lut *cmd_resp; 351671d10453SEric Joyner struct ice_aq_desc desc; 351771d10453SEric Joyner enum ice_status status; 3518d08b8680SEric Joyner u8 *lut; 3519d08b8680SEric Joyner 3520d08b8680SEric Joyner if (!params) 3521d08b8680SEric Joyner return ICE_ERR_PARAM; 3522d08b8680SEric Joyner 3523d08b8680SEric Joyner vsi_handle = params->vsi_handle; 3524d08b8680SEric Joyner lut = params->lut; 3525d08b8680SEric Joyner 3526d08b8680SEric Joyner if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) 3527d08b8680SEric Joyner return ICE_ERR_PARAM; 3528d08b8680SEric Joyner 3529d08b8680SEric Joyner lut_size = params->lut_size; 3530d08b8680SEric Joyner lut_type = params->lut_type; 3531d08b8680SEric Joyner glob_lut_idx = params->global_lut_id; 3532d08b8680SEric Joyner vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); 353371d10453SEric Joyner 353471d10453SEric Joyner cmd_resp = &desc.params.get_set_rss_lut; 353571d10453SEric Joyner 353671d10453SEric Joyner if (set) { 353771d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); 353871d10453SEric Joyner desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 353971d10453SEric Joyner } else { 354071d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); 354171d10453SEric Joyner } 354271d10453SEric Joyner 354371d10453SEric Joyner cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id << 354471d10453SEric Joyner ICE_AQC_GSET_RSS_LUT_VSI_ID_S) & 354571d10453SEric Joyner ICE_AQC_GSET_RSS_LUT_VSI_ID_M) | 354671d10453SEric Joyner ICE_AQC_GSET_RSS_LUT_VSI_VALID); 354771d10453SEric Joyner 354871d10453SEric Joyner switch (lut_type) { 354971d10453SEric Joyner case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI: 355071d10453SEric Joyner case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF: 355171d10453SEric Joyner case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL: 355271d10453SEric Joyner flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) & 355371d10453SEric Joyner ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M); 355471d10453SEric Joyner break; 355571d10453SEric Joyner default: 355671d10453SEric Joyner status = ICE_ERR_PARAM; 355771d10453SEric Joyner goto ice_aq_get_set_rss_lut_exit; 355871d10453SEric Joyner } 355971d10453SEric Joyner 356071d10453SEric Joyner if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) { 356171d10453SEric Joyner flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) & 356271d10453SEric Joyner ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M); 356371d10453SEric Joyner 356471d10453SEric Joyner if (!set) 356571d10453SEric Joyner goto ice_aq_get_set_rss_lut_send; 356671d10453SEric Joyner } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 356771d10453SEric Joyner if (!set) 356871d10453SEric Joyner goto ice_aq_get_set_rss_lut_send; 356971d10453SEric Joyner } else { 357071d10453SEric Joyner goto ice_aq_get_set_rss_lut_send; 357171d10453SEric Joyner } 357271d10453SEric Joyner 357371d10453SEric Joyner /* LUT size is only valid for Global and PF table types */ 357471d10453SEric Joyner switch (lut_size) { 357571d10453SEric Joyner case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128: 357671d10453SEric Joyner flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG << 357771d10453SEric Joyner ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 357871d10453SEric Joyner ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 357971d10453SEric Joyner break; 358071d10453SEric Joyner case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512: 358171d10453SEric Joyner flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG << 358271d10453SEric Joyner ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 358371d10453SEric Joyner ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 358471d10453SEric Joyner break; 358571d10453SEric Joyner case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K: 358671d10453SEric Joyner if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) { 358771d10453SEric Joyner flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG << 358871d10453SEric Joyner ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) & 358971d10453SEric Joyner ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M; 359071d10453SEric Joyner break; 359171d10453SEric Joyner } 359271d10453SEric Joyner /* fall-through */ 359371d10453SEric Joyner default: 359471d10453SEric Joyner status = ICE_ERR_PARAM; 359571d10453SEric Joyner goto ice_aq_get_set_rss_lut_exit; 359671d10453SEric Joyner } 359771d10453SEric Joyner 359871d10453SEric Joyner ice_aq_get_set_rss_lut_send: 359971d10453SEric Joyner cmd_resp->flags = CPU_TO_LE16(flags); 360071d10453SEric Joyner status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL); 360171d10453SEric Joyner 360271d10453SEric Joyner ice_aq_get_set_rss_lut_exit: 360371d10453SEric Joyner return status; 360471d10453SEric Joyner } 360571d10453SEric Joyner 360671d10453SEric Joyner /** 360771d10453SEric Joyner * ice_aq_get_rss_lut 360871d10453SEric Joyner * @hw: pointer to the hardware structure 3609d08b8680SEric Joyner * @get_params: RSS LUT parameters used to specify which RSS LUT to get 361071d10453SEric Joyner * 361171d10453SEric Joyner * get the RSS lookup table, PF or VSI type 361271d10453SEric Joyner */ 361371d10453SEric Joyner enum ice_status 3614d08b8680SEric Joyner ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) 361571d10453SEric Joyner { 3616d08b8680SEric Joyner return __ice_aq_get_set_rss_lut(hw, get_params, false); 361771d10453SEric Joyner } 361871d10453SEric Joyner 361971d10453SEric Joyner /** 362071d10453SEric Joyner * ice_aq_set_rss_lut 362171d10453SEric Joyner * @hw: pointer to the hardware structure 3622d08b8680SEric Joyner * @set_params: RSS LUT parameters used to specify how to set the RSS LUT 362371d10453SEric Joyner * 362471d10453SEric Joyner * set the RSS lookup table, PF or VSI type 362571d10453SEric Joyner */ 362671d10453SEric Joyner enum ice_status 3627d08b8680SEric Joyner ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) 362871d10453SEric Joyner { 3629d08b8680SEric Joyner return __ice_aq_get_set_rss_lut(hw, set_params, true); 363071d10453SEric Joyner } 363171d10453SEric Joyner 363271d10453SEric Joyner /** 363371d10453SEric Joyner * __ice_aq_get_set_rss_key 363471d10453SEric Joyner * @hw: pointer to the HW struct 363571d10453SEric Joyner * @vsi_id: VSI FW index 363671d10453SEric Joyner * @key: pointer to key info struct 363771d10453SEric Joyner * @set: set true to set the key, false to get the key 363871d10453SEric Joyner * 363971d10453SEric Joyner * get (0x0B04) or set (0x0B02) the RSS key per VSI 364071d10453SEric Joyner */ 364171d10453SEric Joyner static enum 364271d10453SEric Joyner ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id, 364371d10453SEric Joyner struct ice_aqc_get_set_rss_keys *key, 364471d10453SEric Joyner bool set) 364571d10453SEric Joyner { 364671d10453SEric Joyner struct ice_aqc_get_set_rss_key *cmd_resp; 364771d10453SEric Joyner u16 key_size = sizeof(*key); 364871d10453SEric Joyner struct ice_aq_desc desc; 364971d10453SEric Joyner 365071d10453SEric Joyner cmd_resp = &desc.params.get_set_rss_key; 365171d10453SEric Joyner 365271d10453SEric Joyner if (set) { 365371d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key); 365471d10453SEric Joyner desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 365571d10453SEric Joyner } else { 365671d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key); 365771d10453SEric Joyner } 365871d10453SEric Joyner 365971d10453SEric Joyner cmd_resp->vsi_id = CPU_TO_LE16(((vsi_id << 366071d10453SEric Joyner ICE_AQC_GSET_RSS_KEY_VSI_ID_S) & 366171d10453SEric Joyner ICE_AQC_GSET_RSS_KEY_VSI_ID_M) | 366271d10453SEric Joyner ICE_AQC_GSET_RSS_KEY_VSI_VALID); 366371d10453SEric Joyner 366471d10453SEric Joyner return ice_aq_send_cmd(hw, &desc, key, key_size, NULL); 366571d10453SEric Joyner } 366671d10453SEric Joyner 366771d10453SEric Joyner /** 366871d10453SEric Joyner * ice_aq_get_rss_key 366971d10453SEric Joyner * @hw: pointer to the HW struct 367071d10453SEric Joyner * @vsi_handle: software VSI handle 367171d10453SEric Joyner * @key: pointer to key info struct 367271d10453SEric Joyner * 367371d10453SEric Joyner * get the RSS key per VSI 367471d10453SEric Joyner */ 367571d10453SEric Joyner enum ice_status 367671d10453SEric Joyner ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle, 367771d10453SEric Joyner struct ice_aqc_get_set_rss_keys *key) 367871d10453SEric Joyner { 367971d10453SEric Joyner if (!ice_is_vsi_valid(hw, vsi_handle) || !key) 368071d10453SEric Joyner return ICE_ERR_PARAM; 368171d10453SEric Joyner 368271d10453SEric Joyner return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 368371d10453SEric Joyner key, false); 368471d10453SEric Joyner } 368571d10453SEric Joyner 368671d10453SEric Joyner /** 368771d10453SEric Joyner * ice_aq_set_rss_key 368871d10453SEric Joyner * @hw: pointer to the HW struct 368971d10453SEric Joyner * @vsi_handle: software VSI handle 369071d10453SEric Joyner * @keys: pointer to key info struct 369171d10453SEric Joyner * 369271d10453SEric Joyner * set the RSS key per VSI 369371d10453SEric Joyner */ 369471d10453SEric Joyner enum ice_status 369571d10453SEric Joyner ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle, 369671d10453SEric Joyner struct ice_aqc_get_set_rss_keys *keys) 369771d10453SEric Joyner { 369871d10453SEric Joyner if (!ice_is_vsi_valid(hw, vsi_handle) || !keys) 369971d10453SEric Joyner return ICE_ERR_PARAM; 370071d10453SEric Joyner 370171d10453SEric Joyner return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle), 370271d10453SEric Joyner keys, true); 370371d10453SEric Joyner } 370471d10453SEric Joyner 370571d10453SEric Joyner /** 370671d10453SEric Joyner * ice_aq_add_lan_txq 370771d10453SEric Joyner * @hw: pointer to the hardware structure 370871d10453SEric Joyner * @num_qgrps: Number of added queue groups 370971d10453SEric Joyner * @qg_list: list of queue groups to be added 371071d10453SEric Joyner * @buf_size: size of buffer for indirect command 371171d10453SEric Joyner * @cd: pointer to command details structure or NULL 371271d10453SEric Joyner * 371371d10453SEric Joyner * Add Tx LAN queue (0x0C30) 371471d10453SEric Joyner * 371571d10453SEric Joyner * NOTE: 371671d10453SEric Joyner * Prior to calling add Tx LAN queue: 371771d10453SEric Joyner * Initialize the following as part of the Tx queue context: 371871d10453SEric Joyner * Completion queue ID if the queue uses Completion queue, Quanta profile, 371971d10453SEric Joyner * Cache profile and Packet shaper profile. 372071d10453SEric Joyner * 372171d10453SEric Joyner * After add Tx LAN queue AQ command is completed: 372271d10453SEric Joyner * Interrupts should be associated with specific queues, 372371d10453SEric Joyner * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue 372471d10453SEric Joyner * flow. 372571d10453SEric Joyner */ 372671d10453SEric Joyner enum ice_status 372771d10453SEric Joyner ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps, 372871d10453SEric Joyner struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size, 372971d10453SEric Joyner struct ice_sq_cd *cd) 373071d10453SEric Joyner { 373171d10453SEric Joyner struct ice_aqc_add_tx_qgrp *list; 373271d10453SEric Joyner struct ice_aqc_add_txqs *cmd; 373371d10453SEric Joyner struct ice_aq_desc desc; 37347d7af7f8SEric Joyner u16 i, sum_size = 0; 373571d10453SEric Joyner 373671d10453SEric Joyner ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 373771d10453SEric Joyner 373871d10453SEric Joyner cmd = &desc.params.add_txqs; 373971d10453SEric Joyner 374071d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs); 374171d10453SEric Joyner 374271d10453SEric Joyner if (!qg_list) 374371d10453SEric Joyner return ICE_ERR_PARAM; 374471d10453SEric Joyner 374571d10453SEric Joyner if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 374671d10453SEric Joyner return ICE_ERR_PARAM; 374771d10453SEric Joyner 37487d7af7f8SEric Joyner for (i = 0, list = qg_list; i < num_qgrps; i++) { 37497d7af7f8SEric Joyner sum_size += ice_struct_size(list, txqs, list->num_txqs); 37507d7af7f8SEric Joyner list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + 37517d7af7f8SEric Joyner list->num_txqs); 375271d10453SEric Joyner } 375371d10453SEric Joyner 37547d7af7f8SEric Joyner if (buf_size != sum_size) 375571d10453SEric Joyner return ICE_ERR_PARAM; 375671d10453SEric Joyner 375771d10453SEric Joyner desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 375871d10453SEric Joyner 375971d10453SEric Joyner cmd->num_qgrps = num_qgrps; 376071d10453SEric Joyner 376171d10453SEric Joyner return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 376271d10453SEric Joyner } 376371d10453SEric Joyner 376471d10453SEric Joyner /** 376571d10453SEric Joyner * ice_aq_dis_lan_txq 376671d10453SEric Joyner * @hw: pointer to the hardware structure 376771d10453SEric Joyner * @num_qgrps: number of groups in the list 376871d10453SEric Joyner * @qg_list: the list of groups to disable 376971d10453SEric Joyner * @buf_size: the total size of the qg_list buffer in bytes 377071d10453SEric Joyner * @rst_src: if called due to reset, specifies the reset source 377171d10453SEric Joyner * @vmvf_num: the relative VM or VF number that is undergoing the reset 377271d10453SEric Joyner * @cd: pointer to command details structure or NULL 377371d10453SEric Joyner * 377471d10453SEric Joyner * Disable LAN Tx queue (0x0C31) 377571d10453SEric Joyner */ 377671d10453SEric Joyner static enum ice_status 377771d10453SEric Joyner ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps, 377871d10453SEric Joyner struct ice_aqc_dis_txq_item *qg_list, u16 buf_size, 377971d10453SEric Joyner enum ice_disq_rst_src rst_src, u16 vmvf_num, 378071d10453SEric Joyner struct ice_sq_cd *cd) 378171d10453SEric Joyner { 37827d7af7f8SEric Joyner struct ice_aqc_dis_txq_item *item; 378371d10453SEric Joyner struct ice_aqc_dis_txqs *cmd; 378471d10453SEric Joyner struct ice_aq_desc desc; 378571d10453SEric Joyner enum ice_status status; 378671d10453SEric Joyner u16 i, sz = 0; 378771d10453SEric Joyner 378871d10453SEric Joyner ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 378971d10453SEric Joyner cmd = &desc.params.dis_txqs; 379071d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs); 379171d10453SEric Joyner 379271d10453SEric Joyner /* qg_list can be NULL only in VM/VF reset flow */ 379371d10453SEric Joyner if (!qg_list && !rst_src) 379471d10453SEric Joyner return ICE_ERR_PARAM; 379571d10453SEric Joyner 379671d10453SEric Joyner if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS) 379771d10453SEric Joyner return ICE_ERR_PARAM; 379871d10453SEric Joyner 379971d10453SEric Joyner cmd->num_entries = num_qgrps; 380071d10453SEric Joyner 380171d10453SEric Joyner cmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) & 380271d10453SEric Joyner ICE_AQC_Q_DIS_TIMEOUT_M); 380371d10453SEric Joyner 380471d10453SEric Joyner switch (rst_src) { 380571d10453SEric Joyner case ICE_VM_RESET: 380671d10453SEric Joyner cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; 380771d10453SEric Joyner cmd->vmvf_and_timeout |= 380871d10453SEric Joyner CPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M); 380971d10453SEric Joyner break; 381071d10453SEric Joyner case ICE_VF_RESET: 381171d10453SEric Joyner cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; 381271d10453SEric Joyner /* In this case, FW expects vmvf_num to be absolute VF ID */ 381371d10453SEric Joyner cmd->vmvf_and_timeout |= 381471d10453SEric Joyner CPU_TO_LE16((vmvf_num + hw->func_caps.vf_base_id) & 381571d10453SEric Joyner ICE_AQC_Q_DIS_VMVF_NUM_M); 381671d10453SEric Joyner break; 381771d10453SEric Joyner case ICE_NO_RESET: 381871d10453SEric Joyner default: 381971d10453SEric Joyner break; 382071d10453SEric Joyner } 382171d10453SEric Joyner 382271d10453SEric Joyner /* flush pipe on time out */ 382371d10453SEric Joyner cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; 382471d10453SEric Joyner /* If no queue group info, we are in a reset flow. Issue the AQ */ 382571d10453SEric Joyner if (!qg_list) 382671d10453SEric Joyner goto do_aq; 382771d10453SEric Joyner 382871d10453SEric Joyner /* set RD bit to indicate that command buffer is provided by the driver 382971d10453SEric Joyner * and it needs to be read by the firmware 383071d10453SEric Joyner */ 383171d10453SEric Joyner desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 383271d10453SEric Joyner 38337d7af7f8SEric Joyner for (i = 0, item = qg_list; i < num_qgrps; i++) { 38347d7af7f8SEric Joyner u16 item_size = ice_struct_size(item, q_id, item->num_qs); 383571d10453SEric Joyner 383671d10453SEric Joyner /* If the num of queues is even, add 2 bytes of padding */ 38377d7af7f8SEric Joyner if ((item->num_qs % 2) == 0) 38387d7af7f8SEric Joyner item_size += 2; 38397d7af7f8SEric Joyner 38407d7af7f8SEric Joyner sz += item_size; 38417d7af7f8SEric Joyner 38427d7af7f8SEric Joyner item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size); 384371d10453SEric Joyner } 384471d10453SEric Joyner 384571d10453SEric Joyner if (buf_size != sz) 384671d10453SEric Joyner return ICE_ERR_PARAM; 384771d10453SEric Joyner 384871d10453SEric Joyner do_aq: 384971d10453SEric Joyner status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd); 385071d10453SEric Joyner if (status) { 385171d10453SEric Joyner if (!qg_list) 385271d10453SEric Joyner ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n", 385371d10453SEric Joyner vmvf_num, hw->adminq.sq_last_status); 385471d10453SEric Joyner else 385571d10453SEric Joyner ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n", 385671d10453SEric Joyner LE16_TO_CPU(qg_list[0].q_id[0]), 385771d10453SEric Joyner hw->adminq.sq_last_status); 385871d10453SEric Joyner } 385971d10453SEric Joyner return status; 386071d10453SEric Joyner } 386171d10453SEric Joyner 386271d10453SEric Joyner /** 386371d10453SEric Joyner * ice_aq_move_recfg_lan_txq 386471d10453SEric Joyner * @hw: pointer to the hardware structure 386571d10453SEric Joyner * @num_qs: number of queues to move/reconfigure 386671d10453SEric Joyner * @is_move: true if this operation involves node movement 386771d10453SEric Joyner * @is_tc_change: true if this operation involves a TC change 386871d10453SEric Joyner * @subseq_call: true if this operation is a subsequent call 386971d10453SEric Joyner * @flush_pipe: on timeout, true to flush pipe, false to return EAGAIN 387071d10453SEric Joyner * @timeout: timeout in units of 100 usec (valid values 0-50) 387171d10453SEric Joyner * @blocked_cgds: out param, bitmap of CGDs that timed out if returning EAGAIN 387271d10453SEric Joyner * @buf: struct containing src/dest TEID and per-queue info 387371d10453SEric Joyner * @buf_size: size of buffer for indirect command 387471d10453SEric Joyner * @txqs_moved: out param, number of queues successfully moved 387571d10453SEric Joyner * @cd: pointer to command details structure or NULL 387671d10453SEric Joyner * 387771d10453SEric Joyner * Move / Reconfigure Tx LAN queues (0x0C32) 387871d10453SEric Joyner */ 387971d10453SEric Joyner enum ice_status 388071d10453SEric Joyner ice_aq_move_recfg_lan_txq(struct ice_hw *hw, u8 num_qs, bool is_move, 388171d10453SEric Joyner bool is_tc_change, bool subseq_call, bool flush_pipe, 388271d10453SEric Joyner u8 timeout, u32 *blocked_cgds, 388371d10453SEric Joyner struct ice_aqc_move_txqs_data *buf, u16 buf_size, 388471d10453SEric Joyner u8 *txqs_moved, struct ice_sq_cd *cd) 388571d10453SEric Joyner { 388671d10453SEric Joyner struct ice_aqc_move_txqs *cmd; 388771d10453SEric Joyner struct ice_aq_desc desc; 388871d10453SEric Joyner enum ice_status status; 388971d10453SEric Joyner 389071d10453SEric Joyner cmd = &desc.params.move_txqs; 389171d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_move_recfg_txqs); 389271d10453SEric Joyner 389371d10453SEric Joyner #define ICE_LAN_TXQ_MOVE_TIMEOUT_MAX 50 389471d10453SEric Joyner if (timeout > ICE_LAN_TXQ_MOVE_TIMEOUT_MAX) 389571d10453SEric Joyner return ICE_ERR_PARAM; 389671d10453SEric Joyner 389771d10453SEric Joyner if (is_tc_change && !flush_pipe && !blocked_cgds) 389871d10453SEric Joyner return ICE_ERR_PARAM; 389971d10453SEric Joyner 390071d10453SEric Joyner if (!is_move && !is_tc_change) 390171d10453SEric Joyner return ICE_ERR_PARAM; 390271d10453SEric Joyner 390371d10453SEric Joyner desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); 390471d10453SEric Joyner 390571d10453SEric Joyner if (is_move) 390671d10453SEric Joyner cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_MOVE; 390771d10453SEric Joyner 390871d10453SEric Joyner if (is_tc_change) 390971d10453SEric Joyner cmd->cmd_type |= ICE_AQC_Q_CMD_TYPE_TC_CHANGE; 391071d10453SEric Joyner 391171d10453SEric Joyner if (subseq_call) 391271d10453SEric Joyner cmd->cmd_type |= ICE_AQC_Q_CMD_SUBSEQ_CALL; 391371d10453SEric Joyner 391471d10453SEric Joyner if (flush_pipe) 391571d10453SEric Joyner cmd->cmd_type |= ICE_AQC_Q_CMD_FLUSH_PIPE; 391671d10453SEric Joyner 391771d10453SEric Joyner cmd->num_qs = num_qs; 391871d10453SEric Joyner cmd->timeout = ((timeout << ICE_AQC_Q_CMD_TIMEOUT_S) & 391971d10453SEric Joyner ICE_AQC_Q_CMD_TIMEOUT_M); 392071d10453SEric Joyner 392171d10453SEric Joyner status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 392271d10453SEric Joyner 392371d10453SEric Joyner if (!status && txqs_moved) 392471d10453SEric Joyner *txqs_moved = cmd->num_qs; 392571d10453SEric Joyner 392671d10453SEric Joyner if (hw->adminq.sq_last_status == ICE_AQ_RC_EAGAIN && 392771d10453SEric Joyner is_tc_change && !flush_pipe) 392871d10453SEric Joyner *blocked_cgds = LE32_TO_CPU(cmd->blocked_cgds); 392971d10453SEric Joyner 393071d10453SEric Joyner return status; 393171d10453SEric Joyner } 393271d10453SEric Joyner 393371d10453SEric Joyner /* End of FW Admin Queue command wrappers */ 393471d10453SEric Joyner 393571d10453SEric Joyner /** 393671d10453SEric Joyner * ice_write_byte - write a byte to a packed context structure 393771d10453SEric Joyner * @src_ctx: the context structure to read from 393871d10453SEric Joyner * @dest_ctx: the context to be written to 393971d10453SEric Joyner * @ce_info: a description of the struct to be filled 394071d10453SEric Joyner */ 394171d10453SEric Joyner static void 394271d10453SEric Joyner ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 394371d10453SEric Joyner { 394471d10453SEric Joyner u8 src_byte, dest_byte, mask; 394571d10453SEric Joyner u8 *from, *dest; 394671d10453SEric Joyner u16 shift_width; 394771d10453SEric Joyner 394871d10453SEric Joyner /* copy from the next struct field */ 394971d10453SEric Joyner from = src_ctx + ce_info->offset; 395071d10453SEric Joyner 395171d10453SEric Joyner /* prepare the bits and mask */ 395271d10453SEric Joyner shift_width = ce_info->lsb % 8; 395371d10453SEric Joyner mask = (u8)(BIT(ce_info->width) - 1); 395471d10453SEric Joyner 395571d10453SEric Joyner src_byte = *from; 395671d10453SEric Joyner src_byte &= mask; 395771d10453SEric Joyner 395871d10453SEric Joyner /* shift to correct alignment */ 395971d10453SEric Joyner mask <<= shift_width; 396071d10453SEric Joyner src_byte <<= shift_width; 396171d10453SEric Joyner 396271d10453SEric Joyner /* get the current bits from the target bit string */ 396371d10453SEric Joyner dest = dest_ctx + (ce_info->lsb / 8); 396471d10453SEric Joyner 396571d10453SEric Joyner ice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA); 396671d10453SEric Joyner 396771d10453SEric Joyner dest_byte &= ~mask; /* get the bits not changing */ 396871d10453SEric Joyner dest_byte |= src_byte; /* add in the new bits */ 396971d10453SEric Joyner 397071d10453SEric Joyner /* put it all back */ 397171d10453SEric Joyner ice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA); 397271d10453SEric Joyner } 397371d10453SEric Joyner 397471d10453SEric Joyner /** 397571d10453SEric Joyner * ice_write_word - write a word to a packed context structure 397671d10453SEric Joyner * @src_ctx: the context structure to read from 397771d10453SEric Joyner * @dest_ctx: the context to be written to 397871d10453SEric Joyner * @ce_info: a description of the struct to be filled 397971d10453SEric Joyner */ 398071d10453SEric Joyner static void 398171d10453SEric Joyner ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 398271d10453SEric Joyner { 398371d10453SEric Joyner u16 src_word, mask; 398471d10453SEric Joyner __le16 dest_word; 398571d10453SEric Joyner u8 *from, *dest; 398671d10453SEric Joyner u16 shift_width; 398771d10453SEric Joyner 398871d10453SEric Joyner /* copy from the next struct field */ 398971d10453SEric Joyner from = src_ctx + ce_info->offset; 399071d10453SEric Joyner 399171d10453SEric Joyner /* prepare the bits and mask */ 399271d10453SEric Joyner shift_width = ce_info->lsb % 8; 399371d10453SEric Joyner mask = BIT(ce_info->width) - 1; 399471d10453SEric Joyner 399571d10453SEric Joyner /* don't swizzle the bits until after the mask because the mask bits 399671d10453SEric Joyner * will be in a different bit position on big endian machines 399771d10453SEric Joyner */ 399871d10453SEric Joyner src_word = *(u16 *)from; 399971d10453SEric Joyner src_word &= mask; 400071d10453SEric Joyner 400171d10453SEric Joyner /* shift to correct alignment */ 400271d10453SEric Joyner mask <<= shift_width; 400371d10453SEric Joyner src_word <<= shift_width; 400471d10453SEric Joyner 400571d10453SEric Joyner /* get the current bits from the target bit string */ 400671d10453SEric Joyner dest = dest_ctx + (ce_info->lsb / 8); 400771d10453SEric Joyner 400871d10453SEric Joyner ice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA); 400971d10453SEric Joyner 401071d10453SEric Joyner dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */ 401171d10453SEric Joyner dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */ 401271d10453SEric Joyner 401371d10453SEric Joyner /* put it all back */ 401471d10453SEric Joyner ice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA); 401571d10453SEric Joyner } 401671d10453SEric Joyner 401771d10453SEric Joyner /** 401871d10453SEric Joyner * ice_write_dword - write a dword to a packed context structure 401971d10453SEric Joyner * @src_ctx: the context structure to read from 402071d10453SEric Joyner * @dest_ctx: the context to be written to 402171d10453SEric Joyner * @ce_info: a description of the struct to be filled 402271d10453SEric Joyner */ 402371d10453SEric Joyner static void 402471d10453SEric Joyner ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 402571d10453SEric Joyner { 402671d10453SEric Joyner u32 src_dword, mask; 402771d10453SEric Joyner __le32 dest_dword; 402871d10453SEric Joyner u8 *from, *dest; 402971d10453SEric Joyner u16 shift_width; 403071d10453SEric Joyner 403171d10453SEric Joyner /* copy from the next struct field */ 403271d10453SEric Joyner from = src_ctx + ce_info->offset; 403371d10453SEric Joyner 403471d10453SEric Joyner /* prepare the bits and mask */ 403571d10453SEric Joyner shift_width = ce_info->lsb % 8; 403671d10453SEric Joyner 403771d10453SEric Joyner /* if the field width is exactly 32 on an x86 machine, then the shift 403871d10453SEric Joyner * operation will not work because the SHL instructions count is masked 403971d10453SEric Joyner * to 5 bits so the shift will do nothing 404071d10453SEric Joyner */ 404171d10453SEric Joyner if (ce_info->width < 32) 404271d10453SEric Joyner mask = BIT(ce_info->width) - 1; 404371d10453SEric Joyner else 404471d10453SEric Joyner mask = (u32)~0; 404571d10453SEric Joyner 404671d10453SEric Joyner /* don't swizzle the bits until after the mask because the mask bits 404771d10453SEric Joyner * will be in a different bit position on big endian machines 404871d10453SEric Joyner */ 404971d10453SEric Joyner src_dword = *(u32 *)from; 405071d10453SEric Joyner src_dword &= mask; 405171d10453SEric Joyner 405271d10453SEric Joyner /* shift to correct alignment */ 405371d10453SEric Joyner mask <<= shift_width; 405471d10453SEric Joyner src_dword <<= shift_width; 405571d10453SEric Joyner 405671d10453SEric Joyner /* get the current bits from the target bit string */ 405771d10453SEric Joyner dest = dest_ctx + (ce_info->lsb / 8); 405871d10453SEric Joyner 405971d10453SEric Joyner ice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA); 406071d10453SEric Joyner 406171d10453SEric Joyner dest_dword &= ~(CPU_TO_LE32(mask)); /* get the bits not changing */ 406271d10453SEric Joyner dest_dword |= CPU_TO_LE32(src_dword); /* add in the new bits */ 406371d10453SEric Joyner 406471d10453SEric Joyner /* put it all back */ 406571d10453SEric Joyner ice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA); 406671d10453SEric Joyner } 406771d10453SEric Joyner 406871d10453SEric Joyner /** 406971d10453SEric Joyner * ice_write_qword - write a qword to a packed context structure 407071d10453SEric Joyner * @src_ctx: the context structure to read from 407171d10453SEric Joyner * @dest_ctx: the context to be written to 407271d10453SEric Joyner * @ce_info: a description of the struct to be filled 407371d10453SEric Joyner */ 407471d10453SEric Joyner static void 407571d10453SEric Joyner ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) 407671d10453SEric Joyner { 407771d10453SEric Joyner u64 src_qword, mask; 407871d10453SEric Joyner __le64 dest_qword; 407971d10453SEric Joyner u8 *from, *dest; 408071d10453SEric Joyner u16 shift_width; 408171d10453SEric Joyner 408271d10453SEric Joyner /* copy from the next struct field */ 408371d10453SEric Joyner from = src_ctx + ce_info->offset; 408471d10453SEric Joyner 408571d10453SEric Joyner /* prepare the bits and mask */ 408671d10453SEric Joyner shift_width = ce_info->lsb % 8; 408771d10453SEric Joyner 408871d10453SEric Joyner /* if the field width is exactly 64 on an x86 machine, then the shift 408971d10453SEric Joyner * operation will not work because the SHL instructions count is masked 409071d10453SEric Joyner * to 6 bits so the shift will do nothing 409171d10453SEric Joyner */ 409271d10453SEric Joyner if (ce_info->width < 64) 409371d10453SEric Joyner mask = BIT_ULL(ce_info->width) - 1; 409471d10453SEric Joyner else 409571d10453SEric Joyner mask = (u64)~0; 409671d10453SEric Joyner 409771d10453SEric Joyner /* don't swizzle the bits until after the mask because the mask bits 409871d10453SEric Joyner * will be in a different bit position on big endian machines 409971d10453SEric Joyner */ 410071d10453SEric Joyner src_qword = *(u64 *)from; 410171d10453SEric Joyner src_qword &= mask; 410271d10453SEric Joyner 410371d10453SEric Joyner /* shift to correct alignment */ 410471d10453SEric Joyner mask <<= shift_width; 410571d10453SEric Joyner src_qword <<= shift_width; 410671d10453SEric Joyner 410771d10453SEric Joyner /* get the current bits from the target bit string */ 410871d10453SEric Joyner dest = dest_ctx + (ce_info->lsb / 8); 410971d10453SEric Joyner 411071d10453SEric Joyner ice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA); 411171d10453SEric Joyner 411271d10453SEric Joyner dest_qword &= ~(CPU_TO_LE64(mask)); /* get the bits not changing */ 411371d10453SEric Joyner dest_qword |= CPU_TO_LE64(src_qword); /* add in the new bits */ 411471d10453SEric Joyner 411571d10453SEric Joyner /* put it all back */ 411671d10453SEric Joyner ice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA); 411771d10453SEric Joyner } 411871d10453SEric Joyner 411971d10453SEric Joyner /** 412071d10453SEric Joyner * ice_set_ctx - set context bits in packed structure 41217d7af7f8SEric Joyner * @hw: pointer to the hardware structure 412271d10453SEric Joyner * @src_ctx: pointer to a generic non-packed context structure 412371d10453SEric Joyner * @dest_ctx: pointer to memory for the packed structure 412471d10453SEric Joyner * @ce_info: a description of the structure to be transformed 412571d10453SEric Joyner */ 412671d10453SEric Joyner enum ice_status 41277d7af7f8SEric Joyner ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, 41287d7af7f8SEric Joyner const struct ice_ctx_ele *ce_info) 412971d10453SEric Joyner { 413071d10453SEric Joyner int f; 413171d10453SEric Joyner 413271d10453SEric Joyner for (f = 0; ce_info[f].width; f++) { 413371d10453SEric Joyner /* We have to deal with each element of the FW response 413471d10453SEric Joyner * using the correct size so that we are correct regardless 413571d10453SEric Joyner * of the endianness of the machine. 413671d10453SEric Joyner */ 41377d7af7f8SEric Joyner if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) { 41387d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_QCTX, "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n", 41397d7af7f8SEric Joyner f, ce_info[f].width, ce_info[f].size_of); 41407d7af7f8SEric Joyner continue; 41417d7af7f8SEric Joyner } 414271d10453SEric Joyner switch (ce_info[f].size_of) { 414371d10453SEric Joyner case sizeof(u8): 414471d10453SEric Joyner ice_write_byte(src_ctx, dest_ctx, &ce_info[f]); 414571d10453SEric Joyner break; 414671d10453SEric Joyner case sizeof(u16): 414771d10453SEric Joyner ice_write_word(src_ctx, dest_ctx, &ce_info[f]); 414871d10453SEric Joyner break; 414971d10453SEric Joyner case sizeof(u32): 415071d10453SEric Joyner ice_write_dword(src_ctx, dest_ctx, &ce_info[f]); 415171d10453SEric Joyner break; 415271d10453SEric Joyner case sizeof(u64): 415371d10453SEric Joyner ice_write_qword(src_ctx, dest_ctx, &ce_info[f]); 415471d10453SEric Joyner break; 415571d10453SEric Joyner default: 415671d10453SEric Joyner return ICE_ERR_INVAL_SIZE; 415771d10453SEric Joyner } 415871d10453SEric Joyner } 415971d10453SEric Joyner 416071d10453SEric Joyner return ICE_SUCCESS; 416171d10453SEric Joyner } 416271d10453SEric Joyner 416371d10453SEric Joyner /** 416471d10453SEric Joyner * ice_read_byte - read context byte into struct 416571d10453SEric Joyner * @src_ctx: the context structure to read from 416671d10453SEric Joyner * @dest_ctx: the context to be written to 416771d10453SEric Joyner * @ce_info: a description of the struct to be filled 416871d10453SEric Joyner */ 416971d10453SEric Joyner static void 417071d10453SEric Joyner ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 417171d10453SEric Joyner { 417271d10453SEric Joyner u8 dest_byte, mask; 417371d10453SEric Joyner u8 *src, *target; 417471d10453SEric Joyner u16 shift_width; 417571d10453SEric Joyner 417671d10453SEric Joyner /* prepare the bits and mask */ 417771d10453SEric Joyner shift_width = ce_info->lsb % 8; 417871d10453SEric Joyner mask = (u8)(BIT(ce_info->width) - 1); 417971d10453SEric Joyner 418071d10453SEric Joyner /* shift to correct alignment */ 418171d10453SEric Joyner mask <<= shift_width; 418271d10453SEric Joyner 418371d10453SEric Joyner /* get the current bits from the src bit string */ 418471d10453SEric Joyner src = src_ctx + (ce_info->lsb / 8); 418571d10453SEric Joyner 418671d10453SEric Joyner ice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA); 418771d10453SEric Joyner 418871d10453SEric Joyner dest_byte &= ~(mask); 418971d10453SEric Joyner 419071d10453SEric Joyner dest_byte >>= shift_width; 419171d10453SEric Joyner 419271d10453SEric Joyner /* get the address from the struct field */ 419371d10453SEric Joyner target = dest_ctx + ce_info->offset; 419471d10453SEric Joyner 419571d10453SEric Joyner /* put it back in the struct */ 419671d10453SEric Joyner ice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA); 419771d10453SEric Joyner } 419871d10453SEric Joyner 419971d10453SEric Joyner /** 420071d10453SEric Joyner * ice_read_word - read context word into struct 420171d10453SEric Joyner * @src_ctx: the context structure to read from 420271d10453SEric Joyner * @dest_ctx: the context to be written to 420371d10453SEric Joyner * @ce_info: a description of the struct to be filled 420471d10453SEric Joyner */ 420571d10453SEric Joyner static void 420671d10453SEric Joyner ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 420771d10453SEric Joyner { 420871d10453SEric Joyner u16 dest_word, mask; 420971d10453SEric Joyner u8 *src, *target; 421071d10453SEric Joyner __le16 src_word; 421171d10453SEric Joyner u16 shift_width; 421271d10453SEric Joyner 421371d10453SEric Joyner /* prepare the bits and mask */ 421471d10453SEric Joyner shift_width = ce_info->lsb % 8; 421571d10453SEric Joyner mask = BIT(ce_info->width) - 1; 421671d10453SEric Joyner 421771d10453SEric Joyner /* shift to correct alignment */ 421871d10453SEric Joyner mask <<= shift_width; 421971d10453SEric Joyner 422071d10453SEric Joyner /* get the current bits from the src bit string */ 422171d10453SEric Joyner src = src_ctx + (ce_info->lsb / 8); 422271d10453SEric Joyner 422371d10453SEric Joyner ice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA); 422471d10453SEric Joyner 422571d10453SEric Joyner /* the data in the memory is stored as little endian so mask it 422671d10453SEric Joyner * correctly 422771d10453SEric Joyner */ 422871d10453SEric Joyner src_word &= ~(CPU_TO_LE16(mask)); 422971d10453SEric Joyner 423071d10453SEric Joyner /* get the data back into host order before shifting */ 423171d10453SEric Joyner dest_word = LE16_TO_CPU(src_word); 423271d10453SEric Joyner 423371d10453SEric Joyner dest_word >>= shift_width; 423471d10453SEric Joyner 423571d10453SEric Joyner /* get the address from the struct field */ 423671d10453SEric Joyner target = dest_ctx + ce_info->offset; 423771d10453SEric Joyner 423871d10453SEric Joyner /* put it back in the struct */ 423971d10453SEric Joyner ice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA); 424071d10453SEric Joyner } 424171d10453SEric Joyner 424271d10453SEric Joyner /** 424371d10453SEric Joyner * ice_read_dword - read context dword into struct 424471d10453SEric Joyner * @src_ctx: the context structure to read from 424571d10453SEric Joyner * @dest_ctx: the context to be written to 424671d10453SEric Joyner * @ce_info: a description of the struct to be filled 424771d10453SEric Joyner */ 424871d10453SEric Joyner static void 424971d10453SEric Joyner ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 425071d10453SEric Joyner { 425171d10453SEric Joyner u32 dest_dword, mask; 425271d10453SEric Joyner __le32 src_dword; 425371d10453SEric Joyner u8 *src, *target; 425471d10453SEric Joyner u16 shift_width; 425571d10453SEric Joyner 425671d10453SEric Joyner /* prepare the bits and mask */ 425771d10453SEric Joyner shift_width = ce_info->lsb % 8; 425871d10453SEric Joyner 425971d10453SEric Joyner /* if the field width is exactly 32 on an x86 machine, then the shift 426071d10453SEric Joyner * operation will not work because the SHL instructions count is masked 426171d10453SEric Joyner * to 5 bits so the shift will do nothing 426271d10453SEric Joyner */ 426371d10453SEric Joyner if (ce_info->width < 32) 426471d10453SEric Joyner mask = BIT(ce_info->width) - 1; 426571d10453SEric Joyner else 426671d10453SEric Joyner mask = (u32)~0; 426771d10453SEric Joyner 426871d10453SEric Joyner /* shift to correct alignment */ 426971d10453SEric Joyner mask <<= shift_width; 427071d10453SEric Joyner 427171d10453SEric Joyner /* get the current bits from the src bit string */ 427271d10453SEric Joyner src = src_ctx + (ce_info->lsb / 8); 427371d10453SEric Joyner 427471d10453SEric Joyner ice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA); 427571d10453SEric Joyner 427671d10453SEric Joyner /* the data in the memory is stored as little endian so mask it 427771d10453SEric Joyner * correctly 427871d10453SEric Joyner */ 427971d10453SEric Joyner src_dword &= ~(CPU_TO_LE32(mask)); 428071d10453SEric Joyner 428171d10453SEric Joyner /* get the data back into host order before shifting */ 428271d10453SEric Joyner dest_dword = LE32_TO_CPU(src_dword); 428371d10453SEric Joyner 428471d10453SEric Joyner dest_dword >>= shift_width; 428571d10453SEric Joyner 428671d10453SEric Joyner /* get the address from the struct field */ 428771d10453SEric Joyner target = dest_ctx + ce_info->offset; 428871d10453SEric Joyner 428971d10453SEric Joyner /* put it back in the struct */ 429071d10453SEric Joyner ice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA); 429171d10453SEric Joyner } 429271d10453SEric Joyner 429371d10453SEric Joyner /** 429471d10453SEric Joyner * ice_read_qword - read context qword into struct 429571d10453SEric Joyner * @src_ctx: the context structure to read from 429671d10453SEric Joyner * @dest_ctx: the context to be written to 429771d10453SEric Joyner * @ce_info: a description of the struct to be filled 429871d10453SEric Joyner */ 429971d10453SEric Joyner static void 430071d10453SEric Joyner ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 430171d10453SEric Joyner { 430271d10453SEric Joyner u64 dest_qword, mask; 430371d10453SEric Joyner __le64 src_qword; 430471d10453SEric Joyner u8 *src, *target; 430571d10453SEric Joyner u16 shift_width; 430671d10453SEric Joyner 430771d10453SEric Joyner /* prepare the bits and mask */ 430871d10453SEric Joyner shift_width = ce_info->lsb % 8; 430971d10453SEric Joyner 431071d10453SEric Joyner /* if the field width is exactly 64 on an x86 machine, then the shift 431171d10453SEric Joyner * operation will not work because the SHL instructions count is masked 431271d10453SEric Joyner * to 6 bits so the shift will do nothing 431371d10453SEric Joyner */ 431471d10453SEric Joyner if (ce_info->width < 64) 431571d10453SEric Joyner mask = BIT_ULL(ce_info->width) - 1; 431671d10453SEric Joyner else 431771d10453SEric Joyner mask = (u64)~0; 431871d10453SEric Joyner 431971d10453SEric Joyner /* shift to correct alignment */ 432071d10453SEric Joyner mask <<= shift_width; 432171d10453SEric Joyner 432271d10453SEric Joyner /* get the current bits from the src bit string */ 432371d10453SEric Joyner src = src_ctx + (ce_info->lsb / 8); 432471d10453SEric Joyner 432571d10453SEric Joyner ice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA); 432671d10453SEric Joyner 432771d10453SEric Joyner /* the data in the memory is stored as little endian so mask it 432871d10453SEric Joyner * correctly 432971d10453SEric Joyner */ 433071d10453SEric Joyner src_qword &= ~(CPU_TO_LE64(mask)); 433171d10453SEric Joyner 433271d10453SEric Joyner /* get the data back into host order before shifting */ 433371d10453SEric Joyner dest_qword = LE64_TO_CPU(src_qword); 433471d10453SEric Joyner 433571d10453SEric Joyner dest_qword >>= shift_width; 433671d10453SEric Joyner 433771d10453SEric Joyner /* get the address from the struct field */ 433871d10453SEric Joyner target = dest_ctx + ce_info->offset; 433971d10453SEric Joyner 434071d10453SEric Joyner /* put it back in the struct */ 434171d10453SEric Joyner ice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA); 434271d10453SEric Joyner } 434371d10453SEric Joyner 434471d10453SEric Joyner /** 434571d10453SEric Joyner * ice_get_ctx - extract context bits from a packed structure 434671d10453SEric Joyner * @src_ctx: pointer to a generic packed context structure 434771d10453SEric Joyner * @dest_ctx: pointer to a generic non-packed context structure 434871d10453SEric Joyner * @ce_info: a description of the structure to be read from 434971d10453SEric Joyner */ 435071d10453SEric Joyner enum ice_status 435171d10453SEric Joyner ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) 435271d10453SEric Joyner { 435371d10453SEric Joyner int f; 435471d10453SEric Joyner 435571d10453SEric Joyner for (f = 0; ce_info[f].width; f++) { 435671d10453SEric Joyner switch (ce_info[f].size_of) { 435771d10453SEric Joyner case 1: 435871d10453SEric Joyner ice_read_byte(src_ctx, dest_ctx, &ce_info[f]); 435971d10453SEric Joyner break; 436071d10453SEric Joyner case 2: 436171d10453SEric Joyner ice_read_word(src_ctx, dest_ctx, &ce_info[f]); 436271d10453SEric Joyner break; 436371d10453SEric Joyner case 4: 436471d10453SEric Joyner ice_read_dword(src_ctx, dest_ctx, &ce_info[f]); 436571d10453SEric Joyner break; 436671d10453SEric Joyner case 8: 436771d10453SEric Joyner ice_read_qword(src_ctx, dest_ctx, &ce_info[f]); 436871d10453SEric Joyner break; 436971d10453SEric Joyner default: 437071d10453SEric Joyner /* nothing to do, just keep going */ 437171d10453SEric Joyner break; 437271d10453SEric Joyner } 437371d10453SEric Joyner } 437471d10453SEric Joyner 437571d10453SEric Joyner return ICE_SUCCESS; 437671d10453SEric Joyner } 437771d10453SEric Joyner 437871d10453SEric Joyner /** 437971d10453SEric Joyner * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC 438071d10453SEric Joyner * @hw: pointer to the HW struct 438171d10453SEric Joyner * @vsi_handle: software VSI handle 438271d10453SEric Joyner * @tc: TC number 438371d10453SEric Joyner * @q_handle: software queue handle 438471d10453SEric Joyner */ 438571d10453SEric Joyner struct ice_q_ctx * 438671d10453SEric Joyner ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle) 438771d10453SEric Joyner { 438871d10453SEric Joyner struct ice_vsi_ctx *vsi; 438971d10453SEric Joyner struct ice_q_ctx *q_ctx; 439071d10453SEric Joyner 439171d10453SEric Joyner vsi = ice_get_vsi_ctx(hw, vsi_handle); 439271d10453SEric Joyner if (!vsi) 439371d10453SEric Joyner return NULL; 439471d10453SEric Joyner if (q_handle >= vsi->num_lan_q_entries[tc]) 439571d10453SEric Joyner return NULL; 439671d10453SEric Joyner if (!vsi->lan_q_ctx[tc]) 439771d10453SEric Joyner return NULL; 439871d10453SEric Joyner q_ctx = vsi->lan_q_ctx[tc]; 439971d10453SEric Joyner return &q_ctx[q_handle]; 440071d10453SEric Joyner } 440171d10453SEric Joyner 440271d10453SEric Joyner /** 440371d10453SEric Joyner * ice_ena_vsi_txq 440471d10453SEric Joyner * @pi: port information structure 440571d10453SEric Joyner * @vsi_handle: software VSI handle 440671d10453SEric Joyner * @tc: TC number 440771d10453SEric Joyner * @q_handle: software queue handle 440871d10453SEric Joyner * @num_qgrps: Number of added queue groups 440971d10453SEric Joyner * @buf: list of queue groups to be added 441071d10453SEric Joyner * @buf_size: size of buffer for indirect command 441171d10453SEric Joyner * @cd: pointer to command details structure or NULL 441271d10453SEric Joyner * 441371d10453SEric Joyner * This function adds one LAN queue 441471d10453SEric Joyner */ 441571d10453SEric Joyner enum ice_status 441671d10453SEric Joyner ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, 441771d10453SEric Joyner u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size, 441871d10453SEric Joyner struct ice_sq_cd *cd) 441971d10453SEric Joyner { 442071d10453SEric Joyner struct ice_aqc_txsched_elem_data node = { 0 }; 442171d10453SEric Joyner struct ice_sched_node *parent; 442271d10453SEric Joyner struct ice_q_ctx *q_ctx; 442371d10453SEric Joyner enum ice_status status; 442471d10453SEric Joyner struct ice_hw *hw; 442571d10453SEric Joyner 442671d10453SEric Joyner if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 442771d10453SEric Joyner return ICE_ERR_CFG; 442871d10453SEric Joyner 442971d10453SEric Joyner if (num_qgrps > 1 || buf->num_txqs > 1) 443071d10453SEric Joyner return ICE_ERR_MAX_LIMIT; 443171d10453SEric Joyner 443271d10453SEric Joyner hw = pi->hw; 443371d10453SEric Joyner 443471d10453SEric Joyner if (!ice_is_vsi_valid(hw, vsi_handle)) 443571d10453SEric Joyner return ICE_ERR_PARAM; 443671d10453SEric Joyner 443771d10453SEric Joyner ice_acquire_lock(&pi->sched_lock); 443871d10453SEric Joyner 443971d10453SEric Joyner q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle); 444071d10453SEric Joyner if (!q_ctx) { 444171d10453SEric Joyner ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n", 444271d10453SEric Joyner q_handle); 444371d10453SEric Joyner status = ICE_ERR_PARAM; 444471d10453SEric Joyner goto ena_txq_exit; 444571d10453SEric Joyner } 444671d10453SEric Joyner 444771d10453SEric Joyner /* find a parent node */ 444871d10453SEric Joyner parent = ice_sched_get_free_qparent(pi, vsi_handle, tc, 444971d10453SEric Joyner ICE_SCHED_NODE_OWNER_LAN); 445071d10453SEric Joyner if (!parent) { 445171d10453SEric Joyner status = ICE_ERR_PARAM; 445271d10453SEric Joyner goto ena_txq_exit; 445371d10453SEric Joyner } 445471d10453SEric Joyner 445571d10453SEric Joyner buf->parent_teid = parent->info.node_teid; 445671d10453SEric Joyner node.parent_teid = parent->info.node_teid; 445771d10453SEric Joyner /* Mark that the values in the "generic" section as valid. The default 445871d10453SEric Joyner * value in the "generic" section is zero. This means that : 445971d10453SEric Joyner * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. 446071d10453SEric Joyner * - 0 priority among siblings, indicated by Bit 1-3. 446171d10453SEric Joyner * - WFQ, indicated by Bit 4. 446271d10453SEric Joyner * - 0 Adjustment value is used in PSM credit update flow, indicated by 446371d10453SEric Joyner * Bit 5-6. 446471d10453SEric Joyner * - Bit 7 is reserved. 446571d10453SEric Joyner * Without setting the generic section as valid in valid_sections, the 446671d10453SEric Joyner * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. 446771d10453SEric Joyner */ 44687d7af7f8SEric Joyner buf->txqs[0].info.valid_sections = 44697d7af7f8SEric Joyner ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | 44707d7af7f8SEric Joyner ICE_AQC_ELEM_VALID_EIR; 44717d7af7f8SEric Joyner buf->txqs[0].info.generic = 0; 44727d7af7f8SEric Joyner buf->txqs[0].info.cir_bw.bw_profile_idx = 44737d7af7f8SEric Joyner CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); 44747d7af7f8SEric Joyner buf->txqs[0].info.cir_bw.bw_alloc = 44757d7af7f8SEric Joyner CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); 44767d7af7f8SEric Joyner buf->txqs[0].info.eir_bw.bw_profile_idx = 44777d7af7f8SEric Joyner CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); 44787d7af7f8SEric Joyner buf->txqs[0].info.eir_bw.bw_alloc = 44797d7af7f8SEric Joyner CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); 448071d10453SEric Joyner 448171d10453SEric Joyner /* add the LAN queue */ 448271d10453SEric Joyner status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); 448371d10453SEric Joyner if (status != ICE_SUCCESS) { 448471d10453SEric Joyner ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n", 448571d10453SEric Joyner LE16_TO_CPU(buf->txqs[0].txq_id), 448671d10453SEric Joyner hw->adminq.sq_last_status); 448771d10453SEric Joyner goto ena_txq_exit; 448871d10453SEric Joyner } 448971d10453SEric Joyner 449071d10453SEric Joyner node.node_teid = buf->txqs[0].q_teid; 449171d10453SEric Joyner node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF; 449271d10453SEric Joyner q_ctx->q_handle = q_handle; 449371d10453SEric Joyner q_ctx->q_teid = LE32_TO_CPU(node.node_teid); 449471d10453SEric Joyner 449571d10453SEric Joyner /* add a leaf node into scheduler tree queue layer */ 449671d10453SEric Joyner status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node); 449771d10453SEric Joyner if (!status) 449871d10453SEric Joyner status = ice_sched_replay_q_bw(pi, q_ctx); 449971d10453SEric Joyner 450071d10453SEric Joyner ena_txq_exit: 450171d10453SEric Joyner ice_release_lock(&pi->sched_lock); 450271d10453SEric Joyner return status; 450371d10453SEric Joyner } 450471d10453SEric Joyner 450571d10453SEric Joyner /** 450671d10453SEric Joyner * ice_dis_vsi_txq 450771d10453SEric Joyner * @pi: port information structure 450871d10453SEric Joyner * @vsi_handle: software VSI handle 450971d10453SEric Joyner * @tc: TC number 451071d10453SEric Joyner * @num_queues: number of queues 451171d10453SEric Joyner * @q_handles: pointer to software queue handle array 451271d10453SEric Joyner * @q_ids: pointer to the q_id array 451371d10453SEric Joyner * @q_teids: pointer to queue node teids 451471d10453SEric Joyner * @rst_src: if called due to reset, specifies the reset source 451571d10453SEric Joyner * @vmvf_num: the relative VM or VF number that is undergoing the reset 451671d10453SEric Joyner * @cd: pointer to command details structure or NULL 451771d10453SEric Joyner * 451871d10453SEric Joyner * This function removes queues and their corresponding nodes in SW DB 451971d10453SEric Joyner */ 452071d10453SEric Joyner enum ice_status 452171d10453SEric Joyner ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, 452271d10453SEric Joyner u16 *q_handles, u16 *q_ids, u32 *q_teids, 452371d10453SEric Joyner enum ice_disq_rst_src rst_src, u16 vmvf_num, 452471d10453SEric Joyner struct ice_sq_cd *cd) 452571d10453SEric Joyner { 452671d10453SEric Joyner enum ice_status status = ICE_ERR_DOES_NOT_EXIST; 45277d7af7f8SEric Joyner struct ice_aqc_dis_txq_item *qg_list; 452871d10453SEric Joyner struct ice_q_ctx *q_ctx; 45297d7af7f8SEric Joyner struct ice_hw *hw; 45307d7af7f8SEric Joyner u16 i, buf_size; 453171d10453SEric Joyner 453271d10453SEric Joyner if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 453371d10453SEric Joyner return ICE_ERR_CFG; 453471d10453SEric Joyner 45357d7af7f8SEric Joyner hw = pi->hw; 45367d7af7f8SEric Joyner 453771d10453SEric Joyner if (!num_queues) { 453871d10453SEric Joyner /* if queue is disabled already yet the disable queue command 453971d10453SEric Joyner * has to be sent to complete the VF reset, then call 454071d10453SEric Joyner * ice_aq_dis_lan_txq without any queue information 454171d10453SEric Joyner */ 454271d10453SEric Joyner if (rst_src) 45437d7af7f8SEric Joyner return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src, 454471d10453SEric Joyner vmvf_num, NULL); 454571d10453SEric Joyner return ICE_ERR_CFG; 454671d10453SEric Joyner } 454771d10453SEric Joyner 45487d7af7f8SEric Joyner buf_size = ice_struct_size(qg_list, q_id, 1); 45497d7af7f8SEric Joyner qg_list = (struct ice_aqc_dis_txq_item *)ice_malloc(hw, buf_size); 45507d7af7f8SEric Joyner if (!qg_list) 45517d7af7f8SEric Joyner return ICE_ERR_NO_MEMORY; 45527d7af7f8SEric Joyner 455371d10453SEric Joyner ice_acquire_lock(&pi->sched_lock); 455471d10453SEric Joyner 455571d10453SEric Joyner for (i = 0; i < num_queues; i++) { 455671d10453SEric Joyner struct ice_sched_node *node; 455771d10453SEric Joyner 455871d10453SEric Joyner node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); 455971d10453SEric Joyner if (!node) 456071d10453SEric Joyner continue; 45617d7af7f8SEric Joyner q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]); 456271d10453SEric Joyner if (!q_ctx) { 45637d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n", 456471d10453SEric Joyner q_handles[i]); 456571d10453SEric Joyner continue; 456671d10453SEric Joyner } 456771d10453SEric Joyner if (q_ctx->q_handle != q_handles[i]) { 45687d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n", 456971d10453SEric Joyner q_ctx->q_handle, q_handles[i]); 457071d10453SEric Joyner continue; 457171d10453SEric Joyner } 45727d7af7f8SEric Joyner qg_list->parent_teid = node->info.parent_teid; 45737d7af7f8SEric Joyner qg_list->num_qs = 1; 45747d7af7f8SEric Joyner qg_list->q_id[0] = CPU_TO_LE16(q_ids[i]); 45757d7af7f8SEric Joyner status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src, 45767d7af7f8SEric Joyner vmvf_num, cd); 457771d10453SEric Joyner 457871d10453SEric Joyner if (status != ICE_SUCCESS) 457971d10453SEric Joyner break; 458071d10453SEric Joyner ice_free_sched_node(pi, node); 458171d10453SEric Joyner q_ctx->q_handle = ICE_INVAL_Q_HANDLE; 458271d10453SEric Joyner } 458371d10453SEric Joyner ice_release_lock(&pi->sched_lock); 45847d7af7f8SEric Joyner ice_free(hw, qg_list); 458571d10453SEric Joyner return status; 458671d10453SEric Joyner } 458771d10453SEric Joyner 458871d10453SEric Joyner /** 458971d10453SEric Joyner * ice_cfg_vsi_qs - configure the new/existing VSI queues 459071d10453SEric Joyner * @pi: port information structure 459171d10453SEric Joyner * @vsi_handle: software VSI handle 459271d10453SEric Joyner * @tc_bitmap: TC bitmap 459371d10453SEric Joyner * @maxqs: max queues array per TC 459471d10453SEric Joyner * @owner: LAN or RDMA 459571d10453SEric Joyner * 459671d10453SEric Joyner * This function adds/updates the VSI queues per TC. 459771d10453SEric Joyner */ 459871d10453SEric Joyner static enum ice_status 459971d10453SEric Joyner ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 460071d10453SEric Joyner u16 *maxqs, u8 owner) 460171d10453SEric Joyner { 460271d10453SEric Joyner enum ice_status status = ICE_SUCCESS; 460371d10453SEric Joyner u8 i; 460471d10453SEric Joyner 460571d10453SEric Joyner if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) 460671d10453SEric Joyner return ICE_ERR_CFG; 460771d10453SEric Joyner 460871d10453SEric Joyner if (!ice_is_vsi_valid(pi->hw, vsi_handle)) 460971d10453SEric Joyner return ICE_ERR_PARAM; 461071d10453SEric Joyner 461171d10453SEric Joyner ice_acquire_lock(&pi->sched_lock); 461271d10453SEric Joyner 461371d10453SEric Joyner ice_for_each_traffic_class(i) { 461471d10453SEric Joyner /* configuration is possible only if TC node is present */ 461571d10453SEric Joyner if (!ice_sched_get_tc_node(pi, i)) 461671d10453SEric Joyner continue; 461771d10453SEric Joyner 461871d10453SEric Joyner status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner, 461971d10453SEric Joyner ice_is_tc_ena(tc_bitmap, i)); 462071d10453SEric Joyner if (status) 462171d10453SEric Joyner break; 462271d10453SEric Joyner } 462371d10453SEric Joyner 462471d10453SEric Joyner ice_release_lock(&pi->sched_lock); 462571d10453SEric Joyner return status; 462671d10453SEric Joyner } 462771d10453SEric Joyner 462871d10453SEric Joyner /** 462971d10453SEric Joyner * ice_cfg_vsi_lan - configure VSI LAN queues 463071d10453SEric Joyner * @pi: port information structure 463171d10453SEric Joyner * @vsi_handle: software VSI handle 463271d10453SEric Joyner * @tc_bitmap: TC bitmap 463371d10453SEric Joyner * @max_lanqs: max LAN queues array per TC 463471d10453SEric Joyner * 463571d10453SEric Joyner * This function adds/updates the VSI LAN queues per TC. 463671d10453SEric Joyner */ 463771d10453SEric Joyner enum ice_status 463871d10453SEric Joyner ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap, 463971d10453SEric Joyner u16 *max_lanqs) 464071d10453SEric Joyner { 464171d10453SEric Joyner return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs, 464271d10453SEric Joyner ICE_SCHED_NODE_OWNER_LAN); 464371d10453SEric Joyner } 464471d10453SEric Joyner 464571d10453SEric Joyner /** 46467d7af7f8SEric Joyner * ice_is_main_vsi - checks whether the VSI is main VSI 46477d7af7f8SEric Joyner * @hw: pointer to the HW struct 46487d7af7f8SEric Joyner * @vsi_handle: VSI handle 46497d7af7f8SEric Joyner * 46507d7af7f8SEric Joyner * Checks whether the VSI is the main VSI (the first PF VSI created on 46517d7af7f8SEric Joyner * given PF). 46527d7af7f8SEric Joyner */ 46537d7af7f8SEric Joyner static bool ice_is_main_vsi(struct ice_hw *hw, u16 vsi_handle) 46547d7af7f8SEric Joyner { 46557d7af7f8SEric Joyner return vsi_handle == ICE_MAIN_VSI_HANDLE && hw->vsi_ctx[vsi_handle]; 46567d7af7f8SEric Joyner } 46577d7af7f8SEric Joyner 46587d7af7f8SEric Joyner /** 465971d10453SEric Joyner * ice_replay_pre_init - replay pre initialization 466071d10453SEric Joyner * @hw: pointer to the HW struct 46617d7af7f8SEric Joyner * @sw: pointer to switch info struct for which function initializes filters 466271d10453SEric Joyner * 466371d10453SEric Joyner * Initializes required config data for VSI, FD, ACL, and RSS before replay. 466471d10453SEric Joyner */ 46657d7af7f8SEric Joyner static enum ice_status 46667d7af7f8SEric Joyner ice_replay_pre_init(struct ice_hw *hw, struct ice_switch_info *sw) 466771d10453SEric Joyner { 46687d7af7f8SEric Joyner enum ice_status status; 466971d10453SEric Joyner u8 i; 467071d10453SEric Joyner 467171d10453SEric Joyner /* Delete old entries from replay filter list head if there is any */ 46727d7af7f8SEric Joyner ice_rm_sw_replay_rule_info(hw, sw); 467371d10453SEric Joyner /* In start of replay, move entries into replay_rules list, it 467471d10453SEric Joyner * will allow adding rules entries back to filt_rules list, 467571d10453SEric Joyner * which is operational list. 467671d10453SEric Joyner */ 467771d10453SEric Joyner for (i = 0; i < ICE_MAX_NUM_RECIPES; i++) 467871d10453SEric Joyner LIST_REPLACE_INIT(&sw->recp_list[i].filt_rules, 467971d10453SEric Joyner &sw->recp_list[i].filt_replay_rules); 468071d10453SEric Joyner ice_sched_replay_agg_vsi_preinit(hw); 468171d10453SEric Joyner 46827d7af7f8SEric Joyner status = ice_sched_replay_root_node_bw(hw->port_info); 46837d7af7f8SEric Joyner if (status) 46847d7af7f8SEric Joyner return status; 46857d7af7f8SEric Joyner 468671d10453SEric Joyner return ice_sched_replay_tc_node_bw(hw->port_info); 468771d10453SEric Joyner } 468871d10453SEric Joyner 468971d10453SEric Joyner /** 469071d10453SEric Joyner * ice_replay_vsi - replay VSI configuration 469171d10453SEric Joyner * @hw: pointer to the HW struct 469271d10453SEric Joyner * @vsi_handle: driver VSI handle 469371d10453SEric Joyner * 469471d10453SEric Joyner * Restore all VSI configuration after reset. It is required to call this 469571d10453SEric Joyner * function with main VSI first. 469671d10453SEric Joyner */ 469771d10453SEric Joyner enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle) 469871d10453SEric Joyner { 46997d7af7f8SEric Joyner struct ice_switch_info *sw = hw->switch_info; 47007d7af7f8SEric Joyner struct ice_port_info *pi = hw->port_info; 470171d10453SEric Joyner enum ice_status status; 470271d10453SEric Joyner 470371d10453SEric Joyner if (!ice_is_vsi_valid(hw, vsi_handle)) 470471d10453SEric Joyner return ICE_ERR_PARAM; 470571d10453SEric Joyner 470671d10453SEric Joyner /* Replay pre-initialization if there is any */ 47077d7af7f8SEric Joyner if (ice_is_main_vsi(hw, vsi_handle)) { 47087d7af7f8SEric Joyner status = ice_replay_pre_init(hw, sw); 470971d10453SEric Joyner if (status) 471071d10453SEric Joyner return status; 471171d10453SEric Joyner } 471271d10453SEric Joyner /* Replay per VSI all RSS configurations */ 471371d10453SEric Joyner status = ice_replay_rss_cfg(hw, vsi_handle); 471471d10453SEric Joyner if (status) 471571d10453SEric Joyner return status; 471671d10453SEric Joyner /* Replay per VSI all filters */ 47177d7af7f8SEric Joyner status = ice_replay_vsi_all_fltr(hw, pi, vsi_handle); 471871d10453SEric Joyner if (!status) 471971d10453SEric Joyner status = ice_replay_vsi_agg(hw, vsi_handle); 472071d10453SEric Joyner return status; 472171d10453SEric Joyner } 472271d10453SEric Joyner 472371d10453SEric Joyner /** 472471d10453SEric Joyner * ice_replay_post - post replay configuration cleanup 472571d10453SEric Joyner * @hw: pointer to the HW struct 472671d10453SEric Joyner * 472771d10453SEric Joyner * Post replay cleanup. 472871d10453SEric Joyner */ 472971d10453SEric Joyner void ice_replay_post(struct ice_hw *hw) 473071d10453SEric Joyner { 473171d10453SEric Joyner /* Delete old entries from replay filter list head */ 473271d10453SEric Joyner ice_rm_all_sw_replay_rule_info(hw); 473371d10453SEric Joyner ice_sched_replay_agg(hw); 473471d10453SEric Joyner } 473571d10453SEric Joyner 473671d10453SEric Joyner /** 473771d10453SEric Joyner * ice_stat_update40 - read 40 bit stat from the chip and update stat values 473871d10453SEric Joyner * @hw: ptr to the hardware info 473971d10453SEric Joyner * @reg: offset of 64 bit HW register to read from 474071d10453SEric Joyner * @prev_stat_loaded: bool to specify if previous stats are loaded 474171d10453SEric Joyner * @prev_stat: ptr to previous loaded stat value 474271d10453SEric Joyner * @cur_stat: ptr to current stat value 474371d10453SEric Joyner */ 474471d10453SEric Joyner void 474571d10453SEric Joyner ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 474671d10453SEric Joyner u64 *prev_stat, u64 *cur_stat) 474771d10453SEric Joyner { 474871d10453SEric Joyner u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); 474971d10453SEric Joyner 475071d10453SEric Joyner /* device stats are not reset at PFR, they likely will not be zeroed 475171d10453SEric Joyner * when the driver starts. Thus, save the value from the first read 475271d10453SEric Joyner * without adding to the statistic value so that we report stats which 475371d10453SEric Joyner * count up from zero. 475471d10453SEric Joyner */ 475571d10453SEric Joyner if (!prev_stat_loaded) { 475671d10453SEric Joyner *prev_stat = new_data; 475771d10453SEric Joyner return; 475871d10453SEric Joyner } 475971d10453SEric Joyner 476071d10453SEric Joyner /* Calculate the difference between the new and old values, and then 476171d10453SEric Joyner * add it to the software stat value. 476271d10453SEric Joyner */ 476371d10453SEric Joyner if (new_data >= *prev_stat) 476471d10453SEric Joyner *cur_stat += new_data - *prev_stat; 476571d10453SEric Joyner else 476671d10453SEric Joyner /* to manage the potential roll-over */ 476771d10453SEric Joyner *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; 476871d10453SEric Joyner 476971d10453SEric Joyner /* Update the previously stored value to prepare for next read */ 477071d10453SEric Joyner *prev_stat = new_data; 477171d10453SEric Joyner } 477271d10453SEric Joyner 477371d10453SEric Joyner /** 477471d10453SEric Joyner * ice_stat_update32 - read 32 bit stat from the chip and update stat values 477571d10453SEric Joyner * @hw: ptr to the hardware info 477671d10453SEric Joyner * @reg: offset of HW register to read from 477771d10453SEric Joyner * @prev_stat_loaded: bool to specify if previous stats are loaded 477871d10453SEric Joyner * @prev_stat: ptr to previous loaded stat value 477971d10453SEric Joyner * @cur_stat: ptr to current stat value 478071d10453SEric Joyner */ 478171d10453SEric Joyner void 478271d10453SEric Joyner ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded, 478371d10453SEric Joyner u64 *prev_stat, u64 *cur_stat) 478471d10453SEric Joyner { 478571d10453SEric Joyner u32 new_data; 478671d10453SEric Joyner 478771d10453SEric Joyner new_data = rd32(hw, reg); 478871d10453SEric Joyner 478971d10453SEric Joyner /* device stats are not reset at PFR, they likely will not be zeroed 479071d10453SEric Joyner * when the driver starts. Thus, save the value from the first read 479171d10453SEric Joyner * without adding to the statistic value so that we report stats which 479271d10453SEric Joyner * count up from zero. 479371d10453SEric Joyner */ 479471d10453SEric Joyner if (!prev_stat_loaded) { 479571d10453SEric Joyner *prev_stat = new_data; 479671d10453SEric Joyner return; 479771d10453SEric Joyner } 479871d10453SEric Joyner 479971d10453SEric Joyner /* Calculate the difference between the new and old values, and then 480071d10453SEric Joyner * add it to the software stat value. 480171d10453SEric Joyner */ 480271d10453SEric Joyner if (new_data >= *prev_stat) 480371d10453SEric Joyner *cur_stat += new_data - *prev_stat; 480471d10453SEric Joyner else 480571d10453SEric Joyner /* to manage the potential roll-over */ 480671d10453SEric Joyner *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; 480771d10453SEric Joyner 480871d10453SEric Joyner /* Update the previously stored value to prepare for next read */ 480971d10453SEric Joyner *prev_stat = new_data; 481071d10453SEric Joyner } 481171d10453SEric Joyner 481271d10453SEric Joyner /** 481371d10453SEric Joyner * ice_stat_update_repc - read GLV_REPC stats from chip and update stat values 481471d10453SEric Joyner * @hw: ptr to the hardware info 481571d10453SEric Joyner * @vsi_handle: VSI handle 481671d10453SEric Joyner * @prev_stat_loaded: bool to specify if the previous stat values are loaded 481771d10453SEric Joyner * @cur_stats: ptr to current stats structure 481871d10453SEric Joyner * 481971d10453SEric Joyner * The GLV_REPC statistic register actually tracks two 16bit statistics, and 482071d10453SEric Joyner * thus cannot be read using the normal ice_stat_update32 function. 482171d10453SEric Joyner * 482271d10453SEric Joyner * Read the GLV_REPC register associated with the given VSI, and update the 482371d10453SEric Joyner * rx_no_desc and rx_error values in the ice_eth_stats structure. 482471d10453SEric Joyner * 482571d10453SEric Joyner * Because the statistics in GLV_REPC stick at 0xFFFF, the register must be 482671d10453SEric Joyner * cleared each time it's read. 482771d10453SEric Joyner * 482871d10453SEric Joyner * Note that the GLV_RDPC register also counts the causes that would trigger 482971d10453SEric Joyner * GLV_REPC. However, it does not give the finer grained detail about why the 483071d10453SEric Joyner * packets are being dropped. The GLV_REPC values can be used to distinguish 483171d10453SEric Joyner * whether Rx packets are dropped due to errors or due to no available 483271d10453SEric Joyner * descriptors. 483371d10453SEric Joyner */ 483471d10453SEric Joyner void 483571d10453SEric Joyner ice_stat_update_repc(struct ice_hw *hw, u16 vsi_handle, bool prev_stat_loaded, 483671d10453SEric Joyner struct ice_eth_stats *cur_stats) 483771d10453SEric Joyner { 483871d10453SEric Joyner u16 vsi_num, no_desc, error_cnt; 483971d10453SEric Joyner u32 repc; 484071d10453SEric Joyner 484171d10453SEric Joyner if (!ice_is_vsi_valid(hw, vsi_handle)) 484271d10453SEric Joyner return; 484371d10453SEric Joyner 484471d10453SEric Joyner vsi_num = ice_get_hw_vsi_num(hw, vsi_handle); 484571d10453SEric Joyner 484671d10453SEric Joyner /* If we haven't loaded stats yet, just clear the current value */ 484771d10453SEric Joyner if (!prev_stat_loaded) { 484871d10453SEric Joyner wr32(hw, GLV_REPC(vsi_num), 0); 484971d10453SEric Joyner return; 485071d10453SEric Joyner } 485171d10453SEric Joyner 485271d10453SEric Joyner repc = rd32(hw, GLV_REPC(vsi_num)); 485371d10453SEric Joyner no_desc = (repc & GLV_REPC_NO_DESC_CNT_M) >> GLV_REPC_NO_DESC_CNT_S; 485471d10453SEric Joyner error_cnt = (repc & GLV_REPC_ERROR_CNT_M) >> GLV_REPC_ERROR_CNT_S; 485571d10453SEric Joyner 485671d10453SEric Joyner /* Clear the count by writing to the stats register */ 485771d10453SEric Joyner wr32(hw, GLV_REPC(vsi_num), 0); 485871d10453SEric Joyner 485971d10453SEric Joyner cur_stats->rx_no_desc += no_desc; 486071d10453SEric Joyner cur_stats->rx_errors += error_cnt; 486171d10453SEric Joyner } 486271d10453SEric Joyner 486371d10453SEric Joyner /** 486471d10453SEric Joyner * ice_aq_alternate_write 486571d10453SEric Joyner * @hw: pointer to the hardware structure 486671d10453SEric Joyner * @reg_addr0: address of first dword to be written 486771d10453SEric Joyner * @reg_val0: value to be written under 'reg_addr0' 486871d10453SEric Joyner * @reg_addr1: address of second dword to be written 486971d10453SEric Joyner * @reg_val1: value to be written under 'reg_addr1' 487071d10453SEric Joyner * 487171d10453SEric Joyner * Write one or two dwords to alternate structure. Fields are indicated 487271d10453SEric Joyner * by 'reg_addr0' and 'reg_addr1' register numbers. 487371d10453SEric Joyner */ 487471d10453SEric Joyner enum ice_status 487571d10453SEric Joyner ice_aq_alternate_write(struct ice_hw *hw, u32 reg_addr0, u32 reg_val0, 487671d10453SEric Joyner u32 reg_addr1, u32 reg_val1) 487771d10453SEric Joyner { 487871d10453SEric Joyner struct ice_aqc_read_write_alt_direct *cmd; 487971d10453SEric Joyner struct ice_aq_desc desc; 488071d10453SEric Joyner enum ice_status status; 488171d10453SEric Joyner 488271d10453SEric Joyner cmd = &desc.params.read_write_alt_direct; 488371d10453SEric Joyner 488471d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_write_alt_direct); 488571d10453SEric Joyner cmd->dword0_addr = CPU_TO_LE32(reg_addr0); 488671d10453SEric Joyner cmd->dword1_addr = CPU_TO_LE32(reg_addr1); 488771d10453SEric Joyner cmd->dword0_value = CPU_TO_LE32(reg_val0); 488871d10453SEric Joyner cmd->dword1_value = CPU_TO_LE32(reg_val1); 488971d10453SEric Joyner 489071d10453SEric Joyner status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 489171d10453SEric Joyner 489271d10453SEric Joyner return status; 489371d10453SEric Joyner } 489471d10453SEric Joyner 489571d10453SEric Joyner /** 489671d10453SEric Joyner * ice_aq_alternate_read 489771d10453SEric Joyner * @hw: pointer to the hardware structure 489871d10453SEric Joyner * @reg_addr0: address of first dword to be read 489971d10453SEric Joyner * @reg_val0: pointer for data read from 'reg_addr0' 490071d10453SEric Joyner * @reg_addr1: address of second dword to be read 490171d10453SEric Joyner * @reg_val1: pointer for data read from 'reg_addr1' 490271d10453SEric Joyner * 490371d10453SEric Joyner * Read one or two dwords from alternate structure. Fields are indicated 490471d10453SEric Joyner * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 490571d10453SEric Joyner * is not passed then only register at 'reg_addr0' is read. 490671d10453SEric Joyner */ 490771d10453SEric Joyner enum ice_status 490871d10453SEric Joyner ice_aq_alternate_read(struct ice_hw *hw, u32 reg_addr0, u32 *reg_val0, 490971d10453SEric Joyner u32 reg_addr1, u32 *reg_val1) 491071d10453SEric Joyner { 491171d10453SEric Joyner struct ice_aqc_read_write_alt_direct *cmd; 491271d10453SEric Joyner struct ice_aq_desc desc; 491371d10453SEric Joyner enum ice_status status; 491471d10453SEric Joyner 491571d10453SEric Joyner cmd = &desc.params.read_write_alt_direct; 491671d10453SEric Joyner 491771d10453SEric Joyner if (!reg_val0) 491871d10453SEric Joyner return ICE_ERR_PARAM; 491971d10453SEric Joyner 492071d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_alt_direct); 492171d10453SEric Joyner cmd->dword0_addr = CPU_TO_LE32(reg_addr0); 492271d10453SEric Joyner cmd->dword1_addr = CPU_TO_LE32(reg_addr1); 492371d10453SEric Joyner 492471d10453SEric Joyner status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 492571d10453SEric Joyner 492671d10453SEric Joyner if (status == ICE_SUCCESS) { 492771d10453SEric Joyner *reg_val0 = LE32_TO_CPU(cmd->dword0_value); 492871d10453SEric Joyner 492971d10453SEric Joyner if (reg_val1) 493071d10453SEric Joyner *reg_val1 = LE32_TO_CPU(cmd->dword1_value); 493171d10453SEric Joyner } 493271d10453SEric Joyner 493371d10453SEric Joyner return status; 493471d10453SEric Joyner } 493571d10453SEric Joyner 493671d10453SEric Joyner /** 493771d10453SEric Joyner * ice_aq_alternate_write_done 493871d10453SEric Joyner * @hw: pointer to the HW structure. 493971d10453SEric Joyner * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS 494071d10453SEric Joyner * @reset_needed: indicates the SW should trigger GLOBAL reset 494171d10453SEric Joyner * 494271d10453SEric Joyner * Indicates to the FW that alternate structures have been changed. 494371d10453SEric Joyner */ 494471d10453SEric Joyner enum ice_status 494571d10453SEric Joyner ice_aq_alternate_write_done(struct ice_hw *hw, u8 bios_mode, bool *reset_needed) 494671d10453SEric Joyner { 494771d10453SEric Joyner struct ice_aqc_done_alt_write *cmd; 494871d10453SEric Joyner struct ice_aq_desc desc; 494971d10453SEric Joyner enum ice_status status; 495071d10453SEric Joyner 495171d10453SEric Joyner cmd = &desc.params.done_alt_write; 495271d10453SEric Joyner 495371d10453SEric Joyner if (!reset_needed) 495471d10453SEric Joyner return ICE_ERR_PARAM; 495571d10453SEric Joyner 495671d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_done_alt_write); 495771d10453SEric Joyner cmd->flags = bios_mode; 495871d10453SEric Joyner 495971d10453SEric Joyner status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 496071d10453SEric Joyner if (!status) 496171d10453SEric Joyner *reset_needed = (LE16_TO_CPU(cmd->flags) & 496271d10453SEric Joyner ICE_AQC_RESP_RESET_NEEDED) != 0; 496371d10453SEric Joyner 496471d10453SEric Joyner return status; 496571d10453SEric Joyner } 496671d10453SEric Joyner 496771d10453SEric Joyner /** 496871d10453SEric Joyner * ice_aq_alternate_clear 496971d10453SEric Joyner * @hw: pointer to the HW structure. 497071d10453SEric Joyner * 497171d10453SEric Joyner * Clear the alternate structures of the port from which the function 497271d10453SEric Joyner * is called. 497371d10453SEric Joyner */ 497471d10453SEric Joyner enum ice_status ice_aq_alternate_clear(struct ice_hw *hw) 497571d10453SEric Joyner { 497671d10453SEric Joyner struct ice_aq_desc desc; 497771d10453SEric Joyner enum ice_status status; 497871d10453SEric Joyner 497971d10453SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_port_alt_write); 498071d10453SEric Joyner 498171d10453SEric Joyner status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 498271d10453SEric Joyner 498371d10453SEric Joyner return status; 498471d10453SEric Joyner } 498571d10453SEric Joyner 498671d10453SEric Joyner /** 498771d10453SEric Joyner * ice_sched_query_elem - query element information from HW 498871d10453SEric Joyner * @hw: pointer to the HW struct 498971d10453SEric Joyner * @node_teid: node TEID to be queried 499071d10453SEric Joyner * @buf: buffer to element information 499171d10453SEric Joyner * 499271d10453SEric Joyner * This function queries HW element information 499371d10453SEric Joyner */ 499471d10453SEric Joyner enum ice_status 499571d10453SEric Joyner ice_sched_query_elem(struct ice_hw *hw, u32 node_teid, 49967d7af7f8SEric Joyner struct ice_aqc_txsched_elem_data *buf) 499771d10453SEric Joyner { 499871d10453SEric Joyner u16 buf_size, num_elem_ret = 0; 499971d10453SEric Joyner enum ice_status status; 500071d10453SEric Joyner 500171d10453SEric Joyner buf_size = sizeof(*buf); 500271d10453SEric Joyner ice_memset(buf, 0, buf_size, ICE_NONDMA_MEM); 50037d7af7f8SEric Joyner buf->node_teid = CPU_TO_LE32(node_teid); 500471d10453SEric Joyner status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret, 500571d10453SEric Joyner NULL); 500671d10453SEric Joyner if (status != ICE_SUCCESS || num_elem_ret != 1) 500771d10453SEric Joyner ice_debug(hw, ICE_DBG_SCHED, "query element failed\n"); 500871d10453SEric Joyner return status; 500971d10453SEric Joyner } 501071d10453SEric Joyner 501171d10453SEric Joyner /** 501271d10453SEric Joyner * ice_get_fw_mode - returns FW mode 501371d10453SEric Joyner * @hw: pointer to the HW struct 501471d10453SEric Joyner */ 501571d10453SEric Joyner enum ice_fw_modes ice_get_fw_mode(struct ice_hw *hw) 501671d10453SEric Joyner { 501771d10453SEric Joyner #define ICE_FW_MODE_DBG_M BIT(0) 501871d10453SEric Joyner #define ICE_FW_MODE_REC_M BIT(1) 501971d10453SEric Joyner #define ICE_FW_MODE_ROLLBACK_M BIT(2) 502071d10453SEric Joyner u32 fw_mode; 502171d10453SEric Joyner 502271d10453SEric Joyner /* check the current FW mode */ 502371d10453SEric Joyner fw_mode = rd32(hw, GL_MNG_FWSM) & GL_MNG_FWSM_FW_MODES_M; 502471d10453SEric Joyner 502571d10453SEric Joyner if (fw_mode & ICE_FW_MODE_DBG_M) 502671d10453SEric Joyner return ICE_FW_MODE_DBG; 502771d10453SEric Joyner else if (fw_mode & ICE_FW_MODE_REC_M) 502871d10453SEric Joyner return ICE_FW_MODE_REC; 502971d10453SEric Joyner else if (fw_mode & ICE_FW_MODE_ROLLBACK_M) 503071d10453SEric Joyner return ICE_FW_MODE_ROLLBACK; 503171d10453SEric Joyner else 503271d10453SEric Joyner return ICE_FW_MODE_NORMAL; 503371d10453SEric Joyner } 503471d10453SEric Joyner 503571d10453SEric Joyner /** 503671d10453SEric Joyner * ice_cfg_get_cur_lldp_persist_status 503771d10453SEric Joyner * @hw: pointer to the HW struct 503871d10453SEric Joyner * @lldp_status: return value of LLDP persistent status 503971d10453SEric Joyner * 504071d10453SEric Joyner * Get the current status of LLDP persistent 504171d10453SEric Joyner */ 504271d10453SEric Joyner enum ice_status 504371d10453SEric Joyner ice_get_cur_lldp_persist_status(struct ice_hw *hw, u32 *lldp_status) 504471d10453SEric Joyner { 504571d10453SEric Joyner struct ice_port_info *pi = hw->port_info; 504671d10453SEric Joyner enum ice_status ret; 504771d10453SEric Joyner __le32 raw_data; 504871d10453SEric Joyner u32 data, mask; 504971d10453SEric Joyner 505071d10453SEric Joyner if (!lldp_status) 505171d10453SEric Joyner return ICE_ERR_BAD_PTR; 505271d10453SEric Joyner 505371d10453SEric Joyner ret = ice_acquire_nvm(hw, ICE_RES_READ); 505471d10453SEric Joyner if (ret) 505571d10453SEric Joyner return ret; 505671d10453SEric Joyner 505771d10453SEric Joyner ret = ice_aq_read_nvm(hw, ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID, 505871d10453SEric Joyner ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET, 505971d10453SEric Joyner ICE_AQC_NVM_LLDP_STATUS_RD_LEN, &raw_data, 506071d10453SEric Joyner false, true, NULL); 506171d10453SEric Joyner if (!ret) { 506271d10453SEric Joyner data = LE32_TO_CPU(raw_data); 506371d10453SEric Joyner mask = ICE_AQC_NVM_LLDP_STATUS_M << 506471d10453SEric Joyner (ICE_AQC_NVM_LLDP_STATUS_M_LEN * pi->lport); 506571d10453SEric Joyner data = data & mask; 506671d10453SEric Joyner *lldp_status = data >> 506771d10453SEric Joyner (ICE_AQC_NVM_LLDP_STATUS_M_LEN * pi->lport); 506871d10453SEric Joyner } 506971d10453SEric Joyner 507071d10453SEric Joyner ice_release_nvm(hw); 507171d10453SEric Joyner 507271d10453SEric Joyner return ret; 507371d10453SEric Joyner } 507471d10453SEric Joyner 507571d10453SEric Joyner /** 507671d10453SEric Joyner * ice_get_dflt_lldp_persist_status 507771d10453SEric Joyner * @hw: pointer to the HW struct 507871d10453SEric Joyner * @lldp_status: return value of LLDP persistent status 507971d10453SEric Joyner * 508071d10453SEric Joyner * Get the default status of LLDP persistent 508171d10453SEric Joyner */ 508271d10453SEric Joyner enum ice_status 508371d10453SEric Joyner ice_get_dflt_lldp_persist_status(struct ice_hw *hw, u32 *lldp_status) 508471d10453SEric Joyner { 508571d10453SEric Joyner struct ice_port_info *pi = hw->port_info; 508671d10453SEric Joyner u32 data, mask, loc_data, loc_data_tmp; 508771d10453SEric Joyner enum ice_status ret; 508871d10453SEric Joyner __le16 loc_raw_data; 508971d10453SEric Joyner __le32 raw_data; 509071d10453SEric Joyner 509171d10453SEric Joyner if (!lldp_status) 509271d10453SEric Joyner return ICE_ERR_BAD_PTR; 509371d10453SEric Joyner 509471d10453SEric Joyner ret = ice_acquire_nvm(hw, ICE_RES_READ); 509571d10453SEric Joyner if (ret) 509671d10453SEric Joyner return ret; 509771d10453SEric Joyner 509871d10453SEric Joyner /* Read the offset of EMP_SR_PTR */ 509971d10453SEric Joyner ret = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT, 510071d10453SEric Joyner ICE_AQC_NVM_EMP_SR_PTR_OFFSET, 510171d10453SEric Joyner ICE_AQC_NVM_EMP_SR_PTR_RD_LEN, 510271d10453SEric Joyner &loc_raw_data, false, true, NULL); 510371d10453SEric Joyner if (ret) 510471d10453SEric Joyner goto exit; 510571d10453SEric Joyner 510671d10453SEric Joyner loc_data = LE16_TO_CPU(loc_raw_data); 510771d10453SEric Joyner if (loc_data & ICE_AQC_NVM_EMP_SR_PTR_TYPE_M) { 510871d10453SEric Joyner loc_data &= ICE_AQC_NVM_EMP_SR_PTR_M; 510971d10453SEric Joyner loc_data *= ICE_AQC_NVM_SECTOR_UNIT; 511071d10453SEric Joyner } else { 511171d10453SEric Joyner loc_data *= ICE_AQC_NVM_WORD_UNIT; 511271d10453SEric Joyner } 511371d10453SEric Joyner 511471d10453SEric Joyner /* Read the offset of LLDP configuration pointer */ 511571d10453SEric Joyner loc_data += ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET; 511671d10453SEric Joyner ret = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT, loc_data, 511771d10453SEric Joyner ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN, &loc_raw_data, 511871d10453SEric Joyner false, true, NULL); 511971d10453SEric Joyner if (ret) 512071d10453SEric Joyner goto exit; 512171d10453SEric Joyner 512271d10453SEric Joyner loc_data_tmp = LE16_TO_CPU(loc_raw_data); 512371d10453SEric Joyner loc_data_tmp *= ICE_AQC_NVM_WORD_UNIT; 512471d10453SEric Joyner loc_data += loc_data_tmp; 512571d10453SEric Joyner 512671d10453SEric Joyner /* We need to skip LLDP configuration section length (2 bytes) */ 512771d10453SEric Joyner loc_data += ICE_AQC_NVM_LLDP_CFG_HEADER_LEN; 512871d10453SEric Joyner 512971d10453SEric Joyner /* Read the LLDP Default Configure */ 513071d10453SEric Joyner ret = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT, loc_data, 513171d10453SEric Joyner ICE_AQC_NVM_LLDP_STATUS_RD_LEN, &raw_data, false, 513271d10453SEric Joyner true, NULL); 513371d10453SEric Joyner if (!ret) { 513471d10453SEric Joyner data = LE32_TO_CPU(raw_data); 513571d10453SEric Joyner mask = ICE_AQC_NVM_LLDP_STATUS_M << 513671d10453SEric Joyner (ICE_AQC_NVM_LLDP_STATUS_M_LEN * pi->lport); 513771d10453SEric Joyner data = data & mask; 513871d10453SEric Joyner *lldp_status = data >> 513971d10453SEric Joyner (ICE_AQC_NVM_LLDP_STATUS_M_LEN * pi->lport); 514071d10453SEric Joyner } 514171d10453SEric Joyner 514271d10453SEric Joyner exit: 514371d10453SEric Joyner ice_release_nvm(hw); 514471d10453SEric Joyner 514571d10453SEric Joyner return ret; 514671d10453SEric Joyner } 514771d10453SEric Joyner 514871d10453SEric Joyner /** 514971d10453SEric Joyner * ice_fw_supports_link_override 515071d10453SEric Joyner * @hw: pointer to the hardware structure 515171d10453SEric Joyner * 515271d10453SEric Joyner * Checks if the firmware supports link override 515371d10453SEric Joyner */ 515471d10453SEric Joyner bool ice_fw_supports_link_override(struct ice_hw *hw) 515571d10453SEric Joyner { 515671d10453SEric Joyner if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) { 515771d10453SEric Joyner if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN) 515871d10453SEric Joyner return true; 515971d10453SEric Joyner if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN && 516071d10453SEric Joyner hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH) 516171d10453SEric Joyner return true; 516271d10453SEric Joyner } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) { 516371d10453SEric Joyner return true; 516471d10453SEric Joyner } 516571d10453SEric Joyner 516671d10453SEric Joyner return false; 516771d10453SEric Joyner } 516871d10453SEric Joyner 516971d10453SEric Joyner /** 517071d10453SEric Joyner * ice_get_link_default_override 517171d10453SEric Joyner * @ldo: pointer to the link default override struct 517271d10453SEric Joyner * @pi: pointer to the port info struct 517371d10453SEric Joyner * 517471d10453SEric Joyner * Gets the link default override for a port 517571d10453SEric Joyner */ 517671d10453SEric Joyner enum ice_status 517771d10453SEric Joyner ice_get_link_default_override(struct ice_link_default_override_tlv *ldo, 517871d10453SEric Joyner struct ice_port_info *pi) 517971d10453SEric Joyner { 518071d10453SEric Joyner u16 i, tlv, tlv_len, tlv_start, buf, offset; 518171d10453SEric Joyner struct ice_hw *hw = pi->hw; 518271d10453SEric Joyner enum ice_status status; 518371d10453SEric Joyner 518471d10453SEric Joyner status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len, 518571d10453SEric Joyner ICE_SR_LINK_DEFAULT_OVERRIDE_PTR); 518671d10453SEric Joyner if (status) { 51877d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "Failed to read link override TLV.\n"); 518871d10453SEric Joyner return status; 518971d10453SEric Joyner } 519071d10453SEric Joyner 519171d10453SEric Joyner /* Each port has its own config; calculate for our port */ 519271d10453SEric Joyner tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + 519371d10453SEric Joyner ICE_SR_PFA_LINK_OVERRIDE_OFFSET; 519471d10453SEric Joyner 519571d10453SEric Joyner /* link options first */ 519671d10453SEric Joyner status = ice_read_sr_word(hw, tlv_start, &buf); 519771d10453SEric Joyner if (status) { 51987d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 519971d10453SEric Joyner return status; 520071d10453SEric Joyner } 520171d10453SEric Joyner ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M; 520271d10453SEric Joyner ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> 520371d10453SEric Joyner ICE_LINK_OVERRIDE_PHY_CFG_S; 520471d10453SEric Joyner 520571d10453SEric Joyner /* link PHY config */ 520671d10453SEric Joyner offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET; 520771d10453SEric Joyner status = ice_read_sr_word(hw, offset, &buf); 520871d10453SEric Joyner if (status) { 52097d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "Failed to read override phy config.\n"); 521071d10453SEric Joyner return status; 521171d10453SEric Joyner } 521271d10453SEric Joyner ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; 521371d10453SEric Joyner 521471d10453SEric Joyner /* PHY types low */ 521571d10453SEric Joyner offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET; 521671d10453SEric Joyner for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 521771d10453SEric Joyner status = ice_read_sr_word(hw, (offset + i), &buf); 521871d10453SEric Joyner if (status) { 52197d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 522071d10453SEric Joyner return status; 522171d10453SEric Joyner } 522271d10453SEric Joyner /* shift 16 bits at a time to fill 64 bits */ 522371d10453SEric Joyner ldo->phy_type_low |= ((u64)buf << (i * 16)); 522471d10453SEric Joyner } 522571d10453SEric Joyner 522671d10453SEric Joyner /* PHY types high */ 522771d10453SEric Joyner offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET + 522871d10453SEric Joyner ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; 522971d10453SEric Joyner for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) { 523071d10453SEric Joyner status = ice_read_sr_word(hw, (offset + i), &buf); 523171d10453SEric Joyner if (status) { 52327d7af7f8SEric Joyner ice_debug(hw, ICE_DBG_INIT, "Failed to read override link options.\n"); 523371d10453SEric Joyner return status; 523471d10453SEric Joyner } 523571d10453SEric Joyner /* shift 16 bits at a time to fill 64 bits */ 523671d10453SEric Joyner ldo->phy_type_high |= ((u64)buf << (i * 16)); 523771d10453SEric Joyner } 523871d10453SEric Joyner 523971d10453SEric Joyner return status; 524071d10453SEric Joyner } 52417d7af7f8SEric Joyner 52427d7af7f8SEric Joyner /** 52437d7af7f8SEric Joyner * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled 52447d7af7f8SEric Joyner * @caps: get PHY capability data 52457d7af7f8SEric Joyner */ 52467d7af7f8SEric Joyner bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps) 52477d7af7f8SEric Joyner { 52487d7af7f8SEric Joyner if (caps->caps & ICE_AQC_PHY_AN_MODE || 52497d7af7f8SEric Joyner caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | 52507d7af7f8SEric Joyner ICE_AQC_PHY_AN_EN_CLAUSE73 | 52517d7af7f8SEric Joyner ICE_AQC_PHY_AN_EN_CLAUSE37)) 52527d7af7f8SEric Joyner return true; 52537d7af7f8SEric Joyner 52547d7af7f8SEric Joyner return false; 52557d7af7f8SEric Joyner } 52567d7af7f8SEric Joyner 52577d7af7f8SEric Joyner /** 5258*9cf1841cSEric Joyner * ice_is_fw_health_report_supported 5259*9cf1841cSEric Joyner * @hw: pointer to the hardware structure 5260*9cf1841cSEric Joyner * 5261*9cf1841cSEric Joyner * Return true if firmware supports health status reports, 5262*9cf1841cSEric Joyner * false otherwise 5263*9cf1841cSEric Joyner */ 5264*9cf1841cSEric Joyner bool ice_is_fw_health_report_supported(struct ice_hw *hw) 5265*9cf1841cSEric Joyner { 5266*9cf1841cSEric Joyner if (hw->api_maj_ver > ICE_FW_API_HEALTH_REPORT_MAJ) 5267*9cf1841cSEric Joyner return true; 5268*9cf1841cSEric Joyner 5269*9cf1841cSEric Joyner if (hw->api_maj_ver == ICE_FW_API_HEALTH_REPORT_MAJ) { 5270*9cf1841cSEric Joyner if (hw->api_min_ver > ICE_FW_API_HEALTH_REPORT_MIN) 5271*9cf1841cSEric Joyner return true; 5272*9cf1841cSEric Joyner if (hw->api_min_ver == ICE_FW_API_HEALTH_REPORT_MIN && 5273*9cf1841cSEric Joyner hw->api_patch >= ICE_FW_API_HEALTH_REPORT_PATCH) 5274*9cf1841cSEric Joyner return true; 5275*9cf1841cSEric Joyner } 5276*9cf1841cSEric Joyner 5277*9cf1841cSEric Joyner return false; 5278*9cf1841cSEric Joyner } 5279*9cf1841cSEric Joyner 5280*9cf1841cSEric Joyner /** 5281*9cf1841cSEric Joyner * ice_aq_set_health_status_config - Configure FW health events 5282*9cf1841cSEric Joyner * @hw: pointer to the HW struct 5283*9cf1841cSEric Joyner * @event_source: type of diagnostic events to enable 5284*9cf1841cSEric Joyner * @cd: pointer to command details structure or NULL 5285*9cf1841cSEric Joyner * 5286*9cf1841cSEric Joyner * Configure the health status event types that the firmware will send to this 5287*9cf1841cSEric Joyner * PF. The supported event types are: PF-specific, all PFs, and global 5288*9cf1841cSEric Joyner */ 5289*9cf1841cSEric Joyner enum ice_status 5290*9cf1841cSEric Joyner ice_aq_set_health_status_config(struct ice_hw *hw, u8 event_source, 5291*9cf1841cSEric Joyner struct ice_sq_cd *cd) 5292*9cf1841cSEric Joyner { 5293*9cf1841cSEric Joyner struct ice_aqc_set_health_status_config *cmd; 5294*9cf1841cSEric Joyner struct ice_aq_desc desc; 5295*9cf1841cSEric Joyner 5296*9cf1841cSEric Joyner cmd = &desc.params.set_health_status_config; 5297*9cf1841cSEric Joyner 5298*9cf1841cSEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, 5299*9cf1841cSEric Joyner ice_aqc_opc_set_health_status_config); 5300*9cf1841cSEric Joyner 5301*9cf1841cSEric Joyner cmd->event_source = event_source; 5302*9cf1841cSEric Joyner 5303*9cf1841cSEric Joyner return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); 5304*9cf1841cSEric Joyner } 5305*9cf1841cSEric Joyner 5306*9cf1841cSEric Joyner /** 5307*9cf1841cSEric Joyner * ice_aq_get_port_options 5308*9cf1841cSEric Joyner * @hw: pointer to the hw struct 5309*9cf1841cSEric Joyner * @options: buffer for the resultant port options 5310*9cf1841cSEric Joyner * @option_count: input - size of the buffer in port options structures, 5311*9cf1841cSEric Joyner * output - number of returned port options 5312*9cf1841cSEric Joyner * @lport: logical port to call the command with (optional) 5313*9cf1841cSEric Joyner * @lport_valid: when false, FW uses port owned by the PF instead of lport, 5314*9cf1841cSEric Joyner * when PF owns more than 1 port it must be true 5315*9cf1841cSEric Joyner * @active_option_idx: index of active port option in returned buffer 5316*9cf1841cSEric Joyner * @active_option_valid: active option in returned buffer is valid 5317*9cf1841cSEric Joyner * 5318*9cf1841cSEric Joyner * Calls Get Port Options AQC (0x06ea) and verifies result. 5319*9cf1841cSEric Joyner */ 5320*9cf1841cSEric Joyner enum ice_status 5321*9cf1841cSEric Joyner ice_aq_get_port_options(struct ice_hw *hw, 5322*9cf1841cSEric Joyner struct ice_aqc_get_port_options_elem *options, 5323*9cf1841cSEric Joyner u8 *option_count, u8 lport, bool lport_valid, 5324*9cf1841cSEric Joyner u8 *active_option_idx, bool *active_option_valid) 5325*9cf1841cSEric Joyner { 5326*9cf1841cSEric Joyner struct ice_aqc_get_port_options *cmd; 5327*9cf1841cSEric Joyner struct ice_aq_desc desc; 5328*9cf1841cSEric Joyner enum ice_status status; 5329*9cf1841cSEric Joyner u8 pmd_count; 5330*9cf1841cSEric Joyner u8 max_speed; 5331*9cf1841cSEric Joyner u8 i; 5332*9cf1841cSEric Joyner 5333*9cf1841cSEric Joyner ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); 5334*9cf1841cSEric Joyner 5335*9cf1841cSEric Joyner /* options buffer shall be able to hold max returned options */ 5336*9cf1841cSEric Joyner if (*option_count < ICE_AQC_PORT_OPT_COUNT_M) 5337*9cf1841cSEric Joyner return ICE_ERR_PARAM; 5338*9cf1841cSEric Joyner 5339*9cf1841cSEric Joyner cmd = &desc.params.get_port_options; 5340*9cf1841cSEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_port_options); 5341*9cf1841cSEric Joyner 5342*9cf1841cSEric Joyner if (lport_valid) 5343*9cf1841cSEric Joyner cmd->lport_num = lport; 5344*9cf1841cSEric Joyner cmd->lport_num_valid = lport_valid; 5345*9cf1841cSEric Joyner 5346*9cf1841cSEric Joyner status = ice_aq_send_cmd(hw, &desc, options, 5347*9cf1841cSEric Joyner *option_count * sizeof(*options), NULL); 5348*9cf1841cSEric Joyner if (status != ICE_SUCCESS) 5349*9cf1841cSEric Joyner return status; 5350*9cf1841cSEric Joyner 5351*9cf1841cSEric Joyner /* verify direct FW response & set output parameters */ 5352*9cf1841cSEric Joyner *option_count = cmd->port_options_count & ICE_AQC_PORT_OPT_COUNT_M; 5353*9cf1841cSEric Joyner ice_debug(hw, ICE_DBG_PHY, "options: %x\n", *option_count); 5354*9cf1841cSEric Joyner *active_option_valid = cmd->port_options & ICE_AQC_PORT_OPT_VALID; 5355*9cf1841cSEric Joyner if (*active_option_valid) { 5356*9cf1841cSEric Joyner *active_option_idx = cmd->port_options & 5357*9cf1841cSEric Joyner ICE_AQC_PORT_OPT_ACTIVE_M; 5358*9cf1841cSEric Joyner if (*active_option_idx > (*option_count - 1)) 5359*9cf1841cSEric Joyner return ICE_ERR_OUT_OF_RANGE; 5360*9cf1841cSEric Joyner ice_debug(hw, ICE_DBG_PHY, "active idx: %x\n", 5361*9cf1841cSEric Joyner *active_option_idx); 5362*9cf1841cSEric Joyner } 5363*9cf1841cSEric Joyner 5364*9cf1841cSEric Joyner /* verify indirect FW response & mask output options fields */ 5365*9cf1841cSEric Joyner for (i = 0; i < *option_count; i++) { 5366*9cf1841cSEric Joyner options[i].pmd &= ICE_AQC_PORT_OPT_PMD_COUNT_M; 5367*9cf1841cSEric Joyner options[i].max_lane_speed &= ICE_AQC_PORT_OPT_MAX_LANE_M; 5368*9cf1841cSEric Joyner pmd_count = options[i].pmd; 5369*9cf1841cSEric Joyner max_speed = options[i].max_lane_speed; 5370*9cf1841cSEric Joyner ice_debug(hw, ICE_DBG_PHY, "pmds: %x max speed: %x\n", 5371*9cf1841cSEric Joyner pmd_count, max_speed); 5372*9cf1841cSEric Joyner 5373*9cf1841cSEric Joyner /* check only entries containing valid max pmd speed values, 5374*9cf1841cSEric Joyner * other reserved values may be returned, when logical port 5375*9cf1841cSEric Joyner * used is unrelated to specific option 5376*9cf1841cSEric Joyner */ 5377*9cf1841cSEric Joyner if (max_speed <= ICE_AQC_PORT_OPT_MAX_LANE_100G) { 5378*9cf1841cSEric Joyner if (pmd_count > ICE_MAX_PORT_PER_PCI_DEV) 5379*9cf1841cSEric Joyner return ICE_ERR_OUT_OF_RANGE; 5380*9cf1841cSEric Joyner if (pmd_count > 2 && 5381*9cf1841cSEric Joyner max_speed > ICE_AQC_PORT_OPT_MAX_LANE_25G) 5382*9cf1841cSEric Joyner return ICE_ERR_CFG; 5383*9cf1841cSEric Joyner if (pmd_count > 7 && 5384*9cf1841cSEric Joyner max_speed > ICE_AQC_PORT_OPT_MAX_LANE_10G) 5385*9cf1841cSEric Joyner return ICE_ERR_CFG; 5386*9cf1841cSEric Joyner } 5387*9cf1841cSEric Joyner } 5388*9cf1841cSEric Joyner 5389*9cf1841cSEric Joyner return ICE_SUCCESS; 5390*9cf1841cSEric Joyner } 5391*9cf1841cSEric Joyner 5392*9cf1841cSEric Joyner /** 53937d7af7f8SEric Joyner * ice_aq_set_lldp_mib - Set the LLDP MIB 53947d7af7f8SEric Joyner * @hw: pointer to the HW struct 53957d7af7f8SEric Joyner * @mib_type: Local, Remote or both Local and Remote MIBs 53967d7af7f8SEric Joyner * @buf: pointer to the caller-supplied buffer to store the MIB block 53977d7af7f8SEric Joyner * @buf_size: size of the buffer (in bytes) 53987d7af7f8SEric Joyner * @cd: pointer to command details structure or NULL 53997d7af7f8SEric Joyner * 54007d7af7f8SEric Joyner * Set the LLDP MIB. (0x0A08) 54017d7af7f8SEric Joyner */ 54027d7af7f8SEric Joyner enum ice_status 54037d7af7f8SEric Joyner ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size, 54047d7af7f8SEric Joyner struct ice_sq_cd *cd) 54057d7af7f8SEric Joyner { 54067d7af7f8SEric Joyner struct ice_aqc_lldp_set_local_mib *cmd; 54077d7af7f8SEric Joyner struct ice_aq_desc desc; 54087d7af7f8SEric Joyner 54097d7af7f8SEric Joyner cmd = &desc.params.lldp_set_mib; 54107d7af7f8SEric Joyner 54117d7af7f8SEric Joyner if (buf_size == 0 || !buf) 54127d7af7f8SEric Joyner return ICE_ERR_PARAM; 54137d7af7f8SEric Joyner 54147d7af7f8SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib); 54157d7af7f8SEric Joyner 54167d7af7f8SEric Joyner desc.flags |= CPU_TO_LE16((u16)ICE_AQ_FLAG_RD); 54177d7af7f8SEric Joyner desc.datalen = CPU_TO_LE16(buf_size); 54187d7af7f8SEric Joyner 54197d7af7f8SEric Joyner cmd->type = mib_type; 54207d7af7f8SEric Joyner cmd->length = CPU_TO_LE16(buf_size); 54217d7af7f8SEric Joyner 54227d7af7f8SEric Joyner return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); 54237d7af7f8SEric Joyner } 54247d7af7f8SEric Joyner 54257d7af7f8SEric Joyner /** 54267d7af7f8SEric Joyner * ice_fw_supports_lldp_fltr - check NVM version supports lldp_fltr_ctrl 54277d7af7f8SEric Joyner * @hw: pointer to HW struct 54287d7af7f8SEric Joyner */ 54297d7af7f8SEric Joyner bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) 54307d7af7f8SEric Joyner { 54317d7af7f8SEric Joyner if (hw->mac_type != ICE_MAC_E810) 54327d7af7f8SEric Joyner return false; 54337d7af7f8SEric Joyner 54347d7af7f8SEric Joyner if (hw->api_maj_ver == ICE_FW_API_LLDP_FLTR_MAJ) { 54357d7af7f8SEric Joyner if (hw->api_min_ver > ICE_FW_API_LLDP_FLTR_MIN) 54367d7af7f8SEric Joyner return true; 54377d7af7f8SEric Joyner if (hw->api_min_ver == ICE_FW_API_LLDP_FLTR_MIN && 54387d7af7f8SEric Joyner hw->api_patch >= ICE_FW_API_LLDP_FLTR_PATCH) 54397d7af7f8SEric Joyner return true; 54407d7af7f8SEric Joyner } else if (hw->api_maj_ver > ICE_FW_API_LLDP_FLTR_MAJ) { 54417d7af7f8SEric Joyner return true; 54427d7af7f8SEric Joyner } 54437d7af7f8SEric Joyner return false; 54447d7af7f8SEric Joyner } 54457d7af7f8SEric Joyner 54467d7af7f8SEric Joyner /** 54477d7af7f8SEric Joyner * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter 54487d7af7f8SEric Joyner * @hw: pointer to HW struct 54497d7af7f8SEric Joyner * @vsi_num: absolute HW index for VSI 54507d7af7f8SEric Joyner * @add: boolean for if adding or removing a filter 54517d7af7f8SEric Joyner */ 54527d7af7f8SEric Joyner enum ice_status 54537d7af7f8SEric Joyner ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add) 54547d7af7f8SEric Joyner { 54557d7af7f8SEric Joyner struct ice_aqc_lldp_filter_ctrl *cmd; 54567d7af7f8SEric Joyner struct ice_aq_desc desc; 54577d7af7f8SEric Joyner 54587d7af7f8SEric Joyner cmd = &desc.params.lldp_filter_ctrl; 54597d7af7f8SEric Joyner 54607d7af7f8SEric Joyner ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); 54617d7af7f8SEric Joyner 54627d7af7f8SEric Joyner if (add) 54637d7af7f8SEric Joyner cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; 54647d7af7f8SEric Joyner else 54657d7af7f8SEric Joyner cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; 54667d7af7f8SEric Joyner 54677d7af7f8SEric Joyner cmd->vsi_num = CPU_TO_LE16(vsi_num); 54687d7af7f8SEric Joyner 54697d7af7f8SEric Joyner return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 54707d7af7f8SEric Joyner } 5471*9cf1841cSEric Joyner 5472*9cf1841cSEric Joyner /** 5473*9cf1841cSEric Joyner * ice_fw_supports_report_dflt_cfg 5474*9cf1841cSEric Joyner * @hw: pointer to the hardware structure 5475*9cf1841cSEric Joyner * 5476*9cf1841cSEric Joyner * Checks if the firmware supports report default configuration 5477*9cf1841cSEric Joyner */ 5478*9cf1841cSEric Joyner bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw) 5479*9cf1841cSEric Joyner { 5480*9cf1841cSEric Joyner if (hw->api_maj_ver == ICE_FW_API_REPORT_DFLT_CFG_MAJ) { 5481*9cf1841cSEric Joyner if (hw->api_min_ver > ICE_FW_API_REPORT_DFLT_CFG_MIN) 5482*9cf1841cSEric Joyner return true; 5483*9cf1841cSEric Joyner if (hw->api_min_ver == ICE_FW_API_REPORT_DFLT_CFG_MIN && 5484*9cf1841cSEric Joyner hw->api_patch >= ICE_FW_API_REPORT_DFLT_CFG_PATCH) 5485*9cf1841cSEric Joyner return true; 5486*9cf1841cSEric Joyner } else if (hw->api_maj_ver > ICE_FW_API_REPORT_DFLT_CFG_MAJ) { 5487*9cf1841cSEric Joyner return true; 5488*9cf1841cSEric Joyner } 5489*9cf1841cSEric Joyner return false; 5490*9cf1841cSEric Joyner } 5491