1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2021, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*$FreeBSD$*/ 32 33 #ifndef _ICE_ADMINQ_CMD_H_ 34 #define _ICE_ADMINQ_CMD_H_ 35 36 /* This header file defines the Admin Queue commands, error codes and 37 * descriptor format. It is shared between Firmware and Software. 38 */ 39 40 #define ICE_MAX_VSI 768 41 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 42 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 43 44 struct ice_aqc_generic { 45 __le32 param0; 46 __le32 param1; 47 __le32 addr_high; 48 __le32 addr_low; 49 }; 50 51 /* Get version (direct 0x0001) */ 52 struct ice_aqc_get_ver { 53 __le32 rom_ver; 54 __le32 fw_build; 55 u8 fw_branch; 56 u8 fw_major; 57 u8 fw_minor; 58 u8 fw_patch; 59 u8 api_branch; 60 u8 api_major; 61 u8 api_minor; 62 u8 api_patch; 63 }; 64 65 /* Send driver version (indirect 0x0002) */ 66 struct ice_aqc_driver_ver { 67 u8 major_ver; 68 u8 minor_ver; 69 u8 build_ver; 70 u8 subbuild_ver; 71 u8 reserved[4]; 72 __le32 addr_high; 73 __le32 addr_low; 74 }; 75 76 /* Queue Shutdown (direct 0x0003) */ 77 struct ice_aqc_q_shutdown { 78 u8 driver_unloading; 79 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 80 u8 reserved[15]; 81 }; 82 83 /* Get Expanded Error Code (0x0005, direct) */ 84 struct ice_aqc_get_exp_err { 85 __le32 reason; 86 #define ICE_AQC_EXPANDED_ERROR_NOT_PROVIDED 0xFFFFFFFF 87 __le32 identifier; 88 u8 rsvd[8]; 89 }; 90 91 /* Request resource ownership (direct 0x0008) 92 * Release resource ownership (direct 0x0009) 93 */ 94 struct ice_aqc_req_res { 95 __le16 res_id; 96 #define ICE_AQC_RES_ID_NVM 1 97 #define ICE_AQC_RES_ID_SDP 2 98 #define ICE_AQC_RES_ID_CHNG_LOCK 3 99 #define ICE_AQC_RES_ID_GLBL_LOCK 4 100 __le16 access_type; 101 #define ICE_AQC_RES_ACCESS_READ 1 102 #define ICE_AQC_RES_ACCESS_WRITE 2 103 104 /* Upon successful completion, FW writes this value and driver is 105 * expected to release resource before timeout. This value is provided 106 * in milliseconds. 107 */ 108 __le32 timeout; 109 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 110 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 111 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 112 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 113 /* For SDP: pin ID of the SDP */ 114 __le32 res_number; 115 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 116 __le16 status; 117 #define ICE_AQ_RES_GLBL_SUCCESS 0 118 #define ICE_AQ_RES_GLBL_IN_PROG 1 119 #define ICE_AQ_RES_GLBL_DONE 2 120 u8 reserved[2]; 121 }; 122 123 /* Get function capabilities (indirect 0x000A) 124 * Get device capabilities (indirect 0x000B) 125 */ 126 struct ice_aqc_list_caps { 127 u8 cmd_flags; 128 u8 pf_index; 129 u8 reserved[2]; 130 __le32 count; 131 __le32 addr_high; 132 __le32 addr_low; 133 }; 134 135 /* Device/Function buffer entry, repeated per reported capability */ 136 struct ice_aqc_list_caps_elem { 137 __le16 cap; 138 #define ICE_AQC_CAPS_SWITCHING_MODE 0x0001 139 #define ICE_AQC_CAPS_MANAGEABILITY_MODE 0x0002 140 #define ICE_AQC_CAPS_OS2BMC 0x0004 141 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 142 #define ICE_AQC_MAX_VALID_FUNCTIONS 0x8 143 #define ICE_AQC_CAPS_ALTERNATE_RAM 0x0006 144 #define ICE_AQC_CAPS_WOL_PROXY 0x0008 145 #define ICE_AQC_CAPS_SRIOV 0x0012 146 #define ICE_AQC_CAPS_VF 0x0013 147 #define ICE_AQC_CAPS_802_1QBG 0x0015 148 #define ICE_AQC_CAPS_802_1BR 0x0016 149 #define ICE_AQC_CAPS_VSI 0x0017 150 #define ICE_AQC_CAPS_DCB 0x0018 151 #define ICE_AQC_CAPS_RSVD 0x0021 152 #define ICE_AQC_CAPS_ISCSI 0x0022 153 #define ICE_AQC_CAPS_RSS 0x0040 154 #define ICE_AQC_CAPS_RXQS 0x0041 155 #define ICE_AQC_CAPS_TXQS 0x0042 156 #define ICE_AQC_CAPS_MSIX 0x0043 157 #define ICE_AQC_CAPS_MAX_MTU 0x0047 158 #define ICE_AQC_CAPS_NVM_VER 0x0048 159 #define ICE_AQC_CAPS_OROM_VER 0x004A 160 #define ICE_AQC_CAPS_NET_VER 0x004C 161 #define ICE_AQC_CAPS_CEM 0x00F2 162 #define ICE_AQC_CAPS_IWARP 0x0051 163 #define ICE_AQC_CAPS_LED 0x0061 164 #define ICE_AQC_CAPS_SDP 0x0062 165 #define ICE_AQC_CAPS_WR_CSR_PROT 0x0064 166 #define ICE_AQC_CAPS_LOGI_TO_PHYSI_PORT_MAP 0x0073 167 #define ICE_AQC_CAPS_SKU 0x0074 168 #define ICE_AQC_CAPS_PORT_MAP 0x0075 169 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 170 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 171 172 u8 major_ver; 173 u8 minor_ver; 174 /* Number of resources described by this capability */ 175 __le32 number; 176 /* Only meaningful for some types of resources */ 177 __le32 logical_id; 178 /* Only meaningful for some types of resources */ 179 __le32 phys_id; 180 __le64 rsvd1; 181 __le64 rsvd2; 182 }; 183 184 /* Manage MAC address, read command - indirect (0x0107) 185 * This struct is also used for the response 186 */ 187 struct ice_aqc_manage_mac_read { 188 __le16 flags; /* Zeroed by device driver */ 189 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 190 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 191 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 192 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 193 #define ICE_AQC_MAN_MAC_MC_MAG_EN BIT(8) 194 #define ICE_AQC_MAN_MAC_WOL_PRESERVE_ON_PFR BIT(9) 195 #define ICE_AQC_MAN_MAC_READ_S 4 196 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 197 u8 rsvd[2]; 198 u8 num_addr; /* Used in response */ 199 u8 rsvd1[3]; 200 __le32 addr_high; 201 __le32 addr_low; 202 }; 203 204 /* Response buffer format for manage MAC read command */ 205 struct ice_aqc_manage_mac_read_resp { 206 u8 lport_num; 207 u8 addr_type; 208 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 209 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 210 u8 mac_addr[ETH_ALEN]; 211 }; 212 213 /* Manage MAC address, write command - direct (0x0108) */ 214 struct ice_aqc_manage_mac_write { 215 u8 rsvd; 216 u8 flags; 217 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 218 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 219 #define ICE_AQC_MAN_MAC_WR_S 6 220 #define ICE_AQC_MAN_MAC_WR_M MAKEMASK(3, ICE_AQC_MAN_MAC_WR_S) 221 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 222 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 223 /* byte stream in network order */ 224 u8 mac_addr[ETH_ALEN]; 225 __le32 addr_high; 226 __le32 addr_low; 227 }; 228 229 /* Clear PXE Command and response (direct 0x0110) */ 230 struct ice_aqc_clear_pxe { 231 u8 rx_cnt; 232 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 233 u8 reserved[15]; 234 }; 235 236 /* Configure No-Drop Policy Command (direct 0x0112) */ 237 struct ice_aqc_config_no_drop_policy { 238 u8 opts; 239 #define ICE_AQC_FORCE_NO_DROP BIT(0) 240 u8 rsvd[15]; 241 }; 242 243 /* Get switch configuration (0x0200) */ 244 struct ice_aqc_get_sw_cfg { 245 /* Reserved for command and copy of request flags for response */ 246 __le16 flags; 247 /* First desc in case of command and next_elem in case of response 248 * In case of response, if it is not zero, means all the configuration 249 * was not returned and new command shall be sent with this value in 250 * the 'first desc' field 251 */ 252 __le16 element; 253 /* Reserved for command, only used for response */ 254 __le16 num_elems; 255 __le16 rsvd; 256 __le32 addr_high; 257 __le32 addr_low; 258 }; 259 260 /* Each entry in the response buffer is of the following type: */ 261 struct ice_aqc_get_sw_cfg_resp_elem { 262 /* VSI/Port Number */ 263 __le16 vsi_port_num; 264 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 265 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 266 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 267 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 268 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 269 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 270 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 271 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 272 273 /* SWID VSI/Port belongs to */ 274 __le16 swid; 275 276 /* Bit 14..0 : PF/VF number VSI belongs to 277 * Bit 15 : VF indication bit 278 */ 279 __le16 pf_vf_num; 280 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 281 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 282 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 283 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 284 }; 285 286 /* Set Port parameters, (direct, 0x0203) */ 287 struct ice_aqc_set_port_params { 288 __le16 cmd_flags; 289 #define ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS BIT(0) 290 #define ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS BIT(1) 291 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2) 292 __le16 bad_frame_vsi; 293 #define ICE_AQC_SET_P_PARAMS_VSI_S 0 294 #define ICE_AQC_SET_P_PARAMS_VSI_M (0x3FF << ICE_AQC_SET_P_PARAMS_VSI_S) 295 #define ICE_AQC_SET_P_PARAMS_VSI_VALID BIT(15) 296 __le16 swid; 297 #define ICE_AQC_SET_P_PARAMS_SWID_S 0 298 #define ICE_AQC_SET_P_PARAMS_SWID_M (0xFF << ICE_AQC_SET_P_PARAMS_SWID_S) 299 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S 8 300 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_M \ 301 (0x3F << ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S) 302 #define ICE_AQC_SET_P_PARAMS_IS_LOGI_PORT BIT(14) 303 #define ICE_AQC_SET_P_PARAMS_SWID_VALID BIT(15) 304 u8 reserved[10]; 305 }; 306 307 /* These resource type defines are used for all switch resource 308 * commands where a resource type is required, such as: 309 * Get Resource Allocation command (indirect 0x0204) 310 * Allocate Resources command (indirect 0x0208) 311 * Free Resources command (indirect 0x0209) 312 * Get Allocated Resource Descriptors Command (indirect 0x020A) 313 */ 314 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00 315 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01 316 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02 317 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 318 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 319 #define ICE_AQC_RES_TYPE_RECIPE 0x05 320 #define ICE_AQC_RES_TYPE_PROFILE 0x06 321 #define ICE_AQC_RES_TYPE_SWID 0x07 322 #define ICE_AQC_RES_TYPE_VSI 0x08 323 #define ICE_AQC_RES_TYPE_FLU 0x09 324 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A 325 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B 326 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C 327 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20 328 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 329 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 330 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 331 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30 332 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48 333 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49 334 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50 335 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51 336 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 337 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 338 /* Resource types 0x62-67 are reserved for Hash profile builder */ 339 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68 340 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69 341 342 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7) 343 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 344 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 345 346 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 347 348 #define ICE_AQC_RES_TYPE_S 0 349 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 350 351 /* Get Resource Allocation command (indirect 0x0204) */ 352 struct ice_aqc_get_res_alloc { 353 __le16 resp_elem_num; /* Used in response, reserved in command */ 354 u8 reserved[6]; 355 __le32 addr_high; 356 __le32 addr_low; 357 }; 358 359 /* Get Resource Allocation Response Buffer per response */ 360 struct ice_aqc_get_res_resp_elem { 361 __le16 res_type; /* Types defined above cmd 0x0204 */ 362 __le16 total_capacity; /* Resources available to all PF's */ 363 __le16 total_function; /* Resources allocated for a PF */ 364 __le16 total_shared; /* Resources allocated as shared */ 365 __le16 total_free; /* Resources un-allocated/not reserved by any PF */ 366 }; 367 368 /* Allocate Resources command (indirect 0x0208) 369 * Free Resources command (indirect 0x0209) 370 */ 371 struct ice_aqc_alloc_free_res_cmd { 372 __le16 num_entries; /* Number of Resource entries */ 373 u8 reserved[6]; 374 __le32 addr_high; 375 __le32 addr_low; 376 }; 377 378 /* Resource descriptor */ 379 struct ice_aqc_res_elem { 380 union { 381 __le16 sw_resp; 382 __le16 flu_resp; 383 } e; 384 }; 385 386 /* Buffer for Allocate/Free Resources commands */ 387 struct ice_aqc_alloc_free_res_elem { 388 __le16 res_type; /* Types defined above cmd 0x0204 */ 389 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 390 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 391 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 392 __le16 num_elems; 393 struct ice_aqc_res_elem elem[STRUCT_HACK_VAR_LEN]; 394 }; 395 396 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */ 397 struct ice_aqc_get_allocd_res_desc { 398 union { 399 struct { 400 __le16 res; /* Types defined above cmd 0x0204 */ 401 __le16 first_desc; 402 __le32 reserved; 403 } cmd; 404 struct { 405 __le16 res; 406 __le16 next_desc; 407 __le16 num_desc; 408 __le16 reserved; 409 } resp; 410 } ops; 411 __le32 addr_high; 412 __le32 addr_low; 413 }; 414 415 /* Add VSI (indirect 0x0210) 416 * Update VSI (indirect 0x0211) 417 * Get VSI (indirect 0x0212) 418 * Free VSI (indirect 0x0213) 419 */ 420 struct ice_aqc_add_get_update_free_vsi { 421 __le16 vsi_num; 422 #define ICE_AQ_VSI_NUM_S 0 423 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 424 #define ICE_AQ_VSI_IS_VALID BIT(15) 425 __le16 cmd_flags; 426 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 427 u8 vf_id; 428 u8 reserved; 429 __le16 vsi_flags; 430 #define ICE_AQ_VSI_TYPE_S 0 431 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 432 #define ICE_AQ_VSI_TYPE_VF 0x0 433 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 434 #define ICE_AQ_VSI_TYPE_PF 0x2 435 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 436 __le32 addr_high; 437 __le32 addr_low; 438 }; 439 440 /* Response descriptor for: 441 * Add VSI (indirect 0x0210) 442 * Update VSI (indirect 0x0211) 443 * Free VSI (indirect 0x0213) 444 */ 445 struct ice_aqc_add_update_free_vsi_resp { 446 __le16 vsi_num; 447 __le16 ext_status; 448 __le16 vsi_used; 449 __le16 vsi_free; 450 __le32 addr_high; 451 __le32 addr_low; 452 }; 453 454 struct ice_aqc_get_vsi_resp { 455 __le16 vsi_num; 456 u8 vf_id; 457 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values. 458 * These are found above in struct ice_aqc_add_get_update_free_vsi. 459 */ 460 u8 vsi_flags; 461 __le16 vsi_used; 462 __le16 vsi_free; 463 __le32 addr_high; 464 __le32 addr_low; 465 }; 466 467 struct ice_aqc_vsi_props { 468 __le16 valid_sections; 469 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 470 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 471 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 472 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 473 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 474 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 475 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 476 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 477 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 478 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 479 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 480 /* switch section */ 481 u8 sw_id; 482 u8 sw_flags; 483 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 484 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 485 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 486 u8 sw_flags2; 487 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 488 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \ 489 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 490 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 491 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 492 u8 veb_stat_id; 493 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 494 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 495 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 496 /* security section */ 497 u8 sec_flags; 498 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 499 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 500 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 501 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 502 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 503 u8 sec_reserved; 504 /* VLAN section */ 505 __le16 pvid; /* VLANS include priority bits */ 506 u8 pvlan_reserved[2]; 507 u8 vlan_flags; 508 #define ICE_AQ_VSI_VLAN_MODE_S 0 509 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S) 510 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1 511 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2 512 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3 513 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2) 514 #define ICE_AQ_VSI_VLAN_EMOD_S 3 515 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 516 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S) 517 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S) 518 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S) 519 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 520 u8 pvlan_reserved2[3]; 521 /* ingress egress up sections */ 522 __le32 ingress_table; /* bitmap, 3 bits per up */ 523 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 524 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 525 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 526 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 527 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 528 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 529 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 530 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 531 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 532 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 533 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 534 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 535 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 536 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 537 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 538 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 539 __le32 egress_table; /* same defines as for ingress table */ 540 /* outer tags section */ 541 __le16 outer_tag; 542 u8 outer_tag_flags; 543 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0 544 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S) 545 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0 546 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1 547 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2 548 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 549 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 550 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 551 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 552 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 553 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 554 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4) 555 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6) 556 u8 outer_tag_reserved; 557 /* queue mapping section */ 558 __le16 mapping_flags; 559 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 560 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 561 __le16 q_mapping[16]; 562 #define ICE_AQ_VSI_Q_S 0 563 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 564 __le16 tc_mapping[8]; 565 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 566 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 567 #define ICE_AQ_VSI_TC_Q_NUM_S 11 568 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 569 /* queueing option section */ 570 u8 q_opt_rss; 571 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 572 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 573 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 574 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 575 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 576 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 577 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 578 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 579 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 580 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 581 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 582 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 583 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 584 u8 q_opt_tc; 585 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 586 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 587 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 588 u8 q_opt_flags; 589 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 590 u8 q_opt_reserved[3]; 591 /* outer up section */ 592 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 593 /* section 10 */ 594 __le16 sect_10_reserved; 595 /* flow director section */ 596 __le16 fd_options; 597 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 598 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 599 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 600 __le16 max_fd_fltr_dedicated; 601 __le16 max_fd_fltr_shared; 602 __le16 fd_def_q; 603 #define ICE_AQ_VSI_FD_DEF_Q_S 0 604 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 605 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 606 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 607 __le16 fd_report_opt; 608 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 609 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 610 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 611 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 612 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 613 /* PASID section */ 614 __le32 pasid_id; 615 #define ICE_AQ_VSI_PASID_ID_S 0 616 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 617 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 618 u8 reserved[24]; 619 }; 620 621 /* Add/update mirror rule - direct (0x0260) */ 622 #define ICE_AQC_RULE_ID_VALID_S 7 623 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S) 624 #define ICE_AQC_RULE_ID_S 0 625 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S) 626 627 /* Following defines to be used while processing caller specified mirror list 628 * of VSI indexes. 629 */ 630 /* Action: Byte.bit (1.7) 631 * 0 = Remove VSI from mirror rule 632 * 1 = Add VSI to mirror rule 633 */ 634 #define ICE_AQC_RULE_ACT_S 15 635 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S) 636 /* Action: 1.2:0.0 = Mirrored VSI */ 637 #define ICE_AQC_RULE_MIRRORED_VSI_S 0 638 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S) 639 640 /* This is to be used by add/update mirror rule Admin Queue command. 641 * In case of add mirror rule - if rule ID is specified as 642 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool. 643 * If specified rule_id is valid, then it is used. If specified rule_id 644 * is in use then new mirroring rule is added. 645 */ 646 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF 647 648 struct ice_aqc_add_update_mir_rule { 649 __le16 rule_id; 650 651 __le16 rule_type; 652 #define ICE_AQC_RULE_TYPE_S 0 653 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S) 654 /* VPORT ingress/egress */ 655 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1 656 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2 657 /* Physical port ingress mirroring. 658 * All traffic received by this port 659 */ 660 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6 661 /* Physical port egress mirroring. All traffic sent by this port */ 662 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7 663 664 /* Number of mirrored entries. 665 * The values are in the command buffer 666 */ 667 __le16 num_entries; 668 669 /* Destination VSI */ 670 __le16 dest; 671 __le32 addr_high; 672 __le32 addr_low; 673 }; 674 675 /* Delete mirror rule - direct(0x0261) */ 676 struct ice_aqc_delete_mir_rule { 677 __le16 rule_id; 678 __le16 rsvd; 679 680 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of 681 * the PF allocated resources, otherwise it is returned to the 682 * shared pool 683 */ 684 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0 685 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S) 686 __le16 flags; 687 688 u8 reserved[10]; 689 }; 690 691 /* Set/Get storm config - (direct 0x0280, 0x0281) */ 692 /* This structure holds get storm configuration response and same structure 693 * is used to perform set_storm_cfg 694 */ 695 struct ice_aqc_storm_cfg { 696 __le32 bcast_thresh_size; 697 __le32 mcast_thresh_size; 698 /* Bit 18:0 - Traffic upper threshold size 699 * Bit 31:19 - Reserved 700 */ 701 #define ICE_AQ_THRESHOLD_S 0 702 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S) 703 704 __le32 storm_ctrl_ctrl; 705 /* Bit 0: MDIPW - Drop Multicast packets in previous window 706 * Bit 1: MDICW - Drop multicast packets in current window 707 * Bit 2: BDIPW - Drop broadcast packets in previous window 708 * Bit 3: BDICW - Drop broadcast packets in current window 709 */ 710 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0) 711 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1) 712 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2) 713 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3) 714 /* Bit 7:5 : Reserved */ 715 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The 716 * interval size for applying ingress broadcast or multicast storm 717 * control. 718 */ 719 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8 720 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \ 721 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S) 722 __le32 reserved; 723 }; 724 725 #define ICE_MAX_NUM_RECIPES 64 726 727 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 728 */ 729 struct ice_aqc_sw_rules { 730 /* ops: add switch rules, referring the number of rules. 731 * ops: update switch rules, referring the number of filters 732 * ops: remove switch rules, referring the entry index. 733 * ops: get switch rules, referring to the number of filters. 734 */ 735 __le16 num_rules_fltr_entry_index; 736 u8 reserved[6]; 737 __le32 addr_high; 738 __le32 addr_low; 739 }; 740 741 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 742 * This structures describes the lookup rules and associated actions. "index" 743 * is returned as part of a response to a successful Add command, and can be 744 * used to identify the rule for Update/Get/Remove commands. 745 */ 746 struct ice_sw_rule_lkup_rx_tx { 747 __le16 recipe_id; 748 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 749 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 750 __le16 src; 751 __le32 act; 752 753 /* Bit 0:1 - Action type */ 754 #define ICE_SINGLE_ACT_TYPE_S 0x00 755 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 756 757 /* Bit 2 - Loop back enable 758 * Bit 3 - LAN enable 759 */ 760 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 761 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 762 763 /* Action type = 0 - Forward to VSI or VSI list */ 764 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 765 766 #define ICE_SINGLE_ACT_VSI_ID_S 4 767 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 768 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 769 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 770 /* This bit needs to be set if action is forward to VSI list */ 771 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 772 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 773 #define ICE_SINGLE_ACT_DROP BIT(18) 774 775 /* Action type = 1 - Forward to Queue of Queue group */ 776 #define ICE_SINGLE_ACT_TO_Q 0x1 777 #define ICE_SINGLE_ACT_Q_INDEX_S 4 778 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 779 #define ICE_SINGLE_ACT_Q_REGION_S 15 780 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 781 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 782 783 /* Action type = 2 - Prune */ 784 #define ICE_SINGLE_ACT_PRUNE 0x2 785 #define ICE_SINGLE_ACT_EGRESS BIT(15) 786 #define ICE_SINGLE_ACT_INGRESS BIT(16) 787 #define ICE_SINGLE_ACT_PRUNET BIT(17) 788 /* Bit 18 should be set to 0 for this action */ 789 790 /* Action type = 2 - Pointer */ 791 #define ICE_SINGLE_ACT_PTR 0x2 792 #define ICE_SINGLE_ACT_PTR_VAL_S 4 793 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 794 /* Bit 18 should be set to 1 */ 795 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 796 797 /* Action type = 3 - Other actions. Last two bits 798 * are other action identifier 799 */ 800 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 801 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 802 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 803 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 804 805 /* Bit 17:18 - Defines other actions */ 806 /* Other action = 0 - Mirror VSI */ 807 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 808 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 809 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 810 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 811 812 /* Other action = 3 - Set Stat count */ 813 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 814 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 815 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 816 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 817 818 __le16 index; /* The index of the rule in the lookup table */ 819 /* Length and values of the header to be matched per recipe or 820 * lookup-type 821 */ 822 __le16 hdr_len; 823 u8 hdr[STRUCT_HACK_VAR_LEN]; 824 }; 825 826 /* Add/Update/Remove large action command/response entry 827 * "index" is returned as part of a response to a successful Add command, and 828 * can be used to identify the action for Update/Get/Remove commands. 829 */ 830 struct ice_sw_rule_lg_act { 831 __le16 index; /* Index in large action table */ 832 __le16 size; 833 /* Max number of large actions */ 834 #define ICE_MAX_LG_ACT 4 835 /* Bit 0:1 - Action type */ 836 #define ICE_LG_ACT_TYPE_S 0 837 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 838 839 /* Action type = 0 - Forward to VSI or VSI list */ 840 #define ICE_LG_ACT_VSI_FORWARDING 0 841 #define ICE_LG_ACT_VSI_ID_S 3 842 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 843 #define ICE_LG_ACT_VSI_LIST_ID_S 3 844 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 845 /* This bit needs to be set if action is forward to VSI list */ 846 #define ICE_LG_ACT_VSI_LIST BIT(13) 847 848 #define ICE_LG_ACT_VALID_BIT BIT(16) 849 850 /* Action type = 1 - Forward to Queue of Queue group */ 851 #define ICE_LG_ACT_TO_Q 0x1 852 #define ICE_LG_ACT_Q_INDEX_S 3 853 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 854 #define ICE_LG_ACT_Q_REGION_S 14 855 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 856 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 857 858 /* Action type = 2 - Prune */ 859 #define ICE_LG_ACT_PRUNE 0x2 860 #define ICE_LG_ACT_EGRESS BIT(14) 861 #define ICE_LG_ACT_INGRESS BIT(15) 862 #define ICE_LG_ACT_PRUNET BIT(16) 863 864 /* Action type = 3 - Mirror VSI */ 865 #define ICE_LG_OTHER_ACT_MIRROR 0x3 866 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 867 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 868 869 /* Action type = 5 - Generic Value */ 870 #define ICE_LG_ACT_GENERIC 0x5 871 #define ICE_LG_ACT_GENERIC_VALUE_S 3 872 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 873 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 874 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 875 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 876 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 877 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 878 879 /* Action = 7 - Set Stat count */ 880 #define ICE_LG_ACT_STAT_COUNT 0x7 881 #define ICE_LG_ACT_STAT_COUNT_S 3 882 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 883 __le32 act[STRUCT_HACK_VAR_LEN]; /* array of size for actions */ 884 }; 885 886 /* Add/Update/Remove VSI list command/response entry 887 * "index" is returned as part of a response to a successful Add command, and 888 * can be used to identify the VSI list for Update/Get/Remove commands. 889 */ 890 struct ice_sw_rule_vsi_list { 891 __le16 index; /* Index of VSI/Prune list */ 892 __le16 number_vsi; 893 __le16 vsi[STRUCT_HACK_VAR_LEN]; /* Array of number_vsi VSI numbers */ 894 }; 895 896 #pragma pack(1) 897 /* Query VSI list command/response entry */ 898 struct ice_sw_rule_vsi_list_query { 899 __le16 index; 900 ice_declare_bitmap(vsi_list, ICE_MAX_VSI); 901 }; 902 #pragma pack() 903 904 #pragma pack(1) 905 /* Add switch rule response: 906 * Content of return buffer is same as the input buffer. The status field and 907 * LUT index are updated as part of the response 908 */ 909 struct ice_aqc_sw_rules_elem { 910 __le16 type; /* Switch rule type, one of T_... */ 911 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 912 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 913 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 914 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 915 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 916 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 917 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 918 __le16 status; 919 union { 920 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 921 struct ice_sw_rule_lg_act lg_act; 922 struct ice_sw_rule_vsi_list vsi_list; 923 struct ice_sw_rule_vsi_list_query vsi_list_query; 924 } pdata; 925 }; 926 927 #pragma pack() 928 929 /* PFC Ignore (direct 0x0301) 930 * The command and response use the same descriptor structure 931 */ 932 struct ice_aqc_pfc_ignore { 933 u8 tc_bitmap; 934 u8 cmd_flags; /* unused in response */ 935 #define ICE_AQC_PFC_IGNORE_SET BIT(7) 936 #define ICE_AQC_PFC_IGNORE_CLEAR 0 937 u8 reserved[14]; 938 }; 939 940 /* Set PFC Mode (direct 0x0303) 941 * Query PFC Mode (direct 0x0302) 942 */ 943 struct ice_aqc_set_query_pfc_mode { 944 u8 pfc_mode; 945 /* For Set Command response, reserved in all other cases */ 946 #define ICE_AQC_PFC_NOT_CONFIGURED 0 947 /* For Query Command response, reserved in all other cases */ 948 #define ICE_AQC_DCB_DIS 0 949 #define ICE_AQC_PFC_VLAN_BASED_PFC 1 950 #define ICE_AQC_PFC_DSCP_BASED_PFC 2 951 u8 rsvd[15]; 952 }; 953 954 /* Set DCB Parameters (direct 0x0306) */ 955 struct ice_aqc_set_dcb_params { 956 u8 cmd_flags; /* unused in response */ 957 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0) 958 #define ICE_AQC_PERSIST_DCB_CFG BIT(1) 959 u8 valid_flags; /* unused in response */ 960 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0) 961 #define ICE_AQC_PERSIST_DCB_CFG_VALID BIT(1) 962 u8 rsvd[14]; 963 }; 964 965 /* Get Default Topology (indirect 0x0400) */ 966 struct ice_aqc_get_topo { 967 u8 port_num; 968 u8 num_branches; 969 __le16 reserved1; 970 __le32 reserved2; 971 __le32 addr_high; 972 __le32 addr_low; 973 }; 974 975 /* Update TSE (indirect 0x0403) 976 * Get TSE (indirect 0x0404) 977 * Add TSE (indirect 0x0401) 978 * Delete TSE (indirect 0x040F) 979 * Move TSE (indirect 0x0408) 980 * Suspend Nodes (indirect 0x0409) 981 * Resume Nodes (indirect 0x040A) 982 */ 983 struct ice_aqc_sched_elem_cmd { 984 __le16 num_elem_req; /* Used by commands */ 985 __le16 num_elem_resp; /* Used by responses */ 986 __le32 reserved; 987 __le32 addr_high; 988 __le32 addr_low; 989 }; 990 991 struct ice_aqc_txsched_move_grp_info_hdr { 992 __le32 src_parent_teid; 993 __le32 dest_parent_teid; 994 __le16 num_elems; 995 __le16 reserved; 996 }; 997 998 struct ice_aqc_move_elem { 999 struct ice_aqc_txsched_move_grp_info_hdr hdr; 1000 __le32 teid[STRUCT_HACK_VAR_LEN]; 1001 }; 1002 1003 struct ice_aqc_elem_info_bw { 1004 __le16 bw_profile_idx; 1005 __le16 bw_alloc; 1006 }; 1007 1008 struct ice_aqc_txsched_elem { 1009 u8 elem_type; /* Special field, reserved for some aq calls */ 1010 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 1011 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 1012 #define ICE_AQC_ELEM_TYPE_TC 0x2 1013 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 1014 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 1015 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 1016 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 1017 u8 valid_sections; 1018 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 1019 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 1020 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 1021 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 1022 u8 generic; 1023 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 1024 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 1025 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 1026 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 1027 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 1028 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 1029 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 1030 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 1031 u8 flags; /* Special field, reserved for some aq calls */ 1032 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 1033 struct ice_aqc_elem_info_bw cir_bw; 1034 struct ice_aqc_elem_info_bw eir_bw; 1035 __le16 srl_id; 1036 __le16 reserved2; 1037 }; 1038 1039 struct ice_aqc_txsched_elem_data { 1040 __le32 parent_teid; 1041 __le32 node_teid; 1042 struct ice_aqc_txsched_elem data; 1043 }; 1044 1045 struct ice_aqc_txsched_topo_grp_info_hdr { 1046 __le32 parent_teid; 1047 __le16 num_elems; 1048 __le16 reserved2; 1049 }; 1050 1051 struct ice_aqc_add_elem { 1052 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1053 struct ice_aqc_txsched_elem_data generic[STRUCT_HACK_VAR_LEN]; 1054 }; 1055 1056 struct ice_aqc_get_topo_elem { 1057 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1058 struct ice_aqc_txsched_elem_data 1059 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1060 }; 1061 1062 struct ice_aqc_delete_elem { 1063 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1064 __le32 teid[STRUCT_HACK_VAR_LEN]; 1065 }; 1066 1067 /* Query Port ETS (indirect 0x040E) 1068 * 1069 * This indirect command is used to query port TC node configuration. 1070 */ 1071 struct ice_aqc_query_port_ets { 1072 __le32 port_teid; 1073 __le32 reserved; 1074 __le32 addr_high; 1075 __le32 addr_low; 1076 }; 1077 1078 struct ice_aqc_port_ets_elem { 1079 u8 tc_valid_bits; 1080 u8 reserved[3]; 1081 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 1082 __le32 up2tc; 1083 u8 tc_bw_share[8]; 1084 __le32 port_eir_prof_id; 1085 __le32 port_cir_prof_id; 1086 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 1087 __le32 tc_node_prio; 1088 #define ICE_TC_NODE_PRIO_S 0x4 1089 u8 reserved1[4]; 1090 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 1091 }; 1092 1093 /* Rate limiting profile for 1094 * Add RL profile (indirect 0x0410) 1095 * Query RL profile (indirect 0x0411) 1096 * Remove RL profile (indirect 0x0415) 1097 * These indirect commands acts on single or multiple 1098 * RL profiles with specified data. 1099 */ 1100 struct ice_aqc_rl_profile { 1101 __le16 num_profiles; 1102 __le16 num_processed; /* Only for response. Reserved in Command. */ 1103 u8 reserved[4]; 1104 __le32 addr_high; 1105 __le32 addr_low; 1106 }; 1107 1108 struct ice_aqc_rl_profile_elem { 1109 u8 level; 1110 u8 flags; 1111 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 1112 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 1113 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 1114 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 1115 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 1116 /* The following flag is used for Query RL Profile Data */ 1117 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 1118 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 1119 1120 __le16 profile_id; 1121 __le16 max_burst_size; 1122 __le16 rl_multiply; 1123 __le16 wake_up_calc; 1124 __le16 rl_encode; 1125 }; 1126 1127 /* Configure L2 Node CGD (indirect 0x0414) 1128 * This indirect command allows configuring a congestion domain for given L2 1129 * node TEIDs in the scheduler topology. 1130 */ 1131 struct ice_aqc_cfg_l2_node_cgd { 1132 __le16 num_l2_nodes; 1133 u8 reserved[6]; 1134 __le32 addr_high; 1135 __le32 addr_low; 1136 }; 1137 1138 struct ice_aqc_cfg_l2_node_cgd_elem { 1139 __le32 node_teid; 1140 u8 cgd; 1141 u8 reserved[3]; 1142 }; 1143 1144 /* Query Scheduler Resource Allocation (indirect 0x0412) 1145 * This indirect command retrieves the scheduler resources allocated by 1146 * EMP Firmware to the given PF. 1147 */ 1148 struct ice_aqc_query_txsched_res { 1149 u8 reserved[8]; 1150 __le32 addr_high; 1151 __le32 addr_low; 1152 }; 1153 1154 struct ice_aqc_generic_sched_props { 1155 __le16 phys_levels; 1156 __le16 logical_levels; 1157 u8 flattening_bitmap; 1158 u8 max_device_cgds; 1159 u8 max_pf_cgds; 1160 u8 rsvd0; 1161 __le16 rdma_qsets; 1162 u8 rsvd1[22]; 1163 }; 1164 1165 struct ice_aqc_layer_props { 1166 u8 logical_layer; 1167 u8 chunk_size; 1168 __le16 max_device_nodes; 1169 __le16 max_pf_nodes; 1170 u8 rsvd0[4]; 1171 __le16 max_sibl_grp_sz; 1172 __le16 max_cir_rl_profiles; 1173 __le16 max_eir_rl_profiles; 1174 __le16 max_srl_profiles; 1175 u8 rsvd1[14]; 1176 }; 1177 1178 struct ice_aqc_query_txsched_res_resp { 1179 struct ice_aqc_generic_sched_props sched_props; 1180 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1181 }; 1182 1183 /* Query Node to Root Topology (indirect 0x0413) 1184 * This command uses ice_aqc_get_elem as its data buffer. 1185 */ 1186 struct ice_aqc_query_node_to_root { 1187 __le32 teid; 1188 __le32 num_nodes; /* Response only */ 1189 __le32 addr_high; 1190 __le32 addr_low; 1191 }; 1192 1193 /* Get PHY capabilities (indirect 0x0600) */ 1194 struct ice_aqc_get_phy_caps { 1195 u8 lport_num; 1196 u8 reserved; 1197 __le16 param0; 1198 /* 18.0 - Report qualified modules */ 1199 #define ICE_AQC_GET_PHY_RQM BIT(0) 1200 /* 18.1 - 18.2 : Report mode 1201 * 00b - Report NVM capabilities 1202 * 01b - Report topology capabilities 1203 * 10b - Report SW configured 1204 */ 1205 #define ICE_AQC_REPORT_MODE_S 1 1206 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S) 1207 #define ICE_AQC_REPORT_NVM_CAP 0 1208 #define ICE_AQC_REPORT_TOPO_CAP BIT(1) 1209 #define ICE_AQC_REPORT_SW_CFG BIT(2) 1210 __le32 reserved1; 1211 __le32 addr_high; 1212 __le32 addr_low; 1213 }; 1214 1215 /* This is #define of PHY type (Extended): 1216 * The first set of defines is for phy_type_low. 1217 */ 1218 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 1219 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 1220 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 1221 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 1222 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 1223 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 1224 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 1225 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 1226 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 1227 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 1228 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 1229 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 1230 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 1231 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 1232 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 1233 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 1234 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 1235 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 1236 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 1237 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 1238 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 1239 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 1240 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 1241 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 1242 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 1243 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 1244 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 1245 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 1246 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 1247 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 1248 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 1249 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 1250 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 1251 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 1252 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 1253 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 1254 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 1255 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 1256 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 1257 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 1258 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 1259 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 1260 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 1261 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 1262 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 1263 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 1264 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 1265 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 1266 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 1267 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 1268 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 1269 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 1270 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 1271 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 1272 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 1273 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 1274 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 1275 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 1276 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 1277 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 1278 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 1279 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 1280 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 1281 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 1282 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 1283 /* The second set of defines is for phy_type_high. */ 1284 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 1285 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 1286 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 1287 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 1288 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 1289 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 5 1290 1291 struct ice_aqc_get_phy_caps_data { 1292 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1293 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1294 u8 caps; 1295 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 1296 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 1297 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 1298 #define ICE_AQC_PHY_EN_LINK BIT(3) 1299 #define ICE_AQC_PHY_AN_MODE BIT(4) 1300 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5) 1301 #define ICE_AQC_PHY_EN_LESM BIT(6) 1302 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 1303 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0) 1304 u8 low_power_ctrl_an; 1305 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 1306 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1) 1307 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2) 1308 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3) 1309 __le16 eee_cap; 1310 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1311 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1312 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1313 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1314 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1315 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1316 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1317 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7) 1318 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8) 1319 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9) 1320 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10) 1321 __le16 eeer_value; 1322 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1323 u8 phy_fw_ver[8]; 1324 u8 link_fec_options; 1325 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1326 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1327 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1328 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1329 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1330 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1331 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1332 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0) 1333 u8 module_compliance_enforcement; 1334 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 1335 u8 extended_compliance_code; 1336 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1337 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1338 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1339 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1340 #define ICE_AQC_MOD_TYPE_IDENT 1 1341 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1342 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1343 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1344 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1345 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1346 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1347 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1348 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1349 u8 qualified_module_count; 1350 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1351 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1352 struct { 1353 u8 v_oui[3]; 1354 u8 rsvd3; 1355 u8 v_part[16]; 1356 __le32 v_rev; 1357 __le64 rsvd4; 1358 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1359 }; 1360 1361 /* Set PHY capabilities (direct 0x0601) 1362 * NOTE: This command must be followed by setup link and restart auto-neg 1363 */ 1364 struct ice_aqc_set_phy_cfg { 1365 u8 lport_num; 1366 u8 reserved[7]; 1367 __le32 addr_high; 1368 __le32 addr_low; 1369 }; 1370 1371 /* Set PHY config command data structure */ 1372 struct ice_aqc_set_phy_cfg_data { 1373 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1374 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1375 u8 caps; 1376 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0) 1377 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1378 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1379 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1380 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1381 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1382 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1383 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1384 u8 low_power_ctrl_an; 1385 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1386 __le16 eeer_value; 1387 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1388 u8 module_compliance_enforcement; 1389 }; 1390 1391 /* Set MAC Config command data structure (direct 0x0603) */ 1392 struct ice_aqc_set_mac_cfg { 1393 __le16 max_frame_size; 1394 u8 params; 1395 #define ICE_AQ_SET_MAC_PACE_S 3 1396 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1397 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1398 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1399 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1400 u8 tx_tmr_priority; 1401 __le16 tx_tmr_value; 1402 __le16 fc_refresh_threshold; 1403 u8 drop_opts; 1404 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1405 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1406 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1407 u8 reserved[7]; 1408 }; 1409 1410 /* Restart AN command data structure (direct 0x0605) 1411 * Also used for response, with only the lport_num field present. 1412 */ 1413 struct ice_aqc_restart_an { 1414 u8 lport_num; 1415 u8 reserved; 1416 u8 cmd_flags; 1417 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1418 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1419 u8 reserved2[13]; 1420 }; 1421 1422 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1423 struct ice_aqc_get_link_status { 1424 u8 lport_num; 1425 u8 reserved; 1426 __le16 cmd_flags; 1427 #define ICE_AQ_LSE_M 0x3 1428 #define ICE_AQ_LSE_NOP 0x0 1429 #define ICE_AQ_LSE_DIS 0x2 1430 #define ICE_AQ_LSE_ENA 0x3 1431 /* only response uses this flag */ 1432 #define ICE_AQ_LSE_IS_ENABLED 0x1 1433 __le32 reserved2; 1434 __le32 addr_high; 1435 __le32 addr_low; 1436 }; 1437 1438 /* Get link status response data structure, also used for Link Status Event */ 1439 struct ice_aqc_get_link_status_data { 1440 u8 topo_media_conflict; 1441 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1442 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1443 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1444 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1445 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1446 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1447 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1448 u8 link_cfg_err; 1449 #define ICE_AQ_LINK_CFG_ERR BIT(0) 1450 #define ICE_AQ_LINK_ACT_PORT_OPT_INVAL BIT(2) 1451 #define ICE_AQ_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3) 1452 #define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR BIT(4) 1453 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5) 1454 u8 link_info; 1455 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1456 #define ICE_AQ_LINK_FAULT BIT(1) 1457 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1458 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1459 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1460 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1461 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1462 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1463 u8 an_info; 1464 #define ICE_AQ_AN_COMPLETED BIT(0) 1465 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1466 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1467 #define ICE_AQ_FEC_EN BIT(3) 1468 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1469 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1470 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1471 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1472 u8 ext_info; 1473 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1474 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1475 /* Port Tx Suspended */ 1476 #define ICE_AQ_LINK_TX_S 2 1477 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1478 #define ICE_AQ_LINK_TX_ACTIVE 0 1479 #define ICE_AQ_LINK_TX_DRAINED 1 1480 #define ICE_AQ_LINK_TX_FLUSHED 3 1481 u8 lb_status; 1482 #define ICE_AQ_LINK_LB_PHY_LCL BIT(0) 1483 #define ICE_AQ_LINK_LB_PHY_RMT BIT(1) 1484 #define ICE_AQ_LINK_LB_MAC_LCL BIT(2) 1485 #define ICE_AQ_LINK_LB_PHY_IDX_S 3 1486 #define ICE_AQ_LINK_LB_PHY_IDX_M (0x7 << ICE_AQ_LB_PHY_IDX_S) 1487 __le16 max_frame_size; 1488 u8 cfg; 1489 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1490 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1491 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1492 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0) 1493 /* Pacing Config */ 1494 #define ICE_AQ_CFG_PACING_S 3 1495 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1496 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1497 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1498 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1499 /* External Device Power Ability */ 1500 u8 power_desc; 1501 #define ICE_AQ_PWR_CLASS_M 0x3F 1502 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1503 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1504 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1505 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1506 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1507 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1508 __le16 link_speed; 1509 #define ICE_AQ_LINK_SPEED_M 0x7FF 1510 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1511 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1512 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1513 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1514 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1515 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1516 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1517 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1518 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1519 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1520 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1521 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1522 __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1523 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1524 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1525 }; 1526 1527 /* Set event mask command (direct 0x0613) */ 1528 struct ice_aqc_set_event_mask { 1529 u8 lport_num; 1530 u8 reserved[7]; 1531 __le16 event_mask; 1532 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1533 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1534 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1535 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1536 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1537 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1538 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1539 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1540 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1541 #define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10) 1542 #define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11) 1543 u8 reserved1[6]; 1544 }; 1545 1546 /* Set PHY Loopback command (direct 0x0619) */ 1547 struct ice_aqc_set_phy_lb { 1548 u8 lport_num; 1549 u8 lport_num_valid; 1550 #define ICE_AQ_PHY_LB_PORT_NUM_VALID BIT(0) 1551 u8 phy_index; 1552 u8 lb_mode; 1553 #define ICE_AQ_PHY_LB_EN BIT(0) 1554 #define ICE_AQ_PHY_LB_TYPE_M BIT(1) 1555 #define ICE_AQ_PHY_LB_TYPE_LOCAL 0 1556 #define ICE_AQ_PHY_LB_TYPE_REMOTE ICE_AQ_PHY_LB_TYPE_M 1557 #define ICE_AQ_PHY_LB_LEVEL_M BIT(2) 1558 #define ICE_AQ_PHY_LB_LEVEL_PMD 0 1559 #define ICE_AQ_PHY_LB_LEVEL_PCS ICE_AQ_PHY_LB_LEVEL_M 1560 u8 reserved2[12]; 1561 }; 1562 1563 /* Set MAC Loopback command (direct 0x0620) */ 1564 struct ice_aqc_set_mac_lb { 1565 u8 lb_mode; 1566 #define ICE_AQ_MAC_LB_EN BIT(0) 1567 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1568 u8 reserved[15]; 1569 }; 1570 1571 /* DNL Get Status command (indirect 0x0680) 1572 * Structure used for the response, the command uses the generic 1573 * ice_aqc_generic struct to pass a buffer address to the FW. 1574 */ 1575 struct ice_aqc_dnl_get_status { 1576 u8 ctx; 1577 u8 status; 1578 #define ICE_AQ_DNL_STATUS_IDLE 0x0 1579 #define ICE_AQ_DNL_STATUS_RESERVED 0x1 1580 #define ICE_AQ_DNL_STATUS_STOPPED 0x2 1581 #define ICE_AQ_DNL_STATUS_FATAL 0x3 /* Fatal DNL engine error */ 1582 #define ICE_AQ_DNL_SRC_S 3 1583 #define ICE_AQ_DNL_SRC_M (0x3 << ICE_AQ_DNL_SRC_S) 1584 #define ICE_AQ_DNL_SRC_NVM (0x0 << ICE_AQ_DNL_SRC_S) 1585 #define ICE_AQ_DNL_SRC_NVM_SCRATCH (0x1 << ICE_AQ_DNL_SRC_S) 1586 u8 stack_ptr; 1587 #define ICE_AQ_DNL_ST_PTR_S 0x0 1588 #define ICE_AQ_DNL_ST_PTR_M (0x7 << ICE_AQ_DNL_ST_PTR_S) 1589 u8 engine_flags; 1590 #define ICE_AQ_DNL_FLAGS_ERROR BIT(2) 1591 #define ICE_AQ_DNL_FLAGS_NEGATIVE BIT(3) 1592 #define ICE_AQ_DNL_FLAGS_OVERFLOW BIT(4) 1593 #define ICE_AQ_DNL_FLAGS_ZERO BIT(5) 1594 #define ICE_AQ_DNL_FLAGS_CARRY BIT(6) 1595 #define ICE_AQ_DNL_FLAGS_JUMP BIT(7) 1596 __le16 pc; 1597 __le16 activity_id; 1598 __le32 addr_high; 1599 __le32 addr_low; 1600 }; 1601 1602 struct ice_aqc_dnl_get_status_data { 1603 __le16 activity_err_code; 1604 __le16 act_err_code; 1605 #define ICE_AQ_DNL_ACT_ERR_SUCCESS 0x0000 /* no error */ 1606 #define ICE_AQ_DNL_ACT_ERR_PARSE 0x8001 /* NVM parse error */ 1607 #define ICE_AQ_DNL_ACT_ERR_UNSUPPORTED 0x8002 /* unsupported action */ 1608 #define ICE_AQ_DNL_ACT_ERR_NOT_FOUND 0x8003 /* activity not found */ 1609 #define ICE_AQ_DNL_ACT_ERR_BAD_JUMP 0x8004 /* an illegal jump */ 1610 #define ICE_AQ_DNL_ACT_ERR_PSTO_OVER 0x8005 /* persistent store overflow */ 1611 #define ICE_AQ_DNL_ACT_ERR_ST_OVERFLOW 0x8006 /* stack overflow */ 1612 #define ICE_AQ_DNL_ACT_ERR_TIMEOUT 0x8007 /* activity timeout */ 1613 #define ICE_AQ_DNL_ACT_ERR_BREAK 0x0008 /* stopped at breakpoint */ 1614 #define ICE_AQ_DNL_ACT_ERR_INVAL_ARG 0x0101 /* invalid action argument */ 1615 __le32 execution_time; /* in nanoseconds */ 1616 __le16 lib_ver; 1617 u8 psto_local_sz; 1618 u8 psto_global_sz; 1619 u8 stack_sz; 1620 #define ICE_AQ_DNL_STACK_SZ_S 0 1621 #define ICE_AQ_DNL_STACK_SZ_M (0xF << ICE_AQ_DNL_STACK_SZ_S) 1622 u8 port_count; 1623 #define ICE_AQ_DNL_PORT_CNT_S 0 1624 #define ICE_AQ_DNL_PORT_CNT_M (0x1F << ICE_AQ_DNL_PORT_CNT_S) 1625 __le16 act_cache_cntr; 1626 u32 i2c_clk_cntr; 1627 u32 mdio_clk_cntr; 1628 u32 sb_iosf_clk_cntr; 1629 }; 1630 1631 /* DNL run command (direct 0x0681) */ 1632 struct ice_aqc_dnl_run_command { 1633 u8 reserved0; 1634 u8 command; 1635 #define ICE_AQ_DNL_CMD_S 0 1636 #define ICE_AQ_DNL_CMD_M (0x7 << ICE_AQ_DNL_CMD_S) 1637 #define ICE_AQ_DNL_CMD_RESET 0x0 1638 #define ICE_AQ_DNL_CMD_RUN 0x1 1639 #define ICE_AQ_DNL_CMD_STEP 0x3 1640 #define ICE_AQ_DNL_CMD_ABORT 0x4 1641 #define ICE_AQ_DNL_CMD_SET_PC 0x7 1642 #define ICE_AQ_DNL_CMD_SRC_S 3 1643 #define ICE_AQ_DNL_CMD_SRC_M (0x3 << ICE_AQ_DNL_CMD_SRC_S) 1644 #define ICE_AQ_DNL_CMD_SRC_DNL 0x0 1645 #define ICE_AQ_DNL_CMD_SRC_SCRATCH 0x1 1646 __le16 new_pc; 1647 u8 reserved1[12]; 1648 }; 1649 1650 /* DNL call command (indirect 0x0682) 1651 * Struct is used for both command and response 1652 */ 1653 struct ice_aqc_dnl_call_command { 1654 u8 ctx; /* Used in command, reserved in response */ 1655 u8 reserved; 1656 __le16 activity_id; 1657 __le32 reserved1; 1658 __le32 addr_high; 1659 __le32 addr_low; 1660 }; 1661 1662 /* DNL call command/response buffer (indirect 0x0682) */ 1663 struct ice_aqc_dnl_call { 1664 __le32 stores[4]; 1665 }; 1666 1667 /* Used for both commands: 1668 * DNL read sto command (indirect 0x0683) 1669 * DNL write sto command (indirect 0x0684) 1670 */ 1671 struct ice_aqc_dnl_read_write_command { 1672 u8 ctx; 1673 u8 sto_sel; /* STORE select */ 1674 #define ICE_AQC_DNL_STORE_SELECT_STORE 0x0 1675 #define ICE_AQC_DNL_STORE_SELECT_PSTO 0x1 1676 #define ICE_AQC_DNL_STORE_SELECT_STACK 0x2 1677 __le16 offset; 1678 __le32 data; /* Used for write sto only */ 1679 __le32 addr_high; /* Used for read sto only */ 1680 __le32 addr_low; /* Used for read sto only */ 1681 }; 1682 1683 /* Used for both command responses: 1684 * DNL read sto response (indirect 0x0683) 1685 * DNL write sto response (indirect 0x0684) 1686 */ 1687 struct ice_aqc_dnl_read_write_response { 1688 u8 reserved; 1689 u8 status; /* Reserved for read command */ 1690 __le16 size; /* Reserved for write command */ 1691 __le32 data; /* Reserved for write command */ 1692 __le32 addr_high; /* Reserved for write command */ 1693 __le32 addr_low; /* Reserved for write command */ 1694 }; 1695 1696 /* DNL set breakpoints command (indirect 0x0686) */ 1697 struct ice_aqc_dnl_set_breakpoints_command { 1698 __le32 reserved[2]; 1699 __le32 addr_high; 1700 __le32 addr_low; 1701 }; 1702 1703 /* DNL set breakpoints data buffer structure (indirect 0x0686) */ 1704 struct ice_aqc_dnl_set_breakpoints { 1705 u8 ctx; 1706 u8 ena; /* 0- disabled, 1- enabled */ 1707 __le16 offset; 1708 __le16 activity_id; 1709 }; 1710 1711 /* DNL read log data command(indirect 0x0687) */ 1712 struct ice_aqc_dnl_read_log_command { 1713 __le16 reserved0; 1714 __le16 offset; 1715 __le32 reserved1; 1716 __le32 addr_high; 1717 __le32 addr_low; 1718 1719 }; 1720 1721 /* DNL read log data response(indirect 0x0687) */ 1722 struct ice_aqc_dnl_read_log_response { 1723 __le16 reserved; 1724 __le16 size; 1725 __le32 data; 1726 __le32 addr_high; 1727 __le32 addr_low; 1728 1729 }; 1730 1731 struct ice_aqc_link_topo_addr { 1732 u8 lport_num; 1733 u8 lport_num_valid; 1734 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 1735 u8 node_type_ctx; 1736 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 1737 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 1738 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 1739 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1740 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1741 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1742 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 1743 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 1744 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 1745 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 1746 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1747 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 1748 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 1749 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 1750 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 1751 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 1752 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 1753 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 1754 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 1755 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 1756 u8 index; 1757 __le16 handle; 1758 #define ICE_AQC_LINK_TOPO_HANDLE_S 0 1759 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 1760 /* Used to decode the handle field */ 1761 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1762 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 1763 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 1764 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 1765 /* In case of a Mezzanine type */ 1766 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1767 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1768 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 1769 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 1770 /* In case of a LOM type */ 1771 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 1772 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1773 }; 1774 1775 /* Get Link Topology Handle (direct, 0x06E0) */ 1776 struct ice_aqc_get_link_topo { 1777 struct ice_aqc_link_topo_addr addr; 1778 u8 node_part_num; 1779 u8 rsvd[9]; 1780 }; 1781 1782 /* Get Link Topology Pin (direct, 0x06E1) */ 1783 struct ice_aqc_get_link_topo_pin { 1784 struct ice_aqc_link_topo_addr addr; 1785 u8 input_io_params; 1786 #define ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_S 0 1787 #define ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_M \ 1788 (0x1F << ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_S) 1789 #define ICE_AQC_LINK_TOPO_IO_FUNC_GPIO 0 1790 #define ICE_AQC_LINK_TOPO_IO_FUNC_RESET_N 1 1791 #define ICE_AQC_LINK_TOPO_IO_FUNC_INT_N 2 1792 #define ICE_AQC_LINK_TOPO_IO_FUNC_PRESENT_N 3 1793 #define ICE_AQC_LINK_TOPO_IO_FUNC_TX_DIS 4 1794 #define ICE_AQC_LINK_TOPO_IO_FUNC_MODSEL_N 5 1795 #define ICE_AQC_LINK_TOPO_IO_FUNC_LPMODE 6 1796 #define ICE_AQC_LINK_TOPO_IO_FUNC_TX_FAULT 7 1797 #define ICE_AQC_LINK_TOPO_IO_FUNC_RX_LOSS 8 1798 #define ICE_AQC_LINK_TOPO_IO_FUNC_RS0 9 1799 #define ICE_AQC_LINK_TOPO_IO_FUNC_RS1 10 1800 #define ICE_AQC_LINK_TOPO_IO_FUNC_EEPROM_WP 11 1801 /* 12 repeats intentionally due to two different uses depending on context */ 1802 #define ICE_AQC_LINK_TOPO_IO_FUNC_LED 12 1803 #define ICE_AQC_LINK_TOPO_IO_FUNC_RED_LED 12 1804 #define ICE_AQC_LINK_TOPO_IO_FUNC_GREEN_LED 13 1805 #define ICE_AQC_LINK_TOPO_IO_FUNC_BLUE_LED 14 1806 #define ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S 5 1807 #define ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_M \ 1808 (0x7 << ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S) 1809 /* Use ICE_AQC_LINK_TOPO_NODE_TYPE_* for the type values */ 1810 u8 output_io_params; 1811 #define ICE_AQC_LINK_TOPO_OUTPUT_IO_FUNC_S 0 1812 #define ICE_AQC_LINK_TOPO_OUTPUT_IO_FUNC_M \ 1813 (0x1F << \ ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_NUM_S) 1814 /* Use ICE_AQC_LINK_TOPO_IO_FUNC_* for the non-numerical options */ 1815 #define ICE_AQC_LINK_TOPO_OUTPUT_IO_TYPE_S 5 1816 #define ICE_AQC_LINK_TOPO_OUTPUT_IO_TYPE_M \ 1817 (0x7 << ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S) 1818 /* Use ICE_AQC_LINK_TOPO_NODE_TYPE_* for the type values */ 1819 u8 output_io_flags; 1820 #define ICE_AQC_LINK_TOPO_OUTPUT_SPEED_S 0 1821 #define ICE_AQC_LINK_TOPO_OUTPUT_SPEED_M \ 1822 (0x7 << ICE_AQC_LINK_TOPO_OUTPUT_SPEED_S) 1823 #define ICE_AQC_LINK_TOPO_OUTPUT_INT_S 3 1824 #define ICE_AQC_LINK_TOPO_OUTPUT_INT_M \ 1825 (0x3 << ICE_AQC_LINK_TOPO_OUTPUT_INT_S) 1826 #define ICE_AQC_LINK_TOPO_OUTPUT_POLARITY BIT(5) 1827 #define ICE_AQC_LINK_TOPO_OUTPUT_VALUE BIT(6) 1828 #define ICE_AQC_LINK_TOPO_OUTPUT_DRIVEN BIT(7) 1829 u8 rsvd[7]; 1830 }; 1831 1832 /* Read/Write I2C (direct, 0x06E2/0x06E3) */ 1833 struct ice_aqc_i2c { 1834 struct ice_aqc_link_topo_addr topo_addr; 1835 __le16 i2c_addr; 1836 u8 i2c_params; 1837 #define ICE_AQC_I2C_DATA_SIZE_S 0 1838 #define ICE_AQC_I2C_DATA_SIZE_M (0xF << ICE_AQC_I2C_DATA_SIZE_S) 1839 #define ICE_AQC_I2C_ADDR_TYPE_M BIT(4) 1840 #define ICE_AQC_I2C_ADDR_TYPE_7BIT 0 1841 #define ICE_AQC_I2C_ADDR_TYPE_10BIT ICE_AQC_I2C_ADDR_TYPE_M 1842 #define ICE_AQC_I2C_DATA_OFFSET_S 5 1843 #define ICE_AQC_I2C_DATA_OFFSET_M (0x3 << ICE_AQC_I2C_DATA_OFFSET_S) 1844 #define ICE_AQC_I2C_USE_REPEATED_START BIT(7) 1845 u8 rsvd; 1846 __le16 i2c_bus_addr; 1847 #define ICE_AQC_I2C_ADDR_7BIT_MASK 0x7F 1848 #define ICE_AQC_I2C_ADDR_10BIT_MASK 0x3FF 1849 u8 i2c_data[4]; /* Used only by write command, reserved in read. */ 1850 }; 1851 1852 /* Read I2C Response (direct, 0x06E2) */ 1853 struct ice_aqc_read_i2c_resp { 1854 u8 i2c_data[16]; 1855 }; 1856 1857 /* Read/Write MDIO (direct, 0x06E4/0x06E5) */ 1858 struct ice_aqc_mdio { 1859 struct ice_aqc_link_topo_addr topo_addr; 1860 u8 mdio_device_addr; 1861 #define ICE_AQC_MDIO_DEV_S 0 1862 #define ICE_AQC_MDIO_DEV_M (0x1F << ICE_AQC_MDIO_DEV_S) 1863 #define ICE_AQC_MDIO_CLAUSE_22 BIT(5) 1864 #define ICE_AQC_MDIO_CLAUSE_45 BIT(6) 1865 u8 mdio_bus_address; 1866 #define ICE_AQC_MDIO_BUS_ADDR_S 0 1867 #define ICE_AQC_MDIO_BUS_ADDR_M (0x1F << ICE_AQC_MDIO_BUS_ADDR_S) 1868 __le16 offset; 1869 __le16 data; /* Input in write cmd, output in read cmd. */ 1870 u8 rsvd1[4]; 1871 }; 1872 1873 /* Set/Get GPIO By Function (direct, 0x06E6/0x06E7) */ 1874 struct ice_aqc_gpio_by_func { 1875 struct ice_aqc_link_topo_addr topo_addr; 1876 u8 io_func_num; 1877 #define ICE_AQC_GPIO_FUNC_S 0 1878 #define ICE_AQC_GPIO_FUNC_M (0x1F << ICE_AQC_GPIO_IO_FUNC_NUM_S) 1879 u8 io_value; /* Input in write cmd, output in read cmd. */ 1880 #define ICE_AQC_GPIO_ON BIT(0) 1881 #define ICE_AQC_GPIO_OFF 0 1882 u8 rsvd[8]; 1883 }; 1884 1885 /* Set LED (direct, 0x06E8) */ 1886 struct ice_aqc_set_led { 1887 struct ice_aqc_link_topo_addr topo_addr; 1888 u8 color_and_blink; 1889 #define ICE_AQC_LED_COLOR_S 0 1890 #define ICE_AQC_LED_COLOR_M (0x7 << ICE_AQC_LED_COLOR_S) 1891 #define ICE_AQC_LED_COLOR_SKIP 0 1892 #define ICE_AQC_LED_COLOR_RED 1 1893 #define ICE_AQC_LED_COLOR_ORANGE 2 1894 #define ICE_AQC_LED_COLOR_YELLOW 3 1895 #define ICE_AQC_LED_COLOR_GREEN 4 1896 #define ICE_AQC_LED_COLOR_BLUE 5 1897 #define ICE_AQC_LED_COLOR_PURPLE 6 1898 #define ICE_AQC_LED_BLINK_S 3 1899 #define ICE_AQC_LED_BLINK_M (0x7 << ICE_AQC_LED_BLINK_S) 1900 #define ICE_AQC_LED_BLINK_NONE 0 1901 #define ICE_AQC_LED_BLINK_SLOW 1 1902 #define ICE_AQC_LED_BLINK_SLOW_MAC 2 1903 #define ICE_AQC_LED_BLINK_SLOW_FLTR 3 1904 #define ICE_AQC_LED_BLINK_FAST 5 1905 #define ICE_AQC_LED_BLINK_FAST_MAC 6 1906 #define ICE_AQC_LED_BLINK_FAST_FLTR 7 1907 u8 rsvd[9]; 1908 }; 1909 1910 /* Set Port Identification LED (direct, 0x06E9) */ 1911 struct ice_aqc_set_port_id_led { 1912 u8 lport_num; 1913 u8 lport_num_valid; 1914 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0) 1915 u8 ident_mode; 1916 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1917 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1918 u8 rsvd[13]; 1919 }; 1920 1921 /* Get Port Options (indirect, 0x06EA) */ 1922 struct ice_aqc_get_port_options { 1923 u8 lport_num; 1924 u8 lport_num_valid; 1925 #define ICE_AQC_PORT_OPT_PORT_NUM_VALID BIT(0) 1926 u8 port_options_count; 1927 #define ICE_AQC_PORT_OPT_COUNT_S 0 1928 #define ICE_AQC_PORT_OPT_COUNT_M (0xF << ICE_AQC_PORT_OPT_COUNT_S) 1929 u8 innermost_phy_index; 1930 u8 port_options; 1931 #define ICE_AQC_PORT_OPT_ACTIVE_S 0 1932 #define ICE_AQC_PORT_OPT_ACTIVE_M (0xF << ICE_AQC_PORT_OPT_ACTIVE_S) 1933 #define ICE_AQC_PORT_OPT_FORCED BIT(6) 1934 #define ICE_AQC_PORT_OPT_VALID BIT(7) 1935 u8 rsvd[3]; 1936 __le32 addr_high; 1937 __le32 addr_low; 1938 }; 1939 1940 struct ice_aqc_get_port_options_elem { 1941 u8 pmd; 1942 #define ICE_AQC_PORT_INV_PORT_OPT 4 1943 #define ICE_AQC_PORT_OPT_PMD_COUNT_S 0 1944 #define ICE_AQC_PORT_OPT_PMD_COUNT_M (0xF << ICE_AQC_PORT_OPT_PMD_COUNT_S) 1945 #define ICE_AQC_PORT_OPT_PMD_WIDTH_S 4 1946 #define ICE_AQC_PORT_OPT_PMD_WIDTH_M (0xF << ICE_AQC_PORT_OPT_PMD_WIDTH_S) 1947 u8 max_lane_speed; 1948 #define ICE_AQC_PORT_OPT_MAX_LANE_S 0 1949 #define ICE_AQC_PORT_OPT_MAX_LANE_M (0xF << ICE_AQC_PORT_OPT_MAX_LANE_S) 1950 #define ICE_AQC_PORT_OPT_MAX_LANE_100M 0 1951 #define ICE_AQC_PORT_OPT_MAX_LANE_1G 1 1952 #define ICE_AQC_PORT_OPT_MAX_LANE_2500M 2 1953 #define ICE_AQC_PORT_OPT_MAX_LANE_5G 3 1954 #define ICE_AQC_PORT_OPT_MAX_LANE_10G 4 1955 #define ICE_AQC_PORT_OPT_MAX_LANE_25G 5 1956 #define ICE_AQC_PORT_OPT_MAX_LANE_50G 6 1957 #define ICE_AQC_PORT_OPT_MAX_LANE_100G 7 1958 u8 global_scid[2]; 1959 u8 phy_scid[2]; 1960 }; 1961 1962 /* Set Port Option (direct, 0x06EB) */ 1963 struct ice_aqc_set_port_option { 1964 u8 lport_num; 1965 u8 lport_num_valid; 1966 #define ICE_AQC_SET_PORT_OPT_PORT_NUM_VALID BIT(0) 1967 u8 selected_port_option; 1968 u8 rsvd[13]; 1969 }; 1970 1971 /* Set/Get GPIO (direct, 0x06EC/0x06ED) */ 1972 struct ice_aqc_gpio { 1973 __le16 gpio_ctrl_handle; 1974 #define ICE_AQC_GPIO_HANDLE_S 0 1975 #define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S) 1976 u8 gpio_num; 1977 u8 gpio_val; 1978 u8 rsvd[12]; 1979 }; 1980 1981 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 1982 struct ice_aqc_sff_eeprom { 1983 u8 lport_num; 1984 u8 lport_num_valid; 1985 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 1986 __le16 i2c_bus_addr; 1987 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 1988 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 1989 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 1990 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 1991 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 1992 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 1993 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 1994 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 1995 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 1996 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 1997 #define ICE_AQC_SFF_IS_WRITE BIT(15) 1998 __le16 i2c_mem_addr; 1999 __le16 eeprom_page; 2000 #define ICE_AQC_SFF_EEPROM_BANK_S 0 2001 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 2002 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 2003 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 2004 __le32 addr_high; 2005 __le32 addr_low; 2006 }; 2007 2008 /* SW Set GPIO command (indirect 0x6EF) 2009 * SW Get GPIO command (indirect 0x6F0) 2010 */ 2011 struct ice_aqc_sw_gpio { 2012 __le16 gpio_ctrl_handle; 2013 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S 0 2014 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_M (0x3FF << ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S) 2015 u8 gpio_num; 2016 #define ICE_AQC_SW_GPIO_NUMBER_S 0 2017 #define ICE_AQC_SW_GPIO_NUMBER_M (0x1F << ICE_AQC_SW_GPIO_NUMBER_S) 2018 u8 gpio_params; 2019 #define ICE_AQC_SW_GPIO_PARAMS_DIRECTION BIT(1) 2020 #define ICE_AQC_SW_GPIO_PARAMS_VALUE BIT(0) 2021 u8 rsvd[12]; 2022 }; 2023 2024 /* NVM Read command (indirect 0x0701) 2025 * NVM Erase commands (direct 0x0702) 2026 * NVM Write commands (indirect 0x0703) 2027 * NVM Write Activate commands (direct 0x0707) 2028 * NVM Shadow RAM Dump commands (direct 0x0707) 2029 */ 2030 struct ice_aqc_nvm { 2031 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 2032 __le16 offset_low; 2033 u8 offset_high; /* For Write Activate offset_high is used as flags2 */ 2034 u8 cmd_flags; 2035 #define ICE_AQC_NVM_LAST_CMD BIT(0) 2036 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */ 2037 #define ICE_AQC_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */ 2038 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 2039 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 2040 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 2041 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 2042 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 2043 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 2044 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) 2045 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) 2046 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) 2047 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 2048 #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3) 2049 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 2050 #define ICE_AQC_NVM_POR_FLAG 0 /* Used by NVM Write completion on ARQ */ 2051 #define ICE_AQC_NVM_PERST_FLAG 1 2052 #define ICE_AQC_NVM_EMPR_FLAG 2 2053 __le16 module_typeid; 2054 __le16 length; 2055 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 2056 __le32 addr_high; 2057 __le32 addr_low; 2058 }; 2059 2060 /* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */ 2061 #define ICE_AQC_NVM_SECTOR_UNIT 4096 /* In Bytes */ 2062 #define ICE_AQC_NVM_WORD_UNIT 2 /* In Bytes */ 2063 2064 #define ICE_AQC_NVM_START_POINT 0 2065 #define ICE_AQC_NVM_EMP_SR_PTR_OFFSET 0x90 2066 #define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN 2 /* In Bytes */ 2067 #define ICE_AQC_NVM_EMP_SR_PTR_M MAKEMASK(0x7FFF, 0) 2068 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S 15 2069 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M BIT(15) 2070 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR 1 2071 2072 #define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET 0x46 2073 #define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN 2 /* In Bytes */ 2074 #define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */ 2075 2076 #define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129 2077 #define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */ 2078 #define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0) 2079 #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */ 2080 #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */ 2081 2082 #define ICE_AQC_NVM_MINSREV_MOD_ID 0x130 2083 2084 /* Used for reading and writing MinSRev using 0x0701 and 0x0703. Note that the 2085 * type field is excluded from the section when reading and writing from 2086 * a module using the module_typeid field with these AQ commands. 2087 */ 2088 struct ice_aqc_nvm_minsrev { 2089 __le16 length; 2090 __le16 validity; 2091 #define ICE_AQC_NVM_MINSREV_NVM_VALID BIT(0) 2092 #define ICE_AQC_NVM_MINSREV_OROM_VALID BIT(1) 2093 __le16 nvm_minsrev_l; 2094 __le16 nvm_minsrev_h; 2095 __le16 orom_minsrev_l; 2096 __le16 orom_minsrev_h; 2097 }; 2098 2099 /* Used for 0x0704 as well as for 0x0705 commands */ 2100 struct ice_aqc_nvm_cfg { 2101 u8 cmd_flags; 2102 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0) 2103 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1) 2104 #define ICE_AQC_ANVM_NEW_CFG BIT(2) 2105 u8 reserved; 2106 __le16 count; 2107 __le16 id; 2108 u8 reserved1[2]; 2109 __le32 addr_high; 2110 __le32 addr_low; 2111 }; 2112 2113 struct ice_aqc_nvm_cfg_data { 2114 __le16 field_id; 2115 __le16 field_options; 2116 __le16 field_value; 2117 }; 2118 2119 /* NVM Checksum Command (direct, 0x0706) */ 2120 struct ice_aqc_nvm_checksum { 2121 u8 flags; 2122 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 2123 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 2124 u8 rsvd; 2125 __le16 checksum; /* Used only by response */ 2126 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 2127 u8 rsvd2[12]; 2128 }; 2129 2130 /* 2131 * Send to PF command (indirect 0x0801) ID is only used by PF 2132 * 2133 * Send to VF command (indirect 0x0802) ID is only used by PF 2134 * 2135 */ 2136 struct ice_aqc_pf_vf_msg { 2137 __le32 id; 2138 u32 reserved; 2139 __le32 addr_high; 2140 __le32 addr_low; 2141 }; 2142 2143 /* Write/Read Alternate - Direct (direct 0x0900/0x0902) */ 2144 struct ice_aqc_read_write_alt_direct { 2145 __le32 dword0_addr; 2146 __le32 dword0_value; 2147 __le32 dword1_addr; 2148 __le32 dword1_value; 2149 }; 2150 2151 /* Write/Read Alternate - Indirect (indirect 0x0901/0x0903) */ 2152 struct ice_aqc_read_write_alt_indirect { 2153 __le32 base_dword_addr; 2154 __le32 num_dwords; 2155 __le32 addr_high; 2156 __le32 addr_low; 2157 }; 2158 2159 /* Done Alternate Write (direct 0x0904) */ 2160 struct ice_aqc_done_alt_write { 2161 u8 flags; 2162 #define ICE_AQC_CMD_UEFI_BIOS_MODE BIT(0) 2163 #define ICE_AQC_RESP_RESET_NEEDED BIT(1) 2164 u8 reserved[15]; 2165 }; 2166 2167 /* Clear Port Alternate Write (direct 0x0906) */ 2168 struct ice_aqc_clear_port_alt_write { 2169 u8 reserved[16]; 2170 }; 2171 2172 /* Get LLDP MIB (indirect 0x0A00) 2173 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 2174 * as the format is the same. 2175 */ 2176 struct ice_aqc_lldp_get_mib { 2177 u8 type; 2178 #define ICE_AQ_LLDP_MIB_TYPE_S 0 2179 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 2180 #define ICE_AQ_LLDP_MIB_LOCAL 0 2181 #define ICE_AQ_LLDP_MIB_REMOTE 1 2182 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 2183 #define ICE_AQ_LLDP_BRID_TYPE_S 2 2184 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 2185 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 2186 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 2187 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 2188 #define ICE_AQ_LLDP_TX_S 0x4 2189 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 2190 #define ICE_AQ_LLDP_TX_ACTIVE 0 2191 #define ICE_AQ_LLDP_TX_SUSPENDED 1 2192 #define ICE_AQ_LLDP_TX_FLUSHED 3 2193 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 2194 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 2195 * Get LLDP MIB (0x0A00) response only. 2196 */ 2197 u8 reserved1; 2198 __le16 local_len; 2199 __le16 remote_len; 2200 u8 reserved2[2]; 2201 __le32 addr_high; 2202 __le32 addr_low; 2203 }; 2204 2205 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 2206 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 2207 struct ice_aqc_lldp_set_mib_change { 2208 u8 command; 2209 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2210 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 2211 u8 reserved[15]; 2212 }; 2213 2214 /* Add LLDP TLV (indirect 0x0A02) 2215 * Delete LLDP TLV (indirect 0x0A04) 2216 */ 2217 struct ice_aqc_lldp_add_delete_tlv { 2218 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2219 u8 reserved1[1]; 2220 __le16 len; 2221 u8 reserved2[4]; 2222 __le32 addr_high; 2223 __le32 addr_low; 2224 }; 2225 2226 /* Update LLDP TLV (indirect 0x0A03) */ 2227 struct ice_aqc_lldp_update_tlv { 2228 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2229 u8 reserved; 2230 __le16 old_len; 2231 __le16 new_offset; 2232 __le16 new_len; 2233 __le32 addr_high; 2234 __le32 addr_low; 2235 }; 2236 2237 /* Stop LLDP (direct 0x0A05) */ 2238 struct ice_aqc_lldp_stop { 2239 u8 command; 2240 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 2241 #define ICE_AQ_LLDP_AGENT_STOP 0x0 2242 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 2243 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 2244 u8 reserved[15]; 2245 }; 2246 2247 /* Start LLDP (direct 0x0A06) */ 2248 struct ice_aqc_lldp_start { 2249 u8 command; 2250 #define ICE_AQ_LLDP_AGENT_START BIT(0) 2251 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 2252 u8 reserved[15]; 2253 }; 2254 2255 /* Get CEE DCBX Oper Config (0x0A07) 2256 * The command uses the generic descriptor struct and 2257 * returns the struct below as an indirect response. 2258 */ 2259 struct ice_aqc_get_cee_dcb_cfg_resp { 2260 u8 oper_num_tc; 2261 u8 oper_prio_tc[4]; 2262 u8 oper_tc_bw[8]; 2263 u8 oper_pfc_en; 2264 __le16 oper_app_prio; 2265 #define ICE_AQC_CEE_APP_FCOE_S 0 2266 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 2267 #define ICE_AQC_CEE_APP_ISCSI_S 3 2268 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 2269 #define ICE_AQC_CEE_APP_FIP_S 8 2270 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 2271 __le32 tlv_status; 2272 #define ICE_AQC_CEE_PG_STATUS_S 0 2273 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 2274 #define ICE_AQC_CEE_PFC_STATUS_S 3 2275 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 2276 #define ICE_AQC_CEE_FCOE_STATUS_S 8 2277 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 2278 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 2279 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 2280 #define ICE_AQC_CEE_FIP_STATUS_S 16 2281 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 2282 u8 reserved[12]; 2283 }; 2284 2285 /* Set Local LLDP MIB (indirect 0x0A08) 2286 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 2287 */ 2288 struct ice_aqc_lldp_set_local_mib { 2289 u8 type; 2290 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 2291 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 2292 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 2293 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 2294 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 2295 u8 reserved0; 2296 __le16 length; 2297 u8 reserved1[4]; 2298 __le32 addr_high; 2299 __le32 addr_low; 2300 }; 2301 2302 struct ice_aqc_lldp_set_local_mib_resp { 2303 u8 status; 2304 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0) 2305 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0 2306 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT SET_LOCAL_MIB_RESP_EVENT_M 2307 u8 reserved[15]; 2308 }; 2309 2310 /* Stop/Start LLDP Agent (direct 0x0A09) 2311 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 2312 * The same structure is used for the response, with the command field 2313 * being used as the status field. 2314 */ 2315 struct ice_aqc_lldp_stop_start_specific_agent { 2316 u8 command; 2317 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 2318 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 2319 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 2320 u8 reserved[15]; 2321 }; 2322 2323 /* LLDP Filter Control (direct 0x0A0A) */ 2324 struct ice_aqc_lldp_filter_ctrl { 2325 u8 cmd_flags; 2326 #define ICE_AQC_LLDP_FILTER_ACTION_M MAKEMASK(3, 0) 2327 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0 2328 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1 2329 #define ICE_AQC_LLDP_FILTER_ACTION_UPDATE 0x2 2330 u8 reserved1; 2331 __le16 vsi_num; 2332 u8 reserved2[12]; 2333 }; 2334 2335 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 2336 struct ice_aqc_get_set_rss_key { 2337 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 2338 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 2339 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 2340 __le16 vsi_id; 2341 u8 reserved[6]; 2342 __le32 addr_high; 2343 __le32 addr_low; 2344 }; 2345 2346 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 2347 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 2348 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 2349 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 2350 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 2351 2352 /** 2353 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer 2354 * @standard_rss_key: 40 most significant bytes of hash key 2355 * @extended_hash_key: 12 least significant bytes of hash key 2356 * 2357 * Set/Get 40 byte hash key using standard_rss_key field, and set 2358 * extended_hash_key field to zero. Set/Get 52 byte hash key using 2359 * standard_rss_key field for 40 most significant bytes and the 2360 * extended_hash_key field for the 12 least significant bytes of hash key. 2361 */ 2362 struct ice_aqc_get_set_rss_keys { 2363 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 2364 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 2365 }; 2366 2367 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 2368 struct ice_aqc_get_set_rss_lut { 2369 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 2370 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 2371 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 2372 __le16 vsi_id; 2373 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 2374 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 2375 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 2376 2377 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 2378 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 2379 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 2380 2381 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 2382 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 2383 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 2384 2385 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 2386 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 2387 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 2388 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 2389 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 2390 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 2391 2392 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 2393 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 2394 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 2395 2396 __le16 flags; 2397 __le32 reserved; 2398 __le32 addr_high; 2399 __le32 addr_low; 2400 }; 2401 2402 /* Add Tx LAN Queues (indirect 0x0C30) */ 2403 struct ice_aqc_add_txqs { 2404 u8 num_qgrps; 2405 u8 reserved[3]; 2406 __le32 reserved1; 2407 __le32 addr_high; 2408 __le32 addr_low; 2409 }; 2410 2411 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 2412 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 2413 */ 2414 struct ice_aqc_add_txqs_perq { 2415 __le16 txq_id; 2416 u8 rsvd[2]; 2417 __le32 q_teid; 2418 u8 txq_ctx[22]; 2419 u8 rsvd2[2]; 2420 struct ice_aqc_txsched_elem info; 2421 }; 2422 2423 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 2424 * is an array of the following structs. Please note that the length of 2425 * each struct ice_aqc_add_tx_qgrp is variable due 2426 * to the variable number of queues in each group! 2427 */ 2428 struct ice_aqc_add_tx_qgrp { 2429 __le32 parent_teid; 2430 u8 num_txqs; 2431 u8 rsvd[3]; 2432 struct ice_aqc_add_txqs_perq txqs[STRUCT_HACK_VAR_LEN]; 2433 }; 2434 2435 /* Disable Tx LAN Queues (indirect 0x0C31) */ 2436 struct ice_aqc_dis_txqs { 2437 u8 cmd_type; 2438 #define ICE_AQC_Q_DIS_CMD_S 0 2439 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 2440 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 2441 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 2442 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 2443 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 2444 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 2445 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 2446 u8 num_entries; 2447 __le16 vmvf_and_timeout; 2448 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 2449 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 2450 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 2451 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 2452 __le32 blocked_cgds; 2453 __le32 addr_high; 2454 __le32 addr_low; 2455 }; 2456 2457 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 2458 * contains the following structures, arrayed one after the 2459 * other. 2460 * Note: Since the q_id is 16 bits wide, if the 2461 * number of queues is even, then 2 bytes of alignment MUST be 2462 * added before the start of the next group, to allow correct 2463 * alignment of the parent_teid field. 2464 */ 2465 #pragma pack(1) 2466 struct ice_aqc_dis_txq_item { 2467 __le32 parent_teid; 2468 u8 num_qs; 2469 u8 rsvd; 2470 /* The length of the q_id array varies according to num_qs */ 2471 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 2472 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 2473 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2474 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 2475 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2476 __le16 q_id[STRUCT_HACK_VAR_LEN]; 2477 }; 2478 #pragma pack() 2479 2480 /* Tx LAN Queues Cleanup Event (0x0C31) */ 2481 struct ice_aqc_txqs_cleanup { 2482 __le16 caller_opc; 2483 __le16 cmd_tag; 2484 u8 reserved[12]; 2485 }; 2486 2487 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */ 2488 struct ice_aqc_move_txqs { 2489 u8 cmd_type; 2490 #define ICE_AQC_Q_CMD_TYPE_S 0 2491 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S) 2492 #define ICE_AQC_Q_CMD_TYPE_MOVE 1 2493 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2 2494 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3 2495 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2) 2496 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3) 2497 u8 num_qs; 2498 u8 rsvd; 2499 u8 timeout; 2500 #define ICE_AQC_Q_CMD_TIMEOUT_S 2 2501 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S) 2502 __le32 blocked_cgds; 2503 __le32 addr_high; 2504 __le32 addr_low; 2505 }; 2506 2507 /* Per-queue data buffer for the Move Tx LAN Queues command/response */ 2508 struct ice_aqc_move_txqs_elem { 2509 __le16 txq_id; 2510 u8 q_cgd; 2511 u8 rsvd; 2512 __le32 q_teid; 2513 }; 2514 2515 /* Indirect data buffer for the Move Tx LAN Queues command/response */ 2516 struct ice_aqc_move_txqs_data { 2517 __le32 src_teid; 2518 __le32 dest_teid; 2519 struct ice_aqc_move_txqs_elem txqs[STRUCT_HACK_VAR_LEN]; 2520 }; 2521 2522 /* Download Package (indirect 0x0C40) */ 2523 /* Also used for Update Package (indirect 0x0C42 and 0x0C41) */ 2524 struct ice_aqc_download_pkg { 2525 u8 flags; 2526 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 2527 u8 reserved[3]; 2528 __le32 reserved1; 2529 __le32 addr_high; 2530 __le32 addr_low; 2531 }; 2532 2533 struct ice_aqc_download_pkg_resp { 2534 __le32 error_offset; 2535 __le32 error_info; 2536 __le32 addr_high; 2537 __le32 addr_low; 2538 }; 2539 2540 /* Get Package Info List (indirect 0x0C43) */ 2541 struct ice_aqc_get_pkg_info_list { 2542 __le32 reserved1; 2543 __le32 reserved2; 2544 __le32 addr_high; 2545 __le32 addr_low; 2546 }; 2547 2548 /* Version format for packages */ 2549 struct ice_pkg_ver { 2550 u8 major; 2551 u8 minor; 2552 u8 update; 2553 u8 draft; 2554 }; 2555 2556 #define ICE_PKG_NAME_SIZE 32 2557 #define ICE_SEG_ID_SIZE 28 2558 #define ICE_SEG_NAME_SIZE 28 2559 2560 struct ice_aqc_get_pkg_info { 2561 struct ice_pkg_ver ver; 2562 char name[ICE_SEG_NAME_SIZE]; 2563 __le32 track_id; 2564 u8 is_in_nvm; 2565 u8 is_active; 2566 u8 is_active_at_boot; 2567 u8 is_modified; 2568 }; 2569 2570 /* Get Package Info List response buffer format (0x0C43) */ 2571 struct ice_aqc_get_pkg_info_resp { 2572 __le32 count; 2573 struct ice_aqc_get_pkg_info pkg_info[STRUCT_HACK_VAR_LEN]; 2574 }; 2575 2576 /* Driver Shared Parameters (direct, 0x0C90) */ 2577 struct ice_aqc_driver_shared_params { 2578 u8 set_or_get_op; 2579 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0) 2580 #define ICE_AQC_DRIVER_PARAM_SET 0 2581 #define ICE_AQC_DRIVER_PARAM_GET 1 2582 u8 param_indx; 2583 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15 2584 u8 rsvd[2]; 2585 __le32 param_val; 2586 __le32 addr_high; 2587 __le32 addr_low; 2588 }; 2589 2590 /* Lan Queue Overflow Event (direct, 0x1001) */ 2591 struct ice_aqc_event_lan_overflow { 2592 __le32 prtdcb_ruptq; 2593 __le32 qtx_ctl; 2594 u8 reserved[8]; 2595 }; 2596 2597 /* Set Health Status (direct 0xFF20) */ 2598 struct ice_aqc_set_health_status_config { 2599 u8 event_source; 2600 #define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0) 2601 #define ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1) 2602 #define ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2) 2603 u8 reserved[15]; 2604 }; 2605 2606 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_STRICT 0x101 2607 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_TYPE 0x102 2608 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_QUAL 0x103 2609 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_COMM 0x104 2610 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_CONFLICT 0x105 2611 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_NOT_PRESENT 0x106 2612 #define ICE_AQC_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED 0x107 2613 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT 0x108 2614 #define ICE_AQC_HEALTH_STATUS_ERR_INVALID_LINK_CFG 0x10B 2615 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_ACCESS 0x10C 2616 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_UNREACHABLE 0x10D 2617 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_MOD_LIMITED 0x10F 2618 #define ICE_AQC_HEALTH_STATUS_ERR_PARALLEL_FAULT 0x110 2619 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED 0x111 2620 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST_TOPO 0x112 2621 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST 0x113 2622 #define ICE_AQC_HEALTH_STATUS_ERR_TOPO_CONFLICT 0x114 2623 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS 0x115 2624 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME 0x116 2625 #define ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT 0x117 2626 #define ICE_AQC_HEALTH_STATUS_INFO_RECOVERY 0x500 2627 #define ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS 0x501 2628 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH 0x502 2629 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_AUTH 0x503 2630 #define ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH 0x504 2631 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT 0x505 2632 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT 0x506 2633 #define ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB 0x509 2634 2635 /* Get Health Status codes (indirect 0xFF21) */ 2636 struct ice_aqc_get_supported_health_status_codes { 2637 __le16 health_code_count; 2638 u8 reserved[6]; 2639 __le32 addr_high; 2640 __le32 addr_low; 2641 }; 2642 2643 /* Get Health Status (indirect 0xFF22) */ 2644 struct ice_aqc_get_health_status { 2645 __le16 health_status_count; 2646 u8 reserved[6]; 2647 __le32 addr_high; 2648 __le32 addr_low; 2649 }; 2650 2651 /* Get Health Status event buffer entry, (0xFF22) 2652 * repeated per reported health status 2653 */ 2654 struct ice_aqc_health_status_elem { 2655 __le16 health_status_code; 2656 __le16 event_source; 2657 #define ICE_AQC_HEALTH_STATUS_PF (0x1) 2658 #define ICE_AQC_HEALTH_STATUS_PORT (0x2) 2659 #define ICE_AQC_HEALTH_STATUS_GLOBAL (0x3) 2660 __le32 internal_data1; 2661 #define ICE_AQC_HEALTH_STATUS_UNDEFINED_DATA (0xDEADBEEF) 2662 __le32 internal_data2; 2663 }; 2664 2665 /* Clear Health Status (direct 0xFF23) */ 2666 struct ice_aqc_clear_health_status { 2667 __le32 reserved[4]; 2668 }; 2669 2670 /** 2671 * struct ice_aq_desc - Admin Queue (AQ) descriptor 2672 * @flags: ICE_AQ_FLAG_* flags 2673 * @opcode: AQ command opcode 2674 * @datalen: length in bytes of indirect/external data buffer 2675 * @retval: return value from firmware 2676 * @cookie_high: opaque data high-half 2677 * @cookie_low: opaque data low-half 2678 * @params: command-specific parameters 2679 * 2680 * Descriptor format for commands the driver posts on the Admin Transmit Queue 2681 * (ATQ). The firmware writes back onto the command descriptor and returns 2682 * the result of the command. Asynchronous events that are not an immediate 2683 * result of the command are written to the Admin Receive Queue (ARQ) using 2684 * the same descriptor format. Descriptors are in little-endian notation with 2685 * 32-bit words. 2686 */ 2687 struct ice_aq_desc { 2688 __le16 flags; 2689 __le16 opcode; 2690 __le16 datalen; 2691 __le16 retval; 2692 __le32 cookie_high; 2693 __le32 cookie_low; 2694 union { 2695 u8 raw[16]; 2696 struct ice_aqc_generic generic; 2697 struct ice_aqc_get_ver get_ver; 2698 struct ice_aqc_driver_ver driver_ver; 2699 struct ice_aqc_q_shutdown q_shutdown; 2700 struct ice_aqc_get_exp_err exp_err; 2701 struct ice_aqc_req_res res_owner; 2702 struct ice_aqc_manage_mac_read mac_read; 2703 struct ice_aqc_manage_mac_write mac_write; 2704 struct ice_aqc_clear_pxe clear_pxe; 2705 struct ice_aqc_config_no_drop_policy no_drop; 2706 struct ice_aqc_add_update_mir_rule add_update_rule; 2707 struct ice_aqc_delete_mir_rule del_rule; 2708 struct ice_aqc_list_caps get_cap; 2709 struct ice_aqc_get_phy_caps get_phy; 2710 struct ice_aqc_set_phy_cfg set_phy; 2711 struct ice_aqc_restart_an restart_an; 2712 struct ice_aqc_dnl_get_status get_status; 2713 struct ice_aqc_dnl_run_command dnl_run; 2714 struct ice_aqc_dnl_call_command dnl_call; 2715 struct ice_aqc_dnl_read_write_command dnl_read_write; 2716 struct ice_aqc_dnl_read_write_response dnl_read_write_resp; 2717 struct ice_aqc_dnl_set_breakpoints_command dnl_set_brk; 2718 struct ice_aqc_dnl_read_log_command dnl_read_log; 2719 struct ice_aqc_dnl_read_log_response dnl_read_log_resp; 2720 struct ice_aqc_i2c read_write_i2c; 2721 struct ice_aqc_mdio read_write_mdio; 2722 struct ice_aqc_gpio_by_func read_write_gpio_by_func; 2723 struct ice_aqc_gpio read_write_gpio; 2724 struct ice_aqc_set_led set_led; 2725 struct ice_aqc_sff_eeprom read_write_sff_param; 2726 struct ice_aqc_set_port_id_led set_port_id_led; 2727 struct ice_aqc_get_port_options get_port_options; 2728 struct ice_aqc_set_port_option set_port_option; 2729 struct ice_aqc_get_sw_cfg get_sw_conf; 2730 struct ice_aqc_set_port_params set_port_params; 2731 struct ice_aqc_sw_rules sw_rules; 2732 struct ice_aqc_storm_cfg storm_conf; 2733 struct ice_aqc_get_topo get_topo; 2734 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 2735 struct ice_aqc_query_txsched_res query_sched_res; 2736 struct ice_aqc_query_node_to_root query_node_to_root; 2737 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd; 2738 struct ice_aqc_query_port_ets port_ets; 2739 struct ice_aqc_rl_profile rl_profile; 2740 struct ice_aqc_nvm nvm; 2741 struct ice_aqc_nvm_cfg nvm_cfg; 2742 struct ice_aqc_nvm_checksum nvm_checksum; 2743 struct ice_aqc_pf_vf_msg virt; 2744 struct ice_aqc_read_write_alt_direct read_write_alt_direct; 2745 struct ice_aqc_read_write_alt_indirect read_write_alt_indirect; 2746 struct ice_aqc_done_alt_write done_alt_write; 2747 struct ice_aqc_clear_port_alt_write clear_port_alt_write; 2748 struct ice_aqc_pfc_ignore pfc_ignore; 2749 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode; 2750 struct ice_aqc_set_dcb_params set_dcb_params; 2751 struct ice_aqc_lldp_get_mib lldp_get_mib; 2752 struct ice_aqc_lldp_set_mib_change lldp_set_event; 2753 struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv; 2754 struct ice_aqc_lldp_update_tlv lldp_update_tlv; 2755 struct ice_aqc_lldp_stop lldp_stop; 2756 struct ice_aqc_lldp_start lldp_start; 2757 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 2758 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 2759 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl; 2760 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 2761 struct ice_aqc_get_set_rss_key get_set_rss_key; 2762 struct ice_aqc_add_txqs add_txqs; 2763 struct ice_aqc_dis_txqs dis_txqs; 2764 struct ice_aqc_move_txqs move_txqs; 2765 struct ice_aqc_txqs_cleanup txqs_cleanup; 2766 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 2767 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 2768 struct ice_aqc_get_vsi_resp get_vsi_resp; 2769 struct ice_aqc_download_pkg download_pkg; 2770 struct ice_aqc_get_pkg_info_list get_pkg_info_list; 2771 struct ice_aqc_driver_shared_params drv_shared_params; 2772 struct ice_aqc_set_mac_lb set_mac_lb; 2773 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 2774 struct ice_aqc_get_res_alloc get_res; 2775 struct ice_aqc_get_allocd_res_desc get_res_desc; 2776 struct ice_aqc_set_mac_cfg set_mac_cfg; 2777 struct ice_aqc_set_event_mask set_event_mask; 2778 struct ice_aqc_get_link_status get_link_status; 2779 struct ice_aqc_event_lan_overflow lan_overflow; 2780 struct ice_aqc_get_link_topo get_link_topo; 2781 struct ice_aqc_set_health_status_config 2782 set_health_status_config; 2783 struct ice_aqc_get_supported_health_status_codes 2784 get_supported_health_status_codes; 2785 struct ice_aqc_get_health_status get_health_status; 2786 struct ice_aqc_clear_health_status clear_health_status; 2787 } params; 2788 }; 2789 2790 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 2791 #define ICE_AQ_LG_BUF 512 2792 2793 /* Flags sub-structure 2794 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 2795 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 2796 */ 2797 2798 /* command flags and offsets */ 2799 #define ICE_AQ_FLAG_DD_S 0 2800 #define ICE_AQ_FLAG_CMP_S 1 2801 #define ICE_AQ_FLAG_ERR_S 2 2802 #define ICE_AQ_FLAG_VFE_S 3 2803 #define ICE_AQ_FLAG_LB_S 9 2804 #define ICE_AQ_FLAG_RD_S 10 2805 #define ICE_AQ_FLAG_VFC_S 11 2806 #define ICE_AQ_FLAG_BUF_S 12 2807 #define ICE_AQ_FLAG_SI_S 13 2808 #define ICE_AQ_FLAG_EI_S 14 2809 #define ICE_AQ_FLAG_FE_S 15 2810 2811 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */ 2812 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */ 2813 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 2814 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */ 2815 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 2816 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 2817 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */ 2818 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 2819 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 2820 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */ 2821 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */ 2822 2823 /* error codes */ 2824 enum ice_aq_err { 2825 ICE_AQ_RC_OK = 0, /* Success */ 2826 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 2827 ICE_AQ_RC_ENOENT = 2, /* No such element */ 2828 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */ 2829 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */ 2830 ICE_AQ_RC_EIO = 5, /* I/O error */ 2831 ICE_AQ_RC_ENXIO = 6, /* No such resource */ 2832 ICE_AQ_RC_E2BIG = 7, /* Arg too long */ 2833 ICE_AQ_RC_EAGAIN = 8, /* Try again */ 2834 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 2835 ICE_AQ_RC_EACCES = 10, /* Permission denied */ 2836 ICE_AQ_RC_EFAULT = 11, /* Bad address */ 2837 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 2838 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 2839 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 2840 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 2841 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 2842 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 2843 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */ 2844 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 2845 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 2846 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 2847 ICE_AQ_RC_EFBIG = 22, /* File too big */ 2848 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */ 2849 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 2850 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 2851 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 2852 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 2853 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 2854 ICE_AQ_RC_EACCES_BMCU = 29, /* BMC Update in progress */ 2855 }; 2856 2857 /* Admin Queue command opcodes */ 2858 enum ice_adminq_opc { 2859 /* AQ commands */ 2860 ice_aqc_opc_get_ver = 0x0001, 2861 ice_aqc_opc_driver_ver = 0x0002, 2862 ice_aqc_opc_q_shutdown = 0x0003, 2863 ice_aqc_opc_get_exp_err = 0x0005, 2864 2865 /* resource ownership */ 2866 ice_aqc_opc_req_res = 0x0008, 2867 ice_aqc_opc_release_res = 0x0009, 2868 2869 /* device/function capabilities */ 2870 ice_aqc_opc_list_func_caps = 0x000A, 2871 ice_aqc_opc_list_dev_caps = 0x000B, 2872 2873 /* manage MAC address */ 2874 ice_aqc_opc_manage_mac_read = 0x0107, 2875 ice_aqc_opc_manage_mac_write = 0x0108, 2876 2877 /* PXE */ 2878 ice_aqc_opc_clear_pxe_mode = 0x0110, 2879 2880 ice_aqc_opc_config_no_drop_policy = 0x0112, 2881 2882 /* internal switch commands */ 2883 ice_aqc_opc_get_sw_cfg = 0x0200, 2884 ice_aqc_opc_set_port_params = 0x0203, 2885 2886 /* Alloc/Free/Get Resources */ 2887 ice_aqc_opc_get_res_alloc = 0x0204, 2888 ice_aqc_opc_alloc_res = 0x0208, 2889 ice_aqc_opc_free_res = 0x0209, 2890 ice_aqc_opc_get_allocd_res_desc = 0x020A, 2891 2892 /* VSI commands */ 2893 ice_aqc_opc_add_vsi = 0x0210, 2894 ice_aqc_opc_update_vsi = 0x0211, 2895 ice_aqc_opc_get_vsi_params = 0x0212, 2896 ice_aqc_opc_free_vsi = 0x0213, 2897 2898 /* Mirroring rules - add/update, delete */ 2899 ice_aqc_opc_add_update_mir_rule = 0x0260, 2900 ice_aqc_opc_del_mir_rule = 0x0261, 2901 2902 /* storm configuration */ 2903 ice_aqc_opc_set_storm_cfg = 0x0280, 2904 ice_aqc_opc_get_storm_cfg = 0x0281, 2905 2906 /* switch rules population commands */ 2907 ice_aqc_opc_add_sw_rules = 0x02A0, 2908 ice_aqc_opc_update_sw_rules = 0x02A1, 2909 ice_aqc_opc_remove_sw_rules = 0x02A2, 2910 ice_aqc_opc_get_sw_rules = 0x02A3, 2911 ice_aqc_opc_clear_pf_cfg = 0x02A4, 2912 2913 /* DCB commands */ 2914 ice_aqc_opc_pfc_ignore = 0x0301, 2915 ice_aqc_opc_query_pfc_mode = 0x0302, 2916 ice_aqc_opc_set_pfc_mode = 0x0303, 2917 ice_aqc_opc_set_dcb_params = 0x0306, 2918 2919 /* transmit scheduler commands */ 2920 ice_aqc_opc_get_dflt_topo = 0x0400, 2921 ice_aqc_opc_add_sched_elems = 0x0401, 2922 ice_aqc_opc_cfg_sched_elems = 0x0403, 2923 ice_aqc_opc_get_sched_elems = 0x0404, 2924 ice_aqc_opc_move_sched_elems = 0x0408, 2925 ice_aqc_opc_suspend_sched_elems = 0x0409, 2926 ice_aqc_opc_resume_sched_elems = 0x040A, 2927 ice_aqc_opc_query_port_ets = 0x040E, 2928 ice_aqc_opc_delete_sched_elems = 0x040F, 2929 ice_aqc_opc_add_rl_profiles = 0x0410, 2930 ice_aqc_opc_query_rl_profiles = 0x0411, 2931 ice_aqc_opc_query_sched_res = 0x0412, 2932 ice_aqc_opc_query_node_to_root = 0x0413, 2933 ice_aqc_opc_cfg_l2_node_cgd = 0x0414, 2934 ice_aqc_opc_remove_rl_profiles = 0x0415, 2935 2936 /* PHY commands */ 2937 ice_aqc_opc_get_phy_caps = 0x0600, 2938 ice_aqc_opc_set_phy_cfg = 0x0601, 2939 ice_aqc_opc_set_mac_cfg = 0x0603, 2940 ice_aqc_opc_restart_an = 0x0605, 2941 ice_aqc_opc_get_link_status = 0x0607, 2942 ice_aqc_opc_set_event_mask = 0x0613, 2943 ice_aqc_opc_set_mac_lb = 0x0620, 2944 ice_aqc_opc_dnl_get_status = 0x0680, 2945 ice_aqc_opc_dnl_run = 0x0681, 2946 ice_aqc_opc_dnl_call = 0x0682, 2947 ice_aqc_opc_dnl_read_sto = 0x0683, 2948 ice_aqc_opc_dnl_write_sto = 0x0684, 2949 ice_aqc_opc_dnl_set_breakpoints = 0x0686, 2950 ice_aqc_opc_dnl_read_log = 0x0687, 2951 ice_aqc_opc_get_link_topo = 0x06E0, 2952 ice_aqc_opc_get_link_topo_pin = 0x06E1, 2953 ice_aqc_opc_read_i2c = 0x06E2, 2954 ice_aqc_opc_write_i2c = 0x06E3, 2955 ice_aqc_opc_read_mdio = 0x06E4, 2956 ice_aqc_opc_write_mdio = 0x06E5, 2957 ice_aqc_opc_set_gpio_by_func = 0x06E6, 2958 ice_aqc_opc_get_gpio_by_func = 0x06E7, 2959 ice_aqc_opc_set_led = 0x06E8, 2960 ice_aqc_opc_set_port_id_led = 0x06E9, 2961 ice_aqc_opc_get_port_options = 0x06EA, 2962 ice_aqc_opc_set_port_option = 0x06EB, 2963 ice_aqc_opc_set_gpio = 0x06EC, 2964 ice_aqc_opc_get_gpio = 0x06ED, 2965 ice_aqc_opc_sff_eeprom = 0x06EE, 2966 ice_aqc_opc_sw_set_gpio = 0x06EF, 2967 ice_aqc_opc_sw_get_gpio = 0x06F0, 2968 2969 /* NVM commands */ 2970 ice_aqc_opc_nvm_read = 0x0701, 2971 ice_aqc_opc_nvm_erase = 0x0702, 2972 ice_aqc_opc_nvm_write = 0x0703, 2973 ice_aqc_opc_nvm_cfg_read = 0x0704, 2974 ice_aqc_opc_nvm_cfg_write = 0x0705, 2975 ice_aqc_opc_nvm_checksum = 0x0706, 2976 ice_aqc_opc_nvm_write_activate = 0x0707, 2977 ice_aqc_opc_nvm_sr_dump = 0x0707, 2978 ice_aqc_opc_nvm_save_factory_settings = 0x0708, 2979 ice_aqc_opc_nvm_update_empr = 0x0709, 2980 ice_aqc_opc_nvm_pkg_data = 0x070A, 2981 ice_aqc_opc_nvm_pass_component_tbl = 0x070B, 2982 2983 /* PF/VF mailbox commands */ 2984 ice_mbx_opc_send_msg_to_pf = 0x0801, 2985 ice_mbx_opc_send_msg_to_vf = 0x0802, 2986 /* Alternate Structure Commands */ 2987 ice_aqc_opc_write_alt_direct = 0x0900, 2988 ice_aqc_opc_write_alt_indirect = 0x0901, 2989 ice_aqc_opc_read_alt_direct = 0x0902, 2990 ice_aqc_opc_read_alt_indirect = 0x0903, 2991 ice_aqc_opc_done_alt_write = 0x0904, 2992 ice_aqc_opc_clear_port_alt_write = 0x0906, 2993 /* LLDP commands */ 2994 ice_aqc_opc_lldp_get_mib = 0x0A00, 2995 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 2996 ice_aqc_opc_lldp_add_tlv = 0x0A02, 2997 ice_aqc_opc_lldp_update_tlv = 0x0A03, 2998 ice_aqc_opc_lldp_delete_tlv = 0x0A04, 2999 ice_aqc_opc_lldp_stop = 0x0A05, 3000 ice_aqc_opc_lldp_start = 0x0A06, 3001 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 3002 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 3003 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 3004 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A, 3005 3006 /* RSS commands */ 3007 ice_aqc_opc_set_rss_key = 0x0B02, 3008 ice_aqc_opc_set_rss_lut = 0x0B03, 3009 ice_aqc_opc_get_rss_key = 0x0B04, 3010 ice_aqc_opc_get_rss_lut = 0x0B05, 3011 3012 /* Tx queue handling commands/events */ 3013 ice_aqc_opc_add_txqs = 0x0C30, 3014 ice_aqc_opc_dis_txqs = 0x0C31, 3015 ice_aqc_opc_txqs_cleanup = 0x0C31, 3016 ice_aqc_opc_move_recfg_txqs = 0x0C32, 3017 3018 /* package commands */ 3019 ice_aqc_opc_download_pkg = 0x0C40, 3020 ice_aqc_opc_upload_section = 0x0C41, 3021 ice_aqc_opc_update_pkg = 0x0C42, 3022 ice_aqc_opc_get_pkg_info_list = 0x0C43, 3023 3024 ice_aqc_opc_driver_shared_params = 0x0C90, 3025 3026 /* Standalone Commands/Events */ 3027 ice_aqc_opc_event_lan_overflow = 0x1001, 3028 3029 /* SystemDiagnostic commands */ 3030 ice_aqc_opc_set_health_status_config = 0xFF20, 3031 ice_aqc_opc_get_supported_health_status_codes = 0xFF21, 3032 ice_aqc_opc_get_health_status = 0xFF22, 3033 ice_aqc_opc_clear_health_status = 0xFF23 3034 }; 3035 3036 #endif /* _ICE_ADMINQ_CMD_H_ */ 3037