1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2021, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*$FreeBSD$*/ 32 33 #ifndef _ICE_ADMINQ_CMD_H_ 34 #define _ICE_ADMINQ_CMD_H_ 35 36 /* This header file defines the Admin Queue commands, error codes and 37 * descriptor format. It is shared between Firmware and Software. 38 */ 39 40 #define ICE_MAX_VSI 768 41 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 42 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 43 44 struct ice_aqc_generic { 45 __le32 param0; 46 __le32 param1; 47 __le32 addr_high; 48 __le32 addr_low; 49 }; 50 51 /* Get version (direct 0x0001) */ 52 struct ice_aqc_get_ver { 53 __le32 rom_ver; 54 __le32 fw_build; 55 u8 fw_branch; 56 u8 fw_major; 57 u8 fw_minor; 58 u8 fw_patch; 59 u8 api_branch; 60 u8 api_major; 61 u8 api_minor; 62 u8 api_patch; 63 }; 64 65 /* Send driver version (indirect 0x0002) */ 66 struct ice_aqc_driver_ver { 67 u8 major_ver; 68 u8 minor_ver; 69 u8 build_ver; 70 u8 subbuild_ver; 71 u8 reserved[4]; 72 __le32 addr_high; 73 __le32 addr_low; 74 }; 75 76 /* Queue Shutdown (direct 0x0003) */ 77 struct ice_aqc_q_shutdown { 78 u8 driver_unloading; 79 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 80 u8 reserved[15]; 81 }; 82 83 /* Get Expanded Error Code (0x0005, direct) */ 84 struct ice_aqc_get_exp_err { 85 __le32 reason; 86 #define ICE_AQC_EXPANDED_ERROR_NOT_PROVIDED 0xFFFFFFFF 87 __le32 identifier; 88 u8 rsvd[8]; 89 }; 90 91 /* Request resource ownership (direct 0x0008) 92 * Release resource ownership (direct 0x0009) 93 */ 94 struct ice_aqc_req_res { 95 __le16 res_id; 96 #define ICE_AQC_RES_ID_NVM 1 97 #define ICE_AQC_RES_ID_SDP 2 98 #define ICE_AQC_RES_ID_CHNG_LOCK 3 99 #define ICE_AQC_RES_ID_GLBL_LOCK 4 100 __le16 access_type; 101 #define ICE_AQC_RES_ACCESS_READ 1 102 #define ICE_AQC_RES_ACCESS_WRITE 2 103 104 /* Upon successful completion, FW writes this value and driver is 105 * expected to release resource before timeout. This value is provided 106 * in milliseconds. 107 */ 108 __le32 timeout; 109 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 110 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 111 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 112 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 113 /* For SDP: pin ID of the SDP */ 114 __le32 res_number; 115 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 116 __le16 status; 117 #define ICE_AQ_RES_GLBL_SUCCESS 0 118 #define ICE_AQ_RES_GLBL_IN_PROG 1 119 #define ICE_AQ_RES_GLBL_DONE 2 120 u8 reserved[2]; 121 }; 122 123 /* Get function capabilities (indirect 0x000A) 124 * Get device capabilities (indirect 0x000B) 125 */ 126 struct ice_aqc_list_caps { 127 u8 cmd_flags; 128 u8 pf_index; 129 u8 reserved[2]; 130 __le32 count; 131 __le32 addr_high; 132 __le32 addr_low; 133 }; 134 135 /* Device/Function buffer entry, repeated per reported capability */ 136 struct ice_aqc_list_caps_elem { 137 __le16 cap; 138 #define ICE_AQC_CAPS_SWITCHING_MODE 0x0001 139 #define ICE_AQC_CAPS_MANAGEABILITY_MODE 0x0002 140 #define ICE_AQC_CAPS_OS2BMC 0x0004 141 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 142 #define ICE_AQC_MAX_VALID_FUNCTIONS 0x8 143 #define ICE_AQC_CAPS_ALTERNATE_RAM 0x0006 144 #define ICE_AQC_CAPS_WOL_PROXY 0x0008 145 #define ICE_AQC_CAPS_SRIOV 0x0012 146 #define ICE_AQC_CAPS_VF 0x0013 147 #define ICE_AQC_CAPS_802_1QBG 0x0015 148 #define ICE_AQC_CAPS_802_1BR 0x0016 149 #define ICE_AQC_CAPS_VSI 0x0017 150 #define ICE_AQC_CAPS_DCB 0x0018 151 #define ICE_AQC_CAPS_RSVD 0x0021 152 #define ICE_AQC_CAPS_ISCSI 0x0022 153 #define ICE_AQC_CAPS_RSS 0x0040 154 #define ICE_AQC_CAPS_RXQS 0x0041 155 #define ICE_AQC_CAPS_TXQS 0x0042 156 #define ICE_AQC_CAPS_MSIX 0x0043 157 #define ICE_AQC_CAPS_MAX_MTU 0x0047 158 #define ICE_AQC_CAPS_NVM_VER 0x0048 159 #define ICE_AQC_CAPS_OROM_VER 0x004A 160 #define ICE_AQC_CAPS_NET_VER 0x004C 161 #define ICE_AQC_CAPS_CEM 0x00F2 162 #define ICE_AQC_CAPS_IWARP 0x0051 163 #define ICE_AQC_CAPS_LED 0x0061 164 #define ICE_AQC_CAPS_SDP 0x0062 165 #define ICE_AQC_CAPS_WR_CSR_PROT 0x0064 166 #define ICE_AQC_CAPS_LOGI_TO_PHYSI_PORT_MAP 0x0073 167 #define ICE_AQC_CAPS_SKU 0x0074 168 #define ICE_AQC_CAPS_PORT_MAP 0x0075 169 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 170 #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077 171 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 172 173 u8 major_ver; 174 u8 minor_ver; 175 /* Number of resources described by this capability */ 176 __le32 number; 177 /* Only meaningful for some types of resources */ 178 __le32 logical_id; 179 /* Only meaningful for some types of resources */ 180 __le32 phys_id; 181 __le64 rsvd1; 182 __le64 rsvd2; 183 }; 184 185 /* Manage MAC address, read command - indirect (0x0107) 186 * This struct is also used for the response 187 */ 188 struct ice_aqc_manage_mac_read { 189 __le16 flags; /* Zeroed by device driver */ 190 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 191 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 192 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 193 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 194 #define ICE_AQC_MAN_MAC_MC_MAG_EN BIT(8) 195 #define ICE_AQC_MAN_MAC_WOL_PRESERVE_ON_PFR BIT(9) 196 #define ICE_AQC_MAN_MAC_READ_S 4 197 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 198 u8 rsvd[2]; 199 u8 num_addr; /* Used in response */ 200 u8 rsvd1[3]; 201 __le32 addr_high; 202 __le32 addr_low; 203 }; 204 205 /* Response buffer format for manage MAC read command */ 206 struct ice_aqc_manage_mac_read_resp { 207 u8 lport_num; 208 u8 addr_type; 209 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 210 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 211 u8 mac_addr[ETH_ALEN]; 212 }; 213 214 /* Manage MAC address, write command - direct (0x0108) */ 215 struct ice_aqc_manage_mac_write { 216 u8 rsvd; 217 u8 flags; 218 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 219 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 220 #define ICE_AQC_MAN_MAC_WR_S 6 221 #define ICE_AQC_MAN_MAC_WR_M MAKEMASK(3, ICE_AQC_MAN_MAC_WR_S) 222 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 223 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 224 /* byte stream in network order */ 225 u8 mac_addr[ETH_ALEN]; 226 __le32 addr_high; 227 __le32 addr_low; 228 }; 229 230 /* Clear PXE Command and response (direct 0x0110) */ 231 struct ice_aqc_clear_pxe { 232 u8 rx_cnt; 233 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 234 u8 reserved[15]; 235 }; 236 237 /* Configure No-Drop Policy Command (direct 0x0112) */ 238 struct ice_aqc_config_no_drop_policy { 239 u8 opts; 240 #define ICE_AQC_FORCE_NO_DROP BIT(0) 241 u8 rsvd[15]; 242 }; 243 244 /* Get switch configuration (0x0200) */ 245 struct ice_aqc_get_sw_cfg { 246 /* Reserved for command and copy of request flags for response */ 247 __le16 flags; 248 /* First desc in case of command and next_elem in case of response 249 * In case of response, if it is not zero, means all the configuration 250 * was not returned and new command shall be sent with this value in 251 * the 'first desc' field 252 */ 253 __le16 element; 254 /* Reserved for command, only used for response */ 255 __le16 num_elems; 256 __le16 rsvd; 257 __le32 addr_high; 258 __le32 addr_low; 259 }; 260 261 /* Each entry in the response buffer is of the following type: */ 262 struct ice_aqc_get_sw_cfg_resp_elem { 263 /* VSI/Port Number */ 264 __le16 vsi_port_num; 265 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 266 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 267 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 268 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 269 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 270 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 271 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 272 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 273 274 /* SWID VSI/Port belongs to */ 275 __le16 swid; 276 277 /* Bit 14..0 : PF/VF number VSI belongs to 278 * Bit 15 : VF indication bit 279 */ 280 __le16 pf_vf_num; 281 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 282 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 283 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 284 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 285 }; 286 287 /* Set Port parameters, (direct, 0x0203) */ 288 struct ice_aqc_set_port_params { 289 __le16 cmd_flags; 290 #define ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS BIT(0) 291 #define ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS BIT(1) 292 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2) 293 __le16 bad_frame_vsi; 294 #define ICE_AQC_SET_P_PARAMS_VSI_S 0 295 #define ICE_AQC_SET_P_PARAMS_VSI_M (0x3FF << ICE_AQC_SET_P_PARAMS_VSI_S) 296 #define ICE_AQC_SET_P_PARAMS_VSI_VALID BIT(15) 297 __le16 swid; 298 #define ICE_AQC_SET_P_PARAMS_SWID_S 0 299 #define ICE_AQC_SET_P_PARAMS_SWID_M (0xFF << ICE_AQC_SET_P_PARAMS_SWID_S) 300 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S 8 301 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_M \ 302 (0x3F << ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S) 303 #define ICE_AQC_SET_P_PARAMS_IS_LOGI_PORT BIT(14) 304 #define ICE_AQC_SET_P_PARAMS_SWID_VALID BIT(15) 305 u8 reserved[10]; 306 }; 307 308 /* These resource type defines are used for all switch resource 309 * commands where a resource type is required, such as: 310 * Get Resource Allocation command (indirect 0x0204) 311 * Allocate Resources command (indirect 0x0208) 312 * Free Resources command (indirect 0x0209) 313 * Get Allocated Resource Descriptors Command (indirect 0x020A) 314 */ 315 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00 316 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01 317 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02 318 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 319 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 320 #define ICE_AQC_RES_TYPE_RECIPE 0x05 321 #define ICE_AQC_RES_TYPE_PROFILE 0x06 322 #define ICE_AQC_RES_TYPE_SWID 0x07 323 #define ICE_AQC_RES_TYPE_VSI 0x08 324 #define ICE_AQC_RES_TYPE_FLU 0x09 325 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A 326 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B 327 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C 328 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20 329 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 330 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 331 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 332 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30 333 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48 334 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49 335 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50 336 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51 337 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 338 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 339 /* Resource types 0x62-67 are reserved for Hash profile builder */ 340 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68 341 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69 342 343 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7) 344 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 345 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 346 347 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 348 349 #define ICE_AQC_RES_TYPE_S 0 350 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 351 352 /* Get Resource Allocation command (indirect 0x0204) */ 353 struct ice_aqc_get_res_alloc { 354 __le16 resp_elem_num; /* Used in response, reserved in command */ 355 u8 reserved[6]; 356 __le32 addr_high; 357 __le32 addr_low; 358 }; 359 360 /* Get Resource Allocation Response Buffer per response */ 361 struct ice_aqc_get_res_resp_elem { 362 __le16 res_type; /* Types defined above cmd 0x0204 */ 363 __le16 total_capacity; /* Resources available to all PF's */ 364 __le16 total_function; /* Resources allocated for a PF */ 365 __le16 total_shared; /* Resources allocated as shared */ 366 __le16 total_free; /* Resources un-allocated/not reserved by any PF */ 367 }; 368 369 /* Allocate Resources command (indirect 0x0208) 370 * Free Resources command (indirect 0x0209) 371 */ 372 struct ice_aqc_alloc_free_res_cmd { 373 __le16 num_entries; /* Number of Resource entries */ 374 u8 reserved[6]; 375 __le32 addr_high; 376 __le32 addr_low; 377 }; 378 379 /* Resource descriptor */ 380 struct ice_aqc_res_elem { 381 union { 382 __le16 sw_resp; 383 __le16 flu_resp; 384 } e; 385 }; 386 387 /* Buffer for Allocate/Free Resources commands */ 388 struct ice_aqc_alloc_free_res_elem { 389 __le16 res_type; /* Types defined above cmd 0x0204 */ 390 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 391 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 392 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 393 __le16 num_elems; 394 struct ice_aqc_res_elem elem[STRUCT_HACK_VAR_LEN]; 395 }; 396 397 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */ 398 struct ice_aqc_get_allocd_res_desc { 399 union { 400 struct { 401 __le16 res; /* Types defined above cmd 0x0204 */ 402 __le16 first_desc; 403 __le32 reserved; 404 } cmd; 405 struct { 406 __le16 res; 407 __le16 next_desc; 408 __le16 num_desc; 409 __le16 reserved; 410 } resp; 411 } ops; 412 __le32 addr_high; 413 __le32 addr_low; 414 }; 415 416 /* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */ 417 struct ice_aqc_set_vlan_mode { 418 u8 reserved; 419 u8 l2tag_prio_tagging; 420 #define ICE_AQ_VLAN_PRIO_TAG_S 0 421 #define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S) 422 #define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0 423 #define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1 424 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2 425 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3 426 #define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4 427 #define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4 428 #define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7 429 u8 l2tag_reserved[64]; 430 u8 rdma_packet; 431 #define ICE_AQ_VLAN_RDMA_TAG_S 0 432 #define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S) 433 #define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10 434 #define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A 435 u8 rdma_reserved[2]; 436 u8 mng_vlan_prot_id; 437 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10 438 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11 439 u8 prot_id_reserved[30]; 440 }; 441 442 /* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */ 443 struct ice_aqc_get_vlan_mode { 444 u8 vlan_mode; 445 #define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0) 446 u8 l2tag_prio_tagging; 447 u8 reserved[98]; 448 }; 449 450 /* Add VSI (indirect 0x0210) 451 * Update VSI (indirect 0x0211) 452 * Get VSI (indirect 0x0212) 453 * Free VSI (indirect 0x0213) 454 */ 455 struct ice_aqc_add_get_update_free_vsi { 456 __le16 vsi_num; 457 #define ICE_AQ_VSI_NUM_S 0 458 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 459 #define ICE_AQ_VSI_IS_VALID BIT(15) 460 __le16 cmd_flags; 461 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 462 u8 vf_id; 463 u8 reserved; 464 __le16 vsi_flags; 465 #define ICE_AQ_VSI_TYPE_S 0 466 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 467 #define ICE_AQ_VSI_TYPE_VF 0x0 468 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 469 #define ICE_AQ_VSI_TYPE_PF 0x2 470 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 471 __le32 addr_high; 472 __le32 addr_low; 473 }; 474 475 /* Response descriptor for: 476 * Add VSI (indirect 0x0210) 477 * Update VSI (indirect 0x0211) 478 * Free VSI (indirect 0x0213) 479 */ 480 struct ice_aqc_add_update_free_vsi_resp { 481 __le16 vsi_num; 482 __le16 ext_status; 483 __le16 vsi_used; 484 __le16 vsi_free; 485 __le32 addr_high; 486 __le32 addr_low; 487 }; 488 489 struct ice_aqc_get_vsi_resp { 490 __le16 vsi_num; 491 u8 vf_id; 492 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values. 493 * These are found above in struct ice_aqc_add_get_update_free_vsi. 494 */ 495 u8 vsi_flags; 496 __le16 vsi_used; 497 __le16 vsi_free; 498 __le32 addr_high; 499 __le32 addr_low; 500 }; 501 502 struct ice_aqc_vsi_props { 503 __le16 valid_sections; 504 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 505 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 506 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 507 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 508 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 509 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 510 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 511 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 512 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 513 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 514 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 515 /* switch section */ 516 u8 sw_id; 517 u8 sw_flags; 518 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 519 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 520 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 521 u8 sw_flags2; 522 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 523 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 524 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 525 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 526 u8 veb_stat_id; 527 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 528 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 529 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 530 /* security section */ 531 u8 sec_flags; 532 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 533 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 534 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 535 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 536 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 537 u8 sec_reserved; 538 /* VLAN section */ 539 __le16 port_based_inner_vlan; /* VLANS include priority bits */ 540 u8 inner_vlan_reserved[2]; 541 u8 inner_vlan_flags; 542 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0 543 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S) 544 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 545 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 546 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3 547 #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2) 548 #define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3 549 #define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 550 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH (0x0 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 551 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP (0x1 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 552 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR (0x2 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 553 #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 554 #define ICE_AQ_VSI_INNER_VLAN_BLOCK_TX_DESC BIT(5) 555 u8 inner_vlan_reserved2[3]; 556 /* ingress egress up sections */ 557 __le32 ingress_table; /* bitmap, 3 bits per up */ 558 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 559 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 560 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 561 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 562 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 563 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 564 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 565 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 566 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 567 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 568 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 569 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 570 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 571 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 572 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 573 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 574 __le32 egress_table; /* same defines as for ingress table */ 575 /* outer tags section */ 576 __le16 port_based_outer_vlan; 577 u8 outer_vlan_flags; 578 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0 579 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S) 580 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0 581 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1 582 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2 583 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3 584 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 585 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 586 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 587 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 588 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 589 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 590 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4) 591 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5 592 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) 593 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 594 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 595 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3 596 #define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7) 597 u8 outer_vlan_reserved; 598 /* queue mapping section */ 599 __le16 mapping_flags; 600 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 601 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 602 __le16 q_mapping[16]; 603 #define ICE_AQ_VSI_Q_S 0 604 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 605 __le16 tc_mapping[8]; 606 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 607 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 608 #define ICE_AQ_VSI_TC_Q_NUM_S 11 609 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 610 /* queueing option section */ 611 u8 q_opt_rss; 612 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 613 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 614 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 615 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 616 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 617 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 618 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 619 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 620 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 621 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 622 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 623 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 624 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 625 u8 q_opt_tc; 626 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 627 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 628 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 629 u8 q_opt_flags; 630 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 631 u8 q_opt_reserved[3]; 632 /* outer up section */ 633 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 634 /* section 10 */ 635 __le16 sect_10_reserved; 636 /* flow director section */ 637 __le16 fd_options; 638 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 639 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 640 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 641 __le16 max_fd_fltr_dedicated; 642 __le16 max_fd_fltr_shared; 643 __le16 fd_def_q; 644 #define ICE_AQ_VSI_FD_DEF_Q_S 0 645 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 646 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 647 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 648 __le16 fd_report_opt; 649 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 650 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 651 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 652 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 653 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 654 /* PASID section */ 655 __le32 pasid_id; 656 #define ICE_AQ_VSI_PASID_ID_S 0 657 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 658 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 659 u8 reserved[24]; 660 }; 661 662 /* Add/update mirror rule - direct (0x0260) */ 663 #define ICE_AQC_RULE_ID_VALID_S 7 664 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S) 665 #define ICE_AQC_RULE_ID_S 0 666 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S) 667 668 /* Following defines to be used while processing caller specified mirror list 669 * of VSI indexes. 670 */ 671 /* Action: Byte.bit (1.7) 672 * 0 = Remove VSI from mirror rule 673 * 1 = Add VSI to mirror rule 674 */ 675 #define ICE_AQC_RULE_ACT_S 15 676 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S) 677 /* Action: 1.2:0.0 = Mirrored VSI */ 678 #define ICE_AQC_RULE_MIRRORED_VSI_S 0 679 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S) 680 681 /* This is to be used by add/update mirror rule Admin Queue command. 682 * In case of add mirror rule - if rule ID is specified as 683 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool. 684 * If specified rule_id is valid, then it is used. If specified rule_id 685 * is in use then new mirroring rule is added. 686 */ 687 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF 688 689 struct ice_aqc_add_update_mir_rule { 690 __le16 rule_id; 691 692 __le16 rule_type; 693 #define ICE_AQC_RULE_TYPE_S 0 694 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S) 695 /* VPORT ingress/egress */ 696 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1 697 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2 698 /* Physical port ingress mirroring. 699 * All traffic received by this port 700 */ 701 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6 702 /* Physical port egress mirroring. All traffic sent by this port */ 703 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7 704 705 /* Number of mirrored entries. 706 * The values are in the command buffer 707 */ 708 __le16 num_entries; 709 710 /* Destination VSI */ 711 __le16 dest; 712 __le32 addr_high; 713 __le32 addr_low; 714 }; 715 716 /* Delete mirror rule - direct(0x0261) */ 717 struct ice_aqc_delete_mir_rule { 718 __le16 rule_id; 719 __le16 rsvd; 720 721 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of 722 * the PF allocated resources, otherwise it is returned to the 723 * shared pool 724 */ 725 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0 726 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S) 727 __le16 flags; 728 729 u8 reserved[10]; 730 }; 731 732 /* Set/Get storm config - (direct 0x0280, 0x0281) */ 733 /* This structure holds get storm configuration response and same structure 734 * is used to perform set_storm_cfg 735 */ 736 struct ice_aqc_storm_cfg { 737 __le32 bcast_thresh_size; 738 __le32 mcast_thresh_size; 739 /* Bit 18:0 - Traffic upper threshold size 740 * Bit 31:19 - Reserved 741 */ 742 #define ICE_AQ_THRESHOLD_S 0 743 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S) 744 745 __le32 storm_ctrl_ctrl; 746 /* Bit 0: MDIPW - Drop Multicast packets in previous window 747 * Bit 1: MDICW - Drop multicast packets in current window 748 * Bit 2: BDIPW - Drop broadcast packets in previous window 749 * Bit 3: BDICW - Drop broadcast packets in current window 750 */ 751 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0) 752 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1) 753 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2) 754 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3) 755 /* Bit 7:5 : Reserved */ 756 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The 757 * interval size for applying ingress broadcast or multicast storm 758 * control. 759 */ 760 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8 761 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \ 762 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S) 763 __le32 reserved; 764 }; 765 766 #define ICE_MAX_NUM_RECIPES 64 767 768 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 769 */ 770 struct ice_aqc_sw_rules { 771 /* ops: add switch rules, referring the number of rules. 772 * ops: update switch rules, referring the number of filters 773 * ops: remove switch rules, referring the entry index. 774 * ops: get switch rules, referring to the number of filters. 775 */ 776 __le16 num_rules_fltr_entry_index; 777 u8 reserved[6]; 778 __le32 addr_high; 779 __le32 addr_low; 780 }; 781 782 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 783 * This structures describes the lookup rules and associated actions. "index" 784 * is returned as part of a response to a successful Add command, and can be 785 * used to identify the rule for Update/Get/Remove commands. 786 */ 787 struct ice_sw_rule_lkup_rx_tx { 788 __le16 recipe_id; 789 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 790 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 791 __le16 src; 792 __le32 act; 793 794 /* Bit 0:1 - Action type */ 795 #define ICE_SINGLE_ACT_TYPE_S 0x00 796 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 797 798 /* Bit 2 - Loop back enable 799 * Bit 3 - LAN enable 800 */ 801 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 802 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 803 804 /* Action type = 0 - Forward to VSI or VSI list */ 805 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 806 807 #define ICE_SINGLE_ACT_VSI_ID_S 4 808 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 809 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 810 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 811 /* This bit needs to be set if action is forward to VSI list */ 812 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 813 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 814 #define ICE_SINGLE_ACT_DROP BIT(18) 815 816 /* Action type = 1 - Forward to Queue of Queue group */ 817 #define ICE_SINGLE_ACT_TO_Q 0x1 818 #define ICE_SINGLE_ACT_Q_INDEX_S 4 819 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 820 #define ICE_SINGLE_ACT_Q_REGION_S 15 821 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 822 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 823 824 /* Action type = 2 - Prune */ 825 #define ICE_SINGLE_ACT_PRUNE 0x2 826 #define ICE_SINGLE_ACT_EGRESS BIT(15) 827 #define ICE_SINGLE_ACT_INGRESS BIT(16) 828 #define ICE_SINGLE_ACT_PRUNET BIT(17) 829 /* Bit 18 should be set to 0 for this action */ 830 831 /* Action type = 2 - Pointer */ 832 #define ICE_SINGLE_ACT_PTR 0x2 833 #define ICE_SINGLE_ACT_PTR_VAL_S 4 834 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 835 /* Bit 18 should be set to 1 */ 836 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 837 838 /* Action type = 3 - Other actions. Last two bits 839 * are other action identifier 840 */ 841 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 842 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 843 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 844 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 845 846 /* Bit 17:18 - Defines other actions */ 847 /* Other action = 0 - Mirror VSI */ 848 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 849 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 850 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 851 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 852 853 /* Other action = 3 - Set Stat count */ 854 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 855 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 856 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 857 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 858 859 __le16 index; /* The index of the rule in the lookup table */ 860 /* Length and values of the header to be matched per recipe or 861 * lookup-type 862 */ 863 __le16 hdr_len; 864 u8 hdr[STRUCT_HACK_VAR_LEN]; 865 }; 866 867 /* Add/Update/Remove large action command/response entry 868 * "index" is returned as part of a response to a successful Add command, and 869 * can be used to identify the action for Update/Get/Remove commands. 870 */ 871 struct ice_sw_rule_lg_act { 872 __le16 index; /* Index in large action table */ 873 __le16 size; 874 /* Max number of large actions */ 875 #define ICE_MAX_LG_ACT 4 876 /* Bit 0:1 - Action type */ 877 #define ICE_LG_ACT_TYPE_S 0 878 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 879 880 /* Action type = 0 - Forward to VSI or VSI list */ 881 #define ICE_LG_ACT_VSI_FORWARDING 0 882 #define ICE_LG_ACT_VSI_ID_S 3 883 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 884 #define ICE_LG_ACT_VSI_LIST_ID_S 3 885 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 886 /* This bit needs to be set if action is forward to VSI list */ 887 #define ICE_LG_ACT_VSI_LIST BIT(13) 888 889 #define ICE_LG_ACT_VALID_BIT BIT(16) 890 891 /* Action type = 1 - Forward to Queue of Queue group */ 892 #define ICE_LG_ACT_TO_Q 0x1 893 #define ICE_LG_ACT_Q_INDEX_S 3 894 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 895 #define ICE_LG_ACT_Q_REGION_S 14 896 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 897 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 898 899 /* Action type = 2 - Prune */ 900 #define ICE_LG_ACT_PRUNE 0x2 901 #define ICE_LG_ACT_EGRESS BIT(14) 902 #define ICE_LG_ACT_INGRESS BIT(15) 903 #define ICE_LG_ACT_PRUNET BIT(16) 904 905 /* Action type = 3 - Mirror VSI */ 906 #define ICE_LG_OTHER_ACT_MIRROR 0x3 907 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 908 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 909 910 /* Action type = 5 - Generic Value */ 911 #define ICE_LG_ACT_GENERIC 0x5 912 #define ICE_LG_ACT_GENERIC_VALUE_S 3 913 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 914 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 915 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 916 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 917 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 918 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 919 920 /* Action = 7 - Set Stat count */ 921 #define ICE_LG_ACT_STAT_COUNT 0x7 922 #define ICE_LG_ACT_STAT_COUNT_S 3 923 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 924 __le32 act[STRUCT_HACK_VAR_LEN]; /* array of size for actions */ 925 }; 926 927 /* Add/Update/Remove VSI list command/response entry 928 * "index" is returned as part of a response to a successful Add command, and 929 * can be used to identify the VSI list for Update/Get/Remove commands. 930 */ 931 struct ice_sw_rule_vsi_list { 932 __le16 index; /* Index of VSI/Prune list */ 933 __le16 number_vsi; 934 __le16 vsi[STRUCT_HACK_VAR_LEN]; /* Array of number_vsi VSI numbers */ 935 }; 936 937 #pragma pack(1) 938 /* Query VSI list command/response entry */ 939 struct ice_sw_rule_vsi_list_query { 940 __le16 index; 941 ice_declare_bitmap(vsi_list, ICE_MAX_VSI); 942 }; 943 #pragma pack() 944 945 #pragma pack(1) 946 /* Add switch rule response: 947 * Content of return buffer is same as the input buffer. The status field and 948 * LUT index are updated as part of the response 949 */ 950 struct ice_aqc_sw_rules_elem { 951 __le16 type; /* Switch rule type, one of T_... */ 952 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 953 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 954 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 955 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 956 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 957 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 958 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 959 __le16 status; 960 union { 961 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 962 struct ice_sw_rule_lg_act lg_act; 963 struct ice_sw_rule_vsi_list vsi_list; 964 struct ice_sw_rule_vsi_list_query vsi_list_query; 965 } pdata; 966 }; 967 968 #pragma pack() 969 970 /* PFC Ignore (direct 0x0301) 971 * The command and response use the same descriptor structure 972 */ 973 struct ice_aqc_pfc_ignore { 974 u8 tc_bitmap; 975 u8 cmd_flags; /* unused in response */ 976 #define ICE_AQC_PFC_IGNORE_SET BIT(7) 977 #define ICE_AQC_PFC_IGNORE_CLEAR 0 978 u8 reserved[14]; 979 }; 980 981 /* Set PFC Mode (direct 0x0303) 982 * Query PFC Mode (direct 0x0302) 983 */ 984 struct ice_aqc_set_query_pfc_mode { 985 u8 pfc_mode; 986 /* For Set Command response, reserved in all other cases */ 987 #define ICE_AQC_PFC_NOT_CONFIGURED 0 988 /* For Query Command response, reserved in all other cases */ 989 #define ICE_AQC_DCB_DIS 0 990 #define ICE_AQC_PFC_VLAN_BASED_PFC 1 991 #define ICE_AQC_PFC_DSCP_BASED_PFC 2 992 u8 rsvd[15]; 993 }; 994 995 /* Set DCB Parameters (direct 0x0306) */ 996 struct ice_aqc_set_dcb_params { 997 u8 cmd_flags; /* unused in response */ 998 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0) 999 #define ICE_AQC_PERSIST_DCB_CFG BIT(1) 1000 u8 valid_flags; /* unused in response */ 1001 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0) 1002 #define ICE_AQC_PERSIST_DCB_CFG_VALID BIT(1) 1003 u8 rsvd[14]; 1004 }; 1005 1006 /* Get Default Topology (indirect 0x0400) */ 1007 struct ice_aqc_get_topo { 1008 u8 port_num; 1009 u8 num_branches; 1010 __le16 reserved1; 1011 __le32 reserved2; 1012 __le32 addr_high; 1013 __le32 addr_low; 1014 }; 1015 1016 /* Update TSE (indirect 0x0403) 1017 * Get TSE (indirect 0x0404) 1018 * Add TSE (indirect 0x0401) 1019 * Delete TSE (indirect 0x040F) 1020 * Move TSE (indirect 0x0408) 1021 * Suspend Nodes (indirect 0x0409) 1022 * Resume Nodes (indirect 0x040A) 1023 */ 1024 struct ice_aqc_sched_elem_cmd { 1025 __le16 num_elem_req; /* Used by commands */ 1026 __le16 num_elem_resp; /* Used by responses */ 1027 __le32 reserved; 1028 __le32 addr_high; 1029 __le32 addr_low; 1030 }; 1031 1032 struct ice_aqc_txsched_move_grp_info_hdr { 1033 __le32 src_parent_teid; 1034 __le32 dest_parent_teid; 1035 __le16 num_elems; 1036 u8 flags; 1037 u8 reserved; 1038 }; 1039 1040 struct ice_aqc_move_elem { 1041 struct ice_aqc_txsched_move_grp_info_hdr hdr; 1042 __le32 teid[STRUCT_HACK_VAR_LEN]; 1043 }; 1044 1045 struct ice_aqc_elem_info_bw { 1046 __le16 bw_profile_idx; 1047 __le16 bw_alloc; 1048 }; 1049 1050 struct ice_aqc_txsched_elem { 1051 u8 elem_type; /* Special field, reserved for some aq calls */ 1052 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 1053 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 1054 #define ICE_AQC_ELEM_TYPE_TC 0x2 1055 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 1056 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 1057 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 1058 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 1059 u8 valid_sections; 1060 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 1061 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 1062 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 1063 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 1064 u8 generic; 1065 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 1066 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 1067 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 1068 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 1069 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 1070 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 1071 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 1072 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 1073 u8 flags; /* Special field, reserved for some aq calls */ 1074 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 1075 struct ice_aqc_elem_info_bw cir_bw; 1076 struct ice_aqc_elem_info_bw eir_bw; 1077 __le16 srl_id; 1078 __le16 reserved2; 1079 }; 1080 1081 struct ice_aqc_txsched_elem_data { 1082 __le32 parent_teid; 1083 __le32 node_teid; 1084 struct ice_aqc_txsched_elem data; 1085 }; 1086 1087 struct ice_aqc_txsched_topo_grp_info_hdr { 1088 __le32 parent_teid; 1089 __le16 num_elems; 1090 __le16 reserved2; 1091 }; 1092 1093 struct ice_aqc_add_elem { 1094 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1095 struct ice_aqc_txsched_elem_data generic[STRUCT_HACK_VAR_LEN]; 1096 }; 1097 1098 struct ice_aqc_get_topo_elem { 1099 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1100 struct ice_aqc_txsched_elem_data 1101 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1102 }; 1103 1104 struct ice_aqc_delete_elem { 1105 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1106 __le32 teid[STRUCT_HACK_VAR_LEN]; 1107 }; 1108 1109 /* Query Port ETS (indirect 0x040E) 1110 * 1111 * This indirect command is used to query port TC node configuration. 1112 */ 1113 struct ice_aqc_query_port_ets { 1114 __le32 port_teid; 1115 __le32 reserved; 1116 __le32 addr_high; 1117 __le32 addr_low; 1118 }; 1119 1120 struct ice_aqc_port_ets_elem { 1121 u8 tc_valid_bits; 1122 u8 reserved[3]; 1123 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 1124 __le32 up2tc; 1125 u8 tc_bw_share[8]; 1126 __le32 port_eir_prof_id; 1127 __le32 port_cir_prof_id; 1128 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 1129 __le32 tc_node_prio; 1130 #define ICE_TC_NODE_PRIO_S 0x4 1131 u8 reserved1[4]; 1132 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 1133 }; 1134 1135 /* Rate limiting profile for 1136 * Add RL profile (indirect 0x0410) 1137 * Query RL profile (indirect 0x0411) 1138 * Remove RL profile (indirect 0x0415) 1139 * These indirect commands acts on single or multiple 1140 * RL profiles with specified data. 1141 */ 1142 struct ice_aqc_rl_profile { 1143 __le16 num_profiles; 1144 __le16 num_processed; /* Only for response. Reserved in Command. */ 1145 u8 reserved[4]; 1146 __le32 addr_high; 1147 __le32 addr_low; 1148 }; 1149 1150 struct ice_aqc_rl_profile_elem { 1151 u8 level; 1152 u8 flags; 1153 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 1154 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 1155 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 1156 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 1157 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 1158 /* The following flag is used for Query RL Profile Data */ 1159 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 1160 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 1161 1162 __le16 profile_id; 1163 __le16 max_burst_size; 1164 __le16 rl_multiply; 1165 __le16 wake_up_calc; 1166 __le16 rl_encode; 1167 }; 1168 1169 /* Configure L2 Node CGD (indirect 0x0414) 1170 * This indirect command allows configuring a congestion domain for given L2 1171 * node TEIDs in the scheduler topology. 1172 */ 1173 struct ice_aqc_cfg_l2_node_cgd { 1174 __le16 num_l2_nodes; 1175 u8 reserved[6]; 1176 __le32 addr_high; 1177 __le32 addr_low; 1178 }; 1179 1180 struct ice_aqc_cfg_l2_node_cgd_elem { 1181 __le32 node_teid; 1182 u8 cgd; 1183 u8 reserved[3]; 1184 }; 1185 1186 /* Query Scheduler Resource Allocation (indirect 0x0412) 1187 * This indirect command retrieves the scheduler resources allocated by 1188 * EMP Firmware to the given PF. 1189 */ 1190 struct ice_aqc_query_txsched_res { 1191 u8 reserved[8]; 1192 __le32 addr_high; 1193 __le32 addr_low; 1194 }; 1195 1196 struct ice_aqc_generic_sched_props { 1197 __le16 phys_levels; 1198 __le16 logical_levels; 1199 u8 flattening_bitmap; 1200 u8 max_device_cgds; 1201 u8 max_pf_cgds; 1202 u8 rsvd0; 1203 __le16 rdma_qsets; 1204 u8 rsvd1[22]; 1205 }; 1206 1207 struct ice_aqc_layer_props { 1208 u8 logical_layer; 1209 u8 chunk_size; 1210 __le16 max_device_nodes; 1211 __le16 max_pf_nodes; 1212 u8 rsvd0[4]; 1213 __le16 max_sibl_grp_sz; 1214 __le16 max_cir_rl_profiles; 1215 __le16 max_eir_rl_profiles; 1216 __le16 max_srl_profiles; 1217 u8 rsvd1[14]; 1218 }; 1219 1220 struct ice_aqc_query_txsched_res_resp { 1221 struct ice_aqc_generic_sched_props sched_props; 1222 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1223 }; 1224 1225 /* Query Node to Root Topology (indirect 0x0413) 1226 * This command uses ice_aqc_get_elem as its data buffer. 1227 */ 1228 struct ice_aqc_query_node_to_root { 1229 __le32 teid; 1230 __le32 num_nodes; /* Response only */ 1231 __le32 addr_high; 1232 __le32 addr_low; 1233 }; 1234 1235 /* Get PHY capabilities (indirect 0x0600) */ 1236 struct ice_aqc_get_phy_caps { 1237 u8 lport_num; 1238 u8 reserved; 1239 __le16 param0; 1240 /* 18.0 - Report qualified modules */ 1241 #define ICE_AQC_GET_PHY_RQM BIT(0) 1242 /* 18.1 - 18.3 : Report mode 1243 * 000b - Report NVM capabilities 1244 * 001b - Report topology capabilities 1245 * 010b - Report SW configured 1246 * 100b - Report default capabilities 1247 */ 1248 #define ICE_AQC_REPORT_MODE_S 1 1249 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S) 1250 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0 1251 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1) 1252 #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2) 1253 #define ICE_AQC_REPORT_DFLT_CFG BIT(3) 1254 __le32 reserved1; 1255 __le32 addr_high; 1256 __le32 addr_low; 1257 }; 1258 1259 /* This is #define of PHY type (Extended): 1260 * The first set of defines is for phy_type_low. 1261 */ 1262 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 1263 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 1264 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 1265 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 1266 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 1267 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 1268 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 1269 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 1270 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 1271 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 1272 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 1273 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 1274 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 1275 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 1276 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 1277 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 1278 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 1279 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 1280 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 1281 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 1282 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 1283 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 1284 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 1285 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 1286 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 1287 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 1288 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 1289 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 1290 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 1291 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 1292 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 1293 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 1294 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 1295 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 1296 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 1297 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 1298 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 1299 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 1300 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 1301 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 1302 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 1303 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 1304 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 1305 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 1306 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 1307 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 1308 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 1309 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 1310 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 1311 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 1312 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 1313 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 1314 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 1315 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 1316 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 1317 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 1318 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 1319 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 1320 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 1321 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 1322 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 1323 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 1324 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 1325 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 1326 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 1327 /* The second set of defines is for phy_type_high. */ 1328 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 1329 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 1330 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 1331 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 1332 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 1333 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 5 1334 1335 struct ice_aqc_get_phy_caps_data { 1336 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1337 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1338 u8 caps; 1339 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 1340 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 1341 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 1342 #define ICE_AQC_PHY_EN_LINK BIT(3) 1343 #define ICE_AQC_PHY_AN_MODE BIT(4) 1344 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5) 1345 #define ICE_AQC_PHY_EN_LESM BIT(6) 1346 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 1347 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0) 1348 u8 low_power_ctrl_an; 1349 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 1350 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1) 1351 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2) 1352 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3) 1353 __le16 eee_cap; 1354 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1355 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1356 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1357 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1358 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1359 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1360 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1361 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7) 1362 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8) 1363 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9) 1364 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10) 1365 __le16 eeer_value; 1366 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1367 u8 phy_fw_ver[8]; 1368 u8 link_fec_options; 1369 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1370 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1371 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1372 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1373 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1374 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1375 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1376 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0) 1377 u8 module_compliance_enforcement; 1378 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 1379 u8 extended_compliance_code; 1380 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1381 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1382 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1383 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1384 #define ICE_AQC_MOD_TYPE_IDENT 1 1385 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1386 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1387 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1388 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1389 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1390 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1391 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1392 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1393 u8 qualified_module_count; 1394 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1395 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1396 struct { 1397 u8 v_oui[3]; 1398 u8 rsvd3; 1399 u8 v_part[16]; 1400 __le32 v_rev; 1401 __le64 rsvd4; 1402 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1403 }; 1404 1405 /* Set PHY capabilities (direct 0x0601) 1406 * NOTE: This command must be followed by setup link and restart auto-neg 1407 */ 1408 struct ice_aqc_set_phy_cfg { 1409 u8 lport_num; 1410 u8 reserved[7]; 1411 __le32 addr_high; 1412 __le32 addr_low; 1413 }; 1414 1415 /* Set PHY config command data structure */ 1416 struct ice_aqc_set_phy_cfg_data { 1417 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1418 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1419 u8 caps; 1420 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0) 1421 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1422 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1423 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1424 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1425 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1426 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1427 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1428 u8 low_power_ctrl_an; 1429 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1430 __le16 eeer_value; 1431 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1432 u8 module_compliance_enforcement; 1433 }; 1434 1435 /* Set MAC Config command data structure (direct 0x0603) */ 1436 struct ice_aqc_set_mac_cfg { 1437 __le16 max_frame_size; 1438 u8 params; 1439 #define ICE_AQ_SET_MAC_PACE_S 3 1440 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1441 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1442 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1443 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1444 u8 tx_tmr_priority; 1445 __le16 tx_tmr_value; 1446 __le16 fc_refresh_threshold; 1447 u8 drop_opts; 1448 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1449 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1450 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1451 u8 reserved[7]; 1452 }; 1453 1454 /* Restart AN command data structure (direct 0x0605) 1455 * Also used for response, with only the lport_num field present. 1456 */ 1457 struct ice_aqc_restart_an { 1458 u8 lport_num; 1459 u8 reserved; 1460 u8 cmd_flags; 1461 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1462 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1463 u8 reserved2[13]; 1464 }; 1465 1466 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1467 struct ice_aqc_get_link_status { 1468 u8 lport_num; 1469 u8 reserved; 1470 __le16 cmd_flags; 1471 #define ICE_AQ_LSE_M 0x3 1472 #define ICE_AQ_LSE_NOP 0x0 1473 #define ICE_AQ_LSE_DIS 0x2 1474 #define ICE_AQ_LSE_ENA 0x3 1475 /* only response uses this flag */ 1476 #define ICE_AQ_LSE_IS_ENABLED 0x1 1477 __le32 reserved2; 1478 __le32 addr_high; 1479 __le32 addr_low; 1480 }; 1481 1482 /* Get link status response data structure, also used for Link Status Event */ 1483 struct ice_aqc_get_link_status_data { 1484 u8 topo_media_conflict; 1485 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1486 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1487 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1488 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1489 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1490 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1491 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1492 u8 link_cfg_err; 1493 #define ICE_AQ_LINK_CFG_ERR BIT(0) 1494 #define ICE_AQ_LINK_ACT_PORT_OPT_INVAL BIT(2) 1495 #define ICE_AQ_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3) 1496 #define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR BIT(4) 1497 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5) 1498 #define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6) 1499 #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7) 1500 u8 link_info; 1501 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1502 #define ICE_AQ_LINK_FAULT BIT(1) 1503 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1504 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1505 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1506 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1507 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1508 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1509 u8 an_info; 1510 #define ICE_AQ_AN_COMPLETED BIT(0) 1511 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1512 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1513 #define ICE_AQ_FEC_EN BIT(3) 1514 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1515 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1516 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1517 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1518 u8 ext_info; 1519 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1520 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1521 /* Port Tx Suspended */ 1522 #define ICE_AQ_LINK_TX_S 2 1523 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1524 #define ICE_AQ_LINK_TX_ACTIVE 0 1525 #define ICE_AQ_LINK_TX_DRAINED 1 1526 #define ICE_AQ_LINK_TX_FLUSHED 3 1527 u8 lb_status; 1528 #define ICE_AQ_LINK_LB_PHY_LCL BIT(0) 1529 #define ICE_AQ_LINK_LB_PHY_RMT BIT(1) 1530 #define ICE_AQ_LINK_LB_MAC_LCL BIT(2) 1531 #define ICE_AQ_LINK_LB_PHY_IDX_S 3 1532 #define ICE_AQ_LINK_LB_PHY_IDX_M (0x7 << ICE_AQ_LB_PHY_IDX_S) 1533 __le16 max_frame_size; 1534 u8 cfg; 1535 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1536 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1537 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1538 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0) 1539 /* Pacing Config */ 1540 #define ICE_AQ_CFG_PACING_S 3 1541 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1542 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1543 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1544 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1545 /* External Device Power Ability */ 1546 u8 power_desc; 1547 #define ICE_AQ_PWR_CLASS_M 0x3F 1548 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1549 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1550 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1551 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1552 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1553 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1554 __le16 link_speed; 1555 #define ICE_AQ_LINK_SPEED_M 0x7FF 1556 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1557 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1558 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1559 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1560 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1561 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1562 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1563 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1564 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1565 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1566 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1567 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1568 __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1569 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1570 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1571 }; 1572 1573 /* Set event mask command (direct 0x0613) */ 1574 struct ice_aqc_set_event_mask { 1575 u8 lport_num; 1576 u8 reserved[7]; 1577 __le16 event_mask; 1578 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1579 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1580 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1581 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1582 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1583 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1584 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1585 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1586 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1587 #define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10) 1588 #define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11) 1589 u8 reserved1[6]; 1590 }; 1591 1592 /* Set PHY Loopback command (direct 0x0619) */ 1593 struct ice_aqc_set_phy_lb { 1594 u8 lport_num; 1595 u8 lport_num_valid; 1596 #define ICE_AQ_PHY_LB_PORT_NUM_VALID BIT(0) 1597 u8 phy_index; 1598 u8 lb_mode; 1599 #define ICE_AQ_PHY_LB_EN BIT(0) 1600 #define ICE_AQ_PHY_LB_TYPE_M BIT(1) 1601 #define ICE_AQ_PHY_LB_TYPE_LOCAL 0 1602 #define ICE_AQ_PHY_LB_TYPE_REMOTE ICE_AQ_PHY_LB_TYPE_M 1603 #define ICE_AQ_PHY_LB_LEVEL_M BIT(2) 1604 #define ICE_AQ_PHY_LB_LEVEL_PMD 0 1605 #define ICE_AQ_PHY_LB_LEVEL_PCS ICE_AQ_PHY_LB_LEVEL_M 1606 u8 reserved2[12]; 1607 }; 1608 1609 /* Set MAC Loopback command (direct 0x0620) */ 1610 struct ice_aqc_set_mac_lb { 1611 u8 lb_mode; 1612 #define ICE_AQ_MAC_LB_EN BIT(0) 1613 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1614 u8 reserved[15]; 1615 }; 1616 1617 /* DNL Get Status command (indirect 0x0680) 1618 * Structure used for the response, the command uses the generic 1619 * ice_aqc_generic struct to pass a buffer address to the FW. 1620 */ 1621 struct ice_aqc_dnl_get_status { 1622 u8 ctx; 1623 u8 status; 1624 #define ICE_AQ_DNL_STATUS_IDLE 0x0 1625 #define ICE_AQ_DNL_STATUS_RESERVED 0x1 1626 #define ICE_AQ_DNL_STATUS_STOPPED 0x2 1627 #define ICE_AQ_DNL_STATUS_FATAL 0x3 /* Fatal DNL engine error */ 1628 #define ICE_AQ_DNL_SRC_S 3 1629 #define ICE_AQ_DNL_SRC_M (0x3 << ICE_AQ_DNL_SRC_S) 1630 #define ICE_AQ_DNL_SRC_NVM (0x0 << ICE_AQ_DNL_SRC_S) 1631 #define ICE_AQ_DNL_SRC_NVM_SCRATCH (0x1 << ICE_AQ_DNL_SRC_S) 1632 u8 stack_ptr; 1633 #define ICE_AQ_DNL_ST_PTR_S 0x0 1634 #define ICE_AQ_DNL_ST_PTR_M (0x7 << ICE_AQ_DNL_ST_PTR_S) 1635 u8 engine_flags; 1636 #define ICE_AQ_DNL_FLAGS_ERROR BIT(2) 1637 #define ICE_AQ_DNL_FLAGS_NEGATIVE BIT(3) 1638 #define ICE_AQ_DNL_FLAGS_OVERFLOW BIT(4) 1639 #define ICE_AQ_DNL_FLAGS_ZERO BIT(5) 1640 #define ICE_AQ_DNL_FLAGS_CARRY BIT(6) 1641 #define ICE_AQ_DNL_FLAGS_JUMP BIT(7) 1642 __le16 pc; 1643 __le16 activity_id; 1644 __le32 addr_high; 1645 __le32 addr_low; 1646 }; 1647 1648 struct ice_aqc_dnl_get_status_data { 1649 __le16 activity_err_code; 1650 __le16 act_err_code; 1651 #define ICE_AQ_DNL_ACT_ERR_SUCCESS 0x0000 /* no error */ 1652 #define ICE_AQ_DNL_ACT_ERR_PARSE 0x8001 /* NVM parse error */ 1653 #define ICE_AQ_DNL_ACT_ERR_UNSUPPORTED 0x8002 /* unsupported action */ 1654 #define ICE_AQ_DNL_ACT_ERR_NOT_FOUND 0x8003 /* activity not found */ 1655 #define ICE_AQ_DNL_ACT_ERR_BAD_JUMP 0x8004 /* an illegal jump */ 1656 #define ICE_AQ_DNL_ACT_ERR_PSTO_OVER 0x8005 /* persistent store overflow */ 1657 #define ICE_AQ_DNL_ACT_ERR_ST_OVERFLOW 0x8006 /* stack overflow */ 1658 #define ICE_AQ_DNL_ACT_ERR_TIMEOUT 0x8007 /* activity timeout */ 1659 #define ICE_AQ_DNL_ACT_ERR_BREAK 0x0008 /* stopped at breakpoint */ 1660 #define ICE_AQ_DNL_ACT_ERR_INVAL_ARG 0x0101 /* invalid action argument */ 1661 __le32 execution_time; /* in nanoseconds */ 1662 __le16 lib_ver; 1663 u8 psto_local_sz; 1664 u8 psto_global_sz; 1665 u8 stack_sz; 1666 #define ICE_AQ_DNL_STACK_SZ_S 0 1667 #define ICE_AQ_DNL_STACK_SZ_M (0xF << ICE_AQ_DNL_STACK_SZ_S) 1668 u8 port_count; 1669 #define ICE_AQ_DNL_PORT_CNT_S 0 1670 #define ICE_AQ_DNL_PORT_CNT_M (0x1F << ICE_AQ_DNL_PORT_CNT_S) 1671 __le16 act_cache_cntr; 1672 u32 i2c_clk_cntr; 1673 u32 mdio_clk_cntr; 1674 u32 sb_iosf_clk_cntr; 1675 }; 1676 1677 /* DNL run command (direct 0x0681) */ 1678 struct ice_aqc_dnl_run_command { 1679 u8 reserved0; 1680 u8 command; 1681 #define ICE_AQ_DNL_CMD_S 0 1682 #define ICE_AQ_DNL_CMD_M (0x7 << ICE_AQ_DNL_CMD_S) 1683 #define ICE_AQ_DNL_CMD_RESET 0x0 1684 #define ICE_AQ_DNL_CMD_RUN 0x1 1685 #define ICE_AQ_DNL_CMD_STEP 0x3 1686 #define ICE_AQ_DNL_CMD_ABORT 0x4 1687 #define ICE_AQ_DNL_CMD_SET_PC 0x7 1688 #define ICE_AQ_DNL_CMD_SRC_S 3 1689 #define ICE_AQ_DNL_CMD_SRC_M (0x3 << ICE_AQ_DNL_CMD_SRC_S) 1690 #define ICE_AQ_DNL_CMD_SRC_DNL 0x0 1691 #define ICE_AQ_DNL_CMD_SRC_SCRATCH 0x1 1692 __le16 new_pc; 1693 u8 reserved1[12]; 1694 }; 1695 1696 /* DNL call command (indirect 0x0682) 1697 * Struct is used for both command and response 1698 */ 1699 struct ice_aqc_dnl_call_command { 1700 u8 ctx; /* Used in command, reserved in response */ 1701 u8 reserved; 1702 __le16 activity_id; 1703 __le32 reserved1; 1704 __le32 addr_high; 1705 __le32 addr_low; 1706 }; 1707 1708 /* DNL call command/response buffer (indirect 0x0682) */ 1709 struct ice_aqc_dnl_call { 1710 __le32 stores[4]; 1711 }; 1712 1713 /* Used for both commands: 1714 * DNL read sto command (indirect 0x0683) 1715 * DNL write sto command (indirect 0x0684) 1716 */ 1717 struct ice_aqc_dnl_read_write_command { 1718 u8 ctx; 1719 u8 sto_sel; /* STORE select */ 1720 #define ICE_AQC_DNL_STORE_SELECT_STORE 0x0 1721 #define ICE_AQC_DNL_STORE_SELECT_PSTO 0x1 1722 #define ICE_AQC_DNL_STORE_SELECT_STACK 0x2 1723 __le16 offset; 1724 __le32 data; /* Used for write sto only */ 1725 __le32 addr_high; /* Used for read sto only */ 1726 __le32 addr_low; /* Used for read sto only */ 1727 }; 1728 1729 /* Used for both command responses: 1730 * DNL read sto response (indirect 0x0683) 1731 * DNL write sto response (indirect 0x0684) 1732 */ 1733 struct ice_aqc_dnl_read_write_response { 1734 u8 reserved; 1735 u8 status; /* Reserved for read command */ 1736 __le16 size; /* Reserved for write command */ 1737 __le32 data; /* Reserved for write command */ 1738 __le32 addr_high; /* Reserved for write command */ 1739 __le32 addr_low; /* Reserved for write command */ 1740 }; 1741 1742 /* DNL set breakpoints command (indirect 0x0686) */ 1743 struct ice_aqc_dnl_set_breakpoints_command { 1744 __le32 reserved[2]; 1745 __le32 addr_high; 1746 __le32 addr_low; 1747 }; 1748 1749 /* DNL set breakpoints data buffer structure (indirect 0x0686) */ 1750 struct ice_aqc_dnl_set_breakpoints { 1751 u8 ctx; 1752 u8 ena; /* 0- disabled, 1- enabled */ 1753 __le16 offset; 1754 __le16 activity_id; 1755 }; 1756 1757 /* DNL read log data command(indirect 0x0687) */ 1758 struct ice_aqc_dnl_read_log_command { 1759 __le16 reserved0; 1760 __le16 offset; 1761 __le32 reserved1; 1762 __le32 addr_high; 1763 __le32 addr_low; 1764 1765 }; 1766 1767 /* DNL read log data response(indirect 0x0687) */ 1768 struct ice_aqc_dnl_read_log_response { 1769 __le16 reserved; 1770 __le16 size; 1771 __le32 data; 1772 __le32 addr_high; 1773 __le32 addr_low; 1774 1775 }; 1776 1777 struct ice_aqc_link_topo_addr { 1778 u8 lport_num; 1779 u8 lport_num_valid; 1780 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 1781 u8 node_type_ctx; 1782 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 1783 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 1784 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 1785 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1786 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1787 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1788 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 1789 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 1790 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 1791 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 1792 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1793 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 1794 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 1795 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 1796 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 1797 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 1798 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 1799 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 1800 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 1801 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 1802 u8 index; 1803 __le16 handle; 1804 #define ICE_AQC_LINK_TOPO_HANDLE_S 0 1805 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 1806 /* Used to decode the handle field */ 1807 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1808 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 1809 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 1810 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 1811 /* In case of a Mezzanine type */ 1812 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1813 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1814 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 1815 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 1816 /* In case of a LOM type */ 1817 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 1818 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1819 }; 1820 1821 /* Get Link Topology Handle (direct, 0x06E0) */ 1822 struct ice_aqc_get_link_topo { 1823 struct ice_aqc_link_topo_addr addr; 1824 u8 node_part_num; 1825 u8 rsvd[9]; 1826 }; 1827 1828 /* Get Link Topology Pin (direct, 0x06E1) */ 1829 struct ice_aqc_get_link_topo_pin { 1830 struct ice_aqc_link_topo_addr addr; 1831 u8 input_io_params; 1832 #define ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_S 0 1833 #define ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_M \ 1834 (0x1F << ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_S) 1835 #define ICE_AQC_LINK_TOPO_IO_FUNC_GPIO 0 1836 #define ICE_AQC_LINK_TOPO_IO_FUNC_RESET_N 1 1837 #define ICE_AQC_LINK_TOPO_IO_FUNC_INT_N 2 1838 #define ICE_AQC_LINK_TOPO_IO_FUNC_PRESENT_N 3 1839 #define ICE_AQC_LINK_TOPO_IO_FUNC_TX_DIS 4 1840 #define ICE_AQC_LINK_TOPO_IO_FUNC_MODSEL_N 5 1841 #define ICE_AQC_LINK_TOPO_IO_FUNC_LPMODE 6 1842 #define ICE_AQC_LINK_TOPO_IO_FUNC_TX_FAULT 7 1843 #define ICE_AQC_LINK_TOPO_IO_FUNC_RX_LOSS 8 1844 #define ICE_AQC_LINK_TOPO_IO_FUNC_RS0 9 1845 #define ICE_AQC_LINK_TOPO_IO_FUNC_RS1 10 1846 #define ICE_AQC_LINK_TOPO_IO_FUNC_EEPROM_WP 11 1847 /* 12 repeats intentionally due to two different uses depending on context */ 1848 #define ICE_AQC_LINK_TOPO_IO_FUNC_LED 12 1849 #define ICE_AQC_LINK_TOPO_IO_FUNC_RED_LED 12 1850 #define ICE_AQC_LINK_TOPO_IO_FUNC_GREEN_LED 13 1851 #define ICE_AQC_LINK_TOPO_IO_FUNC_BLUE_LED 14 1852 #define ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S 5 1853 #define ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_M \ 1854 (0x7 << ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S) 1855 /* Use ICE_AQC_LINK_TOPO_NODE_TYPE_* for the type values */ 1856 u8 output_io_params; 1857 #define ICE_AQC_LINK_TOPO_OUTPUT_IO_FUNC_S 0 1858 #define ICE_AQC_LINK_TOPO_OUTPUT_IO_FUNC_M \ 1859 (0x1F << \ ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_NUM_S) 1860 /* Use ICE_AQC_LINK_TOPO_IO_FUNC_* for the non-numerical options */ 1861 #define ICE_AQC_LINK_TOPO_OUTPUT_IO_TYPE_S 5 1862 #define ICE_AQC_LINK_TOPO_OUTPUT_IO_TYPE_M \ 1863 (0x7 << ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S) 1864 /* Use ICE_AQC_LINK_TOPO_NODE_TYPE_* for the type values */ 1865 u8 output_io_flags; 1866 #define ICE_AQC_LINK_TOPO_OUTPUT_SPEED_S 0 1867 #define ICE_AQC_LINK_TOPO_OUTPUT_SPEED_M \ 1868 (0x7 << ICE_AQC_LINK_TOPO_OUTPUT_SPEED_S) 1869 #define ICE_AQC_LINK_TOPO_OUTPUT_INT_S 3 1870 #define ICE_AQC_LINK_TOPO_OUTPUT_INT_M \ 1871 (0x3 << ICE_AQC_LINK_TOPO_OUTPUT_INT_S) 1872 #define ICE_AQC_LINK_TOPO_OUTPUT_POLARITY BIT(5) 1873 #define ICE_AQC_LINK_TOPO_OUTPUT_VALUE BIT(6) 1874 #define ICE_AQC_LINK_TOPO_OUTPUT_DRIVEN BIT(7) 1875 u8 rsvd[7]; 1876 }; 1877 1878 /* Read/Write I2C (direct, 0x06E2/0x06E3) */ 1879 struct ice_aqc_i2c { 1880 struct ice_aqc_link_topo_addr topo_addr; 1881 __le16 i2c_addr; 1882 u8 i2c_params; 1883 #define ICE_AQC_I2C_DATA_SIZE_S 0 1884 #define ICE_AQC_I2C_DATA_SIZE_M (0xF << ICE_AQC_I2C_DATA_SIZE_S) 1885 #define ICE_AQC_I2C_ADDR_TYPE_M BIT(4) 1886 #define ICE_AQC_I2C_ADDR_TYPE_7BIT 0 1887 #define ICE_AQC_I2C_ADDR_TYPE_10BIT ICE_AQC_I2C_ADDR_TYPE_M 1888 #define ICE_AQC_I2C_DATA_OFFSET_S 5 1889 #define ICE_AQC_I2C_DATA_OFFSET_M (0x3 << ICE_AQC_I2C_DATA_OFFSET_S) 1890 #define ICE_AQC_I2C_USE_REPEATED_START BIT(7) 1891 u8 rsvd; 1892 __le16 i2c_bus_addr; 1893 #define ICE_AQC_I2C_ADDR_7BIT_MASK 0x7F 1894 #define ICE_AQC_I2C_ADDR_10BIT_MASK 0x3FF 1895 u8 i2c_data[4]; /* Used only by write command, reserved in read. */ 1896 }; 1897 1898 /* Read I2C Response (direct, 0x06E2) */ 1899 struct ice_aqc_read_i2c_resp { 1900 u8 i2c_data[16]; 1901 }; 1902 1903 /* Read/Write MDIO (direct, 0x06E4/0x06E5) */ 1904 struct ice_aqc_mdio { 1905 struct ice_aqc_link_topo_addr topo_addr; 1906 u8 mdio_device_addr; 1907 #define ICE_AQC_MDIO_DEV_S 0 1908 #define ICE_AQC_MDIO_DEV_M (0x1F << ICE_AQC_MDIO_DEV_S) 1909 #define ICE_AQC_MDIO_CLAUSE_22 BIT(5) 1910 #define ICE_AQC_MDIO_CLAUSE_45 BIT(6) 1911 u8 mdio_bus_address; 1912 #define ICE_AQC_MDIO_BUS_ADDR_S 0 1913 #define ICE_AQC_MDIO_BUS_ADDR_M (0x1F << ICE_AQC_MDIO_BUS_ADDR_S) 1914 __le16 offset; 1915 __le16 data; /* Input in write cmd, output in read cmd. */ 1916 u8 rsvd1[4]; 1917 }; 1918 1919 /* Set/Get GPIO By Function (direct, 0x06E6/0x06E7) */ 1920 struct ice_aqc_gpio_by_func { 1921 struct ice_aqc_link_topo_addr topo_addr; 1922 u8 io_func_num; 1923 #define ICE_AQC_GPIO_FUNC_S 0 1924 #define ICE_AQC_GPIO_FUNC_M (0x1F << ICE_AQC_GPIO_IO_FUNC_NUM_S) 1925 u8 io_value; /* Input in write cmd, output in read cmd. */ 1926 #define ICE_AQC_GPIO_ON BIT(0) 1927 #define ICE_AQC_GPIO_OFF 0 1928 u8 rsvd[8]; 1929 }; 1930 1931 /* Set LED (direct, 0x06E8) */ 1932 struct ice_aqc_set_led { 1933 struct ice_aqc_link_topo_addr topo_addr; 1934 u8 color_and_blink; 1935 #define ICE_AQC_LED_COLOR_S 0 1936 #define ICE_AQC_LED_COLOR_M (0x7 << ICE_AQC_LED_COLOR_S) 1937 #define ICE_AQC_LED_COLOR_SKIP 0 1938 #define ICE_AQC_LED_COLOR_RED 1 1939 #define ICE_AQC_LED_COLOR_ORANGE 2 1940 #define ICE_AQC_LED_COLOR_YELLOW 3 1941 #define ICE_AQC_LED_COLOR_GREEN 4 1942 #define ICE_AQC_LED_COLOR_BLUE 5 1943 #define ICE_AQC_LED_COLOR_PURPLE 6 1944 #define ICE_AQC_LED_BLINK_S 3 1945 #define ICE_AQC_LED_BLINK_M (0x7 << ICE_AQC_LED_BLINK_S) 1946 #define ICE_AQC_LED_BLINK_NONE 0 1947 #define ICE_AQC_LED_BLINK_SLOW 1 1948 #define ICE_AQC_LED_BLINK_SLOW_MAC 2 1949 #define ICE_AQC_LED_BLINK_SLOW_FLTR 3 1950 #define ICE_AQC_LED_BLINK_FAST 5 1951 #define ICE_AQC_LED_BLINK_FAST_MAC 6 1952 #define ICE_AQC_LED_BLINK_FAST_FLTR 7 1953 u8 rsvd[9]; 1954 }; 1955 1956 /* Set Port Identification LED (direct, 0x06E9) */ 1957 struct ice_aqc_set_port_id_led { 1958 u8 lport_num; 1959 u8 lport_num_valid; 1960 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0) 1961 u8 ident_mode; 1962 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1963 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1964 u8 rsvd[13]; 1965 }; 1966 1967 /* Get Port Options (indirect, 0x06EA) */ 1968 struct ice_aqc_get_port_options { 1969 u8 lport_num; 1970 u8 lport_num_valid; 1971 #define ICE_AQC_PORT_OPT_PORT_NUM_VALID BIT(0) 1972 u8 port_options_count; 1973 #define ICE_AQC_PORT_OPT_COUNT_S 0 1974 #define ICE_AQC_PORT_OPT_COUNT_M (0xF << ICE_AQC_PORT_OPT_COUNT_S) 1975 u8 innermost_phy_index; 1976 u8 port_options; 1977 #define ICE_AQC_PORT_OPT_ACTIVE_S 0 1978 #define ICE_AQC_PORT_OPT_ACTIVE_M (0xF << ICE_AQC_PORT_OPT_ACTIVE_S) 1979 #define ICE_AQC_PORT_OPT_FORCED BIT(6) 1980 #define ICE_AQC_PORT_OPT_VALID BIT(7) 1981 u8 pending_port_option_status; 1982 #define ICE_AQC_PENDING_PORT_OPT_IDX_S 0 1983 #define ICE_AQC_PENDING_PORT_OPT_IDX_M (0xF << ICE_AQC_PENDING_PORT_OPT_IDX_S) 1984 #define ICE_AQC_PENDING_PORT_OPT_VALID BIT(7) 1985 u8 rsvd[2]; 1986 __le32 addr_high; 1987 __le32 addr_low; 1988 }; 1989 1990 struct ice_aqc_get_port_options_elem { 1991 u8 pmd; 1992 #define ICE_AQC_PORT_INV_PORT_OPT 4 1993 #define ICE_AQC_PORT_OPT_PMD_COUNT_S 0 1994 #define ICE_AQC_PORT_OPT_PMD_COUNT_M (0xF << ICE_AQC_PORT_OPT_PMD_COUNT_S) 1995 #define ICE_AQC_PORT_OPT_PMD_WIDTH_S 4 1996 #define ICE_AQC_PORT_OPT_PMD_WIDTH_M (0xF << ICE_AQC_PORT_OPT_PMD_WIDTH_S) 1997 u8 max_lane_speed; 1998 #define ICE_AQC_PORT_OPT_MAX_LANE_S 0 1999 #define ICE_AQC_PORT_OPT_MAX_LANE_M (0xF << ICE_AQC_PORT_OPT_MAX_LANE_S) 2000 #define ICE_AQC_PORT_OPT_MAX_LANE_100M 0 2001 #define ICE_AQC_PORT_OPT_MAX_LANE_1G 1 2002 #define ICE_AQC_PORT_OPT_MAX_LANE_2500M 2 2003 #define ICE_AQC_PORT_OPT_MAX_LANE_5G 3 2004 #define ICE_AQC_PORT_OPT_MAX_LANE_10G 4 2005 #define ICE_AQC_PORT_OPT_MAX_LANE_25G 5 2006 #define ICE_AQC_PORT_OPT_MAX_LANE_50G 6 2007 #define ICE_AQC_PORT_OPT_MAX_LANE_100G 7 2008 u8 global_scid[2]; 2009 u8 phy_scid[2]; 2010 u8 pf2port_cid[2]; 2011 }; 2012 2013 /* Set Port Option (direct, 0x06EB) */ 2014 struct ice_aqc_set_port_option { 2015 u8 lport_num; 2016 u8 lport_num_valid; 2017 #define ICE_AQC_SET_PORT_OPT_PORT_NUM_VALID BIT(0) 2018 u8 selected_port_option; 2019 u8 rsvd[13]; 2020 }; 2021 2022 /* Set/Get GPIO (direct, 0x06EC/0x06ED) */ 2023 struct ice_aqc_gpio { 2024 __le16 gpio_ctrl_handle; 2025 #define ICE_AQC_GPIO_HANDLE_S 0 2026 #define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S) 2027 u8 gpio_num; 2028 u8 gpio_val; 2029 u8 rsvd[12]; 2030 }; 2031 2032 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 2033 struct ice_aqc_sff_eeprom { 2034 u8 lport_num; 2035 u8 lport_num_valid; 2036 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 2037 __le16 i2c_bus_addr; 2038 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 2039 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 2040 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 2041 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 2042 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 2043 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 2044 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 2045 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 2046 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 2047 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 2048 #define ICE_AQC_SFF_IS_WRITE BIT(15) 2049 __le16 i2c_mem_addr; 2050 __le16 eeprom_page; 2051 #define ICE_AQC_SFF_EEPROM_BANK_S 0 2052 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 2053 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 2054 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 2055 __le32 addr_high; 2056 __le32 addr_low; 2057 }; 2058 2059 /* SW Set GPIO command (indirect 0x6EF) 2060 * SW Get GPIO command (indirect 0x6F0) 2061 */ 2062 struct ice_aqc_sw_gpio { 2063 __le16 gpio_ctrl_handle; 2064 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S 0 2065 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_M (0x3FF << ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S) 2066 u8 gpio_num; 2067 #define ICE_AQC_SW_GPIO_NUMBER_S 0 2068 #define ICE_AQC_SW_GPIO_NUMBER_M (0x1F << ICE_AQC_SW_GPIO_NUMBER_S) 2069 u8 gpio_params; 2070 #define ICE_AQC_SW_GPIO_PARAMS_DIRECTION BIT(1) 2071 #define ICE_AQC_SW_GPIO_PARAMS_VALUE BIT(0) 2072 u8 rsvd[12]; 2073 }; 2074 2075 /* Program topology device NVM (direct, 0x06F2) */ 2076 struct ice_aqc_program_topology_device_nvm { 2077 u8 lport_num; 2078 u8 lport_num_valid; 2079 u8 node_type_ctx; 2080 u8 index; 2081 u8 rsvd[12]; 2082 }; 2083 2084 /* Read topology device NVM (indirect, 0x06F3) */ 2085 struct ice_aqc_read_topology_device_nvm { 2086 u8 lport_num; 2087 u8 lport_num_valid; 2088 u8 node_type_ctx; 2089 u8 index; 2090 __le32 start_address; 2091 u8 data_read[8]; 2092 }; 2093 2094 /* NVM Read command (indirect 0x0701) 2095 * NVM Erase commands (direct 0x0702) 2096 * NVM Write commands (indirect 0x0703) 2097 * NVM Write Activate commands (direct 0x0707) 2098 * NVM Shadow RAM Dump commands (direct 0x0707) 2099 */ 2100 struct ice_aqc_nvm { 2101 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 2102 __le16 offset_low; 2103 u8 offset_high; /* For Write Activate offset_high is used as flags2 */ 2104 u8 cmd_flags; 2105 #define ICE_AQC_NVM_LAST_CMD BIT(0) 2106 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */ 2107 #define ICE_AQC_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */ 2108 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 2109 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 2110 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 2111 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 2112 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 2113 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 2114 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) 2115 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) 2116 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) 2117 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 2118 #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3) 2119 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 2120 #define ICE_AQC_NVM_POR_FLAG 0 /* Used by NVM Write completion on ARQ */ 2121 #define ICE_AQC_NVM_PERST_FLAG 1 2122 #define ICE_AQC_NVM_EMPR_FLAG 2 2123 #define ICE_AQC_NVM_EMPR_ENA BIT(0) 2124 __le16 module_typeid; 2125 __le16 length; 2126 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 2127 __le32 addr_high; 2128 __le32 addr_low; 2129 }; 2130 2131 /* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */ 2132 #define ICE_AQC_NVM_SECTOR_UNIT 4096 /* In Bytes */ 2133 #define ICE_AQC_NVM_WORD_UNIT 2 /* In Bytes */ 2134 2135 #define ICE_AQC_NVM_START_POINT 0 2136 #define ICE_AQC_NVM_EMP_SR_PTR_OFFSET 0x90 2137 #define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN 2 /* In Bytes */ 2138 #define ICE_AQC_NVM_EMP_SR_PTR_M MAKEMASK(0x7FFF, 0) 2139 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S 15 2140 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M BIT(15) 2141 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR 1 2142 2143 #define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET 0x46 2144 #define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN 2 /* In Bytes */ 2145 #define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */ 2146 2147 #define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129 2148 #define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */ 2149 #define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0) 2150 #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */ 2151 #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */ 2152 2153 #define ICE_AQC_NVM_MINSREV_MOD_ID 0x130 2154 2155 /* Used for reading and writing MinSRev using 0x0701 and 0x0703. Note that the 2156 * type field is excluded from the section when reading and writing from 2157 * a module using the module_typeid field with these AQ commands. 2158 */ 2159 struct ice_aqc_nvm_minsrev { 2160 __le16 length; 2161 __le16 validity; 2162 #define ICE_AQC_NVM_MINSREV_NVM_VALID BIT(0) 2163 #define ICE_AQC_NVM_MINSREV_OROM_VALID BIT(1) 2164 __le16 nvm_minsrev_l; 2165 __le16 nvm_minsrev_h; 2166 __le16 orom_minsrev_l; 2167 __le16 orom_minsrev_h; 2168 }; 2169 2170 /* Used for 0x0704 as well as for 0x0705 commands */ 2171 struct ice_aqc_nvm_cfg { 2172 u8 cmd_flags; 2173 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0) 2174 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1) 2175 #define ICE_AQC_ANVM_NEW_CFG BIT(2) 2176 u8 reserved; 2177 __le16 count; 2178 __le16 id; 2179 u8 reserved1[2]; 2180 __le32 addr_high; 2181 __le32 addr_low; 2182 }; 2183 2184 struct ice_aqc_nvm_cfg_data { 2185 __le16 field_id; 2186 __le16 field_options; 2187 __le16 field_value; 2188 }; 2189 2190 /* NVM Checksum Command (direct, 0x0706) */ 2191 struct ice_aqc_nvm_checksum { 2192 u8 flags; 2193 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 2194 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 2195 u8 rsvd; 2196 __le16 checksum; /* Used only by response */ 2197 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 2198 u8 rsvd2[12]; 2199 }; 2200 2201 /* 2202 * Send to PF command (indirect 0x0801) ID is only used by PF 2203 * 2204 * Send to VF command (indirect 0x0802) ID is only used by PF 2205 * 2206 */ 2207 struct ice_aqc_pf_vf_msg { 2208 __le32 id; 2209 u32 reserved; 2210 __le32 addr_high; 2211 __le32 addr_low; 2212 }; 2213 2214 /* Write/Read Alternate - Direct (direct 0x0900/0x0902) */ 2215 struct ice_aqc_read_write_alt_direct { 2216 __le32 dword0_addr; 2217 __le32 dword0_value; 2218 __le32 dword1_addr; 2219 __le32 dword1_value; 2220 }; 2221 2222 /* Write/Read Alternate - Indirect (indirect 0x0901/0x0903) */ 2223 struct ice_aqc_read_write_alt_indirect { 2224 __le32 base_dword_addr; 2225 __le32 num_dwords; 2226 __le32 addr_high; 2227 __le32 addr_low; 2228 }; 2229 2230 /* Done Alternate Write (direct 0x0904) */ 2231 struct ice_aqc_done_alt_write { 2232 u8 flags; 2233 #define ICE_AQC_CMD_UEFI_BIOS_MODE BIT(0) 2234 #define ICE_AQC_RESP_RESET_NEEDED BIT(1) 2235 u8 reserved[15]; 2236 }; 2237 2238 /* Clear Port Alternate Write (direct 0x0906) */ 2239 struct ice_aqc_clear_port_alt_write { 2240 u8 reserved[16]; 2241 }; 2242 2243 /* Get LLDP MIB (indirect 0x0A00) 2244 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 2245 * as the format is the same. 2246 */ 2247 struct ice_aqc_lldp_get_mib { 2248 u8 type; 2249 #define ICE_AQ_LLDP_MIB_TYPE_S 0 2250 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 2251 #define ICE_AQ_LLDP_MIB_LOCAL 0 2252 #define ICE_AQ_LLDP_MIB_REMOTE 1 2253 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 2254 #define ICE_AQ_LLDP_BRID_TYPE_S 2 2255 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 2256 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 2257 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 2258 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 2259 #define ICE_AQ_LLDP_TX_S 0x4 2260 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 2261 #define ICE_AQ_LLDP_TX_ACTIVE 0 2262 #define ICE_AQ_LLDP_TX_SUSPENDED 1 2263 #define ICE_AQ_LLDP_TX_FLUSHED 3 2264 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 2265 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 2266 * Get LLDP MIB (0x0A00) response only. 2267 */ 2268 u8 reserved1; 2269 __le16 local_len; 2270 __le16 remote_len; 2271 u8 reserved2[2]; 2272 __le32 addr_high; 2273 __le32 addr_low; 2274 }; 2275 2276 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 2277 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 2278 struct ice_aqc_lldp_set_mib_change { 2279 u8 command; 2280 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2281 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 2282 u8 reserved[15]; 2283 }; 2284 2285 /* Add LLDP TLV (indirect 0x0A02) 2286 * Delete LLDP TLV (indirect 0x0A04) 2287 */ 2288 struct ice_aqc_lldp_add_delete_tlv { 2289 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2290 u8 reserved1[1]; 2291 __le16 len; 2292 u8 reserved2[4]; 2293 __le32 addr_high; 2294 __le32 addr_low; 2295 }; 2296 2297 /* Update LLDP TLV (indirect 0x0A03) */ 2298 struct ice_aqc_lldp_update_tlv { 2299 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2300 u8 reserved; 2301 __le16 old_len; 2302 __le16 new_offset; 2303 __le16 new_len; 2304 __le32 addr_high; 2305 __le32 addr_low; 2306 }; 2307 2308 /* Stop LLDP (direct 0x0A05) */ 2309 struct ice_aqc_lldp_stop { 2310 u8 command; 2311 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 2312 #define ICE_AQ_LLDP_AGENT_STOP 0x0 2313 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 2314 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 2315 u8 reserved[15]; 2316 }; 2317 2318 /* Start LLDP (direct 0x0A06) */ 2319 struct ice_aqc_lldp_start { 2320 u8 command; 2321 #define ICE_AQ_LLDP_AGENT_START BIT(0) 2322 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 2323 u8 reserved[15]; 2324 }; 2325 2326 /* Get CEE DCBX Oper Config (0x0A07) 2327 * The command uses the generic descriptor struct and 2328 * returns the struct below as an indirect response. 2329 */ 2330 struct ice_aqc_get_cee_dcb_cfg_resp { 2331 u8 oper_num_tc; 2332 u8 oper_prio_tc[4]; 2333 u8 oper_tc_bw[8]; 2334 u8 oper_pfc_en; 2335 __le16 oper_app_prio; 2336 #define ICE_AQC_CEE_APP_FCOE_S 0 2337 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 2338 #define ICE_AQC_CEE_APP_ISCSI_S 3 2339 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 2340 #define ICE_AQC_CEE_APP_FIP_S 8 2341 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 2342 __le32 tlv_status; 2343 #define ICE_AQC_CEE_PG_STATUS_S 0 2344 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 2345 #define ICE_AQC_CEE_PFC_STATUS_S 3 2346 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 2347 #define ICE_AQC_CEE_FCOE_STATUS_S 8 2348 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 2349 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 2350 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 2351 #define ICE_AQC_CEE_FIP_STATUS_S 16 2352 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 2353 u8 reserved[12]; 2354 }; 2355 2356 /* Set Local LLDP MIB (indirect 0x0A08) 2357 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 2358 */ 2359 struct ice_aqc_lldp_set_local_mib { 2360 u8 type; 2361 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 2362 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 2363 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 2364 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 2365 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 2366 u8 reserved0; 2367 __le16 length; 2368 u8 reserved1[4]; 2369 __le32 addr_high; 2370 __le32 addr_low; 2371 }; 2372 2373 struct ice_aqc_lldp_set_local_mib_resp { 2374 u8 status; 2375 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0) 2376 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0 2377 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT SET_LOCAL_MIB_RESP_EVENT_M 2378 u8 reserved[15]; 2379 }; 2380 2381 /* Stop/Start LLDP Agent (direct 0x0A09) 2382 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 2383 * The same structure is used for the response, with the command field 2384 * being used as the status field. 2385 */ 2386 struct ice_aqc_lldp_stop_start_specific_agent { 2387 u8 command; 2388 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 2389 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 2390 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 2391 u8 reserved[15]; 2392 }; 2393 2394 /* LLDP Filter Control (direct 0x0A0A) */ 2395 struct ice_aqc_lldp_filter_ctrl { 2396 u8 cmd_flags; 2397 #define ICE_AQC_LLDP_FILTER_ACTION_M MAKEMASK(3, 0) 2398 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0 2399 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1 2400 #define ICE_AQC_LLDP_FILTER_ACTION_UPDATE 0x2 2401 u8 reserved1; 2402 __le16 vsi_num; 2403 u8 reserved2[12]; 2404 }; 2405 2406 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 2407 struct ice_aqc_get_set_rss_key { 2408 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 2409 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 2410 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 2411 __le16 vsi_id; 2412 u8 reserved[6]; 2413 __le32 addr_high; 2414 __le32 addr_low; 2415 }; 2416 2417 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 2418 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 2419 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 2420 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 2421 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 2422 2423 /** 2424 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer 2425 * @standard_rss_key: 40 most significant bytes of hash key 2426 * @extended_hash_key: 12 least significant bytes of hash key 2427 * 2428 * Set/Get 40 byte hash key using standard_rss_key field, and set 2429 * extended_hash_key field to zero. Set/Get 52 byte hash key using 2430 * standard_rss_key field for 40 most significant bytes and the 2431 * extended_hash_key field for the 12 least significant bytes of hash key. 2432 */ 2433 struct ice_aqc_get_set_rss_keys { 2434 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 2435 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 2436 }; 2437 2438 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 2439 struct ice_aqc_get_set_rss_lut { 2440 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 2441 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 2442 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 2443 __le16 vsi_id; 2444 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 2445 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 2446 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 2447 2448 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 2449 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 2450 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 2451 2452 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 2453 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 2454 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 2455 2456 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 2457 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 2458 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 2459 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 2460 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 2461 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 2462 2463 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 2464 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 2465 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 2466 2467 __le16 flags; 2468 __le32 reserved; 2469 __le32 addr_high; 2470 __le32 addr_low; 2471 }; 2472 2473 /* Add Tx LAN Queues (indirect 0x0C30) */ 2474 struct ice_aqc_add_txqs { 2475 u8 num_qgrps; 2476 u8 reserved[3]; 2477 __le32 reserved1; 2478 __le32 addr_high; 2479 __le32 addr_low; 2480 }; 2481 2482 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 2483 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 2484 */ 2485 struct ice_aqc_add_txqs_perq { 2486 __le16 txq_id; 2487 u8 rsvd[2]; 2488 __le32 q_teid; 2489 u8 txq_ctx[22]; 2490 u8 rsvd2[2]; 2491 struct ice_aqc_txsched_elem info; 2492 }; 2493 2494 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 2495 * is an array of the following structs. Please note that the length of 2496 * each struct ice_aqc_add_tx_qgrp is variable due 2497 * to the variable number of queues in each group! 2498 */ 2499 struct ice_aqc_add_tx_qgrp { 2500 __le32 parent_teid; 2501 u8 num_txqs; 2502 u8 rsvd[3]; 2503 struct ice_aqc_add_txqs_perq txqs[STRUCT_HACK_VAR_LEN]; 2504 }; 2505 2506 /* Disable Tx LAN Queues (indirect 0x0C31) */ 2507 struct ice_aqc_dis_txqs { 2508 u8 cmd_type; 2509 #define ICE_AQC_Q_DIS_CMD_S 0 2510 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 2511 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 2512 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 2513 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 2514 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 2515 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 2516 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 2517 u8 num_entries; 2518 __le16 vmvf_and_timeout; 2519 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 2520 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 2521 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 2522 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 2523 __le32 blocked_cgds; 2524 __le32 addr_high; 2525 __le32 addr_low; 2526 }; 2527 2528 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 2529 * contains the following structures, arrayed one after the 2530 * other. 2531 * Note: Since the q_id is 16 bits wide, if the 2532 * number of queues is even, then 2 bytes of alignment MUST be 2533 * added before the start of the next group, to allow correct 2534 * alignment of the parent_teid field. 2535 */ 2536 #pragma pack(1) 2537 struct ice_aqc_dis_txq_item { 2538 __le32 parent_teid; 2539 u8 num_qs; 2540 u8 rsvd; 2541 /* The length of the q_id array varies according to num_qs */ 2542 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 2543 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 2544 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2545 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 2546 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2547 __le16 q_id[STRUCT_HACK_VAR_LEN]; 2548 }; 2549 #pragma pack() 2550 2551 /* Tx LAN Queues Cleanup Event (0x0C31) */ 2552 struct ice_aqc_txqs_cleanup { 2553 __le16 caller_opc; 2554 __le16 cmd_tag; 2555 u8 reserved[12]; 2556 }; 2557 2558 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */ 2559 struct ice_aqc_move_txqs { 2560 u8 cmd_type; 2561 #define ICE_AQC_Q_CMD_TYPE_S 0 2562 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S) 2563 #define ICE_AQC_Q_CMD_TYPE_MOVE 1 2564 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2 2565 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3 2566 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2) 2567 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3) 2568 u8 num_qs; 2569 u8 rsvd; 2570 u8 timeout; 2571 #define ICE_AQC_Q_CMD_TIMEOUT_S 2 2572 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S) 2573 __le32 blocked_cgds; 2574 __le32 addr_high; 2575 __le32 addr_low; 2576 }; 2577 2578 /* Per-queue data buffer for the Move Tx LAN Queues command/response */ 2579 struct ice_aqc_move_txqs_elem { 2580 __le16 txq_id; 2581 u8 q_cgd; 2582 u8 rsvd; 2583 __le32 q_teid; 2584 }; 2585 2586 /* Indirect data buffer for the Move Tx LAN Queues command/response */ 2587 struct ice_aqc_move_txqs_data { 2588 __le32 src_teid; 2589 __le32 dest_teid; 2590 struct ice_aqc_move_txqs_elem txqs[STRUCT_HACK_VAR_LEN]; 2591 }; 2592 2593 /* Download Package (indirect 0x0C40) */ 2594 /* Also used for Update Package (indirect 0x0C42 and 0x0C41) */ 2595 struct ice_aqc_download_pkg { 2596 u8 flags; 2597 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 2598 u8 reserved[3]; 2599 __le32 reserved1; 2600 __le32 addr_high; 2601 __le32 addr_low; 2602 }; 2603 2604 struct ice_aqc_download_pkg_resp { 2605 __le32 error_offset; 2606 __le32 error_info; 2607 __le32 addr_high; 2608 __le32 addr_low; 2609 }; 2610 2611 /* Get Package Info List (indirect 0x0C43) */ 2612 struct ice_aqc_get_pkg_info_list { 2613 __le32 reserved1; 2614 __le32 reserved2; 2615 __le32 addr_high; 2616 __le32 addr_low; 2617 }; 2618 2619 /* Version format for packages */ 2620 struct ice_pkg_ver { 2621 u8 major; 2622 u8 minor; 2623 u8 update; 2624 u8 draft; 2625 }; 2626 2627 #define ICE_PKG_NAME_SIZE 32 2628 #define ICE_SEG_ID_SIZE 28 2629 #define ICE_SEG_NAME_SIZE 28 2630 2631 struct ice_aqc_get_pkg_info { 2632 struct ice_pkg_ver ver; 2633 char name[ICE_SEG_NAME_SIZE]; 2634 __le32 track_id; 2635 u8 is_in_nvm; 2636 u8 is_active; 2637 u8 is_active_at_boot; 2638 u8 is_modified; 2639 }; 2640 2641 /* Get Package Info List response buffer format (0x0C43) */ 2642 struct ice_aqc_get_pkg_info_resp { 2643 __le32 count; 2644 struct ice_aqc_get_pkg_info pkg_info[STRUCT_HACK_VAR_LEN]; 2645 }; 2646 2647 /* Driver Shared Parameters (direct, 0x0C90) */ 2648 struct ice_aqc_driver_shared_params { 2649 u8 set_or_get_op; 2650 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0) 2651 #define ICE_AQC_DRIVER_PARAM_SET 0 2652 #define ICE_AQC_DRIVER_PARAM_GET 1 2653 u8 param_indx; 2654 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15 2655 u8 rsvd[2]; 2656 __le32 param_val; 2657 __le32 addr_high; 2658 __le32 addr_low; 2659 }; 2660 2661 /* Lan Queue Overflow Event (direct, 0x1001) */ 2662 struct ice_aqc_event_lan_overflow { 2663 __le32 prtdcb_ruptq; 2664 __le32 qtx_ctl; 2665 u8 reserved[8]; 2666 }; 2667 2668 /* Set Health Status (direct 0xFF20) */ 2669 struct ice_aqc_set_health_status_config { 2670 u8 event_source; 2671 #define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0) 2672 #define ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1) 2673 #define ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2) 2674 u8 reserved[15]; 2675 }; 2676 2677 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_STRICT 0x101 2678 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_TYPE 0x102 2679 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_QUAL 0x103 2680 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_COMM 0x104 2681 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_CONFLICT 0x105 2682 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_NOT_PRESENT 0x106 2683 #define ICE_AQC_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED 0x107 2684 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT 0x108 2685 #define ICE_AQC_HEALTH_STATUS_ERR_INVALID_LINK_CFG 0x10B 2686 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_ACCESS 0x10C 2687 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_UNREACHABLE 0x10D 2688 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_MOD_LIMITED 0x10F 2689 #define ICE_AQC_HEALTH_STATUS_ERR_PARALLEL_FAULT 0x110 2690 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED 0x111 2691 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST_TOPO 0x112 2692 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST 0x113 2693 #define ICE_AQC_HEALTH_STATUS_ERR_TOPO_CONFLICT 0x114 2694 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS 0x115 2695 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME 0x116 2696 #define ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT 0x117 2697 #define ICE_AQC_HEALTH_STATUS_INFO_RECOVERY 0x500 2698 #define ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS 0x501 2699 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH 0x502 2700 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_AUTH 0x503 2701 #define ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH 0x504 2702 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT 0x505 2703 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT 0x506 2704 #define ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB 0x509 2705 2706 /* Get Health Status codes (indirect 0xFF21) */ 2707 struct ice_aqc_get_supported_health_status_codes { 2708 __le16 health_code_count; 2709 u8 reserved[6]; 2710 __le32 addr_high; 2711 __le32 addr_low; 2712 }; 2713 2714 /* Get Health Status (indirect 0xFF22) */ 2715 struct ice_aqc_get_health_status { 2716 __le16 health_status_count; 2717 u8 reserved[6]; 2718 __le32 addr_high; 2719 __le32 addr_low; 2720 }; 2721 2722 /* Get Health Status event buffer entry, (0xFF22) 2723 * repeated per reported health status 2724 */ 2725 struct ice_aqc_health_status_elem { 2726 __le16 health_status_code; 2727 __le16 event_source; 2728 #define ICE_AQC_HEALTH_STATUS_PF (0x1) 2729 #define ICE_AQC_HEALTH_STATUS_PORT (0x2) 2730 #define ICE_AQC_HEALTH_STATUS_GLOBAL (0x3) 2731 __le32 internal_data1; 2732 #define ICE_AQC_HEALTH_STATUS_UNDEFINED_DATA (0xDEADBEEF) 2733 __le32 internal_data2; 2734 }; 2735 2736 /* Clear Health Status (direct 0xFF23) */ 2737 struct ice_aqc_clear_health_status { 2738 __le32 reserved[4]; 2739 }; 2740 2741 /* Set FW Logging configuration (indirect 0xFF30) 2742 * Register for FW Logging (indirect 0xFF31) 2743 * Query FW Logging (indirect 0xFF32) 2744 * FW Log Event (indirect 0xFF33) 2745 * Get FW Log (indirect 0xFF34) 2746 * Clear FW Log (indirect 0xFF35) 2747 */ 2748 2749 struct ice_aqc_fw_log { 2750 u8 cmd_flags; 2751 #define ICE_AQC_FW_LOG_CONF_UART_EN BIT(0) 2752 #define ICE_AQC_FW_LOG_CONF_AQ_EN BIT(1) 2753 #define ICE_AQC_FW_LOG_CONF_SET_VALID BIT(3) 2754 #define ICE_AQC_FW_LOG_AQ_REGISTER BIT(0) 2755 #define ICE_AQC_FW_LOG_AQ_QUERY BIT(2) 2756 #define ICE_AQC_FW_LOG_PERSISTENT BIT(0) 2757 u8 rsp_flag; 2758 #define ICE_AQC_FW_LOG_MORE_DATA BIT(1) 2759 __le16 fw_rt_msb; 2760 union { 2761 struct { 2762 __le32 fw_rt_lsb; 2763 } sync; 2764 struct { 2765 __le16 log_resolution; 2766 #define ICE_AQC_FW_LOG_MIN_RESOLUTION (1) 2767 #define ICE_AQC_FW_LOG_MAX_RESOLUTION (128) 2768 __le16 mdl_cnt; 2769 } cfg; 2770 } ops; 2771 __le32 addr_high; 2772 __le32 addr_low; 2773 }; 2774 2775 /* Response Buffer for: 2776 * Set Firmware Logging Configuration (0xFF30) 2777 * Query FW Logging (0xFF32) 2778 */ 2779 struct ice_aqc_fw_log_cfg_resp { 2780 __le16 module_identifier; 2781 u8 log_level; 2782 u8 rsvd0; 2783 }; 2784 2785 /** 2786 * struct ice_aq_desc - Admin Queue (AQ) descriptor 2787 * @flags: ICE_AQ_FLAG_* flags 2788 * @opcode: AQ command opcode 2789 * @datalen: length in bytes of indirect/external data buffer 2790 * @retval: return value from firmware 2791 * @cookie_high: opaque data high-half 2792 * @cookie_low: opaque data low-half 2793 * @params: command-specific parameters 2794 * 2795 * Descriptor format for commands the driver posts on the Admin Transmit Queue 2796 * (ATQ). The firmware writes back onto the command descriptor and returns 2797 * the result of the command. Asynchronous events that are not an immediate 2798 * result of the command are written to the Admin Receive Queue (ARQ) using 2799 * the same descriptor format. Descriptors are in little-endian notation with 2800 * 32-bit words. 2801 */ 2802 struct ice_aq_desc { 2803 __le16 flags; 2804 __le16 opcode; 2805 __le16 datalen; 2806 __le16 retval; 2807 __le32 cookie_high; 2808 __le32 cookie_low; 2809 union { 2810 u8 raw[16]; 2811 struct ice_aqc_generic generic; 2812 struct ice_aqc_get_ver get_ver; 2813 struct ice_aqc_driver_ver driver_ver; 2814 struct ice_aqc_q_shutdown q_shutdown; 2815 struct ice_aqc_get_exp_err exp_err; 2816 struct ice_aqc_req_res res_owner; 2817 struct ice_aqc_manage_mac_read mac_read; 2818 struct ice_aqc_manage_mac_write mac_write; 2819 struct ice_aqc_clear_pxe clear_pxe; 2820 struct ice_aqc_config_no_drop_policy no_drop; 2821 struct ice_aqc_add_update_mir_rule add_update_rule; 2822 struct ice_aqc_delete_mir_rule del_rule; 2823 struct ice_aqc_list_caps get_cap; 2824 struct ice_aqc_get_phy_caps get_phy; 2825 struct ice_aqc_set_phy_cfg set_phy; 2826 struct ice_aqc_restart_an restart_an; 2827 struct ice_aqc_dnl_get_status get_status; 2828 struct ice_aqc_dnl_run_command dnl_run; 2829 struct ice_aqc_dnl_call_command dnl_call; 2830 struct ice_aqc_dnl_read_write_command dnl_read_write; 2831 struct ice_aqc_dnl_read_write_response dnl_read_write_resp; 2832 struct ice_aqc_dnl_set_breakpoints_command dnl_set_brk; 2833 struct ice_aqc_dnl_read_log_command dnl_read_log; 2834 struct ice_aqc_dnl_read_log_response dnl_read_log_resp; 2835 struct ice_aqc_i2c read_write_i2c; 2836 struct ice_aqc_read_i2c_resp read_i2c_resp; 2837 struct ice_aqc_mdio read_write_mdio; 2838 struct ice_aqc_gpio_by_func read_write_gpio_by_func; 2839 struct ice_aqc_gpio read_write_gpio; 2840 struct ice_aqc_set_led set_led; 2841 struct ice_aqc_mdio read_mdio; 2842 struct ice_aqc_mdio write_mdio; 2843 struct ice_aqc_sff_eeprom read_write_sff_param; 2844 struct ice_aqc_set_port_id_led set_port_id_led; 2845 struct ice_aqc_get_port_options get_port_options; 2846 struct ice_aqc_set_port_option set_port_option; 2847 struct ice_aqc_get_sw_cfg get_sw_conf; 2848 struct ice_aqc_set_port_params set_port_params; 2849 struct ice_aqc_sw_rules sw_rules; 2850 struct ice_aqc_storm_cfg storm_conf; 2851 struct ice_aqc_get_topo get_topo; 2852 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 2853 struct ice_aqc_query_txsched_res query_sched_res; 2854 struct ice_aqc_query_node_to_root query_node_to_root; 2855 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd; 2856 struct ice_aqc_query_port_ets port_ets; 2857 struct ice_aqc_rl_profile rl_profile; 2858 struct ice_aqc_nvm nvm; 2859 struct ice_aqc_nvm_cfg nvm_cfg; 2860 struct ice_aqc_nvm_checksum nvm_checksum; 2861 struct ice_aqc_pf_vf_msg virt; 2862 struct ice_aqc_read_write_alt_direct read_write_alt_direct; 2863 struct ice_aqc_read_write_alt_indirect read_write_alt_indirect; 2864 struct ice_aqc_done_alt_write done_alt_write; 2865 struct ice_aqc_clear_port_alt_write clear_port_alt_write; 2866 struct ice_aqc_pfc_ignore pfc_ignore; 2867 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode; 2868 struct ice_aqc_set_dcb_params set_dcb_params; 2869 struct ice_aqc_lldp_get_mib lldp_get_mib; 2870 struct ice_aqc_lldp_set_mib_change lldp_set_event; 2871 struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv; 2872 struct ice_aqc_lldp_update_tlv lldp_update_tlv; 2873 struct ice_aqc_lldp_stop lldp_stop; 2874 struct ice_aqc_lldp_start lldp_start; 2875 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 2876 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 2877 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl; 2878 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 2879 struct ice_aqc_get_set_rss_key get_set_rss_key; 2880 struct ice_aqc_add_txqs add_txqs; 2881 struct ice_aqc_dis_txqs dis_txqs; 2882 struct ice_aqc_move_txqs move_txqs; 2883 struct ice_aqc_txqs_cleanup txqs_cleanup; 2884 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 2885 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 2886 struct ice_aqc_get_vsi_resp get_vsi_resp; 2887 struct ice_aqc_download_pkg download_pkg; 2888 struct ice_aqc_get_pkg_info_list get_pkg_info_list; 2889 struct ice_aqc_driver_shared_params drv_shared_params; 2890 struct ice_aqc_set_mac_lb set_mac_lb; 2891 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 2892 struct ice_aqc_get_res_alloc get_res; 2893 struct ice_aqc_get_allocd_res_desc get_res_desc; 2894 struct ice_aqc_set_mac_cfg set_mac_cfg; 2895 struct ice_aqc_set_event_mask set_event_mask; 2896 struct ice_aqc_get_link_status get_link_status; 2897 struct ice_aqc_event_lan_overflow lan_overflow; 2898 struct ice_aqc_get_link_topo get_link_topo; 2899 struct ice_aqc_set_health_status_config 2900 set_health_status_config; 2901 struct ice_aqc_get_supported_health_status_codes 2902 get_supported_health_status_codes; 2903 struct ice_aqc_get_health_status get_health_status; 2904 struct ice_aqc_clear_health_status clear_health_status; 2905 } params; 2906 }; 2907 2908 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 2909 #define ICE_AQ_LG_BUF 512 2910 2911 /* Flags sub-structure 2912 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 2913 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 2914 */ 2915 2916 /* command flags and offsets */ 2917 #define ICE_AQ_FLAG_DD_S 0 2918 #define ICE_AQ_FLAG_CMP_S 1 2919 #define ICE_AQ_FLAG_ERR_S 2 2920 #define ICE_AQ_FLAG_VFE_S 3 2921 #define ICE_AQ_FLAG_LB_S 9 2922 #define ICE_AQ_FLAG_RD_S 10 2923 #define ICE_AQ_FLAG_VFC_S 11 2924 #define ICE_AQ_FLAG_BUF_S 12 2925 #define ICE_AQ_FLAG_SI_S 13 2926 #define ICE_AQ_FLAG_EI_S 14 2927 #define ICE_AQ_FLAG_FE_S 15 2928 2929 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */ 2930 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */ 2931 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 2932 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */ 2933 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 2934 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 2935 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */ 2936 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 2937 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 2938 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */ 2939 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */ 2940 2941 /* error codes */ 2942 enum ice_aq_err { 2943 ICE_AQ_RC_OK = 0, /* Success */ 2944 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 2945 ICE_AQ_RC_ENOENT = 2, /* No such element */ 2946 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */ 2947 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */ 2948 ICE_AQ_RC_EIO = 5, /* I/O error */ 2949 ICE_AQ_RC_ENXIO = 6, /* No such resource */ 2950 ICE_AQ_RC_E2BIG = 7, /* Arg too long */ 2951 ICE_AQ_RC_EAGAIN = 8, /* Try again */ 2952 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 2953 ICE_AQ_RC_EACCES = 10, /* Permission denied */ 2954 ICE_AQ_RC_EFAULT = 11, /* Bad address */ 2955 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 2956 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 2957 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 2958 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 2959 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 2960 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 2961 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */ 2962 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 2963 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 2964 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 2965 ICE_AQ_RC_EFBIG = 22, /* File too big */ 2966 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */ 2967 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 2968 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 2969 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 2970 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 2971 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 2972 ICE_AQ_RC_EACCES_BMCU = 29, /* BMC Update in progress */ 2973 }; 2974 2975 /* Admin Queue command opcodes */ 2976 enum ice_adminq_opc { 2977 /* AQ commands */ 2978 ice_aqc_opc_get_ver = 0x0001, 2979 ice_aqc_opc_driver_ver = 0x0002, 2980 ice_aqc_opc_q_shutdown = 0x0003, 2981 ice_aqc_opc_get_exp_err = 0x0005, 2982 2983 /* resource ownership */ 2984 ice_aqc_opc_req_res = 0x0008, 2985 ice_aqc_opc_release_res = 0x0009, 2986 2987 /* device/function capabilities */ 2988 ice_aqc_opc_list_func_caps = 0x000A, 2989 ice_aqc_opc_list_dev_caps = 0x000B, 2990 2991 /* manage MAC address */ 2992 ice_aqc_opc_manage_mac_read = 0x0107, 2993 ice_aqc_opc_manage_mac_write = 0x0108, 2994 2995 /* PXE */ 2996 ice_aqc_opc_clear_pxe_mode = 0x0110, 2997 2998 ice_aqc_opc_config_no_drop_policy = 0x0112, 2999 3000 /* internal switch commands */ 3001 ice_aqc_opc_get_sw_cfg = 0x0200, 3002 ice_aqc_opc_set_port_params = 0x0203, 3003 3004 /* Alloc/Free/Get Resources */ 3005 ice_aqc_opc_get_res_alloc = 0x0204, 3006 ice_aqc_opc_alloc_res = 0x0208, 3007 ice_aqc_opc_free_res = 0x0209, 3008 ice_aqc_opc_get_allocd_res_desc = 0x020A, 3009 ice_aqc_opc_set_vlan_mode_parameters = 0x020C, 3010 ice_aqc_opc_get_vlan_mode_parameters = 0x020D, 3011 3012 /* VSI commands */ 3013 ice_aqc_opc_add_vsi = 0x0210, 3014 ice_aqc_opc_update_vsi = 0x0211, 3015 ice_aqc_opc_get_vsi_params = 0x0212, 3016 ice_aqc_opc_free_vsi = 0x0213, 3017 3018 /* Mirroring rules - add/update, delete */ 3019 ice_aqc_opc_add_update_mir_rule = 0x0260, 3020 ice_aqc_opc_del_mir_rule = 0x0261, 3021 3022 /* storm configuration */ 3023 ice_aqc_opc_set_storm_cfg = 0x0280, 3024 ice_aqc_opc_get_storm_cfg = 0x0281, 3025 3026 /* switch rules population commands */ 3027 ice_aqc_opc_add_sw_rules = 0x02A0, 3028 ice_aqc_opc_update_sw_rules = 0x02A1, 3029 ice_aqc_opc_remove_sw_rules = 0x02A2, 3030 ice_aqc_opc_get_sw_rules = 0x02A3, 3031 ice_aqc_opc_clear_pf_cfg = 0x02A4, 3032 3033 /* DCB commands */ 3034 ice_aqc_opc_pfc_ignore = 0x0301, 3035 ice_aqc_opc_query_pfc_mode = 0x0302, 3036 ice_aqc_opc_set_pfc_mode = 0x0303, 3037 ice_aqc_opc_set_dcb_params = 0x0306, 3038 3039 /* transmit scheduler commands */ 3040 ice_aqc_opc_get_dflt_topo = 0x0400, 3041 ice_aqc_opc_add_sched_elems = 0x0401, 3042 ice_aqc_opc_cfg_sched_elems = 0x0403, 3043 ice_aqc_opc_get_sched_elems = 0x0404, 3044 ice_aqc_opc_move_sched_elems = 0x0408, 3045 ice_aqc_opc_suspend_sched_elems = 0x0409, 3046 ice_aqc_opc_resume_sched_elems = 0x040A, 3047 ice_aqc_opc_query_port_ets = 0x040E, 3048 ice_aqc_opc_delete_sched_elems = 0x040F, 3049 ice_aqc_opc_add_rl_profiles = 0x0410, 3050 ice_aqc_opc_query_rl_profiles = 0x0411, 3051 ice_aqc_opc_query_sched_res = 0x0412, 3052 ice_aqc_opc_query_node_to_root = 0x0413, 3053 ice_aqc_opc_cfg_l2_node_cgd = 0x0414, 3054 ice_aqc_opc_remove_rl_profiles = 0x0415, 3055 3056 /* PHY commands */ 3057 ice_aqc_opc_get_phy_caps = 0x0600, 3058 ice_aqc_opc_set_phy_cfg = 0x0601, 3059 ice_aqc_opc_set_mac_cfg = 0x0603, 3060 ice_aqc_opc_restart_an = 0x0605, 3061 ice_aqc_opc_get_link_status = 0x0607, 3062 ice_aqc_opc_set_event_mask = 0x0613, 3063 ice_aqc_opc_set_mac_lb = 0x0620, 3064 ice_aqc_opc_dnl_get_status = 0x0680, 3065 ice_aqc_opc_dnl_run = 0x0681, 3066 ice_aqc_opc_dnl_call = 0x0682, 3067 ice_aqc_opc_dnl_read_sto = 0x0683, 3068 ice_aqc_opc_dnl_write_sto = 0x0684, 3069 ice_aqc_opc_dnl_set_breakpoints = 0x0686, 3070 ice_aqc_opc_dnl_read_log = 0x0687, 3071 ice_aqc_opc_get_link_topo = 0x06E0, 3072 ice_aqc_opc_get_link_topo_pin = 0x06E1, 3073 ice_aqc_opc_read_i2c = 0x06E2, 3074 ice_aqc_opc_write_i2c = 0x06E3, 3075 ice_aqc_opc_read_mdio = 0x06E4, 3076 ice_aqc_opc_write_mdio = 0x06E5, 3077 ice_aqc_opc_set_gpio_by_func = 0x06E6, 3078 ice_aqc_opc_get_gpio_by_func = 0x06E7, 3079 ice_aqc_opc_set_led = 0x06E8, 3080 ice_aqc_opc_set_port_id_led = 0x06E9, 3081 ice_aqc_opc_get_port_options = 0x06EA, 3082 ice_aqc_opc_set_port_option = 0x06EB, 3083 ice_aqc_opc_set_gpio = 0x06EC, 3084 ice_aqc_opc_get_gpio = 0x06ED, 3085 ice_aqc_opc_sff_eeprom = 0x06EE, 3086 ice_aqc_opc_sw_set_gpio = 0x06EF, 3087 ice_aqc_opc_sw_get_gpio = 0x06F0, 3088 ice_aqc_opc_program_topology_device_nvm = 0x06F2, 3089 ice_aqc_opc_read_topology_device_nvm = 0x06F3, 3090 3091 /* NVM commands */ 3092 ice_aqc_opc_nvm_read = 0x0701, 3093 ice_aqc_opc_nvm_erase = 0x0702, 3094 ice_aqc_opc_nvm_write = 0x0703, 3095 ice_aqc_opc_nvm_cfg_read = 0x0704, 3096 ice_aqc_opc_nvm_cfg_write = 0x0705, 3097 ice_aqc_opc_nvm_checksum = 0x0706, 3098 ice_aqc_opc_nvm_write_activate = 0x0707, 3099 ice_aqc_opc_nvm_sr_dump = 0x0707, 3100 ice_aqc_opc_nvm_save_factory_settings = 0x0708, 3101 ice_aqc_opc_nvm_update_empr = 0x0709, 3102 ice_aqc_opc_nvm_pkg_data = 0x070A, 3103 ice_aqc_opc_nvm_pass_component_tbl = 0x070B, 3104 3105 /* PF/VF mailbox commands */ 3106 ice_mbx_opc_send_msg_to_pf = 0x0801, 3107 ice_mbx_opc_send_msg_to_vf = 0x0802, 3108 /* Alternate Structure Commands */ 3109 ice_aqc_opc_write_alt_direct = 0x0900, 3110 ice_aqc_opc_write_alt_indirect = 0x0901, 3111 ice_aqc_opc_read_alt_direct = 0x0902, 3112 ice_aqc_opc_read_alt_indirect = 0x0903, 3113 ice_aqc_opc_done_alt_write = 0x0904, 3114 ice_aqc_opc_clear_port_alt_write = 0x0906, 3115 /* LLDP commands */ 3116 ice_aqc_opc_lldp_get_mib = 0x0A00, 3117 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 3118 ice_aqc_opc_lldp_add_tlv = 0x0A02, 3119 ice_aqc_opc_lldp_update_tlv = 0x0A03, 3120 ice_aqc_opc_lldp_delete_tlv = 0x0A04, 3121 ice_aqc_opc_lldp_stop = 0x0A05, 3122 ice_aqc_opc_lldp_start = 0x0A06, 3123 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 3124 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 3125 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 3126 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A, 3127 3128 /* RSS commands */ 3129 ice_aqc_opc_set_rss_key = 0x0B02, 3130 ice_aqc_opc_set_rss_lut = 0x0B03, 3131 ice_aqc_opc_get_rss_key = 0x0B04, 3132 ice_aqc_opc_get_rss_lut = 0x0B05, 3133 3134 /* Tx queue handling commands/events */ 3135 ice_aqc_opc_add_txqs = 0x0C30, 3136 ice_aqc_opc_dis_txqs = 0x0C31, 3137 ice_aqc_opc_txqs_cleanup = 0x0C31, 3138 ice_aqc_opc_move_recfg_txqs = 0x0C32, 3139 3140 /* package commands */ 3141 ice_aqc_opc_download_pkg = 0x0C40, 3142 ice_aqc_opc_upload_section = 0x0C41, 3143 ice_aqc_opc_update_pkg = 0x0C42, 3144 ice_aqc_opc_get_pkg_info_list = 0x0C43, 3145 3146 ice_aqc_opc_driver_shared_params = 0x0C90, 3147 3148 /* Standalone Commands/Events */ 3149 ice_aqc_opc_event_lan_overflow = 0x1001, 3150 3151 /* SystemDiagnostic commands */ 3152 ice_aqc_opc_set_health_status_config = 0xFF20, 3153 ice_aqc_opc_get_supported_health_status_codes = 0xFF21, 3154 ice_aqc_opc_get_health_status = 0xFF22, 3155 ice_aqc_opc_clear_health_status = 0xFF23, 3156 3157 /* FW Logging Commands */ 3158 ice_aqc_opc_fw_logs_config = 0xFF30, 3159 ice_aqc_opc_fw_logs_register = 0xFF31, 3160 ice_aqc_opc_fw_logs_query = 0xFF32, 3161 ice_aqc_opc_fw_logs_event = 0xFF33, 3162 ice_aqc_opc_fw_logs_get = 0xFF34, 3163 ice_aqc_opc_fw_logs_clear = 0xFF35 3164 }; 3165 3166 #endif /* _ICE_ADMINQ_CMD_H_ */ 3167