1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2023, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _ICE_ADMINQ_CMD_H_ 33 #define _ICE_ADMINQ_CMD_H_ 34 35 /* This header file defines the Admin Queue commands, error codes and 36 * descriptor format. It is shared between Firmware and Software. 37 */ 38 39 #include "ice_osdep.h" 40 #include "ice_defs.h" 41 #include "ice_bitops.h" 42 43 #define ICE_MAX_VSI 768 44 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 45 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 46 47 enum ice_aq_res_access_type { 48 ICE_RES_READ = 1, 49 ICE_RES_WRITE 50 }; 51 52 struct ice_aqc_generic { 53 __le32 param0; 54 __le32 param1; 55 __le32 addr_high; 56 __le32 addr_low; 57 }; 58 59 /* Get version (direct 0x0001) */ 60 struct ice_aqc_get_ver { 61 __le32 rom_ver; 62 __le32 fw_build; 63 u8 fw_branch; 64 u8 fw_major; 65 u8 fw_minor; 66 u8 fw_patch; 67 u8 api_branch; 68 u8 api_major; 69 u8 api_minor; 70 u8 api_patch; 71 }; 72 73 /* Send driver version (indirect 0x0002) */ 74 struct ice_aqc_driver_ver { 75 u8 major_ver; 76 u8 minor_ver; 77 u8 build_ver; 78 u8 subbuild_ver; 79 u8 reserved[4]; 80 __le32 addr_high; 81 __le32 addr_low; 82 }; 83 84 /* Queue Shutdown (direct 0x0003) */ 85 struct ice_aqc_q_shutdown { 86 u8 driver_unloading; 87 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 88 u8 reserved[15]; 89 }; 90 91 /* Get Expanded Error Code (0x0005, direct) */ 92 struct ice_aqc_get_exp_err { 93 __le32 reason; 94 #define ICE_AQC_EXPANDED_ERROR_NOT_PROVIDED 0xFFFFFFFF 95 __le32 identifier; 96 u8 rsvd[8]; 97 }; 98 99 /* Request resource ownership (direct 0x0008) 100 * Release resource ownership (direct 0x0009) 101 */ 102 struct ice_aqc_req_res { 103 __le16 res_id; 104 #define ICE_AQC_RES_ID_NVM 1 105 #define ICE_AQC_RES_ID_SDP 2 106 #define ICE_AQC_RES_ID_CHNG_LOCK 3 107 #define ICE_AQC_RES_ID_GLBL_LOCK 4 108 __le16 access_type; 109 #define ICE_AQC_RES_ACCESS_READ 1 110 #define ICE_AQC_RES_ACCESS_WRITE 2 111 112 /* Upon successful completion, FW writes this value and driver is 113 * expected to release resource before timeout. This value is provided 114 * in milliseconds. 115 */ 116 __le32 timeout; 117 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 118 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 119 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 120 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 121 /* For SDP: pin ID of the SDP */ 122 __le32 res_number; 123 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 124 __le16 status; 125 #define ICE_AQ_RES_GLBL_SUCCESS 0 126 #define ICE_AQ_RES_GLBL_IN_PROG 1 127 #define ICE_AQ_RES_GLBL_DONE 2 128 u8 reserved[2]; 129 }; 130 131 /* Get function capabilities (indirect 0x000A) 132 * Get device capabilities (indirect 0x000B) 133 */ 134 struct ice_aqc_list_caps { 135 u8 cmd_flags; 136 u8 pf_index; 137 u8 reserved[2]; 138 __le32 count; 139 __le32 addr_high; 140 __le32 addr_low; 141 }; 142 143 /* Device/Function buffer entry, repeated per reported capability */ 144 struct ice_aqc_list_caps_elem { 145 __le16 cap; 146 #define ICE_AQC_CAPS_SWITCHING_MODE 0x0001 147 #define ICE_AQC_CAPS_MANAGEABILITY_MODE 0x0002 148 #define ICE_AQC_CAPS_OS2BMC 0x0004 149 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 150 #define ICE_AQC_MAX_VALID_FUNCTIONS 0x8 151 #define ICE_AQC_CAPS_ALTERNATE_RAM 0x0006 152 #define ICE_AQC_CAPS_WOL_PROXY 0x0008 153 #define ICE_AQC_CAPS_SRIOV 0x0012 154 #define ICE_AQC_CAPS_VF 0x0013 155 #define ICE_AQC_CAPS_802_1QBG 0x0015 156 #define ICE_AQC_CAPS_802_1BR 0x0016 157 #define ICE_AQC_CAPS_VSI 0x0017 158 #define ICE_AQC_CAPS_DCB 0x0018 159 #define ICE_AQC_CAPS_RSVD 0x0021 160 #define ICE_AQC_CAPS_ISCSI 0x0022 161 #define ICE_AQC_CAPS_RSS 0x0040 162 #define ICE_AQC_CAPS_RXQS 0x0041 163 #define ICE_AQC_CAPS_TXQS 0x0042 164 #define ICE_AQC_CAPS_MSIX 0x0043 165 #define ICE_AQC_CAPS_MAX_MTU 0x0047 166 #define ICE_AQC_CAPS_CEM 0x00F2 167 #define ICE_AQC_CAPS_IWARP 0x0051 168 #define ICE_AQC_CAPS_LED 0x0061 169 #define ICE_AQC_CAPS_SDP 0x0062 170 #define ICE_AQC_CAPS_WR_CSR_PROT 0x0064 171 #define ICE_AQC_CAPS_LOGI_TO_PHYSI_PORT_MAP 0x0073 172 #define ICE_AQC_CAPS_SKU 0x0074 173 #define ICE_AQC_CAPS_PORT_MAP 0x0075 174 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 175 #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077 176 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 177 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0 0x0081 178 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1 0x0082 179 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2 0x0083 180 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG3 0x0084 181 #define ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE 0x0085 182 #define ICE_AQC_CAPS_NAC_TOPOLOGY 0x0087 183 #define ICE_AQC_CAPS_DYN_FLATTENING 0x0090 184 #define ICE_AQC_CAPS_ROCEV2_LAG 0x0092 185 186 u8 major_ver; 187 u8 minor_ver; 188 /* Number of resources described by this capability */ 189 __le32 number; 190 /* Only meaningful for some types of resources */ 191 __le32 logical_id; 192 /* Only meaningful for some types of resources */ 193 __le32 phys_id; 194 __le64 rsvd1; 195 __le64 rsvd2; 196 }; 197 198 /* Manage MAC address, read command - indirect (0x0107) 199 * This struct is also used for the response 200 */ 201 struct ice_aqc_manage_mac_read { 202 __le16 flags; /* Zeroed by device driver */ 203 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 204 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 205 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 206 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 207 #define ICE_AQC_MAN_MAC_MC_MAG_EN BIT(8) 208 #define ICE_AQC_MAN_MAC_WOL_PRESERVE_ON_PFR BIT(9) 209 #define ICE_AQC_MAN_MAC_READ_S 4 210 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 211 u8 rsvd[2]; 212 u8 num_addr; /* Used in response */ 213 u8 rsvd1[3]; 214 __le32 addr_high; 215 __le32 addr_low; 216 }; 217 218 /* Response buffer format for manage MAC read command */ 219 struct ice_aqc_manage_mac_read_resp { 220 u8 lport_num; 221 u8 addr_type; 222 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 223 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 224 u8 mac_addr[ETH_ALEN]; 225 }; 226 227 /* Manage MAC address, write command - direct (0x0108) */ 228 struct ice_aqc_manage_mac_write { 229 u8 rsvd; 230 u8 flags; 231 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 232 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 233 #define ICE_AQC_MAN_MAC_WR_S 6 234 #define ICE_AQC_MAN_MAC_WR_M MAKEMASK(3, ICE_AQC_MAN_MAC_WR_S) 235 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 236 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 237 /* byte stream in network order */ 238 u8 mac_addr[ETH_ALEN]; 239 __le32 addr_high; 240 __le32 addr_low; 241 }; 242 243 /* Clear PXE Command and response (direct 0x0110) */ 244 struct ice_aqc_clear_pxe { 245 u8 rx_cnt; 246 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 247 u8 reserved[15]; 248 }; 249 250 /* Configure No-Drop Policy Command (direct 0x0112) */ 251 struct ice_aqc_config_no_drop_policy { 252 u8 opts; 253 #define ICE_AQC_FORCE_NO_DROP BIT(0) 254 u8 rsvd[15]; 255 }; 256 257 /* Get switch configuration (0x0200) */ 258 struct ice_aqc_get_sw_cfg { 259 /* Reserved for command and copy of request flags for response */ 260 __le16 flags; 261 /* First desc in case of command and next_elem in case of response 262 * In case of response, if it is not zero, means all the configuration 263 * was not returned and new command shall be sent with this value in 264 * the 'first desc' field 265 */ 266 __le16 element; 267 /* Reserved for command, only used for response */ 268 __le16 num_elems; 269 __le16 rsvd; 270 __le32 addr_high; 271 __le32 addr_low; 272 }; 273 274 /* Each entry in the response buffer is of the following type: */ 275 struct ice_aqc_get_sw_cfg_resp_elem { 276 /* VSI/Port Number */ 277 __le16 vsi_port_num; 278 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 279 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 280 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 281 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 282 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 283 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 284 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 285 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 286 287 /* SWID VSI/Port belongs to */ 288 __le16 swid; 289 290 /* Bit 14..0 : PF/VF number VSI belongs to 291 * Bit 15 : VF indication bit 292 */ 293 __le16 pf_vf_num; 294 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 295 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 296 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 297 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 298 }; 299 300 /* Set Port parameters, (direct, 0x0203) */ 301 struct ice_aqc_set_port_params { 302 __le16 cmd_flags; 303 #define ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS BIT(0) 304 #define ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS BIT(1) 305 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2) 306 __le16 bad_frame_vsi; 307 #define ICE_AQC_SET_P_PARAMS_VSI_S 0 308 #define ICE_AQC_SET_P_PARAMS_VSI_M (0x3FF << ICE_AQC_SET_P_PARAMS_VSI_S) 309 #define ICE_AQC_SET_P_PARAMS_VSI_VALID BIT(15) 310 __le16 swid; 311 #define ICE_AQC_SET_P_PARAMS_SWID_S 0 312 #define ICE_AQC_SET_P_PARAMS_SWID_M (0xFF << ICE_AQC_SET_P_PARAMS_SWID_S) 313 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S 8 314 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_M \ 315 (0x3F << ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S) 316 #define ICE_AQC_SET_P_PARAMS_IS_LOGI_PORT BIT(14) 317 #define ICE_AQC_SET_P_PARAMS_SWID_VALID BIT(15) 318 u8 reserved[10]; 319 }; 320 321 /* These resource type defines are used for all switch resource 322 * commands where a resource type is required, such as: 323 * Get Resource Allocation command (indirect 0x0204) 324 * Allocate Resources command (indirect 0x0208) 325 * Free Resources command (indirect 0x0209) 326 * Get Allocated Resource Descriptors Command (indirect 0x020A) 327 */ 328 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00 329 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01 330 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02 331 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 332 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 333 #define ICE_AQC_RES_TYPE_RECIPE 0x05 334 #define ICE_AQC_RES_TYPE_PROFILE 0x06 335 #define ICE_AQC_RES_TYPE_SWID 0x07 336 #define ICE_AQC_RES_TYPE_VSI 0x08 337 #define ICE_AQC_RES_TYPE_FLU 0x09 338 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A 339 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B 340 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C 341 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20 342 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 343 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 344 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 345 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30 346 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48 347 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49 348 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50 349 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51 350 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 351 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 352 /* Resource types 0x62-67 are reserved for Hash profile builder */ 353 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68 354 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69 355 356 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7) 357 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 358 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 359 360 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 361 362 #define ICE_AQC_RES_TYPE_S 0 363 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 364 365 /* Get Resource Allocation command (indirect 0x0204) */ 366 struct ice_aqc_get_res_alloc { 367 __le16 resp_elem_num; /* Used in response, reserved in command */ 368 u8 reserved[6]; 369 __le32 addr_high; 370 __le32 addr_low; 371 }; 372 373 /* Get Resource Allocation Response Buffer per response */ 374 struct ice_aqc_get_res_resp_elem { 375 __le16 res_type; /* Types defined above cmd 0x0204 */ 376 __le16 total_capacity; /* Resources available to all PF's */ 377 __le16 total_function; /* Resources allocated for a PF */ 378 __le16 total_shared; /* Resources allocated as shared */ 379 __le16 total_free; /* Resources un-allocated/not reserved by any PF */ 380 }; 381 382 /* Allocate Resources command (indirect 0x0208) 383 * Free Resources command (indirect 0x0209) 384 */ 385 struct ice_aqc_alloc_free_res_cmd { 386 __le16 num_entries; /* Number of Resource entries */ 387 u8 reserved[6]; 388 __le32 addr_high; 389 __le32 addr_low; 390 }; 391 392 /* Resource descriptor */ 393 struct ice_aqc_res_elem { 394 union { 395 __le16 sw_resp; 396 __le16 flu_resp; 397 } e; 398 }; 399 400 /* Buffer for Allocate/Free Resources commands */ 401 struct ice_aqc_alloc_free_res_elem { 402 __le16 res_type; /* Types defined above cmd 0x0204 */ 403 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 404 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 405 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 406 __le16 num_elems; 407 struct ice_aqc_res_elem elem[STRUCT_HACK_VAR_LEN]; 408 }; 409 410 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */ 411 struct ice_aqc_get_allocd_res_desc { 412 union { 413 struct { 414 __le16 res; /* Types defined above cmd 0x0204 */ 415 __le16 first_desc; 416 __le32 reserved; 417 } cmd; 418 struct { 419 __le16 res; 420 __le16 next_desc; 421 __le16 num_desc; 422 __le16 reserved; 423 } resp; 424 } ops; 425 __le32 addr_high; 426 __le32 addr_low; 427 }; 428 429 /* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */ 430 struct ice_aqc_set_vlan_mode { 431 u8 reserved; 432 u8 l2tag_prio_tagging; 433 #define ICE_AQ_VLAN_PRIO_TAG_S 0 434 #define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S) 435 #define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0 436 #define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1 437 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2 438 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3 439 #define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4 440 #define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4 441 #define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7 442 u8 l2tag_reserved[64]; 443 u8 rdma_packet; 444 #define ICE_AQ_VLAN_RDMA_TAG_S 0 445 #define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S) 446 #define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10 447 #define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A 448 u8 rdma_reserved[2]; 449 u8 mng_vlan_prot_id; 450 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10 451 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11 452 u8 prot_id_reserved[30]; 453 }; 454 455 /* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */ 456 struct ice_aqc_get_vlan_mode { 457 u8 vlan_mode; 458 #define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0) 459 u8 l2tag_prio_tagging; 460 u8 reserved[98]; 461 }; 462 463 /* Add VSI (indirect 0x0210) 464 * Update VSI (indirect 0x0211) 465 * Get VSI (indirect 0x0212) 466 * Free VSI (indirect 0x0213) 467 */ 468 struct ice_aqc_add_get_update_free_vsi { 469 __le16 vsi_num; 470 #define ICE_AQ_VSI_NUM_S 0 471 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 472 #define ICE_AQ_VSI_IS_VALID BIT(15) 473 __le16 cmd_flags; 474 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 475 u8 vf_id; 476 u8 reserved; 477 __le16 vsi_flags; 478 #define ICE_AQ_VSI_TYPE_S 0 479 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 480 #define ICE_AQ_VSI_TYPE_VF 0x0 481 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 482 #define ICE_AQ_VSI_TYPE_PF 0x2 483 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 484 __le32 addr_high; 485 __le32 addr_low; 486 }; 487 488 /* Response descriptor for: 489 * Add VSI (indirect 0x0210) 490 * Update VSI (indirect 0x0211) 491 * Free VSI (indirect 0x0213) 492 */ 493 struct ice_aqc_add_update_free_vsi_resp { 494 __le16 vsi_num; 495 __le16 ext_status; 496 __le16 vsi_used; 497 __le16 vsi_free; 498 __le32 addr_high; 499 __le32 addr_low; 500 }; 501 502 struct ice_aqc_get_vsi_resp { 503 __le16 vsi_num; 504 u8 vf_id; 505 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values. 506 * These are found above in struct ice_aqc_add_get_update_free_vsi. 507 */ 508 u8 vsi_flags; 509 __le16 vsi_used; 510 __le16 vsi_free; 511 __le32 addr_high; 512 __le32 addr_low; 513 }; 514 515 struct ice_aqc_vsi_props { 516 __le16 valid_sections; 517 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 518 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 519 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 520 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 521 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 522 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 523 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 524 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 525 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 526 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 527 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 528 /* switch section */ 529 u8 sw_id; 530 u8 sw_flags; 531 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 532 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 533 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 534 u8 sw_flags2; 535 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 536 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 537 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 538 #define ICE_AQ_VSI_SW_FLAG_RX_PASS_PRUNE_ENA BIT(3) 539 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 540 u8 veb_stat_id; 541 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 542 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 543 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 544 /* security section */ 545 u8 sec_flags; 546 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 547 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 548 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 549 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 550 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 551 u8 sec_reserved; 552 /* VLAN section */ 553 __le16 port_based_inner_vlan; /* VLANS include priority bits */ 554 u8 inner_vlan_reserved[2]; 555 u8 inner_vlan_flags; 556 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0 557 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S) 558 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 559 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 560 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3 561 #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2) 562 #define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3 563 #define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 564 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH (0x0 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 565 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP (0x1 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 566 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR (0x2 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 567 #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 568 #define ICE_AQ_VSI_INNER_VLAN_BLOCK_TX_DESC BIT(5) 569 u8 inner_vlan_reserved2[3]; 570 /* ingress egress up sections */ 571 __le32 ingress_table; /* bitmap, 3 bits per up */ 572 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 573 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 574 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 575 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 576 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 577 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 578 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 579 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 580 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 581 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 582 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 583 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 584 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 585 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 586 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 587 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 588 __le32 egress_table; /* same defines as for ingress table */ 589 /* outer tags section */ 590 __le16 port_based_outer_vlan; 591 u8 outer_vlan_flags; 592 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0 593 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S) 594 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0 595 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1 596 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2 597 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3 598 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 599 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 600 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 601 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 602 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 603 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 604 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4) 605 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5 606 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) 607 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 608 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 609 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3 610 #define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7) 611 u8 outer_vlan_reserved; 612 /* queue mapping section */ 613 __le16 mapping_flags; 614 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 615 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 616 __le16 q_mapping[16]; 617 #define ICE_AQ_VSI_Q_S 0 618 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 619 __le16 tc_mapping[8]; 620 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 621 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 622 #define ICE_AQ_VSI_TC_Q_NUM_S 11 623 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 624 /* queueing option section */ 625 u8 q_opt_rss; 626 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 627 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 628 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 629 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 630 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 631 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 632 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 633 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 634 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 635 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 636 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 637 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 638 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 639 u8 q_opt_tc; 640 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 641 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 642 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 643 u8 q_opt_flags; 644 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 645 u8 q_opt_reserved[3]; 646 /* outer up section */ 647 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 648 /* section 10 */ 649 __le16 sect_10_reserved; 650 /* flow director section */ 651 __le16 fd_options; 652 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 653 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 654 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 655 __le16 max_fd_fltr_dedicated; 656 __le16 max_fd_fltr_shared; 657 __le16 fd_def_q; 658 #define ICE_AQ_VSI_FD_DEF_Q_S 0 659 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 660 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 661 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 662 __le16 fd_report_opt; 663 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 664 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 665 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 666 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 667 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 668 /* PASID section */ 669 __le32 pasid_id; 670 #define ICE_AQ_VSI_PASID_ID_S 0 671 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 672 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 673 u8 reserved[24]; 674 }; 675 676 /* Add/update mirror rule - direct (0x0260) */ 677 #define ICE_AQC_RULE_ID_VALID_S 7 678 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S) 679 #define ICE_AQC_RULE_ID_S 0 680 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S) 681 682 /* Following defines to be used while processing caller specified mirror list 683 * of VSI indexes. 684 */ 685 /* Action: Byte.bit (1.7) 686 * 0 = Remove VSI from mirror rule 687 * 1 = Add VSI to mirror rule 688 */ 689 #define ICE_AQC_RULE_ACT_S 15 690 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S) 691 /* Action: 1.2:0.0 = Mirrored VSI */ 692 #define ICE_AQC_RULE_MIRRORED_VSI_S 0 693 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S) 694 695 /* This is to be used by add/update mirror rule Admin Queue command. 696 * In case of add mirror rule - if rule ID is specified as 697 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool. 698 * If specified rule_id is valid, then it is used. If specified rule_id 699 * is in use then new mirroring rule is added. 700 */ 701 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF 702 703 struct ice_aqc_add_update_mir_rule { 704 __le16 rule_id; 705 706 __le16 rule_type; 707 #define ICE_AQC_RULE_TYPE_S 0 708 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S) 709 /* VPORT ingress/egress */ 710 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1 711 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2 712 /* Physical port ingress mirroring. 713 * All traffic received by this port 714 */ 715 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6 716 /* Physical port egress mirroring. All traffic sent by this port */ 717 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7 718 719 /* Number of mirrored entries. 720 * The values are in the command buffer 721 */ 722 __le16 num_entries; 723 724 /* Destination VSI */ 725 __le16 dest; 726 __le32 addr_high; 727 __le32 addr_low; 728 }; 729 730 /* Delete mirror rule - direct(0x0261) */ 731 struct ice_aqc_delete_mir_rule { 732 __le16 rule_id; 733 __le16 rsvd; 734 735 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of 736 * the PF allocated resources, otherwise it is returned to the 737 * shared pool 738 */ 739 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0 740 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S) 741 __le16 flags; 742 743 u8 reserved[10]; 744 }; 745 746 /* Set/Get storm config - (direct 0x0280, 0x0281) */ 747 /* This structure holds get storm configuration response and same structure 748 * is used to perform set_storm_cfg 749 */ 750 struct ice_aqc_storm_cfg { 751 __le32 bcast_thresh_size; 752 __le32 mcast_thresh_size; 753 /* Bit 18:0 - Traffic upper threshold size 754 * Bit 31:19 - Reserved 755 */ 756 #define ICE_AQ_THRESHOLD_S 0 757 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S) 758 759 __le32 storm_ctrl_ctrl; 760 /* Bit 0: MDIPW - Drop Multicast packets in previous window 761 * Bit 1: MDICW - Drop multicast packets in current window 762 * Bit 2: BDIPW - Drop broadcast packets in previous window 763 * Bit 3: BDICW - Drop broadcast packets in current window 764 */ 765 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0) 766 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1) 767 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2) 768 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3) 769 /* Bit 7:5 : Reserved */ 770 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The 771 * interval size for applying ingress broadcast or multicast storm 772 * control. 773 */ 774 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8 775 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \ 776 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S) 777 __le32 reserved; 778 }; 779 780 #define ICE_MAX_NUM_RECIPES 64 781 782 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 783 */ 784 struct ice_aqc_sw_rules { 785 /* ops: add switch rules, referring the number of rules. 786 * ops: update switch rules, referring the number of filters 787 * ops: remove switch rules, referring the entry index. 788 * ops: get switch rules, referring to the number of filters. 789 */ 790 __le16 num_rules_fltr_entry_index; 791 u8 reserved[6]; 792 __le32 addr_high; 793 __le32 addr_low; 794 }; 795 796 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 797 * This structures describes the lookup rules and associated actions. "index" 798 * is returned as part of a response to a successful Add command, and can be 799 * used to identify the rule for Update/Get/Remove commands. 800 */ 801 struct ice_sw_rule_lkup_rx_tx { 802 __le16 recipe_id; 803 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 804 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 805 __le16 src; 806 __le32 act; 807 808 /* Bit 0:1 - Action type */ 809 #define ICE_SINGLE_ACT_TYPE_S 0x00 810 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 811 812 /* Bit 2 - Loop back enable 813 * Bit 3 - LAN enable 814 */ 815 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 816 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 817 818 /* Action type = 0 - Forward to VSI or VSI list */ 819 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 820 821 #define ICE_SINGLE_ACT_VSI_ID_S 4 822 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 823 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 824 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 825 /* This bit needs to be set if action is forward to VSI list */ 826 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 827 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 828 #define ICE_SINGLE_ACT_DROP BIT(18) 829 830 /* Action type = 1 - Forward to Queue of Queue group */ 831 #define ICE_SINGLE_ACT_TO_Q 0x1 832 #define ICE_SINGLE_ACT_Q_INDEX_S 4 833 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 834 #define ICE_SINGLE_ACT_Q_REGION_S 15 835 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 836 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 837 838 /* Action type = 2 - Prune */ 839 #define ICE_SINGLE_ACT_PRUNE 0x2 840 #define ICE_SINGLE_ACT_EGRESS BIT(15) 841 #define ICE_SINGLE_ACT_INGRESS BIT(16) 842 #define ICE_SINGLE_ACT_PRUNET BIT(17) 843 /* Bit 18 should be set to 0 for this action */ 844 845 /* Action type = 2 - Pointer */ 846 #define ICE_SINGLE_ACT_PTR 0x2 847 #define ICE_SINGLE_ACT_PTR_VAL_S 4 848 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 849 /* Bit 17 should be set if pointed action includes a FWD cmd */ 850 #define ICE_SINGLE_ACT_PTR_HAS_FWD BIT(17) 851 /* Bit 18 should be set to 1 */ 852 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 853 854 /* Action type = 3 - Other actions. Last two bits 855 * are other action identifier 856 */ 857 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 858 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 859 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 860 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 861 862 /* Bit 17:18 - Defines other actions */ 863 /* Other action = 0 - Mirror VSI */ 864 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 865 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 866 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 867 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 868 869 /* Other action = 3 - Set Stat count */ 870 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 871 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 872 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 873 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 874 875 __le16 index; /* The index of the rule in the lookup table */ 876 /* Length and values of the header to be matched per recipe or 877 * lookup-type 878 */ 879 __le16 hdr_len; 880 u8 hdr[STRUCT_HACK_VAR_LEN]; 881 }; 882 883 /* Add/Update/Remove large action command/response entry 884 * "index" is returned as part of a response to a successful Add command, and 885 * can be used to identify the action for Update/Get/Remove commands. 886 */ 887 struct ice_sw_rule_lg_act { 888 __le16 index; /* Index in large action table */ 889 __le16 size; 890 /* Max number of large actions */ 891 #define ICE_MAX_LG_ACT 4 892 /* Bit 0:1 - Action type */ 893 #define ICE_LG_ACT_TYPE_S 0 894 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 895 896 /* Action type = 0 - Forward to VSI or VSI list */ 897 #define ICE_LG_ACT_VSI_FORWARDING 0 898 #define ICE_LG_ACT_VSI_ID_S 3 899 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 900 #define ICE_LG_ACT_VSI_LIST_ID_S 3 901 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 902 /* This bit needs to be set if action is forward to VSI list */ 903 #define ICE_LG_ACT_VSI_LIST BIT(13) 904 905 #define ICE_LG_ACT_VALID_BIT BIT(16) 906 907 /* Action type = 1 - Forward to Queue of Queue group */ 908 #define ICE_LG_ACT_TO_Q 0x1 909 #define ICE_LG_ACT_Q_INDEX_S 3 910 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 911 #define ICE_LG_ACT_Q_REGION_S 14 912 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 913 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 914 915 /* Action type = 2 - Prune */ 916 #define ICE_LG_ACT_PRUNE 0x2 917 #define ICE_LG_ACT_EGRESS BIT(14) 918 #define ICE_LG_ACT_INGRESS BIT(15) 919 #define ICE_LG_ACT_PRUNET BIT(16) 920 921 /* Action type = 3 - Mirror VSI */ 922 #define ICE_LG_OTHER_ACT_MIRROR 0x3 923 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 924 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 925 926 /* Action type = 5 - Generic Value */ 927 #define ICE_LG_ACT_GENERIC 0x5 928 #define ICE_LG_ACT_GENERIC_VALUE_S 3 929 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 930 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 931 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 932 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 933 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 934 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 935 936 /* Action = 7 - Set Stat count */ 937 #define ICE_LG_ACT_STAT_COUNT 0x7 938 #define ICE_LG_ACT_STAT_COUNT_S 3 939 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 940 __le32 act[STRUCT_HACK_VAR_LEN]; /* array of size for actions */ 941 }; 942 943 /* Add/Update/Remove VSI list command/response entry 944 * "index" is returned as part of a response to a successful Add command, and 945 * can be used to identify the VSI list for Update/Get/Remove commands. 946 */ 947 struct ice_sw_rule_vsi_list { 948 __le16 index; /* Index of VSI/Prune list */ 949 __le16 number_vsi; 950 __le16 vsi[STRUCT_HACK_VAR_LEN]; /* Array of number_vsi VSI numbers */ 951 }; 952 953 #pragma pack(1) 954 /* Query VSI list command/response entry */ 955 struct ice_sw_rule_vsi_list_query { 956 __le16 index; 957 ice_declare_bitmap(vsi_list, ICE_MAX_VSI); 958 }; 959 #pragma pack() 960 961 #pragma pack(1) 962 /* Add switch rule response: 963 * Content of return buffer is same as the input buffer. The status field and 964 * LUT index are updated as part of the response 965 */ 966 struct ice_aqc_sw_rules_elem { 967 __le16 type; /* Switch rule type, one of T_... */ 968 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 969 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 970 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 971 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 972 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 973 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 974 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 975 __le16 status; 976 union { 977 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 978 struct ice_sw_rule_lg_act lg_act; 979 struct ice_sw_rule_vsi_list vsi_list; 980 struct ice_sw_rule_vsi_list_query vsi_list_query; 981 } pdata; 982 }; 983 984 #pragma pack() 985 986 /* PFC Ignore (direct 0x0301) 987 * The command and response use the same descriptor structure 988 */ 989 struct ice_aqc_pfc_ignore { 990 u8 tc_bitmap; 991 u8 cmd_flags; /* unused in response */ 992 #define ICE_AQC_PFC_IGNORE_SET BIT(7) 993 #define ICE_AQC_PFC_IGNORE_CLEAR 0 994 u8 reserved[14]; 995 }; 996 997 /* Set PFC Mode (direct 0x0303) 998 * Query PFC Mode (direct 0x0302) 999 */ 1000 struct ice_aqc_set_query_pfc_mode { 1001 u8 pfc_mode; 1002 /* For Set Command response, reserved in all other cases */ 1003 #define ICE_AQC_PFC_NOT_CONFIGURED 0 1004 /* For Query Command response, reserved in all other cases */ 1005 #define ICE_AQC_DCB_DIS 0 1006 #define ICE_AQC_PFC_VLAN_BASED_PFC 1 1007 #define ICE_AQC_PFC_DSCP_BASED_PFC 2 1008 u8 rsvd[15]; 1009 }; 1010 1011 /* Set DCB Parameters (direct 0x0306) */ 1012 struct ice_aqc_set_dcb_params { 1013 u8 cmd_flags; /* unused in response */ 1014 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0) 1015 #define ICE_AQC_PERSIST_DCB_CFG BIT(1) 1016 u8 valid_flags; /* unused in response */ 1017 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0) 1018 #define ICE_AQC_PERSIST_DCB_CFG_VALID BIT(1) 1019 u8 rsvd[14]; 1020 }; 1021 1022 /* Get Default Topology (indirect 0x0400) */ 1023 struct ice_aqc_get_topo { 1024 u8 port_num; 1025 u8 num_branches; 1026 __le16 reserved1; 1027 __le32 reserved2; 1028 __le32 addr_high; 1029 __le32 addr_low; 1030 }; 1031 1032 /* Get/Set Tx Topology (indirect 0x0418/0x0417) */ 1033 struct ice_aqc_get_set_tx_topo { 1034 u8 set_flags; 1035 #define ICE_AQC_TX_TOPO_FLAGS_CORRER BIT(0) 1036 #define ICE_AQC_TX_TOPO_FLAGS_SRC_RAM BIT(1) 1037 #define ICE_AQC_TX_TOPO_FLAGS_SET_PSM BIT(2) 1038 #define ICE_AQC_TX_TOPO_FLAGS_LOAD_NEW BIT(4) 1039 #define ICE_AQC_TX_TOPO_FLAGS_ISSUED BIT(5) 1040 u8 get_flags; 1041 #define ICE_AQC_TX_TOPO_GET_NO_UPDATE 0 1042 #define ICE_AQC_TX_TOPO_GET_PSM 1 1043 #define ICE_AQC_TX_TOPO_GET_RAM 2 1044 __le16 reserved1; 1045 __le32 reserved2; 1046 __le32 addr_high; 1047 __le32 addr_low; 1048 }; 1049 1050 /* Update TSE (indirect 0x0403) 1051 * Get TSE (indirect 0x0404) 1052 * Add TSE (indirect 0x0401) 1053 * Delete TSE (indirect 0x040F) 1054 * Move TSE (indirect 0x0408) 1055 * Suspend Nodes (indirect 0x0409) 1056 * Resume Nodes (indirect 0x040A) 1057 */ 1058 struct ice_aqc_sched_elem_cmd { 1059 __le16 num_elem_req; /* Used by commands */ 1060 __le16 num_elem_resp; /* Used by responses */ 1061 __le32 reserved; 1062 __le32 addr_high; 1063 __le32 addr_low; 1064 }; 1065 1066 struct ice_aqc_txsched_move_grp_info_hdr { 1067 __le32 src_parent_teid; 1068 __le32 dest_parent_teid; 1069 __le16 num_elems; 1070 u8 flags; 1071 u8 reserved; 1072 }; 1073 1074 struct ice_aqc_move_elem { 1075 struct ice_aqc_txsched_move_grp_info_hdr hdr; 1076 __le32 teid[STRUCT_HACK_VAR_LEN]; 1077 }; 1078 1079 struct ice_aqc_elem_info_bw { 1080 __le16 bw_profile_idx; 1081 __le16 bw_alloc; 1082 }; 1083 1084 struct ice_aqc_txsched_elem { 1085 u8 elem_type; /* Special field, reserved for some aq calls */ 1086 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 1087 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 1088 #define ICE_AQC_ELEM_TYPE_TC 0x2 1089 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 1090 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 1091 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 1092 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 1093 u8 valid_sections; 1094 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 1095 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 1096 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 1097 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 1098 u8 generic; 1099 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 1100 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 1101 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 1102 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 1103 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 1104 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 1105 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 1106 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 1107 u8 flags; /* Special field, reserved for some aq calls */ 1108 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 1109 struct ice_aqc_elem_info_bw cir_bw; 1110 struct ice_aqc_elem_info_bw eir_bw; 1111 __le16 srl_id; 1112 __le16 reserved2; 1113 }; 1114 1115 struct ice_aqc_txsched_elem_data { 1116 __le32 parent_teid; 1117 __le32 node_teid; 1118 struct ice_aqc_txsched_elem data; 1119 }; 1120 1121 struct ice_aqc_txsched_topo_grp_info_hdr { 1122 __le32 parent_teid; 1123 __le16 num_elems; 1124 __le16 reserved2; 1125 }; 1126 1127 struct ice_aqc_add_elem { 1128 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1129 struct ice_aqc_txsched_elem_data generic[STRUCT_HACK_VAR_LEN]; 1130 }; 1131 1132 struct ice_aqc_get_topo_elem { 1133 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1134 struct ice_aqc_txsched_elem_data 1135 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1136 }; 1137 1138 struct ice_aqc_delete_elem { 1139 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1140 __le32 teid[STRUCT_HACK_VAR_LEN]; 1141 }; 1142 1143 /* Query Port ETS (indirect 0x040E) 1144 * 1145 * This indirect command is used to query port TC node configuration. 1146 */ 1147 struct ice_aqc_query_port_ets { 1148 __le32 port_teid; 1149 __le32 reserved; 1150 __le32 addr_high; 1151 __le32 addr_low; 1152 }; 1153 1154 struct ice_aqc_port_ets_elem { 1155 u8 tc_valid_bits; 1156 u8 reserved[3]; 1157 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 1158 __le32 up2tc; 1159 u8 tc_bw_share[8]; 1160 __le32 port_eir_prof_id; 1161 __le32 port_cir_prof_id; 1162 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 1163 __le32 tc_node_prio; 1164 #define ICE_TC_NODE_PRIO_S 0x4 1165 u8 reserved1[4]; 1166 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 1167 }; 1168 1169 /* Rate limiting profile for 1170 * Add RL profile (indirect 0x0410) 1171 * Query RL profile (indirect 0x0411) 1172 * Remove RL profile (indirect 0x0415) 1173 * These indirect commands acts on single or multiple 1174 * RL profiles with specified data. 1175 */ 1176 struct ice_aqc_rl_profile { 1177 __le16 num_profiles; 1178 __le16 num_processed; /* Only for response. Reserved in Command. */ 1179 u8 reserved[4]; 1180 __le32 addr_high; 1181 __le32 addr_low; 1182 }; 1183 1184 struct ice_aqc_rl_profile_elem { 1185 u8 level; 1186 u8 flags; 1187 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 1188 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 1189 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 1190 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 1191 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 1192 /* The following flag is used for Query RL Profile Data */ 1193 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 1194 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 1195 1196 __le16 profile_id; 1197 __le16 max_burst_size; 1198 __le16 rl_multiply; 1199 __le16 wake_up_calc; 1200 __le16 rl_encode; 1201 }; 1202 1203 /* Config Node Attributes (indirect 0x0419) 1204 * Query Node Attributes (indirect 0x041A) 1205 */ 1206 struct ice_aqc_node_attr { 1207 __le16 num_entries; /* Number of attributes structures in the buffer */ 1208 u8 reserved[6]; 1209 __le32 addr_high; 1210 __le32 addr_low; 1211 }; 1212 1213 struct ice_aqc_node_attr_elem { 1214 __le32 node_teid; 1215 __le16 max_children; 1216 __le16 children_level; 1217 }; 1218 1219 /* Configure L2 Node CGD (indirect 0x0414) 1220 * This indirect command allows configuring a congestion domain for given L2 1221 * node TEIDs in the scheduler topology. 1222 */ 1223 struct ice_aqc_cfg_l2_node_cgd { 1224 __le16 num_l2_nodes; 1225 u8 reserved[6]; 1226 __le32 addr_high; 1227 __le32 addr_low; 1228 }; 1229 1230 struct ice_aqc_cfg_l2_node_cgd_elem { 1231 __le32 node_teid; 1232 u8 cgd; 1233 u8 reserved[3]; 1234 }; 1235 1236 /* Query Scheduler Resource Allocation (indirect 0x0412) 1237 * This indirect command retrieves the scheduler resources allocated by 1238 * EMP Firmware to the given PF. 1239 */ 1240 struct ice_aqc_query_txsched_res { 1241 u8 reserved[8]; 1242 __le32 addr_high; 1243 __le32 addr_low; 1244 }; 1245 1246 struct ice_aqc_generic_sched_props { 1247 __le16 phys_levels; 1248 __le16 logical_levels; 1249 u8 flattening_bitmap; 1250 u8 max_device_cgds; 1251 u8 max_pf_cgds; 1252 u8 rsvd0; 1253 __le16 rdma_qsets; 1254 u8 rsvd1[22]; 1255 }; 1256 1257 struct ice_aqc_layer_props { 1258 u8 logical_layer; 1259 u8 chunk_size; 1260 __le16 max_device_nodes; 1261 __le16 max_pf_nodes; 1262 u8 rsvd0[4]; 1263 __le16 max_sibl_grp_sz; 1264 __le16 max_cir_rl_profiles; 1265 __le16 max_eir_rl_profiles; 1266 __le16 max_srl_profiles; 1267 u8 rsvd1[14]; 1268 }; 1269 1270 struct ice_aqc_query_txsched_res_resp { 1271 struct ice_aqc_generic_sched_props sched_props; 1272 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1273 }; 1274 1275 /* Query Node to Root Topology (indirect 0x0413) 1276 * This command uses ice_aqc_get_elem as its data buffer. 1277 */ 1278 struct ice_aqc_query_node_to_root { 1279 __le32 teid; 1280 __le32 num_nodes; /* Response only */ 1281 __le32 addr_high; 1282 __le32 addr_low; 1283 }; 1284 1285 /* Get PHY capabilities (indirect 0x0600) */ 1286 struct ice_aqc_get_phy_caps { 1287 u8 lport_num; 1288 u8 reserved; 1289 __le16 param0; 1290 /* 18.0 - Report qualified modules */ 1291 #define ICE_AQC_GET_PHY_RQM BIT(0) 1292 /* 18.1 - 18.3 : Report mode 1293 * 000b - Report topology capabilities, without media 1294 * 001b - Report topology capabilities, with media 1295 * 010b - Report Active configuration 1296 * 011b - Report PHY Type and FEC mode capabilities 1297 * 100b - Report Default capabilities 1298 */ 1299 #define ICE_AQC_REPORT_MODE_S 1 1300 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S) 1301 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0 1302 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1) 1303 #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2) 1304 #define ICE_AQC_REPORT_DFLT_CFG BIT(3) 1305 __le32 reserved1; 1306 __le32 addr_high; 1307 __le32 addr_low; 1308 }; 1309 1310 /* This is #define of PHY type (Extended): 1311 * The first set of defines is for phy_type_low. 1312 */ 1313 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 1314 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 1315 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 1316 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 1317 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 1318 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 1319 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 1320 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 1321 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 1322 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 1323 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 1324 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 1325 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 1326 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 1327 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 1328 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 1329 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 1330 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 1331 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 1332 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 1333 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 1334 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 1335 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 1336 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 1337 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 1338 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 1339 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 1340 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 1341 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 1342 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 1343 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 1344 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 1345 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 1346 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 1347 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 1348 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 1349 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 1350 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 1351 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 1352 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 1353 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 1354 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 1355 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 1356 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 1357 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 1358 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 1359 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 1360 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 1361 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 1362 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 1363 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 1364 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 1365 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 1366 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 1367 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 1368 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 1369 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 1370 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 1371 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 1372 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 1373 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 1374 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 1375 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 1376 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 1377 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 1378 /* The second set of defines is for phy_type_high. */ 1379 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 1380 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 1381 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 1382 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 1383 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 1384 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 4 1385 1386 struct ice_aqc_get_phy_caps_data { 1387 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1388 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1389 u8 caps; 1390 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 1391 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 1392 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 1393 #define ICE_AQC_PHY_EN_LINK BIT(3) 1394 #define ICE_AQC_PHY_AN_MODE BIT(4) 1395 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5) 1396 #define ICE_AQC_PHY_EN_LESM BIT(6) 1397 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 1398 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0) 1399 u8 low_power_ctrl_an; 1400 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 1401 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1) 1402 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2) 1403 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3) 1404 __le16 eee_cap; 1405 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1406 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1407 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1408 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1409 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1410 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1411 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1412 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7) 1413 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8) 1414 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9) 1415 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10) 1416 __le16 eeer_value; 1417 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1418 u8 phy_fw_ver[8]; 1419 u8 link_fec_options; 1420 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1421 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1422 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1423 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1424 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1425 #define ICE_AQC_PHY_FEC_DIS BIT(5) 1426 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1427 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1428 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0) 1429 u8 module_compliance_enforcement; 1430 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 1431 u8 extended_compliance_code; 1432 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1433 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1434 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1435 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1436 #define ICE_AQC_MOD_TYPE_IDENT 1 1437 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1438 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1439 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1440 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1441 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1442 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1443 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1444 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1445 u8 qualified_module_count; 1446 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1447 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1448 struct { 1449 u8 v_oui[3]; 1450 u8 rsvd3; 1451 u8 v_part[16]; 1452 __le32 v_rev; 1453 __le64 rsvd4; 1454 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1455 }; 1456 1457 /* Set PHY capabilities (direct 0x0601) 1458 * NOTE: This command must be followed by setup link and restart auto-neg 1459 */ 1460 struct ice_aqc_set_phy_cfg { 1461 u8 lport_num; 1462 u8 reserved[7]; 1463 __le32 addr_high; 1464 __le32 addr_low; 1465 }; 1466 1467 /* Set PHY config command data structure */ 1468 struct ice_aqc_set_phy_cfg_data { 1469 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1470 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1471 u8 caps; 1472 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0) 1473 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1474 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1475 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1476 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1477 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1478 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1479 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1480 u8 low_power_ctrl_an; 1481 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1482 __le16 eeer_value; 1483 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1484 u8 module_compliance_enforcement; 1485 }; 1486 1487 /* Set MAC Config command data structure (direct 0x0603) */ 1488 struct ice_aqc_set_mac_cfg { 1489 __le16 max_frame_size; 1490 u8 params; 1491 #define ICE_AQ_SET_MAC_PACE_S 3 1492 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1493 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1494 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1495 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1496 u8 tx_tmr_priority; 1497 __le16 tx_tmr_value; 1498 __le16 fc_refresh_threshold; 1499 u8 drop_opts; 1500 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1501 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1502 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1503 u8 reserved[7]; 1504 }; 1505 1506 /* Restart AN command data structure (direct 0x0605) 1507 * Also used for response, with only the lport_num field present. 1508 */ 1509 struct ice_aqc_restart_an { 1510 u8 lport_num; 1511 u8 reserved; 1512 u8 cmd_flags; 1513 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1514 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1515 u8 reserved2[13]; 1516 }; 1517 1518 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1519 struct ice_aqc_get_link_status { 1520 u8 lport_num; 1521 u8 reserved; 1522 __le16 cmd_flags; 1523 #define ICE_AQ_LSE_M 0x3 1524 #define ICE_AQ_LSE_NOP 0x0 1525 #define ICE_AQ_LSE_DIS 0x2 1526 #define ICE_AQ_LSE_ENA 0x3 1527 /* only response uses this flag */ 1528 #define ICE_AQ_LSE_IS_ENABLED 0x1 1529 __le32 reserved2; 1530 __le32 addr_high; 1531 __le32 addr_low; 1532 }; 1533 1534 enum ice_get_link_status_data_version { 1535 ICE_GET_LINK_STATUS_DATA_V1 = 1, 1536 }; 1537 1538 #define ICE_GET_LINK_STATUS_DATALEN_V1 32 1539 1540 /* Get link status response data structure, also used for Link Status Event */ 1541 struct ice_aqc_get_link_status_data { 1542 u8 topo_media_conflict; 1543 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1544 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1545 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1546 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1547 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1548 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1549 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1550 u8 link_cfg_err; 1551 #define ICE_AQ_LINK_CFG_ERR BIT(0) 1552 #define ICE_AQ_LINK_ACT_PORT_OPT_INVAL BIT(2) 1553 #define ICE_AQ_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3) 1554 #define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR BIT(4) 1555 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5) 1556 #define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6) 1557 #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7) 1558 u8 link_info; 1559 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1560 #define ICE_AQ_LINK_FAULT BIT(1) 1561 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1562 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1563 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1564 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1565 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1566 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1567 u8 an_info; 1568 #define ICE_AQ_AN_COMPLETED BIT(0) 1569 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1570 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1571 #define ICE_AQ_FEC_EN BIT(3) 1572 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1573 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1574 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1575 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1576 u8 ext_info; 1577 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1578 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1579 /* Port Tx Suspended */ 1580 #define ICE_AQ_LINK_TX_S 2 1581 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1582 #define ICE_AQ_LINK_TX_ACTIVE 0 1583 #define ICE_AQ_LINK_TX_DRAINED 1 1584 #define ICE_AQ_LINK_TX_FLUSHED 3 1585 u8 lb_status; 1586 #define ICE_AQ_LINK_LB_PHY_LCL BIT(0) 1587 #define ICE_AQ_LINK_LB_PHY_RMT BIT(1) 1588 #define ICE_AQ_LINK_LB_MAC_LCL BIT(2) 1589 #define ICE_AQ_LINK_LB_PHY_IDX_S 3 1590 #define ICE_AQ_LINK_LB_PHY_IDX_M (0x7 << ICE_AQ_LB_PHY_IDX_S) 1591 __le16 max_frame_size; 1592 u8 cfg; 1593 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1594 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1595 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1596 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0) 1597 /* Pacing Config */ 1598 #define ICE_AQ_CFG_PACING_S 3 1599 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1600 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1601 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1602 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1603 /* External Device Power Ability */ 1604 u8 power_desc; 1605 #define ICE_AQ_PWR_CLASS_M 0x3F 1606 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1607 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1608 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1609 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1610 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1611 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1612 __le16 link_speed; 1613 #define ICE_AQ_LINK_SPEED_M 0x7FF 1614 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1615 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1616 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1617 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1618 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1619 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1620 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1621 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1622 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1623 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1624 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1625 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1626 __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1627 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1628 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1629 }; 1630 1631 /* Set event mask command (direct 0x0613) */ 1632 struct ice_aqc_set_event_mask { 1633 u8 lport_num; 1634 u8 reserved[7]; 1635 __le16 event_mask; 1636 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1637 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1638 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1639 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1640 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1641 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1642 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1643 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1644 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1645 #define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10) 1646 #define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11) 1647 #define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12) 1648 u8 reserved1[6]; 1649 }; 1650 1651 /* Set PHY Loopback command (direct 0x0619) */ 1652 struct ice_aqc_set_phy_lb { 1653 u8 lport_num; 1654 u8 lport_num_valid; 1655 #define ICE_AQ_PHY_LB_PORT_NUM_VALID BIT(0) 1656 u8 phy_index; 1657 u8 lb_mode; 1658 #define ICE_AQ_PHY_LB_EN BIT(0) 1659 #define ICE_AQ_PHY_LB_TYPE_M BIT(1) 1660 #define ICE_AQ_PHY_LB_TYPE_LOCAL 0 1661 #define ICE_AQ_PHY_LB_TYPE_REMOTE ICE_AQ_PHY_LB_TYPE_M 1662 #define ICE_AQ_PHY_LB_LEVEL_M BIT(2) 1663 #define ICE_AQ_PHY_LB_LEVEL_PMD 0 1664 #define ICE_AQ_PHY_LB_LEVEL_PCS ICE_AQ_PHY_LB_LEVEL_M 1665 u8 reserved2[12]; 1666 }; 1667 1668 /* Set MAC Loopback command (direct 0x0620) */ 1669 struct ice_aqc_set_mac_lb { 1670 u8 lb_mode; 1671 #define ICE_AQ_MAC_LB_EN BIT(0) 1672 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1673 u8 reserved[15]; 1674 }; 1675 1676 /* DNL Get Status command (indirect 0x0680) 1677 * Structure used for the response, the command uses the generic 1678 * ice_aqc_generic struct to pass a buffer address to the FW. 1679 */ 1680 struct ice_aqc_dnl_get_status { 1681 u8 ctx; 1682 u8 status; 1683 #define ICE_AQ_DNL_STATUS_IDLE 0x0 1684 #define ICE_AQ_DNL_STATUS_RESERVED 0x1 1685 #define ICE_AQ_DNL_STATUS_STOPPED 0x2 1686 #define ICE_AQ_DNL_STATUS_FATAL 0x3 /* Fatal DNL engine error */ 1687 #define ICE_AQ_DNL_SRC_S 3 1688 #define ICE_AQ_DNL_SRC_M (0x3 << ICE_AQ_DNL_SRC_S) 1689 #define ICE_AQ_DNL_SRC_NVM (0x0 << ICE_AQ_DNL_SRC_S) 1690 #define ICE_AQ_DNL_SRC_NVM_SCRATCH (0x1 << ICE_AQ_DNL_SRC_S) 1691 u8 stack_ptr; 1692 #define ICE_AQ_DNL_ST_PTR_S 0x0 1693 #define ICE_AQ_DNL_ST_PTR_M (0x7 << ICE_AQ_DNL_ST_PTR_S) 1694 u8 engine_flags; 1695 #define ICE_AQ_DNL_FLAGS_ERROR BIT(2) 1696 #define ICE_AQ_DNL_FLAGS_NEGATIVE BIT(3) 1697 #define ICE_AQ_DNL_FLAGS_OVERFLOW BIT(4) 1698 #define ICE_AQ_DNL_FLAGS_ZERO BIT(5) 1699 #define ICE_AQ_DNL_FLAGS_CARRY BIT(6) 1700 #define ICE_AQ_DNL_FLAGS_JUMP BIT(7) 1701 __le16 pc; 1702 __le16 activity_id; 1703 __le32 addr_high; 1704 __le32 addr_low; 1705 }; 1706 1707 struct ice_aqc_dnl_get_status_data { 1708 __le16 activity_err_code; 1709 __le16 act_err_code; 1710 #define ICE_AQ_DNL_ACT_ERR_SUCCESS 0x0000 /* no error */ 1711 #define ICE_AQ_DNL_ACT_ERR_PARSE 0x8001 /* NVM parse error */ 1712 #define ICE_AQ_DNL_ACT_ERR_UNSUPPORTED 0x8002 /* unsupported action */ 1713 #define ICE_AQ_DNL_ACT_ERR_NOT_FOUND 0x8003 /* activity not found */ 1714 #define ICE_AQ_DNL_ACT_ERR_BAD_JUMP 0x8004 /* an illegal jump */ 1715 #define ICE_AQ_DNL_ACT_ERR_PSTO_OVER 0x8005 /* persistent store overflow */ 1716 #define ICE_AQ_DNL_ACT_ERR_ST_OVERFLOW 0x8006 /* stack overflow */ 1717 #define ICE_AQ_DNL_ACT_ERR_TIMEOUT 0x8007 /* activity timeout */ 1718 #define ICE_AQ_DNL_ACT_ERR_BREAK 0x0008 /* stopped at breakpoint */ 1719 #define ICE_AQ_DNL_ACT_ERR_INVAL_ARG 0x0101 /* invalid action argument */ 1720 __le32 execution_time; /* in nanoseconds */ 1721 __le16 lib_ver; 1722 u8 psto_local_sz; 1723 u8 psto_global_sz; 1724 u8 stack_sz; 1725 #define ICE_AQ_DNL_STACK_SZ_S 0 1726 #define ICE_AQ_DNL_STACK_SZ_M (0xF << ICE_AQ_DNL_STACK_SZ_S) 1727 u8 port_count; 1728 #define ICE_AQ_DNL_PORT_CNT_S 0 1729 #define ICE_AQ_DNL_PORT_CNT_M (0x1F << ICE_AQ_DNL_PORT_CNT_S) 1730 __le16 act_cache_cntr; 1731 u32 i2c_clk_cntr; 1732 u32 mdio_clk_cntr; 1733 u32 sb_iosf_clk_cntr; 1734 }; 1735 1736 /* DNL run command (direct 0x0681) */ 1737 struct ice_aqc_dnl_run_command { 1738 u8 reserved0; 1739 u8 command; 1740 #define ICE_AQ_DNL_CMD_S 0 1741 #define ICE_AQ_DNL_CMD_M (0x7 << ICE_AQ_DNL_CMD_S) 1742 #define ICE_AQ_DNL_CMD_RESET 0x0 1743 #define ICE_AQ_DNL_CMD_RUN 0x1 1744 #define ICE_AQ_DNL_CMD_STEP 0x3 1745 #define ICE_AQ_DNL_CMD_ABORT 0x4 1746 #define ICE_AQ_DNL_CMD_SET_PC 0x7 1747 #define ICE_AQ_DNL_CMD_SRC_S 3 1748 #define ICE_AQ_DNL_CMD_SRC_M (0x3 << ICE_AQ_DNL_CMD_SRC_S) 1749 #define ICE_AQ_DNL_CMD_SRC_DNL 0x0 1750 #define ICE_AQ_DNL_CMD_SRC_SCRATCH 0x1 1751 __le16 new_pc; 1752 u8 reserved1[12]; 1753 }; 1754 1755 /* DNL call command (indirect 0x0682) 1756 * Struct is used for both command and response 1757 */ 1758 struct ice_aqc_dnl_call_command { 1759 u8 ctx; /* Used in command, reserved in response */ 1760 u8 reserved; 1761 __le16 activity_id; 1762 __le32 reserved1; 1763 __le32 addr_high; 1764 __le32 addr_low; 1765 }; 1766 1767 /* DNL call command/response buffer (indirect 0x0682) */ 1768 struct ice_aqc_dnl_call { 1769 __le32 stores[4]; 1770 }; 1771 1772 /* Used for both commands: 1773 * DNL read sto command (indirect 0x0683) 1774 * DNL write sto command (indirect 0x0684) 1775 */ 1776 struct ice_aqc_dnl_read_write_command { 1777 u8 ctx; 1778 u8 sto_sel; /* STORE select */ 1779 #define ICE_AQC_DNL_STORE_SELECT_STORE 0x0 1780 #define ICE_AQC_DNL_STORE_SELECT_PSTO 0x1 1781 #define ICE_AQC_DNL_STORE_SELECT_STACK 0x2 1782 __le16 offset; 1783 __le32 data; /* Used for write sto only */ 1784 __le32 addr_high; /* Used for read sto only */ 1785 __le32 addr_low; /* Used for read sto only */ 1786 }; 1787 1788 /* Used for both command responses: 1789 * DNL read sto response (indirect 0x0683) 1790 * DNL write sto response (indirect 0x0684) 1791 */ 1792 struct ice_aqc_dnl_read_write_response { 1793 u8 reserved; 1794 u8 status; /* Reserved for read command */ 1795 __le16 size; /* Reserved for write command */ 1796 __le32 data; /* Reserved for write command */ 1797 __le32 addr_high; /* Reserved for write command */ 1798 __le32 addr_low; /* Reserved for write command */ 1799 }; 1800 1801 /* DNL set breakpoints command (indirect 0x0686) */ 1802 struct ice_aqc_dnl_set_breakpoints_command { 1803 __le32 reserved[2]; 1804 __le32 addr_high; 1805 __le32 addr_low; 1806 }; 1807 1808 /* DNL set breakpoints data buffer structure (indirect 0x0686) */ 1809 struct ice_aqc_dnl_set_breakpoints { 1810 u8 ctx; 1811 u8 ena; /* 0- disabled, 1- enabled */ 1812 __le16 offset; 1813 __le16 activity_id; 1814 }; 1815 1816 /* DNL read log data command(indirect 0x0687) */ 1817 struct ice_aqc_dnl_read_log_command { 1818 __le16 reserved0; 1819 __le16 offset; 1820 __le32 reserved1; 1821 __le32 addr_high; 1822 __le32 addr_low; 1823 1824 }; 1825 1826 /* DNL read log data response(indirect 0x0687) */ 1827 struct ice_aqc_dnl_read_log_response { 1828 __le16 reserved; 1829 __le16 size; 1830 __le32 data; 1831 __le32 addr_high; 1832 __le32 addr_low; 1833 1834 }; 1835 1836 struct ice_aqc_link_topo_params { 1837 u8 lport_num; 1838 u8 lport_num_valid; 1839 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 1840 u8 node_type_ctx; 1841 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 1842 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 1843 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 1844 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1845 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1846 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1847 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 1848 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 1849 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 1850 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 1851 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1852 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 1853 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 1854 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 1855 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 1856 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 1857 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 1858 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 1859 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 1860 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 1861 u8 index; 1862 }; 1863 1864 struct ice_aqc_link_topo_addr { 1865 struct ice_aqc_link_topo_params topo_params; 1866 __le16 handle; 1867 #define ICE_AQC_LINK_TOPO_HANDLE_S 0 1868 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 1869 /* Used to decode the handle field */ 1870 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1871 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 1872 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 1873 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 1874 /* In case of a Mezzanine type */ 1875 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1876 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1877 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 1878 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 1879 /* In case of a LOM type */ 1880 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 1881 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1882 }; 1883 1884 /* Get Link Topology Handle (direct, 0x06E0) */ 1885 struct ice_aqc_get_link_topo { 1886 struct ice_aqc_link_topo_addr addr; 1887 u8 node_part_num; 1888 #define ICE_ACQ_GET_LINK_TOPO_NODE_NR_PCA9575 0x21 1889 u8 rsvd[9]; 1890 }; 1891 1892 /* Read/Write I2C (direct, 0x06E2/0x06E3) */ 1893 struct ice_aqc_i2c { 1894 struct ice_aqc_link_topo_addr topo_addr; 1895 __le16 i2c_addr; 1896 u8 i2c_params; 1897 #define ICE_AQC_I2C_DATA_SIZE_S 0 1898 #define ICE_AQC_I2C_DATA_SIZE_M (0xF << ICE_AQC_I2C_DATA_SIZE_S) 1899 #define ICE_AQC_I2C_ADDR_TYPE_M BIT(4) 1900 #define ICE_AQC_I2C_ADDR_TYPE_7BIT 0 1901 #define ICE_AQC_I2C_ADDR_TYPE_10BIT ICE_AQC_I2C_ADDR_TYPE_M 1902 #define ICE_AQC_I2C_DATA_OFFSET_S 5 1903 #define ICE_AQC_I2C_DATA_OFFSET_M (0x3 << ICE_AQC_I2C_DATA_OFFSET_S) 1904 #define ICE_AQC_I2C_USE_REPEATED_START BIT(7) 1905 u8 rsvd; 1906 __le16 i2c_bus_addr; 1907 #define ICE_AQC_I2C_ADDR_7BIT_MASK 0x7F 1908 #define ICE_AQC_I2C_ADDR_10BIT_MASK 0x3FF 1909 u8 i2c_data[4]; /* Used only by write command, reserved in read. */ 1910 }; 1911 1912 /* Read I2C Response (direct, 0x06E2) */ 1913 struct ice_aqc_read_i2c_resp { 1914 u8 i2c_data[16]; 1915 }; 1916 1917 /* Read/Write MDIO (direct, 0x06E4/0x06E5) */ 1918 struct ice_aqc_mdio { 1919 struct ice_aqc_link_topo_addr topo_addr; 1920 u8 mdio_device_addr; 1921 #define ICE_AQC_MDIO_DEV_S 0 1922 #define ICE_AQC_MDIO_DEV_M (0x1F << ICE_AQC_MDIO_DEV_S) 1923 #define ICE_AQC_MDIO_CLAUSE_22 BIT(5) 1924 #define ICE_AQC_MDIO_CLAUSE_45 BIT(6) 1925 u8 mdio_bus_address; 1926 #define ICE_AQC_MDIO_BUS_ADDR_S 0 1927 #define ICE_AQC_MDIO_BUS_ADDR_M (0x1F << ICE_AQC_MDIO_BUS_ADDR_S) 1928 __le16 offset; 1929 __le16 data; /* Input in write cmd, output in read cmd. */ 1930 u8 rsvd1[4]; 1931 }; 1932 1933 /* Set/Get GPIO By Function (direct, 0x06E6/0x06E7) */ 1934 struct ice_aqc_gpio_by_func { 1935 struct ice_aqc_link_topo_addr topo_addr; 1936 u8 io_func_num; 1937 #define ICE_AQC_GPIO_FUNC_S 0 1938 #define ICE_AQC_GPIO_FUNC_M (0x1F << ICE_AQC_GPIO_IO_FUNC_NUM_S) 1939 u8 io_value; /* Input in write cmd, output in read cmd. */ 1940 #define ICE_AQC_GPIO_ON BIT(0) 1941 #define ICE_AQC_GPIO_OFF 0 1942 u8 rsvd[8]; 1943 }; 1944 1945 /* Set LED (direct, 0x06E8) */ 1946 struct ice_aqc_set_led { 1947 struct ice_aqc_link_topo_addr topo_addr; 1948 u8 color_and_blink; 1949 #define ICE_AQC_LED_COLOR_S 0 1950 #define ICE_AQC_LED_COLOR_M (0x7 << ICE_AQC_LED_COLOR_S) 1951 #define ICE_AQC_LED_COLOR_SKIP 0 1952 #define ICE_AQC_LED_COLOR_RED 1 1953 #define ICE_AQC_LED_COLOR_ORANGE 2 1954 #define ICE_AQC_LED_COLOR_YELLOW 3 1955 #define ICE_AQC_LED_COLOR_GREEN 4 1956 #define ICE_AQC_LED_COLOR_BLUE 5 1957 #define ICE_AQC_LED_COLOR_PURPLE 6 1958 #define ICE_AQC_LED_BLINK_S 3 1959 #define ICE_AQC_LED_BLINK_M (0x7 << ICE_AQC_LED_BLINK_S) 1960 #define ICE_AQC_LED_BLINK_NONE 0 1961 #define ICE_AQC_LED_BLINK_SLOW 1 1962 #define ICE_AQC_LED_BLINK_SLOW_MAC 2 1963 #define ICE_AQC_LED_BLINK_SLOW_FLTR 3 1964 #define ICE_AQC_LED_BLINK_FAST 5 1965 #define ICE_AQC_LED_BLINK_FAST_MAC 6 1966 #define ICE_AQC_LED_BLINK_FAST_FLTR 7 1967 u8 rsvd[9]; 1968 }; 1969 1970 /* Set Port Identification LED (direct, 0x06E9) */ 1971 struct ice_aqc_set_port_id_led { 1972 u8 lport_num; 1973 u8 lport_num_valid; 1974 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0) 1975 u8 ident_mode; 1976 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1977 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1978 u8 rsvd[13]; 1979 }; 1980 1981 /* Get Port Options (indirect, 0x06EA) */ 1982 struct ice_aqc_get_port_options { 1983 u8 lport_num; 1984 u8 lport_num_valid; 1985 #define ICE_AQC_PORT_OPT_PORT_NUM_VALID BIT(0) 1986 u8 port_options_count; 1987 #define ICE_AQC_PORT_OPT_COUNT_S 0 1988 #define ICE_AQC_PORT_OPT_COUNT_M (0xF << ICE_AQC_PORT_OPT_COUNT_S) 1989 #define ICE_AQC_PORT_OPT_MAX 16 1990 u8 innermost_phy_index; 1991 u8 port_options; 1992 #define ICE_AQC_PORT_OPT_ACTIVE_S 0 1993 #define ICE_AQC_PORT_OPT_ACTIVE_M (0xF << ICE_AQC_PORT_OPT_ACTIVE_S) 1994 #define ICE_AQC_PORT_OPT_FORCED BIT(6) 1995 #define ICE_AQC_PORT_OPT_VALID BIT(7) 1996 u8 pending_port_option_status; 1997 #define ICE_AQC_PENDING_PORT_OPT_IDX_S 0 1998 #define ICE_AQC_PENDING_PORT_OPT_IDX_M (0xF << ICE_AQC_PENDING_PORT_OPT_IDX_S) 1999 #define ICE_AQC_PENDING_PORT_OPT_VALID BIT(7) 2000 u8 rsvd[2]; 2001 __le32 addr_high; 2002 __le32 addr_low; 2003 }; 2004 2005 struct ice_aqc_get_port_options_elem { 2006 u8 pmd; 2007 #define ICE_AQC_PORT_INV_PORT_OPT 4 2008 #define ICE_AQC_PORT_OPT_PMD_COUNT_S 0 2009 #define ICE_AQC_PORT_OPT_PMD_COUNT_M (0xF << ICE_AQC_PORT_OPT_PMD_COUNT_S) 2010 #define ICE_AQC_PORT_OPT_PMD_WIDTH_S 4 2011 #define ICE_AQC_PORT_OPT_PMD_WIDTH_M (0xF << ICE_AQC_PORT_OPT_PMD_WIDTH_S) 2012 u8 max_lane_speed; 2013 #define ICE_AQC_PORT_OPT_MAX_LANE_S 0 2014 #define ICE_AQC_PORT_OPT_MAX_LANE_M (0xF << ICE_AQC_PORT_OPT_MAX_LANE_S) 2015 #define ICE_AQC_PORT_OPT_MAX_LANE_100M 0 2016 #define ICE_AQC_PORT_OPT_MAX_LANE_1G 1 2017 #define ICE_AQC_PORT_OPT_MAX_LANE_2500M 2 2018 #define ICE_AQC_PORT_OPT_MAX_LANE_5G 3 2019 #define ICE_AQC_PORT_OPT_MAX_LANE_10G 4 2020 #define ICE_AQC_PORT_OPT_MAX_LANE_25G 5 2021 #define ICE_AQC_PORT_OPT_MAX_LANE_50G 6 2022 #define ICE_AQC_PORT_OPT_MAX_LANE_100G 7 2023 u8 global_scid[2]; 2024 u8 phy_scid[2]; 2025 u8 pf2port_cid[2]; 2026 }; 2027 2028 /* Set Port Option (direct, 0x06EB) */ 2029 struct ice_aqc_set_port_option { 2030 u8 lport_num; 2031 u8 lport_num_valid; 2032 #define ICE_AQC_SET_PORT_OPT_PORT_NUM_VALID BIT(0) 2033 u8 selected_port_option; 2034 u8 rsvd[13]; 2035 }; 2036 2037 /* Set/Get GPIO (direct, 0x06EC/0x06ED) */ 2038 struct ice_aqc_gpio { 2039 __le16 gpio_ctrl_handle; 2040 #define ICE_AQC_GPIO_HANDLE_S 0 2041 #define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S) 2042 u8 gpio_num; 2043 u8 gpio_val; 2044 u8 rsvd[12]; 2045 }; 2046 2047 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 2048 struct ice_aqc_sff_eeprom { 2049 u8 lport_num; 2050 u8 lport_num_valid; 2051 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 2052 __le16 i2c_bus_addr; 2053 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 2054 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 2055 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 2056 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 2057 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 2058 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 2059 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 2060 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 2061 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 2062 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 2063 #define ICE_AQC_SFF_IS_WRITE BIT(15) 2064 __le16 i2c_mem_addr; 2065 __le16 eeprom_page; 2066 #define ICE_AQC_SFF_EEPROM_BANK_S 0 2067 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 2068 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 2069 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 2070 __le32 addr_high; 2071 __le32 addr_low; 2072 }; 2073 2074 /* SW Set GPIO command (indirect 0x6EF) 2075 * SW Get GPIO command (indirect 0x6F0) 2076 */ 2077 struct ice_aqc_sw_gpio { 2078 __le16 gpio_ctrl_handle; 2079 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S 0 2080 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_M (0x3FF << ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S) 2081 u8 gpio_num; 2082 #define ICE_AQC_SW_GPIO_NUMBER_S 0 2083 #define ICE_AQC_SW_GPIO_NUMBER_M (0x1F << ICE_AQC_SW_GPIO_NUMBER_S) 2084 u8 gpio_params; 2085 #define ICE_AQC_SW_GPIO_PARAMS_DIRECTION BIT(1) 2086 #define ICE_AQC_SW_GPIO_PARAMS_VALUE BIT(0) 2087 u8 rsvd[12]; 2088 }; 2089 2090 /* Program Topology Device NVM (direct, 0x06F2) */ 2091 struct ice_aqc_prog_topo_dev_nvm { 2092 struct ice_aqc_link_topo_params topo_params; 2093 u8 rsvd[12]; 2094 }; 2095 2096 /* Read Topology Device NVM (direct, 0x06F3) */ 2097 struct ice_aqc_read_topo_dev_nvm { 2098 struct ice_aqc_link_topo_params topo_params; 2099 __le32 start_address; 2100 #define ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE 8 2101 u8 data_read[ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE]; 2102 }; 2103 2104 /* NVM Read command (indirect 0x0701) 2105 * NVM Erase commands (direct 0x0702) 2106 * NVM Write commands (indirect 0x0703) 2107 * NVM Write Activate commands (direct 0x0707) 2108 * NVM Shadow RAM Dump commands (direct 0x0707) 2109 */ 2110 struct ice_aqc_nvm { 2111 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 2112 __le16 offset_low; 2113 u8 offset_high; /* For Write Activate offset_high is used as flags2 */ 2114 u8 cmd_flags; 2115 #define ICE_AQC_NVM_LAST_CMD BIT(0) 2116 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */ 2117 #define ICE_AQC_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */ 2118 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 2119 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 2120 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 2121 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 2122 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 2123 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 2124 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) 2125 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) 2126 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) 2127 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 2128 #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3) 2129 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 2130 #define ICE_AQC_NVM_RESET_LVL_M MAKEMASK(0x3, 0) /* Write reply only */ 2131 #define ICE_AQC_NVM_POR_FLAG 0 2132 #define ICE_AQC_NVM_PERST_FLAG 1 2133 #define ICE_AQC_NVM_EMPR_FLAG 2 2134 #define ICE_AQC_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */ 2135 /* For Write Activate, several flags are sent as part of a separate 2136 * flags2 field using a separate byte. For simplicity of the software 2137 * interface, we pass the flags as a 16 bit value so these flags are 2138 * all offset by 8 bits 2139 */ 2140 #define ICE_AQC_NVM_ACTIV_REQ_EMPR BIT(8) /* NVM Write Activate only */ 2141 __le16 module_typeid; 2142 __le16 length; 2143 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 2144 __le32 addr_high; 2145 __le32 addr_low; 2146 }; 2147 2148 /* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */ 2149 #define ICE_AQC_NVM_SECTOR_UNIT 4096 /* In Bytes */ 2150 #define ICE_AQC_NVM_WORD_UNIT 2 /* In Bytes */ 2151 2152 #define ICE_AQC_NVM_START_POINT 0 2153 #define ICE_AQC_NVM_EMP_SR_PTR_OFFSET 0x90 2154 #define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN 2 /* In Bytes */ 2155 #define ICE_AQC_NVM_EMP_SR_PTR_M MAKEMASK(0x7FFF, 0) 2156 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S 15 2157 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M BIT(15) 2158 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR 1 2159 2160 #define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET 0x46 2161 #define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN 2 /* In Bytes */ 2162 #define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */ 2163 2164 #define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129 2165 #define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */ 2166 #define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0) 2167 #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */ 2168 #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */ 2169 2170 #define ICE_AQC_NVM_MINSREV_MOD_ID 0x130 2171 #define ICE_AQC_NVM_TX_TOPO_MOD_ID 0x14B 2172 2173 /* Used for reading and writing MinSRev using 0x0701 and 0x0703. Note that the 2174 * type field is excluded from the section when reading and writing from 2175 * a module using the module_typeid field with these AQ commands. 2176 */ 2177 struct ice_aqc_nvm_minsrev { 2178 __le16 length; 2179 __le16 validity; 2180 #define ICE_AQC_NVM_MINSREV_NVM_VALID BIT(0) 2181 #define ICE_AQC_NVM_MINSREV_OROM_VALID BIT(1) 2182 __le16 nvm_minsrev_l; 2183 __le16 nvm_minsrev_h; 2184 __le16 orom_minsrev_l; 2185 __le16 orom_minsrev_h; 2186 }; 2187 2188 struct ice_aqc_nvm_tx_topo_user_sel { 2189 __le16 length; 2190 u8 data; 2191 #define ICE_AQC_NVM_TX_TOPO_USER_SEL BIT(4) 2192 u8 reserved; 2193 }; 2194 2195 /* Used for 0x0704 as well as for 0x0705 commands */ 2196 struct ice_aqc_nvm_cfg { 2197 u8 cmd_flags; 2198 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0) 2199 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1) 2200 #define ICE_AQC_ANVM_NEW_CFG BIT(2) 2201 u8 reserved; 2202 __le16 count; 2203 __le16 id; 2204 u8 reserved1[2]; 2205 __le32 addr_high; 2206 __le32 addr_low; 2207 }; 2208 2209 struct ice_aqc_nvm_cfg_data { 2210 __le16 field_id; 2211 __le16 field_options; 2212 __le16 field_value; 2213 }; 2214 2215 /* NVM Checksum Command (direct, 0x0706) */ 2216 struct ice_aqc_nvm_checksum { 2217 u8 flags; 2218 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 2219 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 2220 u8 rsvd; 2221 __le16 checksum; /* Used only by response */ 2222 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 2223 u8 rsvd2[12]; 2224 }; 2225 2226 /* 2227 * Send to PF command (indirect 0x0801) ID is only used by PF 2228 * 2229 * Send to VF command (indirect 0x0802) ID is only used by PF 2230 * 2231 */ 2232 struct ice_aqc_pf_vf_msg { 2233 __le32 id; 2234 u32 reserved; 2235 __le32 addr_high; 2236 __le32 addr_low; 2237 }; 2238 2239 /* Write/Read Alternate - Direct (direct 0x0900/0x0902) */ 2240 struct ice_aqc_read_write_alt_direct { 2241 __le32 dword0_addr; 2242 __le32 dword0_value; 2243 __le32 dword1_addr; 2244 __le32 dword1_value; 2245 }; 2246 2247 /* Write/Read Alternate - Indirect (indirect 0x0901/0x0903) */ 2248 struct ice_aqc_read_write_alt_indirect { 2249 __le32 base_dword_addr; 2250 __le32 num_dwords; 2251 __le32 addr_high; 2252 __le32 addr_low; 2253 }; 2254 2255 /* Done Alternate Write (direct 0x0904) */ 2256 struct ice_aqc_done_alt_write { 2257 u8 flags; 2258 #define ICE_AQC_CMD_UEFI_BIOS_MODE BIT(0) 2259 #define ICE_AQC_RESP_RESET_NEEDED BIT(1) 2260 u8 reserved[15]; 2261 }; 2262 2263 /* Clear Port Alternate Write (direct 0x0906) */ 2264 struct ice_aqc_clear_port_alt_write { 2265 u8 reserved[16]; 2266 }; 2267 2268 /* Get LLDP MIB (indirect 0x0A00) 2269 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 2270 * as the format is the same. 2271 */ 2272 struct ice_aqc_lldp_get_mib { 2273 u8 type; 2274 #define ICE_AQ_LLDP_MIB_TYPE_S 0 2275 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 2276 #define ICE_AQ_LLDP_MIB_LOCAL 0 2277 #define ICE_AQ_LLDP_MIB_REMOTE 1 2278 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 2279 #define ICE_AQ_LLDP_BRID_TYPE_S 2 2280 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 2281 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 2282 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 2283 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 2284 #define ICE_AQ_LLDP_TX_S 0x4 2285 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 2286 #define ICE_AQ_LLDP_TX_ACTIVE 0 2287 #define ICE_AQ_LLDP_TX_SUSPENDED 1 2288 #define ICE_AQ_LLDP_TX_FLUSHED 3 2289 /* DCBX mode */ 2290 #define ICE_AQ_LLDP_DCBX_S 6 2291 #define ICE_AQ_LLDP_DCBX_M (0x3 << ICE_AQ_LLDP_DCBX_S) 2292 #define ICE_AQ_LLDP_DCBX_NA 0 2293 #define ICE_AQ_LLDP_DCBX_CEE 1 2294 #define ICE_AQ_LLDP_DCBX_IEEE 2 2295 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 2296 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 2297 * Get LLDP MIB (0x0A00) response only. 2298 */ 2299 u8 state; 2300 #define ICE_AQ_LLDP_MIB_CHANGE_STATE_S 0 2301 #define ICE_AQ_LLDP_MIB_CHANGE_STATE_M \ 2302 (0x1 << ICE_AQ_LLDP_MIB_CHANGE_STATE_S) 2303 #define ICE_AQ_LLDP_MIB_CHANGE_EXECUTED 0 2304 #define ICE_AQ_LLDP_MIB_CHANGE_PENDING 1 2305 __le16 local_len; 2306 __le16 remote_len; 2307 u8 reserved[2]; 2308 __le32 addr_high; 2309 __le32 addr_low; 2310 }; 2311 2312 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 2313 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 2314 struct ice_aqc_lldp_set_mib_change { 2315 u8 command; 2316 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2317 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 2318 #define ICE_AQ_LLDP_MIB_PENDING_S 1 2319 #define ICE_AQ_LLDP_MIB_PENDING_M \ 2320 (0x1 << ICE_AQ_LLDP_MIB_PENDING_S) 2321 #define ICE_AQ_LLDP_MIB_PENDING_DISABLE 0 2322 #define ICE_AQ_LLDP_MIB_PENDING_ENABLE 1 2323 u8 reserved[15]; 2324 }; 2325 2326 /* Add LLDP TLV (indirect 0x0A02) 2327 * Delete LLDP TLV (indirect 0x0A04) 2328 */ 2329 struct ice_aqc_lldp_add_delete_tlv { 2330 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2331 u8 reserved1[1]; 2332 __le16 len; 2333 u8 reserved2[4]; 2334 __le32 addr_high; 2335 __le32 addr_low; 2336 }; 2337 2338 /* Update LLDP TLV (indirect 0x0A03) */ 2339 struct ice_aqc_lldp_update_tlv { 2340 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2341 u8 reserved; 2342 __le16 old_len; 2343 __le16 new_offset; 2344 __le16 new_len; 2345 __le32 addr_high; 2346 __le32 addr_low; 2347 }; 2348 2349 /* Stop LLDP (direct 0x0A05) */ 2350 struct ice_aqc_lldp_stop { 2351 u8 command; 2352 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 2353 #define ICE_AQ_LLDP_AGENT_STOP 0x0 2354 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 2355 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 2356 u8 reserved[15]; 2357 }; 2358 2359 /* Start LLDP (direct 0x0A06) */ 2360 struct ice_aqc_lldp_start { 2361 u8 command; 2362 #define ICE_AQ_LLDP_AGENT_START BIT(0) 2363 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 2364 u8 reserved[15]; 2365 }; 2366 2367 /* Get CEE DCBX Oper Config (0x0A07) 2368 * The command uses the generic descriptor struct and 2369 * returns the struct below as an indirect response. 2370 */ 2371 struct ice_aqc_get_cee_dcb_cfg_resp { 2372 u8 oper_num_tc; 2373 u8 oper_prio_tc[4]; 2374 u8 oper_tc_bw[8]; 2375 u8 oper_pfc_en; 2376 __le16 oper_app_prio; 2377 #define ICE_AQC_CEE_APP_FCOE_S 0 2378 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 2379 #define ICE_AQC_CEE_APP_ISCSI_S 3 2380 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 2381 #define ICE_AQC_CEE_APP_FIP_S 8 2382 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 2383 __le32 tlv_status; 2384 #define ICE_AQC_CEE_PG_STATUS_S 0 2385 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 2386 #define ICE_AQC_CEE_PFC_STATUS_S 3 2387 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 2388 #define ICE_AQC_CEE_FCOE_STATUS_S 8 2389 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 2390 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 2391 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 2392 #define ICE_AQC_CEE_FIP_STATUS_S 16 2393 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 2394 u8 reserved[12]; 2395 }; 2396 2397 /* Set Local LLDP MIB (indirect 0x0A08) 2398 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 2399 */ 2400 struct ice_aqc_lldp_set_local_mib { 2401 u8 type; 2402 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 2403 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 2404 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 2405 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 2406 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 2407 u8 reserved0; 2408 __le16 length; 2409 u8 reserved1[4]; 2410 __le32 addr_high; 2411 __le32 addr_low; 2412 }; 2413 2414 struct ice_aqc_lldp_set_local_mib_resp { 2415 u8 status; 2416 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0) 2417 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0 2418 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT SET_LOCAL_MIB_RESP_EVENT_M 2419 u8 reserved[15]; 2420 }; 2421 2422 /* Stop/Start LLDP Agent (direct 0x0A09) 2423 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 2424 * The same structure is used for the response, with the command field 2425 * being used as the status field. 2426 */ 2427 struct ice_aqc_lldp_stop_start_specific_agent { 2428 u8 command; 2429 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 2430 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 2431 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 2432 u8 reserved[15]; 2433 }; 2434 2435 /* LLDP Filter Control (direct 0x0A0A) */ 2436 struct ice_aqc_lldp_filter_ctrl { 2437 u8 cmd_flags; 2438 #define ICE_AQC_LLDP_FILTER_ACTION_M MAKEMASK(3, 0) 2439 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0 2440 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1 2441 #define ICE_AQC_LLDP_FILTER_ACTION_UPDATE 0x2 2442 u8 reserved1; 2443 __le16 vsi_num; 2444 u8 reserved2[12]; 2445 }; 2446 2447 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 2448 struct ice_aqc_get_set_rss_key { 2449 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 2450 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 2451 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 2452 __le16 vsi_id; 2453 u8 reserved[6]; 2454 __le32 addr_high; 2455 __le32 addr_low; 2456 }; 2457 2458 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 2459 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 2460 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 2461 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 2462 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 2463 2464 /** 2465 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer 2466 * @standard_rss_key: 40 most significant bytes of hash key 2467 * @extended_hash_key: 12 least significant bytes of hash key 2468 * 2469 * Set/Get 40 byte hash key using standard_rss_key field, and set 2470 * extended_hash_key field to zero. Set/Get 52 byte hash key using 2471 * standard_rss_key field for 40 most significant bytes and the 2472 * extended_hash_key field for the 12 least significant bytes of hash key. 2473 */ 2474 struct ice_aqc_get_set_rss_keys { 2475 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 2476 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 2477 }; 2478 2479 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 2480 struct ice_aqc_get_set_rss_lut { 2481 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 2482 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 2483 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 2484 __le16 vsi_id; 2485 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 2486 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 2487 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 2488 2489 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 2490 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 2491 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 2492 2493 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 2494 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 2495 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 2496 2497 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 2498 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 2499 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 2500 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 2501 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 2502 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 2503 2504 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 2505 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 2506 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 2507 2508 __le16 flags; 2509 __le32 reserved; 2510 __le32 addr_high; 2511 __le32 addr_low; 2512 }; 2513 2514 /* Add Tx LAN Queues (indirect 0x0C30) */ 2515 struct ice_aqc_add_txqs { 2516 u8 num_qgrps; 2517 u8 reserved[3]; 2518 __le32 reserved1; 2519 __le32 addr_high; 2520 __le32 addr_low; 2521 }; 2522 2523 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 2524 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 2525 */ 2526 struct ice_aqc_add_txqs_perq { 2527 __le16 txq_id; 2528 u8 rsvd[2]; 2529 __le32 q_teid; 2530 u8 txq_ctx[22]; 2531 u8 rsvd2[2]; 2532 struct ice_aqc_txsched_elem info; 2533 }; 2534 2535 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 2536 * is an array of the following structs. Please note that the length of 2537 * each struct ice_aqc_add_tx_qgrp is variable due 2538 * to the variable number of queues in each group! 2539 */ 2540 struct ice_aqc_add_tx_qgrp { 2541 __le32 parent_teid; 2542 u8 num_txqs; 2543 u8 rsvd[3]; 2544 struct ice_aqc_add_txqs_perq txqs[STRUCT_HACK_VAR_LEN]; 2545 }; 2546 2547 /* Disable Tx LAN Queues (indirect 0x0C31) */ 2548 struct ice_aqc_dis_txqs { 2549 u8 cmd_type; 2550 #define ICE_AQC_Q_DIS_CMD_S 0 2551 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 2552 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 2553 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 2554 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 2555 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 2556 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 2557 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 2558 u8 num_entries; 2559 __le16 vmvf_and_timeout; 2560 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 2561 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 2562 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 2563 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 2564 __le32 blocked_cgds; 2565 __le32 addr_high; 2566 __le32 addr_low; 2567 }; 2568 2569 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 2570 * contains the following structures, arrayed one after the 2571 * other. 2572 * Note: Since the q_id is 16 bits wide, if the 2573 * number of queues is even, then 2 bytes of alignment MUST be 2574 * added before the start of the next group, to allow correct 2575 * alignment of the parent_teid field. 2576 */ 2577 #pragma pack(1) 2578 struct ice_aqc_dis_txq_item { 2579 __le32 parent_teid; 2580 u8 num_qs; 2581 u8 rsvd; 2582 /* The length of the q_id array varies according to num_qs */ 2583 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 2584 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 2585 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2586 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 2587 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2588 __le16 q_id[STRUCT_HACK_VAR_LEN]; 2589 }; 2590 #pragma pack() 2591 2592 /* Tx LAN Queues Cleanup Event (0x0C31) */ 2593 struct ice_aqc_txqs_cleanup { 2594 __le16 caller_opc; 2595 __le16 cmd_tag; 2596 u8 reserved[12]; 2597 }; 2598 2599 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */ 2600 struct ice_aqc_move_txqs { 2601 u8 cmd_type; 2602 #define ICE_AQC_Q_CMD_TYPE_S 0 2603 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S) 2604 #define ICE_AQC_Q_CMD_TYPE_MOVE 1 2605 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2 2606 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3 2607 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2) 2608 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3) 2609 u8 num_qs; 2610 u8 rsvd; 2611 u8 timeout; 2612 #define ICE_AQC_Q_CMD_TIMEOUT_S 2 2613 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S) 2614 __le32 blocked_cgds; 2615 __le32 addr_high; 2616 __le32 addr_low; 2617 }; 2618 2619 /* Per-queue data buffer for the Move Tx LAN Queues command/response */ 2620 struct ice_aqc_move_txqs_elem { 2621 __le16 txq_id; 2622 u8 q_cgd; 2623 u8 rsvd; 2624 __le32 q_teid; 2625 }; 2626 2627 /* Indirect data buffer for the Move Tx LAN Queues command/response */ 2628 struct ice_aqc_move_txqs_data { 2629 __le32 src_teid; 2630 __le32 dest_teid; 2631 struct ice_aqc_move_txqs_elem txqs[STRUCT_HACK_VAR_LEN]; 2632 }; 2633 2634 /* Add Tx RDMA Queue Set (indirect 0x0C33) */ 2635 struct ice_aqc_add_rdma_qset { 2636 u8 num_qset_grps; 2637 u8 reserved[7]; 2638 __le32 addr_high; 2639 __le32 addr_low; 2640 }; 2641 2642 /* This is the descriptor of each qset entry for the Add Tx RDMA Queue Set 2643 * command (0x0C33). Only used within struct ice_aqc_add_rdma_qset. 2644 */ 2645 struct ice_aqc_add_tx_rdma_qset_entry { 2646 __le16 tx_qset_id; 2647 u8 rsvd[2]; 2648 __le32 qset_teid; 2649 struct ice_aqc_txsched_elem info; 2650 }; 2651 2652 /* The format of the command buffer for Add Tx RDMA Queue Set(0x0C33) 2653 * is an array of the following structs. Please note that the length of 2654 * each struct ice_aqc_add_rdma_qset is variable due to the variable 2655 * number of queues in each group! 2656 */ 2657 struct ice_aqc_add_rdma_qset_data { 2658 __le32 parent_teid; 2659 __le16 num_qsets; 2660 u8 rsvd[2]; 2661 struct ice_aqc_add_tx_rdma_qset_entry rdma_qsets[STRUCT_HACK_VAR_LEN]; 2662 }; 2663 2664 /* Move RDMA Queue Set (indirect 0x0C34) */ 2665 struct ice_aqc_move_rdma_qset_cmd { 2666 u8 num_rdma_qset; /* Used by commands and response */ 2667 #define ICE_AQC_PF_MODE_SAME_PF 0x0 2668 #define ICE_AQC_PF_MODE_GIVE_OWNERSHIP 0x1 2669 #define ICE_AQC_PF_MODE_KEEP_OWNERSHIP 0x2 2670 u8 flags; 2671 u8 reserved[6]; 2672 __le32 addr_high; 2673 __le32 addr_low; 2674 }; 2675 2676 /* Buffer */ 2677 struct ice_aqc_move_rdma_qset_buffer_desc { 2678 __le16 tx_qset_id; 2679 __le16 qset_teid; 2680 }; 2681 2682 struct ice_aqc_move_rdma_qset_buffer { 2683 __le32 src_parent_teid; 2684 __le32 dest_parent_teid; 2685 struct ice_aqc_move_rdma_qset_buffer_desc descs[STRUCT_HACK_VAR_LEN]; 2686 }; 2687 2688 /* Download Package (indirect 0x0C40) */ 2689 /* Also used for Update Package (indirect 0x0C42 and 0x0C41) */ 2690 struct ice_aqc_download_pkg { 2691 u8 flags; 2692 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 2693 u8 reserved[3]; 2694 __le32 reserved1; 2695 __le32 addr_high; 2696 __le32 addr_low; 2697 }; 2698 2699 struct ice_aqc_download_pkg_resp { 2700 __le32 error_offset; 2701 __le32 error_info; 2702 __le32 addr_high; 2703 __le32 addr_low; 2704 }; 2705 2706 /* Get Package Info List (indirect 0x0C43) */ 2707 struct ice_aqc_get_pkg_info_list { 2708 __le32 reserved1; 2709 __le32 reserved2; 2710 __le32 addr_high; 2711 __le32 addr_low; 2712 }; 2713 2714 /* Version format for packages */ 2715 struct ice_pkg_ver { 2716 u8 major; 2717 u8 minor; 2718 u8 update; 2719 u8 draft; 2720 }; 2721 2722 #define ICE_PKG_NAME_SIZE 32 2723 #define ICE_SEG_ID_SIZE 28 2724 #define ICE_SEG_NAME_SIZE 28 2725 2726 struct ice_aqc_get_pkg_info { 2727 struct ice_pkg_ver ver; 2728 char name[ICE_SEG_NAME_SIZE]; 2729 __le32 track_id; 2730 u8 is_in_nvm; 2731 u8 is_active; 2732 u8 is_active_at_boot; 2733 u8 is_modified; 2734 }; 2735 2736 /* Get Package Info List response buffer format (0x0C43) */ 2737 struct ice_aqc_get_pkg_info_resp { 2738 __le32 count; 2739 struct ice_aqc_get_pkg_info pkg_info[STRUCT_HACK_VAR_LEN]; 2740 }; 2741 2742 /* Driver Shared Parameters (direct, 0x0C90) */ 2743 struct ice_aqc_driver_shared_params { 2744 u8 set_or_get_op; 2745 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0) 2746 #define ICE_AQC_DRIVER_PARAM_SET ((u8)0) 2747 #define ICE_AQC_DRIVER_PARAM_GET ((u8)1) 2748 u8 param_indx; 2749 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15 2750 u8 rsvd[2]; 2751 __le32 param_val; 2752 __le32 addr_high; 2753 __le32 addr_low; 2754 }; 2755 2756 /* Lan Queue Overflow Event (direct, 0x1001) */ 2757 struct ice_aqc_event_lan_overflow { 2758 __le32 prtdcb_ruptq; 2759 __le32 qtx_ctl; 2760 u8 reserved[8]; 2761 }; 2762 2763 /* Debug Dump Internal Data (indirect 0xFF08) */ 2764 struct ice_aqc_debug_dump_internals { 2765 u8 cluster_id; 2766 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW 0 2767 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED 2 2768 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES 3 2769 /* EMP_DRAM only dumpable in device debug mode */ 2770 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_EMP_DRAM 4 2771 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK 5 2772 /* AUX_REGS only dumpable in device debug mode */ 2773 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_AUX_REGS 6 2774 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB 7 2775 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P 8 2776 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_QUEUE_MNG 9 2777 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_FULL_CSR_SPACE 21 2778 u8 reserved; 2779 __le16 table_id; /* Used only for non-memory clusters */ 2780 __le32 idx; /* In table entries for tables, in bytes for memory */ 2781 __le32 addr_high; 2782 __le32 addr_low; 2783 }; 2784 2785 enum ice_aqc_fw_logging_mod { 2786 ICE_AQC_FW_LOG_ID_GENERAL = 0, 2787 ICE_AQC_FW_LOG_ID_CTRL, 2788 ICE_AQC_FW_LOG_ID_LINK, 2789 ICE_AQC_FW_LOG_ID_LINK_TOPO, 2790 ICE_AQC_FW_LOG_ID_DNL, 2791 ICE_AQC_FW_LOG_ID_I2C, 2792 ICE_AQC_FW_LOG_ID_SDP, 2793 ICE_AQC_FW_LOG_ID_MDIO, 2794 ICE_AQC_FW_LOG_ID_ADMINQ, 2795 ICE_AQC_FW_LOG_ID_HDMA, 2796 ICE_AQC_FW_LOG_ID_LLDP, 2797 ICE_AQC_FW_LOG_ID_DCBX, 2798 ICE_AQC_FW_LOG_ID_DCB, 2799 ICE_AQC_FW_LOG_ID_XLR, 2800 ICE_AQC_FW_LOG_ID_NVM, 2801 ICE_AQC_FW_LOG_ID_AUTH, 2802 ICE_AQC_FW_LOG_ID_VPD, 2803 ICE_AQC_FW_LOG_ID_IOSF, 2804 ICE_AQC_FW_LOG_ID_PARSER, 2805 ICE_AQC_FW_LOG_ID_SW, 2806 ICE_AQC_FW_LOG_ID_SCHEDULER, 2807 ICE_AQC_FW_LOG_ID_TXQ, 2808 ICE_AQC_FW_LOG_ID_RSVD, 2809 ICE_AQC_FW_LOG_ID_POST, 2810 ICE_AQC_FW_LOG_ID_WATCHDOG, 2811 ICE_AQC_FW_LOG_ID_TASK_DISPATCH, 2812 ICE_AQC_FW_LOG_ID_MNG, 2813 ICE_AQC_FW_LOG_ID_SYNCE, 2814 ICE_AQC_FW_LOG_ID_HEALTH, 2815 ICE_AQC_FW_LOG_ID_TSDRV, 2816 ICE_AQC_FW_LOG_ID_PFREG, 2817 ICE_AQC_FW_LOG_ID_MDLVER, 2818 ICE_AQC_FW_LOG_ID_MAX, 2819 }; 2820 2821 /* Set Health Status (direct 0xFF20) */ 2822 struct ice_aqc_set_health_status_config { 2823 u8 event_source; 2824 #define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0) 2825 #define ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1) 2826 #define ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2) 2827 u8 reserved[15]; 2828 }; 2829 2830 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_STRICT 0x101 2831 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_TYPE 0x102 2832 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_QUAL 0x103 2833 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_COMM 0x104 2834 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_CONFLICT 0x105 2835 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_NOT_PRESENT 0x106 2836 #define ICE_AQC_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED 0x107 2837 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT 0x108 2838 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_DIAGNOSTIC_FEATURE 0x109 2839 #define ICE_AQC_HEALTH_STATUS_ERR_INVALID_LINK_CFG 0x10B 2840 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_ACCESS 0x10C 2841 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_UNREACHABLE 0x10D 2842 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_MOD_LIMITED 0x10F 2843 #define ICE_AQC_HEALTH_STATUS_ERR_PARALLEL_FAULT 0x110 2844 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED 0x111 2845 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST_TOPO 0x112 2846 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST 0x113 2847 #define ICE_AQC_HEALTH_STATUS_ERR_TOPO_CONFLICT 0x114 2848 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS 0x115 2849 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME 0x116 2850 #define ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT 0x117 2851 #define ICE_AQC_HEALTH_STATUS_ERR_PHY_NVM_PROG 0x120 2852 #define ICE_AQC_HEALTH_STATUS_ERR_PHY_FW_LOAD 0x121 2853 #define ICE_AQC_HEALTH_STATUS_INFO_RECOVERY 0x500 2854 #define ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS 0x501 2855 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH 0x502 2856 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_AUTH 0x503 2857 #define ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH 0x504 2858 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT 0x505 2859 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT 0x506 2860 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_SEC_VIOLATION 0x507 2861 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_SEC_VIOLATION 0x508 2862 #define ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB 0x509 2863 #define ICE_AQC_HEALTH_STATUS_ERR_MNG_TIMEOUT 0x50A 2864 #define ICE_AQC_HEALTH_STATUS_ERR_BMC_RESET 0x50B 2865 #define ICE_AQC_HEALTH_STATUS_ERR_LAST_MNG_FAIL 0x50C 2866 #define ICE_AQC_HEALTH_STATUS_ERR_RESOURCE_ALLOC_FAIL 0x50D 2867 #define ICE_AQC_HEALTH_STATUS_ERR_FW_LOOP 0x1000 2868 #define ICE_AQC_HEALTH_STATUS_ERR_FW_PFR_FAIL 0x1001 2869 #define ICE_AQC_HEALTH_STATUS_ERR_LAST_FAIL_AQ 0x1002 2870 2871 /* Get Health Status codes (indirect 0xFF21) */ 2872 struct ice_aqc_get_supported_health_status_codes { 2873 __le16 health_code_count; 2874 u8 reserved[6]; 2875 __le32 addr_high; 2876 __le32 addr_low; 2877 }; 2878 2879 /* Get Health Status (indirect 0xFF22) */ 2880 struct ice_aqc_get_health_status { 2881 __le16 health_status_count; 2882 u8 reserved[6]; 2883 __le32 addr_high; 2884 __le32 addr_low; 2885 }; 2886 2887 /* Get Health Status event buffer entry, (0xFF22) 2888 * repeated per reported health status 2889 */ 2890 struct ice_aqc_health_status_elem { 2891 __le16 health_status_code; 2892 __le16 event_source; 2893 #define ICE_AQC_HEALTH_STATUS_PF (0x1) 2894 #define ICE_AQC_HEALTH_STATUS_PORT (0x2) 2895 #define ICE_AQC_HEALTH_STATUS_GLOBAL (0x3) 2896 __le32 internal_data1; 2897 #define ICE_AQC_HEALTH_STATUS_UNDEFINED_DATA (0xDEADBEEF) 2898 __le32 internal_data2; 2899 }; 2900 2901 /* Clear Health Status (direct 0xFF23) */ 2902 struct ice_aqc_clear_health_status { 2903 __le32 reserved[4]; 2904 }; 2905 2906 /* Set FW Logging configuration (indirect 0xFF30) 2907 * Register for FW Logging (indirect 0xFF31) 2908 * Query FW Logging (indirect 0xFF32) 2909 * FW Log Event (indirect 0xFF33) 2910 * Get FW Log (indirect 0xFF34) 2911 * Clear FW Log (indirect 0xFF35) 2912 */ 2913 struct ice_aqc_fw_log { 2914 u8 cmd_flags; 2915 #define ICE_AQC_FW_LOG_CONF_UART_EN BIT(0) 2916 #define ICE_AQC_FW_LOG_CONF_AQ_EN BIT(1) 2917 #define ICE_AQC_FW_LOG_QUERY_REGISTERED BIT(2) 2918 #define ICE_AQC_FW_LOG_CONF_SET_VALID BIT(3) 2919 #define ICE_AQC_FW_LOG_AQ_REGISTER BIT(0) 2920 #define ICE_AQC_FW_LOG_AQ_QUERY BIT(2) 2921 #define ICE_AQC_FW_LOG_PERSISTENT BIT(0) 2922 u8 rsp_flag; 2923 #define ICE_AQC_FW_LOG_MORE_DATA BIT(1) 2924 __le16 fw_rt_msb; 2925 union { 2926 struct { 2927 __le32 fw_rt_lsb; 2928 } sync; 2929 struct { 2930 __le16 log_resolution; 2931 #define ICE_AQC_FW_LOG_MIN_RESOLUTION (1) 2932 #define ICE_AQC_FW_LOG_MAX_RESOLUTION (128) 2933 __le16 mdl_cnt; 2934 } cfg; 2935 } ops; 2936 __le32 addr_high; 2937 __le32 addr_low; 2938 }; 2939 2940 /* Response Buffer for: 2941 * Set Firmware Logging Configuration (0xFF30) 2942 * Query FW Logging (0xFF32) 2943 */ 2944 struct ice_aqc_fw_log_cfg_resp { 2945 __le16 module_identifier; 2946 u8 log_level; 2947 u8 rsvd0; 2948 }; 2949 2950 /** 2951 * struct ice_aq_desc - Admin Queue (AQ) descriptor 2952 * @flags: ICE_AQ_FLAG_* flags 2953 * @opcode: AQ command opcode 2954 * @datalen: length in bytes of indirect/external data buffer 2955 * @retval: return value from firmware 2956 * @cookie_high: opaque data high-half 2957 * @cookie_low: opaque data low-half 2958 * @params: command-specific parameters 2959 * 2960 * Descriptor format for commands the driver posts on the Admin Transmit Queue 2961 * (ATQ). The firmware writes back onto the command descriptor and returns 2962 * the result of the command. Asynchronous events that are not an immediate 2963 * result of the command are written to the Admin Receive Queue (ARQ) using 2964 * the same descriptor format. Descriptors are in little-endian notation with 2965 * 32-bit words. 2966 */ 2967 struct ice_aq_desc { 2968 __le16 flags; 2969 __le16 opcode; 2970 __le16 datalen; 2971 __le16 retval; 2972 __le32 cookie_high; 2973 __le32 cookie_low; 2974 union { 2975 u8 raw[16]; 2976 struct ice_aqc_generic generic; 2977 struct ice_aqc_get_ver get_ver; 2978 struct ice_aqc_driver_ver driver_ver; 2979 struct ice_aqc_q_shutdown q_shutdown; 2980 struct ice_aqc_get_exp_err exp_err; 2981 struct ice_aqc_req_res res_owner; 2982 struct ice_aqc_manage_mac_read mac_read; 2983 struct ice_aqc_manage_mac_write mac_write; 2984 struct ice_aqc_clear_pxe clear_pxe; 2985 struct ice_aqc_config_no_drop_policy no_drop; 2986 struct ice_aqc_add_update_mir_rule add_update_rule; 2987 struct ice_aqc_delete_mir_rule del_rule; 2988 struct ice_aqc_list_caps get_cap; 2989 struct ice_aqc_get_phy_caps get_phy; 2990 struct ice_aqc_set_phy_cfg set_phy; 2991 struct ice_aqc_restart_an restart_an; 2992 struct ice_aqc_dnl_get_status get_status; 2993 struct ice_aqc_dnl_run_command dnl_run; 2994 struct ice_aqc_dnl_call_command dnl_call; 2995 struct ice_aqc_dnl_read_write_command dnl_read_write; 2996 struct ice_aqc_dnl_read_write_response dnl_read_write_resp; 2997 struct ice_aqc_dnl_set_breakpoints_command dnl_set_brk; 2998 struct ice_aqc_dnl_read_log_command dnl_read_log; 2999 struct ice_aqc_dnl_read_log_response dnl_read_log_resp; 3000 struct ice_aqc_i2c read_write_i2c; 3001 struct ice_aqc_read_i2c_resp read_i2c_resp; 3002 struct ice_aqc_mdio read_write_mdio; 3003 struct ice_aqc_gpio_by_func read_write_gpio_by_func; 3004 struct ice_aqc_gpio read_write_gpio; 3005 struct ice_aqc_sw_gpio sw_read_write_gpio; 3006 struct ice_aqc_set_led set_led; 3007 struct ice_aqc_mdio read_mdio; 3008 struct ice_aqc_mdio write_mdio; 3009 struct ice_aqc_sff_eeprom read_write_sff_param; 3010 struct ice_aqc_set_port_id_led set_port_id_led; 3011 struct ice_aqc_get_port_options get_port_options; 3012 struct ice_aqc_set_port_option set_port_option; 3013 struct ice_aqc_get_sw_cfg get_sw_conf; 3014 struct ice_aqc_set_port_params set_port_params; 3015 struct ice_aqc_sw_rules sw_rules; 3016 struct ice_aqc_storm_cfg storm_conf; 3017 struct ice_aqc_get_topo get_topo; 3018 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 3019 struct ice_aqc_query_txsched_res query_sched_res; 3020 struct ice_aqc_query_node_to_root query_node_to_root; 3021 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd; 3022 struct ice_aqc_query_port_ets port_ets; 3023 struct ice_aqc_rl_profile rl_profile; 3024 struct ice_aqc_node_attr node_attr; 3025 struct ice_aqc_nvm nvm; 3026 struct ice_aqc_nvm_cfg nvm_cfg; 3027 struct ice_aqc_nvm_checksum nvm_checksum; 3028 struct ice_aqc_pf_vf_msg virt; 3029 struct ice_aqc_read_write_alt_direct read_write_alt_direct; 3030 struct ice_aqc_read_write_alt_indirect read_write_alt_indirect; 3031 struct ice_aqc_done_alt_write done_alt_write; 3032 struct ice_aqc_clear_port_alt_write clear_port_alt_write; 3033 struct ice_aqc_pfc_ignore pfc_ignore; 3034 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode; 3035 struct ice_aqc_set_dcb_params set_dcb_params; 3036 struct ice_aqc_lldp_get_mib lldp_get_mib; 3037 struct ice_aqc_lldp_set_mib_change lldp_set_event; 3038 struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv; 3039 struct ice_aqc_lldp_update_tlv lldp_update_tlv; 3040 struct ice_aqc_lldp_stop lldp_stop; 3041 struct ice_aqc_lldp_start lldp_start; 3042 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 3043 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 3044 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl; 3045 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 3046 struct ice_aqc_get_set_rss_key get_set_rss_key; 3047 struct ice_aqc_add_txqs add_txqs; 3048 struct ice_aqc_dis_txqs dis_txqs; 3049 struct ice_aqc_move_txqs move_txqs; 3050 struct ice_aqc_add_rdma_qset add_rdma_qset; 3051 struct ice_aqc_move_rdma_qset_cmd move_rdma_qset; 3052 struct ice_aqc_txqs_cleanup txqs_cleanup; 3053 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 3054 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 3055 struct ice_aqc_get_vsi_resp get_vsi_resp; 3056 struct ice_aqc_download_pkg download_pkg; 3057 struct ice_aqc_get_pkg_info_list get_pkg_info_list; 3058 struct ice_aqc_driver_shared_params drv_shared_params; 3059 struct ice_aqc_fw_log fw_log; 3060 struct ice_aqc_debug_dump_internals debug_dump; 3061 struct ice_aqc_set_mac_lb set_mac_lb; 3062 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 3063 struct ice_aqc_get_res_alloc get_res; 3064 struct ice_aqc_get_allocd_res_desc get_res_desc; 3065 struct ice_aqc_set_mac_cfg set_mac_cfg; 3066 struct ice_aqc_set_event_mask set_event_mask; 3067 struct ice_aqc_get_link_status get_link_status; 3068 struct ice_aqc_event_lan_overflow lan_overflow; 3069 struct ice_aqc_get_link_topo get_link_topo; 3070 struct ice_aqc_set_health_status_config 3071 set_health_status_config; 3072 struct ice_aqc_get_supported_health_status_codes 3073 get_supported_health_status_codes; 3074 struct ice_aqc_get_health_status get_health_status; 3075 struct ice_aqc_clear_health_status clear_health_status; 3076 struct ice_aqc_prog_topo_dev_nvm prog_topo_dev_nvm; 3077 struct ice_aqc_read_topo_dev_nvm read_topo_dev_nvm; 3078 struct ice_aqc_get_set_tx_topo get_set_tx_topo; 3079 } params; 3080 }; 3081 3082 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 3083 #define ICE_AQ_LG_BUF 512 3084 3085 /* Flags sub-structure 3086 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 3087 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 3088 */ 3089 3090 /* command flags and offsets */ 3091 #define ICE_AQ_FLAG_DD_S 0 3092 #define ICE_AQ_FLAG_CMP_S 1 3093 #define ICE_AQ_FLAG_ERR_S 2 3094 #define ICE_AQ_FLAG_VFE_S 3 3095 #define ICE_AQ_FLAG_LB_S 9 3096 #define ICE_AQ_FLAG_RD_S 10 3097 #define ICE_AQ_FLAG_VFC_S 11 3098 #define ICE_AQ_FLAG_BUF_S 12 3099 #define ICE_AQ_FLAG_SI_S 13 3100 #define ICE_AQ_FLAG_EI_S 14 3101 #define ICE_AQ_FLAG_FE_S 15 3102 3103 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */ 3104 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */ 3105 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 3106 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */ 3107 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 3108 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 3109 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */ 3110 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 3111 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 3112 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */ 3113 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */ 3114 3115 /* error codes */ 3116 enum ice_aq_err { 3117 ICE_AQ_RC_OK = 0, /* Success */ 3118 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 3119 ICE_AQ_RC_ENOENT = 2, /* No such element */ 3120 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */ 3121 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */ 3122 ICE_AQ_RC_EIO = 5, /* I/O error */ 3123 ICE_AQ_RC_ENXIO = 6, /* No such resource */ 3124 ICE_AQ_RC_E2BIG = 7, /* Arg too long */ 3125 ICE_AQ_RC_EAGAIN = 8, /* Try again */ 3126 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 3127 ICE_AQ_RC_EACCES = 10, /* Permission denied */ 3128 ICE_AQ_RC_EFAULT = 11, /* Bad address */ 3129 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 3130 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 3131 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 3132 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 3133 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 3134 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 3135 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */ 3136 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 3137 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 3138 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 3139 ICE_AQ_RC_EFBIG = 22, /* File too big */ 3140 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */ 3141 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 3142 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 3143 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 3144 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 3145 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 3146 ICE_AQ_RC_EACCES_BMCU = 29, /* BMC Update in progress */ 3147 }; 3148 3149 /* Admin Queue command opcodes */ 3150 enum ice_adminq_opc { 3151 /* AQ commands */ 3152 ice_aqc_opc_get_ver = 0x0001, 3153 ice_aqc_opc_driver_ver = 0x0002, 3154 ice_aqc_opc_q_shutdown = 0x0003, 3155 ice_aqc_opc_get_exp_err = 0x0005, 3156 3157 /* resource ownership */ 3158 ice_aqc_opc_req_res = 0x0008, 3159 ice_aqc_opc_release_res = 0x0009, 3160 3161 /* device/function capabilities */ 3162 ice_aqc_opc_list_func_caps = 0x000A, 3163 ice_aqc_opc_list_dev_caps = 0x000B, 3164 3165 /* manage MAC address */ 3166 ice_aqc_opc_manage_mac_read = 0x0107, 3167 ice_aqc_opc_manage_mac_write = 0x0108, 3168 3169 /* PXE */ 3170 ice_aqc_opc_clear_pxe_mode = 0x0110, 3171 3172 ice_aqc_opc_config_no_drop_policy = 0x0112, 3173 3174 /* internal switch commands */ 3175 ice_aqc_opc_get_sw_cfg = 0x0200, 3176 ice_aqc_opc_set_port_params = 0x0203, 3177 3178 /* Alloc/Free/Get Resources */ 3179 ice_aqc_opc_get_res_alloc = 0x0204, 3180 ice_aqc_opc_alloc_res = 0x0208, 3181 ice_aqc_opc_free_res = 0x0209, 3182 ice_aqc_opc_get_allocd_res_desc = 0x020A, 3183 ice_aqc_opc_set_vlan_mode_parameters = 0x020C, 3184 ice_aqc_opc_get_vlan_mode_parameters = 0x020D, 3185 3186 /* VSI commands */ 3187 ice_aqc_opc_add_vsi = 0x0210, 3188 ice_aqc_opc_update_vsi = 0x0211, 3189 ice_aqc_opc_get_vsi_params = 0x0212, 3190 ice_aqc_opc_free_vsi = 0x0213, 3191 3192 /* Mirroring rules - add/update, delete */ 3193 ice_aqc_opc_add_update_mir_rule = 0x0260, 3194 ice_aqc_opc_del_mir_rule = 0x0261, 3195 3196 /* storm configuration */ 3197 ice_aqc_opc_set_storm_cfg = 0x0280, 3198 ice_aqc_opc_get_storm_cfg = 0x0281, 3199 3200 /* switch rules population commands */ 3201 ice_aqc_opc_add_sw_rules = 0x02A0, 3202 ice_aqc_opc_update_sw_rules = 0x02A1, 3203 ice_aqc_opc_remove_sw_rules = 0x02A2, 3204 ice_aqc_opc_get_sw_rules = 0x02A3, 3205 ice_aqc_opc_clear_pf_cfg = 0x02A4, 3206 3207 /* DCB commands */ 3208 ice_aqc_opc_pfc_ignore = 0x0301, 3209 ice_aqc_opc_query_pfc_mode = 0x0302, 3210 ice_aqc_opc_set_pfc_mode = 0x0303, 3211 ice_aqc_opc_set_dcb_params = 0x0306, 3212 3213 /* transmit scheduler commands */ 3214 ice_aqc_opc_get_dflt_topo = 0x0400, 3215 ice_aqc_opc_add_sched_elems = 0x0401, 3216 ice_aqc_opc_cfg_sched_elems = 0x0403, 3217 ice_aqc_opc_get_sched_elems = 0x0404, 3218 ice_aqc_opc_move_sched_elems = 0x0408, 3219 ice_aqc_opc_suspend_sched_elems = 0x0409, 3220 ice_aqc_opc_resume_sched_elems = 0x040A, 3221 ice_aqc_opc_query_port_ets = 0x040E, 3222 ice_aqc_opc_delete_sched_elems = 0x040F, 3223 ice_aqc_opc_add_rl_profiles = 0x0410, 3224 ice_aqc_opc_query_rl_profiles = 0x0411, 3225 ice_aqc_opc_query_sched_res = 0x0412, 3226 ice_aqc_opc_query_node_to_root = 0x0413, 3227 ice_aqc_opc_cfg_l2_node_cgd = 0x0414, 3228 ice_aqc_opc_remove_rl_profiles = 0x0415, 3229 ice_aqc_opc_set_tx_topo = 0x0417, 3230 ice_aqc_opc_get_tx_topo = 0x0418, 3231 ice_aqc_opc_cfg_node_attr = 0x0419, 3232 ice_aqc_opc_query_node_attr = 0x041A, 3233 3234 /* PHY commands */ 3235 ice_aqc_opc_get_phy_caps = 0x0600, 3236 ice_aqc_opc_set_phy_cfg = 0x0601, 3237 ice_aqc_opc_set_mac_cfg = 0x0603, 3238 ice_aqc_opc_restart_an = 0x0605, 3239 ice_aqc_opc_get_link_status = 0x0607, 3240 ice_aqc_opc_set_event_mask = 0x0613, 3241 ice_aqc_opc_set_mac_lb = 0x0620, 3242 ice_aqc_opc_dnl_get_status = 0x0680, 3243 ice_aqc_opc_dnl_run = 0x0681, 3244 ice_aqc_opc_dnl_call = 0x0682, 3245 ice_aqc_opc_dnl_read_sto = 0x0683, 3246 ice_aqc_opc_dnl_write_sto = 0x0684, 3247 ice_aqc_opc_dnl_set_breakpoints = 0x0686, 3248 ice_aqc_opc_dnl_read_log = 0x0687, 3249 ice_aqc_opc_get_link_topo = 0x06E0, 3250 ice_aqc_opc_read_i2c = 0x06E2, 3251 ice_aqc_opc_write_i2c = 0x06E3, 3252 ice_aqc_opc_read_mdio = 0x06E4, 3253 ice_aqc_opc_write_mdio = 0x06E5, 3254 ice_aqc_opc_set_gpio_by_func = 0x06E6, 3255 ice_aqc_opc_get_gpio_by_func = 0x06E7, 3256 ice_aqc_opc_set_led = 0x06E8, 3257 ice_aqc_opc_set_port_id_led = 0x06E9, 3258 ice_aqc_opc_get_port_options = 0x06EA, 3259 ice_aqc_opc_set_port_option = 0x06EB, 3260 ice_aqc_opc_set_gpio = 0x06EC, 3261 ice_aqc_opc_get_gpio = 0x06ED, 3262 ice_aqc_opc_sff_eeprom = 0x06EE, 3263 ice_aqc_opc_sw_set_gpio = 0x06EF, 3264 ice_aqc_opc_sw_get_gpio = 0x06F0, 3265 ice_aqc_opc_prog_topo_dev_nvm = 0x06F2, 3266 ice_aqc_opc_read_topo_dev_nvm = 0x06F3, 3267 3268 /* NVM commands */ 3269 ice_aqc_opc_nvm_read = 0x0701, 3270 ice_aqc_opc_nvm_erase = 0x0702, 3271 ice_aqc_opc_nvm_write = 0x0703, 3272 ice_aqc_opc_nvm_cfg_read = 0x0704, 3273 ice_aqc_opc_nvm_cfg_write = 0x0705, 3274 ice_aqc_opc_nvm_checksum = 0x0706, 3275 ice_aqc_opc_nvm_write_activate = 0x0707, 3276 ice_aqc_opc_nvm_sr_dump = 0x0707, 3277 ice_aqc_opc_nvm_save_factory_settings = 0x0708, 3278 ice_aqc_opc_nvm_update_empr = 0x0709, 3279 ice_aqc_opc_nvm_pkg_data = 0x070A, 3280 ice_aqc_opc_nvm_pass_component_tbl = 0x070B, 3281 3282 /* PF/VF mailbox commands */ 3283 ice_mbx_opc_send_msg_to_pf = 0x0801, 3284 ice_mbx_opc_send_msg_to_vf = 0x0802, 3285 /* Alternate Structure Commands */ 3286 ice_aqc_opc_write_alt_direct = 0x0900, 3287 ice_aqc_opc_write_alt_indirect = 0x0901, 3288 ice_aqc_opc_read_alt_direct = 0x0902, 3289 ice_aqc_opc_read_alt_indirect = 0x0903, 3290 ice_aqc_opc_done_alt_write = 0x0904, 3291 ice_aqc_opc_clear_port_alt_write = 0x0906, 3292 /* LLDP commands */ 3293 ice_aqc_opc_lldp_get_mib = 0x0A00, 3294 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 3295 ice_aqc_opc_lldp_add_tlv = 0x0A02, 3296 ice_aqc_opc_lldp_update_tlv = 0x0A03, 3297 ice_aqc_opc_lldp_delete_tlv = 0x0A04, 3298 ice_aqc_opc_lldp_stop = 0x0A05, 3299 ice_aqc_opc_lldp_start = 0x0A06, 3300 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 3301 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 3302 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 3303 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A, 3304 ice_execute_pending_lldp_mib = 0x0A0B, 3305 3306 /* RSS commands */ 3307 ice_aqc_opc_set_rss_key = 0x0B02, 3308 ice_aqc_opc_set_rss_lut = 0x0B03, 3309 ice_aqc_opc_get_rss_key = 0x0B04, 3310 ice_aqc_opc_get_rss_lut = 0x0B05, 3311 3312 /* Tx queue handling commands/events */ 3313 ice_aqc_opc_add_txqs = 0x0C30, 3314 ice_aqc_opc_dis_txqs = 0x0C31, 3315 ice_aqc_opc_txqs_cleanup = 0x0C31, 3316 ice_aqc_opc_move_recfg_txqs = 0x0C32, 3317 ice_aqc_opc_add_rdma_qset = 0x0C33, 3318 ice_aqc_opc_move_rdma_qset = 0x0C34, 3319 3320 /* package commands */ 3321 ice_aqc_opc_download_pkg = 0x0C40, 3322 ice_aqc_opc_upload_section = 0x0C41, 3323 ice_aqc_opc_update_pkg = 0x0C42, 3324 ice_aqc_opc_get_pkg_info_list = 0x0C43, 3325 3326 ice_aqc_opc_driver_shared_params = 0x0C90, 3327 3328 /* Standalone Commands/Events */ 3329 ice_aqc_opc_event_lan_overflow = 0x1001, 3330 3331 /* debug commands */ 3332 ice_aqc_opc_debug_dump_internals = 0xFF08, 3333 3334 /* SystemDiagnostic commands */ 3335 ice_aqc_opc_set_health_status_config = 0xFF20, 3336 ice_aqc_opc_get_supported_health_status_codes = 0xFF21, 3337 ice_aqc_opc_get_health_status = 0xFF22, 3338 ice_aqc_opc_clear_health_status = 0xFF23, 3339 3340 /* FW Logging Commands */ 3341 ice_aqc_opc_fw_logs_config = 0xFF30, 3342 ice_aqc_opc_fw_logs_register = 0xFF31, 3343 ice_aqc_opc_fw_logs_query = 0xFF32, 3344 ice_aqc_opc_fw_logs_event = 0xFF33, 3345 ice_aqc_opc_fw_logs_get = 0xFF34, 3346 ice_aqc_opc_fw_logs_clear = 0xFF35 3347 }; 3348 3349 #endif /* _ICE_ADMINQ_CMD_H_ */ 3350