1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2020, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*$FreeBSD$*/ 32 33 #ifndef _ICE_ADMINQ_CMD_H_ 34 #define _ICE_ADMINQ_CMD_H_ 35 36 /* This header file defines the Admin Queue commands, error codes and 37 * descriptor format. It is shared between Firmware and Software. 38 */ 39 40 #define ICE_MAX_VSI 768 41 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 42 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 43 44 struct ice_aqc_generic { 45 __le32 param0; 46 __le32 param1; 47 __le32 addr_high; 48 __le32 addr_low; 49 }; 50 51 /* Get version (direct 0x0001) */ 52 struct ice_aqc_get_ver { 53 __le32 rom_ver; 54 __le32 fw_build; 55 u8 fw_branch; 56 u8 fw_major; 57 u8 fw_minor; 58 u8 fw_patch; 59 u8 api_branch; 60 u8 api_major; 61 u8 api_minor; 62 u8 api_patch; 63 }; 64 65 /* Send driver version (indirect 0x0002) */ 66 struct ice_aqc_driver_ver { 67 u8 major_ver; 68 u8 minor_ver; 69 u8 build_ver; 70 u8 subbuild_ver; 71 u8 reserved[4]; 72 __le32 addr_high; 73 __le32 addr_low; 74 }; 75 76 /* Queue Shutdown (direct 0x0003) */ 77 struct ice_aqc_q_shutdown { 78 u8 driver_unloading; 79 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 80 u8 reserved[15]; 81 }; 82 83 /* Get Expanded Error Code (0x0005, direct) */ 84 struct ice_aqc_get_exp_err { 85 __le32 reason; 86 #define ICE_AQC_EXPANDED_ERROR_NOT_PROVIDED 0xFFFFFFFF 87 __le32 identifier; 88 u8 rsvd[8]; 89 }; 90 91 /* Request resource ownership (direct 0x0008) 92 * Release resource ownership (direct 0x0009) 93 */ 94 struct ice_aqc_req_res { 95 __le16 res_id; 96 #define ICE_AQC_RES_ID_NVM 1 97 #define ICE_AQC_RES_ID_SDP 2 98 #define ICE_AQC_RES_ID_CHNG_LOCK 3 99 #define ICE_AQC_RES_ID_GLBL_LOCK 4 100 __le16 access_type; 101 #define ICE_AQC_RES_ACCESS_READ 1 102 #define ICE_AQC_RES_ACCESS_WRITE 2 103 104 /* Upon successful completion, FW writes this value and driver is 105 * expected to release resource before timeout. This value is provided 106 * in milliseconds. 107 */ 108 __le32 timeout; 109 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 110 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 111 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 112 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 113 /* For SDP: pin ID of the SDP */ 114 __le32 res_number; 115 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 116 __le16 status; 117 #define ICE_AQ_RES_GLBL_SUCCESS 0 118 #define ICE_AQ_RES_GLBL_IN_PROG 1 119 #define ICE_AQ_RES_GLBL_DONE 2 120 u8 reserved[2]; 121 }; 122 123 /* Get function capabilities (indirect 0x000A) 124 * Get device capabilities (indirect 0x000B) 125 */ 126 struct ice_aqc_list_caps { 127 u8 cmd_flags; 128 u8 pf_index; 129 u8 reserved[2]; 130 __le32 count; 131 __le32 addr_high; 132 __le32 addr_low; 133 }; 134 135 /* Device/Function buffer entry, repeated per reported capability */ 136 struct ice_aqc_list_caps_elem { 137 __le16 cap; 138 #define ICE_AQC_CAPS_SWITCHING_MODE 0x0001 139 #define ICE_AQC_CAPS_MANAGEABILITY_MODE 0x0002 140 #define ICE_AQC_CAPS_OS2BMC 0x0004 141 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 142 #define ICE_AQC_MAX_VALID_FUNCTIONS 0x8 143 #define ICE_AQC_CAPS_ALTERNATE_RAM 0x0006 144 #define ICE_AQC_CAPS_WOL_PROXY 0x0008 145 #define ICE_AQC_CAPS_SRIOV 0x0012 146 #define ICE_AQC_CAPS_VF 0x0013 147 #define ICE_AQC_CAPS_802_1QBG 0x0015 148 #define ICE_AQC_CAPS_802_1BR 0x0016 149 #define ICE_AQC_CAPS_VSI 0x0017 150 #define ICE_AQC_CAPS_DCB 0x0018 151 #define ICE_AQC_CAPS_RSVD 0x0021 152 #define ICE_AQC_CAPS_ISCSI 0x0022 153 #define ICE_AQC_CAPS_RSS 0x0040 154 #define ICE_AQC_CAPS_RXQS 0x0041 155 #define ICE_AQC_CAPS_TXQS 0x0042 156 #define ICE_AQC_CAPS_MSIX 0x0043 157 #define ICE_AQC_CAPS_MAX_MTU 0x0047 158 #define ICE_AQC_CAPS_NVM_VER 0x0048 159 #define ICE_AQC_CAPS_OROM_VER 0x004A 160 #define ICE_AQC_CAPS_NET_VER 0x004C 161 #define ICE_AQC_CAPS_CEM 0x00F2 162 #define ICE_AQC_CAPS_IWARP 0x0051 163 #define ICE_AQC_CAPS_LED 0x0061 164 #define ICE_AQC_CAPS_SDP 0x0062 165 #define ICE_AQC_CAPS_WR_CSR_PROT 0x0064 166 #define ICE_AQC_CAPS_LOGI_TO_PHYSI_PORT_MAP 0x0073 167 #define ICE_AQC_CAPS_SKU 0x0074 168 #define ICE_AQC_CAPS_PORT_MAP 0x0075 169 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 170 171 u8 major_ver; 172 u8 minor_ver; 173 /* Number of resources described by this capability */ 174 __le32 number; 175 /* Only meaningful for some types of resources */ 176 __le32 logical_id; 177 /* Only meaningful for some types of resources */ 178 __le32 phys_id; 179 __le64 rsvd1; 180 __le64 rsvd2; 181 }; 182 183 /* Manage MAC address, read command - indirect (0x0107) 184 * This struct is also used for the response 185 */ 186 struct ice_aqc_manage_mac_read { 187 __le16 flags; /* Zeroed by device driver */ 188 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 189 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 190 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 191 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 192 #define ICE_AQC_MAN_MAC_MC_MAG_EN BIT(8) 193 #define ICE_AQC_MAN_MAC_WOL_PRESERVE_ON_PFR BIT(9) 194 #define ICE_AQC_MAN_MAC_READ_S 4 195 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 196 u8 rsvd[2]; 197 u8 num_addr; /* Used in response */ 198 u8 rsvd1[3]; 199 __le32 addr_high; 200 __le32 addr_low; 201 }; 202 203 /* Response buffer format for manage MAC read command */ 204 struct ice_aqc_manage_mac_read_resp { 205 u8 lport_num; 206 u8 addr_type; 207 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 208 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 209 u8 mac_addr[ETH_ALEN]; 210 }; 211 212 /* Manage MAC address, write command - direct (0x0108) */ 213 struct ice_aqc_manage_mac_write { 214 u8 rsvd; 215 u8 flags; 216 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 217 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 218 #define ICE_AQC_MAN_MAC_WR_S 6 219 #define ICE_AQC_MAN_MAC_WR_M MAKEMASK(3, ICE_AQC_MAN_MAC_WR_S) 220 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 221 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 222 /* byte stream in network order */ 223 u8 mac_addr[ETH_ALEN]; 224 __le32 addr_high; 225 __le32 addr_low; 226 }; 227 228 /* Clear PXE Command and response (direct 0x0110) */ 229 struct ice_aqc_clear_pxe { 230 u8 rx_cnt; 231 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 232 u8 reserved[15]; 233 }; 234 235 /* Configure No-Drop Policy Command (direct 0x0112) */ 236 struct ice_aqc_config_no_drop_policy { 237 u8 opts; 238 #define ICE_AQC_FORCE_NO_DROP BIT(0) 239 u8 rsvd[15]; 240 }; 241 242 /* Get switch configuration (0x0200) */ 243 struct ice_aqc_get_sw_cfg { 244 /* Reserved for command and copy of request flags for response */ 245 __le16 flags; 246 /* First desc in case of command and next_elem in case of response 247 * In case of response, if it is not zero, means all the configuration 248 * was not returned and new command shall be sent with this value in 249 * the 'first desc' field 250 */ 251 __le16 element; 252 /* Reserved for command, only used for response */ 253 __le16 num_elems; 254 __le16 rsvd; 255 __le32 addr_high; 256 __le32 addr_low; 257 }; 258 259 /* Each entry in the response buffer is of the following type: */ 260 struct ice_aqc_get_sw_cfg_resp_elem { 261 /* VSI/Port Number */ 262 __le16 vsi_port_num; 263 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 264 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 265 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 266 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 267 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 268 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 269 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 270 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 271 272 /* SWID VSI/Port belongs to */ 273 __le16 swid; 274 275 /* Bit 14..0 : PF/VF number VSI belongs to 276 * Bit 15 : VF indication bit 277 */ 278 __le16 pf_vf_num; 279 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 280 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 281 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 282 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 283 }; 284 285 /* Set Port parameters, (direct, 0x0203) */ 286 struct ice_aqc_set_port_params { 287 __le16 cmd_flags; 288 #define ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS BIT(0) 289 #define ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS BIT(1) 290 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2) 291 __le16 bad_frame_vsi; 292 #define ICE_AQC_SET_P_PARAMS_VSI_S 0 293 #define ICE_AQC_SET_P_PARAMS_VSI_M (0x3FF << ICE_AQC_SET_P_PARAMS_VSI_S) 294 #define ICE_AQC_SET_P_PARAMS_VSI_VALID BIT(15) 295 __le16 swid; 296 #define ICE_AQC_SET_P_PARAMS_SWID_S 0 297 #define ICE_AQC_SET_P_PARAMS_SWID_M (0xFF << ICE_AQC_SET_P_PARAMS_SWID_S) 298 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S 8 299 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_M \ 300 (0x3F << ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S) 301 #define ICE_AQC_SET_P_PARAMS_IS_LOGI_PORT BIT(14) 302 #define ICE_AQC_SET_P_PARAMS_SWID_VALID BIT(15) 303 u8 reserved[10]; 304 }; 305 306 /* These resource type defines are used for all switch resource 307 * commands where a resource type is required, such as: 308 * Get Resource Allocation command (indirect 0x0204) 309 * Allocate Resources command (indirect 0x0208) 310 * Free Resources command (indirect 0x0209) 311 * Get Allocated Resource Descriptors Command (indirect 0x020A) 312 */ 313 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00 314 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01 315 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02 316 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 317 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 318 #define ICE_AQC_RES_TYPE_RECIPE 0x05 319 #define ICE_AQC_RES_TYPE_PROFILE 0x06 320 #define ICE_AQC_RES_TYPE_SWID 0x07 321 #define ICE_AQC_RES_TYPE_VSI 0x08 322 #define ICE_AQC_RES_TYPE_FLU 0x09 323 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A 324 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B 325 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C 326 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20 327 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 328 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 329 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 330 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30 331 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48 332 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49 333 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50 334 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51 335 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 336 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 337 /* Resource types 0x62-67 are reserved for Hash profile builder */ 338 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68 339 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69 340 341 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7) 342 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 343 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 344 345 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 346 347 #define ICE_AQC_RES_TYPE_S 0 348 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 349 350 /* Get Resource Allocation command (indirect 0x0204) */ 351 struct ice_aqc_get_res_alloc { 352 __le16 resp_elem_num; /* Used in response, reserved in command */ 353 u8 reserved[6]; 354 __le32 addr_high; 355 __le32 addr_low; 356 }; 357 358 /* Get Resource Allocation Response Buffer per response */ 359 struct ice_aqc_get_res_resp_elem { 360 __le16 res_type; /* Types defined above cmd 0x0204 */ 361 __le16 total_capacity; /* Resources available to all PF's */ 362 __le16 total_function; /* Resources allocated for a PF */ 363 __le16 total_shared; /* Resources allocated as shared */ 364 __le16 total_free; /* Resources un-allocated/not reserved by any PF */ 365 }; 366 367 /* Allocate Resources command (indirect 0x0208) 368 * Free Resources command (indirect 0x0209) 369 */ 370 struct ice_aqc_alloc_free_res_cmd { 371 __le16 num_entries; /* Number of Resource entries */ 372 u8 reserved[6]; 373 __le32 addr_high; 374 __le32 addr_low; 375 }; 376 377 /* Resource descriptor */ 378 struct ice_aqc_res_elem { 379 union { 380 __le16 sw_resp; 381 __le16 flu_resp; 382 } e; 383 }; 384 385 /* Buffer for Allocate/Free Resources commands */ 386 struct ice_aqc_alloc_free_res_elem { 387 __le16 res_type; /* Types defined above cmd 0x0204 */ 388 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 389 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 390 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 391 __le16 num_elems; 392 struct ice_aqc_res_elem elem[STRUCT_HACK_VAR_LEN]; 393 }; 394 395 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */ 396 struct ice_aqc_get_allocd_res_desc { 397 union { 398 struct { 399 __le16 res; /* Types defined above cmd 0x0204 */ 400 __le16 first_desc; 401 __le32 reserved; 402 } cmd; 403 struct { 404 __le16 res; 405 __le16 next_desc; 406 __le16 num_desc; 407 __le16 reserved; 408 } resp; 409 } ops; 410 __le32 addr_high; 411 __le32 addr_low; 412 }; 413 414 /* Add VSI (indirect 0x0210) 415 * Update VSI (indirect 0x0211) 416 * Get VSI (indirect 0x0212) 417 * Free VSI (indirect 0x0213) 418 */ 419 struct ice_aqc_add_get_update_free_vsi { 420 __le16 vsi_num; 421 #define ICE_AQ_VSI_NUM_S 0 422 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 423 #define ICE_AQ_VSI_IS_VALID BIT(15) 424 __le16 cmd_flags; 425 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 426 u8 vf_id; 427 u8 reserved; 428 __le16 vsi_flags; 429 #define ICE_AQ_VSI_TYPE_S 0 430 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 431 #define ICE_AQ_VSI_TYPE_VF 0x0 432 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 433 #define ICE_AQ_VSI_TYPE_PF 0x2 434 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 435 __le32 addr_high; 436 __le32 addr_low; 437 }; 438 439 /* Response descriptor for: 440 * Add VSI (indirect 0x0210) 441 * Update VSI (indirect 0x0211) 442 * Free VSI (indirect 0x0213) 443 */ 444 struct ice_aqc_add_update_free_vsi_resp { 445 __le16 vsi_num; 446 __le16 ext_status; 447 __le16 vsi_used; 448 __le16 vsi_free; 449 __le32 addr_high; 450 __le32 addr_low; 451 }; 452 453 struct ice_aqc_get_vsi_resp { 454 __le16 vsi_num; 455 u8 vf_id; 456 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values. 457 * These are found above in struct ice_aqc_add_get_update_free_vsi. 458 */ 459 u8 vsi_flags; 460 __le16 vsi_used; 461 __le16 vsi_free; 462 __le32 addr_high; 463 __le32 addr_low; 464 }; 465 466 struct ice_aqc_vsi_props { 467 __le16 valid_sections; 468 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 469 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 470 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 471 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 472 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 473 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 474 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 475 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 476 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 477 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 478 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 479 /* switch section */ 480 u8 sw_id; 481 u8 sw_flags; 482 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 483 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 484 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 485 u8 sw_flags2; 486 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 487 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \ 488 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 489 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 490 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 491 u8 veb_stat_id; 492 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 493 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 494 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 495 /* security section */ 496 u8 sec_flags; 497 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 498 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 499 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 500 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 501 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 502 u8 sec_reserved; 503 /* VLAN section */ 504 __le16 pvid; /* VLANS include priority bits */ 505 u8 pvlan_reserved[2]; 506 u8 vlan_flags; 507 #define ICE_AQ_VSI_VLAN_MODE_S 0 508 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S) 509 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1 510 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2 511 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3 512 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2) 513 #define ICE_AQ_VSI_VLAN_EMOD_S 3 514 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 515 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S) 516 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S) 517 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S) 518 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) 519 u8 pvlan_reserved2[3]; 520 /* ingress egress up sections */ 521 __le32 ingress_table; /* bitmap, 3 bits per up */ 522 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 523 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 524 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 525 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 526 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 527 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 528 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 529 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 530 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 531 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 532 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 533 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 534 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 535 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 536 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 537 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 538 __le32 egress_table; /* same defines as for ingress table */ 539 /* outer tags section */ 540 __le16 outer_tag; 541 u8 outer_tag_flags; 542 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0 543 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S) 544 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0 545 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1 546 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2 547 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 548 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 549 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 550 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 551 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 552 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 553 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4) 554 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6) 555 u8 outer_tag_reserved; 556 /* queue mapping section */ 557 __le16 mapping_flags; 558 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 559 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 560 __le16 q_mapping[16]; 561 #define ICE_AQ_VSI_Q_S 0 562 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 563 __le16 tc_mapping[8]; 564 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 565 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 566 #define ICE_AQ_VSI_TC_Q_NUM_S 11 567 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 568 /* queueing option section */ 569 u8 q_opt_rss; 570 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 571 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 572 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 573 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 574 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 575 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 576 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 577 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 578 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 579 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 580 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 581 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 582 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 583 u8 q_opt_tc; 584 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 585 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 586 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 587 u8 q_opt_flags; 588 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 589 u8 q_opt_reserved[3]; 590 /* outer up section */ 591 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 592 /* section 10 */ 593 __le16 sect_10_reserved; 594 /* flow director section */ 595 __le16 fd_options; 596 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 597 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 598 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 599 __le16 max_fd_fltr_dedicated; 600 __le16 max_fd_fltr_shared; 601 __le16 fd_def_q; 602 #define ICE_AQ_VSI_FD_DEF_Q_S 0 603 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 604 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 605 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 606 __le16 fd_report_opt; 607 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 608 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 609 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 610 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 611 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 612 /* PASID section */ 613 __le32 pasid_id; 614 #define ICE_AQ_VSI_PASID_ID_S 0 615 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 616 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 617 u8 reserved[24]; 618 }; 619 620 /* Add/update mirror rule - direct (0x0260) */ 621 #define ICE_AQC_RULE_ID_VALID_S 7 622 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S) 623 #define ICE_AQC_RULE_ID_S 0 624 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S) 625 626 /* Following defines to be used while processing caller specified mirror list 627 * of VSI indexes. 628 */ 629 /* Action: Byte.bit (1.7) 630 * 0 = Remove VSI from mirror rule 631 * 1 = Add VSI to mirror rule 632 */ 633 #define ICE_AQC_RULE_ACT_S 15 634 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S) 635 /* Action: 1.2:0.0 = Mirrored VSI */ 636 #define ICE_AQC_RULE_MIRRORED_VSI_S 0 637 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S) 638 639 /* This is to be used by add/update mirror rule Admin Queue command. 640 * In case of add mirror rule - if rule ID is specified as 641 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool. 642 * If specified rule_id is valid, then it is used. If specified rule_id 643 * is in use then new mirroring rule is added. 644 */ 645 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF 646 647 struct ice_aqc_add_update_mir_rule { 648 __le16 rule_id; 649 650 __le16 rule_type; 651 #define ICE_AQC_RULE_TYPE_S 0 652 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S) 653 /* VPORT ingress/egress */ 654 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1 655 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2 656 /* Physical port ingress mirroring. 657 * All traffic received by this port 658 */ 659 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6 660 /* Physical port egress mirroring. All traffic sent by this port */ 661 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7 662 663 /* Number of mirrored entries. 664 * The values are in the command buffer 665 */ 666 __le16 num_entries; 667 668 /* Destination VSI */ 669 __le16 dest; 670 __le32 addr_high; 671 __le32 addr_low; 672 }; 673 674 /* Delete mirror rule - direct(0x0261) */ 675 struct ice_aqc_delete_mir_rule { 676 __le16 rule_id; 677 __le16 rsvd; 678 679 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of 680 * the PF allocated resources, otherwise it is returned to the 681 * shared pool 682 */ 683 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0 684 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S) 685 __le16 flags; 686 687 u8 reserved[10]; 688 }; 689 690 /* Set/Get storm config - (direct 0x0280, 0x0281) */ 691 /* This structure holds get storm configuration response and same structure 692 * is used to perform set_storm_cfg 693 */ 694 struct ice_aqc_storm_cfg { 695 __le32 bcast_thresh_size; 696 __le32 mcast_thresh_size; 697 /* Bit 18:0 - Traffic upper threshold size 698 * Bit 31:19 - Reserved 699 */ 700 #define ICE_AQ_THRESHOLD_S 0 701 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S) 702 703 __le32 storm_ctrl_ctrl; 704 /* Bit 0: MDIPW - Drop Multicast packets in previous window 705 * Bit 1: MDICW - Drop multicast packets in current window 706 * Bit 2: BDIPW - Drop broadcast packets in previous window 707 * Bit 3: BDICW - Drop broadcast packets in current window 708 */ 709 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0) 710 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1) 711 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2) 712 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3) 713 /* Bit 7:5 : Reserved */ 714 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The 715 * interval size for applying ingress broadcast or multicast storm 716 * control. 717 */ 718 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8 719 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \ 720 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S) 721 __le32 reserved; 722 }; 723 724 #define ICE_MAX_NUM_RECIPES 64 725 726 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 727 */ 728 struct ice_aqc_sw_rules { 729 /* ops: add switch rules, referring the number of rules. 730 * ops: update switch rules, referring the number of filters 731 * ops: remove switch rules, referring the entry index. 732 * ops: get switch rules, referring to the number of filters. 733 */ 734 __le16 num_rules_fltr_entry_index; 735 u8 reserved[6]; 736 __le32 addr_high; 737 __le32 addr_low; 738 }; 739 740 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 741 * This structures describes the lookup rules and associated actions. "index" 742 * is returned as part of a response to a successful Add command, and can be 743 * used to identify the rule for Update/Get/Remove commands. 744 */ 745 struct ice_sw_rule_lkup_rx_tx { 746 __le16 recipe_id; 747 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 748 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 749 __le16 src; 750 __le32 act; 751 752 /* Bit 0:1 - Action type */ 753 #define ICE_SINGLE_ACT_TYPE_S 0x00 754 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 755 756 /* Bit 2 - Loop back enable 757 * Bit 3 - LAN enable 758 */ 759 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 760 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 761 762 /* Action type = 0 - Forward to VSI or VSI list */ 763 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 764 765 #define ICE_SINGLE_ACT_VSI_ID_S 4 766 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 767 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 768 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 769 /* This bit needs to be set if action is forward to VSI list */ 770 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 771 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 772 #define ICE_SINGLE_ACT_DROP BIT(18) 773 774 /* Action type = 1 - Forward to Queue of Queue group */ 775 #define ICE_SINGLE_ACT_TO_Q 0x1 776 #define ICE_SINGLE_ACT_Q_INDEX_S 4 777 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 778 #define ICE_SINGLE_ACT_Q_REGION_S 15 779 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 780 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 781 782 /* Action type = 2 - Prune */ 783 #define ICE_SINGLE_ACT_PRUNE 0x2 784 #define ICE_SINGLE_ACT_EGRESS BIT(15) 785 #define ICE_SINGLE_ACT_INGRESS BIT(16) 786 #define ICE_SINGLE_ACT_PRUNET BIT(17) 787 /* Bit 18 should be set to 0 for this action */ 788 789 /* Action type = 2 - Pointer */ 790 #define ICE_SINGLE_ACT_PTR 0x2 791 #define ICE_SINGLE_ACT_PTR_VAL_S 4 792 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 793 /* Bit 18 should be set to 1 */ 794 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 795 796 /* Action type = 3 - Other actions. Last two bits 797 * are other action identifier 798 */ 799 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 800 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 801 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 802 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 803 804 /* Bit 17:18 - Defines other actions */ 805 /* Other action = 0 - Mirror VSI */ 806 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 807 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 808 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 809 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 810 811 /* Other action = 3 - Set Stat count */ 812 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 813 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 814 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 815 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 816 817 __le16 index; /* The index of the rule in the lookup table */ 818 /* Length and values of the header to be matched per recipe or 819 * lookup-type 820 */ 821 __le16 hdr_len; 822 u8 hdr[STRUCT_HACK_VAR_LEN]; 823 }; 824 825 /* Add/Update/Remove large action command/response entry 826 * "index" is returned as part of a response to a successful Add command, and 827 * can be used to identify the action for Update/Get/Remove commands. 828 */ 829 struct ice_sw_rule_lg_act { 830 __le16 index; /* Index in large action table */ 831 __le16 size; 832 /* Max number of large actions */ 833 #define ICE_MAX_LG_ACT 4 834 /* Bit 0:1 - Action type */ 835 #define ICE_LG_ACT_TYPE_S 0 836 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 837 838 /* Action type = 0 - Forward to VSI or VSI list */ 839 #define ICE_LG_ACT_VSI_FORWARDING 0 840 #define ICE_LG_ACT_VSI_ID_S 3 841 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 842 #define ICE_LG_ACT_VSI_LIST_ID_S 3 843 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 844 /* This bit needs to be set if action is forward to VSI list */ 845 #define ICE_LG_ACT_VSI_LIST BIT(13) 846 847 #define ICE_LG_ACT_VALID_BIT BIT(16) 848 849 /* Action type = 1 - Forward to Queue of Queue group */ 850 #define ICE_LG_ACT_TO_Q 0x1 851 #define ICE_LG_ACT_Q_INDEX_S 3 852 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 853 #define ICE_LG_ACT_Q_REGION_S 14 854 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 855 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 856 857 /* Action type = 2 - Prune */ 858 #define ICE_LG_ACT_PRUNE 0x2 859 #define ICE_LG_ACT_EGRESS BIT(14) 860 #define ICE_LG_ACT_INGRESS BIT(15) 861 #define ICE_LG_ACT_PRUNET BIT(16) 862 863 /* Action type = 3 - Mirror VSI */ 864 #define ICE_LG_OTHER_ACT_MIRROR 0x3 865 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 866 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 867 868 /* Action type = 5 - Generic Value */ 869 #define ICE_LG_ACT_GENERIC 0x5 870 #define ICE_LG_ACT_GENERIC_VALUE_S 3 871 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 872 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 873 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 874 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 875 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 876 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 877 878 /* Action = 7 - Set Stat count */ 879 #define ICE_LG_ACT_STAT_COUNT 0x7 880 #define ICE_LG_ACT_STAT_COUNT_S 3 881 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 882 __le32 act[STRUCT_HACK_VAR_LEN]; /* array of size for actions */ 883 }; 884 885 /* Add/Update/Remove VSI list command/response entry 886 * "index" is returned as part of a response to a successful Add command, and 887 * can be used to identify the VSI list for Update/Get/Remove commands. 888 */ 889 struct ice_sw_rule_vsi_list { 890 __le16 index; /* Index of VSI/Prune list */ 891 __le16 number_vsi; 892 __le16 vsi[STRUCT_HACK_VAR_LEN]; /* Array of number_vsi VSI numbers */ 893 }; 894 895 #pragma pack(1) 896 /* Query VSI list command/response entry */ 897 struct ice_sw_rule_vsi_list_query { 898 __le16 index; 899 ice_declare_bitmap(vsi_list, ICE_MAX_VSI); 900 }; 901 #pragma pack() 902 903 #pragma pack(1) 904 /* Add switch rule response: 905 * Content of return buffer is same as the input buffer. The status field and 906 * LUT index are updated as part of the response 907 */ 908 struct ice_aqc_sw_rules_elem { 909 __le16 type; /* Switch rule type, one of T_... */ 910 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 911 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 912 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 913 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 914 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 915 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 916 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 917 __le16 status; 918 union { 919 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; 920 struct ice_sw_rule_lg_act lg_act; 921 struct ice_sw_rule_vsi_list vsi_list; 922 struct ice_sw_rule_vsi_list_query vsi_list_query; 923 } pdata; 924 }; 925 926 #pragma pack() 927 928 /* PFC Ignore (direct 0x0301) 929 * The command and response use the same descriptor structure 930 */ 931 struct ice_aqc_pfc_ignore { 932 u8 tc_bitmap; 933 u8 cmd_flags; /* unused in response */ 934 #define ICE_AQC_PFC_IGNORE_SET BIT(7) 935 #define ICE_AQC_PFC_IGNORE_CLEAR 0 936 u8 reserved[14]; 937 }; 938 939 /* Set PFC Mode (direct 0x0303) 940 * Query PFC Mode (direct 0x0302) 941 */ 942 struct ice_aqc_set_query_pfc_mode { 943 u8 pfc_mode; 944 /* For Set Command response, reserved in all other cases */ 945 #define ICE_AQC_PFC_NOT_CONFIGURED 0 946 /* For Query Command response, reserved in all other cases */ 947 #define ICE_AQC_DCB_DIS 0 948 #define ICE_AQC_PFC_VLAN_BASED_PFC 1 949 #define ICE_AQC_PFC_DSCP_BASED_PFC 2 950 u8 rsvd[15]; 951 }; 952 953 /* Set DCB Parameters (direct 0x0306) */ 954 struct ice_aqc_set_dcb_params { 955 u8 cmd_flags; /* unused in response */ 956 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0) 957 #define ICE_AQC_PERSIST_DCB_CFG BIT(1) 958 u8 valid_flags; /* unused in response */ 959 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0) 960 #define ICE_AQC_PERSIST_DCB_CFG_VALID BIT(1) 961 u8 rsvd[14]; 962 }; 963 964 /* Get Default Topology (indirect 0x0400) */ 965 struct ice_aqc_get_topo { 966 u8 port_num; 967 u8 num_branches; 968 __le16 reserved1; 969 __le32 reserved2; 970 __le32 addr_high; 971 __le32 addr_low; 972 }; 973 974 /* Update TSE (indirect 0x0403) 975 * Get TSE (indirect 0x0404) 976 * Add TSE (indirect 0x0401) 977 * Delete TSE (indirect 0x040F) 978 * Move TSE (indirect 0x0408) 979 * Suspend Nodes (indirect 0x0409) 980 * Resume Nodes (indirect 0x040A) 981 */ 982 struct ice_aqc_sched_elem_cmd { 983 __le16 num_elem_req; /* Used by commands */ 984 __le16 num_elem_resp; /* Used by responses */ 985 __le32 reserved; 986 __le32 addr_high; 987 __le32 addr_low; 988 }; 989 990 struct ice_aqc_txsched_move_grp_info_hdr { 991 __le32 src_parent_teid; 992 __le32 dest_parent_teid; 993 __le16 num_elems; 994 __le16 reserved; 995 }; 996 997 struct ice_aqc_move_elem { 998 struct ice_aqc_txsched_move_grp_info_hdr hdr; 999 __le32 teid[STRUCT_HACK_VAR_LEN]; 1000 }; 1001 1002 struct ice_aqc_elem_info_bw { 1003 __le16 bw_profile_idx; 1004 __le16 bw_alloc; 1005 }; 1006 1007 struct ice_aqc_txsched_elem { 1008 u8 elem_type; /* Special field, reserved for some aq calls */ 1009 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 1010 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 1011 #define ICE_AQC_ELEM_TYPE_TC 0x2 1012 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 1013 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 1014 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 1015 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 1016 u8 valid_sections; 1017 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 1018 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 1019 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 1020 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 1021 u8 generic; 1022 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 1023 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 1024 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 1025 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 1026 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 1027 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 1028 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 1029 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 1030 u8 flags; /* Special field, reserved for some aq calls */ 1031 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 1032 struct ice_aqc_elem_info_bw cir_bw; 1033 struct ice_aqc_elem_info_bw eir_bw; 1034 __le16 srl_id; 1035 __le16 reserved2; 1036 }; 1037 1038 struct ice_aqc_txsched_elem_data { 1039 __le32 parent_teid; 1040 __le32 node_teid; 1041 struct ice_aqc_txsched_elem data; 1042 }; 1043 1044 struct ice_aqc_txsched_topo_grp_info_hdr { 1045 __le32 parent_teid; 1046 __le16 num_elems; 1047 __le16 reserved2; 1048 }; 1049 1050 struct ice_aqc_add_elem { 1051 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1052 struct ice_aqc_txsched_elem_data generic[STRUCT_HACK_VAR_LEN]; 1053 }; 1054 1055 struct ice_aqc_get_topo_elem { 1056 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1057 struct ice_aqc_txsched_elem_data 1058 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1059 }; 1060 1061 struct ice_aqc_delete_elem { 1062 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1063 __le32 teid[STRUCT_HACK_VAR_LEN]; 1064 }; 1065 1066 /* Query Port ETS (indirect 0x040E) 1067 * 1068 * This indirect command is used to query port TC node configuration. 1069 */ 1070 struct ice_aqc_query_port_ets { 1071 __le32 port_teid; 1072 __le32 reserved; 1073 __le32 addr_high; 1074 __le32 addr_low; 1075 }; 1076 1077 struct ice_aqc_port_ets_elem { 1078 u8 tc_valid_bits; 1079 u8 reserved[3]; 1080 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 1081 __le32 up2tc; 1082 u8 tc_bw_share[8]; 1083 __le32 port_eir_prof_id; 1084 __le32 port_cir_prof_id; 1085 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 1086 __le32 tc_node_prio; 1087 #define ICE_TC_NODE_PRIO_S 0x4 1088 u8 reserved1[4]; 1089 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 1090 }; 1091 1092 /* Rate limiting profile for 1093 * Add RL profile (indirect 0x0410) 1094 * Query RL profile (indirect 0x0411) 1095 * Remove RL profile (indirect 0x0415) 1096 * These indirect commands acts on single or multiple 1097 * RL profiles with specified data. 1098 */ 1099 struct ice_aqc_rl_profile { 1100 __le16 num_profiles; 1101 __le16 num_processed; /* Only for response. Reserved in Command. */ 1102 u8 reserved[4]; 1103 __le32 addr_high; 1104 __le32 addr_low; 1105 }; 1106 1107 struct ice_aqc_rl_profile_elem { 1108 u8 level; 1109 u8 flags; 1110 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 1111 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 1112 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 1113 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 1114 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 1115 /* The following flag is used for Query RL Profile Data */ 1116 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 1117 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 1118 1119 __le16 profile_id; 1120 __le16 max_burst_size; 1121 __le16 rl_multiply; 1122 __le16 wake_up_calc; 1123 __le16 rl_encode; 1124 }; 1125 1126 /* Configure L2 Node CGD (indirect 0x0414) 1127 * This indirect command allows configuring a congestion domain for given L2 1128 * node TEIDs in the scheduler topology. 1129 */ 1130 struct ice_aqc_cfg_l2_node_cgd { 1131 __le16 num_l2_nodes; 1132 u8 reserved[6]; 1133 __le32 addr_high; 1134 __le32 addr_low; 1135 }; 1136 1137 struct ice_aqc_cfg_l2_node_cgd_elem { 1138 __le32 node_teid; 1139 u8 cgd; 1140 u8 reserved[3]; 1141 }; 1142 1143 /* Query Scheduler Resource Allocation (indirect 0x0412) 1144 * This indirect command retrieves the scheduler resources allocated by 1145 * EMP Firmware to the given PF. 1146 */ 1147 struct ice_aqc_query_txsched_res { 1148 u8 reserved[8]; 1149 __le32 addr_high; 1150 __le32 addr_low; 1151 }; 1152 1153 struct ice_aqc_generic_sched_props { 1154 __le16 phys_levels; 1155 __le16 logical_levels; 1156 u8 flattening_bitmap; 1157 u8 max_device_cgds; 1158 u8 max_pf_cgds; 1159 u8 rsvd0; 1160 __le16 rdma_qsets; 1161 u8 rsvd1[22]; 1162 }; 1163 1164 struct ice_aqc_layer_props { 1165 u8 logical_layer; 1166 u8 chunk_size; 1167 __le16 max_device_nodes; 1168 __le16 max_pf_nodes; 1169 u8 rsvd0[4]; 1170 __le16 max_sibl_grp_sz; 1171 __le16 max_cir_rl_profiles; 1172 __le16 max_eir_rl_profiles; 1173 __le16 max_srl_profiles; 1174 u8 rsvd1[14]; 1175 }; 1176 1177 struct ice_aqc_query_txsched_res_resp { 1178 struct ice_aqc_generic_sched_props sched_props; 1179 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1180 }; 1181 1182 /* Query Node to Root Topology (indirect 0x0413) 1183 * This command uses ice_aqc_get_elem as its data buffer. 1184 */ 1185 struct ice_aqc_query_node_to_root { 1186 __le32 teid; 1187 __le32 num_nodes; /* Response only */ 1188 __le32 addr_high; 1189 __le32 addr_low; 1190 }; 1191 1192 /* Get PHY capabilities (indirect 0x0600) */ 1193 struct ice_aqc_get_phy_caps { 1194 u8 lport_num; 1195 u8 reserved; 1196 __le16 param0; 1197 /* 18.0 - Report qualified modules */ 1198 #define ICE_AQC_GET_PHY_RQM BIT(0) 1199 /* 18.1 - 18.2 : Report mode 1200 * 00b - Report NVM capabilities 1201 * 01b - Report topology capabilities 1202 * 10b - Report SW configured 1203 */ 1204 #define ICE_AQC_REPORT_MODE_S 1 1205 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S) 1206 #define ICE_AQC_REPORT_NVM_CAP 0 1207 #define ICE_AQC_REPORT_TOPO_CAP BIT(1) 1208 #define ICE_AQC_REPORT_SW_CFG BIT(2) 1209 __le32 reserved1; 1210 __le32 addr_high; 1211 __le32 addr_low; 1212 }; 1213 1214 /* This is #define of PHY type (Extended): 1215 * The first set of defines is for phy_type_low. 1216 */ 1217 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 1218 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 1219 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 1220 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 1221 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 1222 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 1223 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 1224 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 1225 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 1226 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 1227 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 1228 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 1229 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 1230 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 1231 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 1232 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 1233 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 1234 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 1235 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 1236 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 1237 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 1238 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 1239 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 1240 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 1241 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 1242 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 1243 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 1244 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 1245 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 1246 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 1247 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 1248 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 1249 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 1250 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 1251 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 1252 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 1253 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 1254 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 1255 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 1256 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 1257 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 1258 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 1259 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 1260 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 1261 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 1262 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 1263 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 1264 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 1265 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 1266 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 1267 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 1268 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 1269 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 1270 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 1271 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 1272 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 1273 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 1274 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 1275 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 1276 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 1277 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 1278 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 1279 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 1280 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 1281 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 1282 /* The second set of defines is for phy_type_high. */ 1283 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 1284 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 1285 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 1286 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 1287 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 1288 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 5 1289 1290 struct ice_aqc_get_phy_caps_data { 1291 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1292 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1293 u8 caps; 1294 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 1295 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 1296 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 1297 #define ICE_AQC_PHY_EN_LINK BIT(3) 1298 #define ICE_AQC_PHY_AN_MODE BIT(4) 1299 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5) 1300 #define ICE_AQC_PHY_EN_LESM BIT(6) 1301 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 1302 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0) 1303 u8 low_power_ctrl_an; 1304 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 1305 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1) 1306 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2) 1307 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3) 1308 __le16 eee_cap; 1309 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1310 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1311 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1312 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1313 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1314 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1315 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1316 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7) 1317 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8) 1318 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9) 1319 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10) 1320 __le16 eeer_value; 1321 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1322 u8 phy_fw_ver[8]; 1323 u8 link_fec_options; 1324 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1325 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1326 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1327 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1328 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1329 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1330 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1331 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0) 1332 u8 module_compliance_enforcement; 1333 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 1334 u8 extended_compliance_code; 1335 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1336 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1337 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1338 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1339 #define ICE_AQC_MOD_TYPE_IDENT 1 1340 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1341 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1342 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1343 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1344 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1345 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1346 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1347 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1348 u8 qualified_module_count; 1349 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1350 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1351 struct { 1352 u8 v_oui[3]; 1353 u8 rsvd3; 1354 u8 v_part[16]; 1355 __le32 v_rev; 1356 __le64 rsvd4; 1357 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1358 }; 1359 1360 /* Set PHY capabilities (direct 0x0601) 1361 * NOTE: This command must be followed by setup link and restart auto-neg 1362 */ 1363 struct ice_aqc_set_phy_cfg { 1364 u8 lport_num; 1365 u8 reserved[7]; 1366 __le32 addr_high; 1367 __le32 addr_low; 1368 }; 1369 1370 /* Set PHY config command data structure */ 1371 struct ice_aqc_set_phy_cfg_data { 1372 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1373 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1374 u8 caps; 1375 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0) 1376 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1377 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1378 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1379 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1380 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1381 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1382 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1383 u8 low_power_ctrl_an; 1384 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1385 __le16 eeer_value; 1386 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1387 u8 module_compliance_enforcement; 1388 }; 1389 1390 /* Set MAC Config command data structure (direct 0x0603) */ 1391 struct ice_aqc_set_mac_cfg { 1392 __le16 max_frame_size; 1393 u8 params; 1394 #define ICE_AQ_SET_MAC_PACE_S 3 1395 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1396 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1397 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1398 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1399 u8 tx_tmr_priority; 1400 __le16 tx_tmr_value; 1401 __le16 fc_refresh_threshold; 1402 u8 drop_opts; 1403 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1404 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1405 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1406 u8 reserved[7]; 1407 }; 1408 1409 /* Restart AN command data structure (direct 0x0605) 1410 * Also used for response, with only the lport_num field present. 1411 */ 1412 struct ice_aqc_restart_an { 1413 u8 lport_num; 1414 u8 reserved; 1415 u8 cmd_flags; 1416 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1417 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1418 u8 reserved2[13]; 1419 }; 1420 1421 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1422 struct ice_aqc_get_link_status { 1423 u8 lport_num; 1424 u8 reserved; 1425 __le16 cmd_flags; 1426 #define ICE_AQ_LSE_M 0x3 1427 #define ICE_AQ_LSE_NOP 0x0 1428 #define ICE_AQ_LSE_DIS 0x2 1429 #define ICE_AQ_LSE_ENA 0x3 1430 /* only response uses this flag */ 1431 #define ICE_AQ_LSE_IS_ENABLED 0x1 1432 __le32 reserved2; 1433 __le32 addr_high; 1434 __le32 addr_low; 1435 }; 1436 1437 /* Get link status response data structure, also used for Link Status Event */ 1438 struct ice_aqc_get_link_status_data { 1439 u8 topo_media_conflict; 1440 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1441 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1442 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1443 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1444 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1445 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1446 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1447 u8 link_cfg_err; 1448 #define ICE_AQ_LINK_CFG_ERR BIT(0) 1449 #define ICE_AQ_LINK_ACT_PORT_OPT_INVAL BIT(2) 1450 #define ICE_AQ_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3) 1451 #define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR BIT(4) 1452 u8 link_info; 1453 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1454 #define ICE_AQ_LINK_FAULT BIT(1) 1455 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1456 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1457 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1458 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1459 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1460 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1461 u8 an_info; 1462 #define ICE_AQ_AN_COMPLETED BIT(0) 1463 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1464 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1465 #define ICE_AQ_FEC_EN BIT(3) 1466 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1467 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1468 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1469 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1470 u8 ext_info; 1471 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1472 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1473 /* Port Tx Suspended */ 1474 #define ICE_AQ_LINK_TX_S 2 1475 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1476 #define ICE_AQ_LINK_TX_ACTIVE 0 1477 #define ICE_AQ_LINK_TX_DRAINED 1 1478 #define ICE_AQ_LINK_TX_FLUSHED 3 1479 u8 lb_status; 1480 #define ICE_AQ_LINK_LB_PHY_LCL BIT(0) 1481 #define ICE_AQ_LINK_LB_PHY_RMT BIT(1) 1482 #define ICE_AQ_LINK_LB_MAC_LCL BIT(2) 1483 #define ICE_AQ_LINK_LB_PHY_IDX_S 3 1484 #define ICE_AQ_LINK_LB_PHY_IDX_M (0x7 << ICE_AQ_LB_PHY_IDX_S) 1485 __le16 max_frame_size; 1486 u8 cfg; 1487 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1488 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1489 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1490 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0) 1491 /* Pacing Config */ 1492 #define ICE_AQ_CFG_PACING_S 3 1493 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1494 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1495 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1496 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1497 /* External Device Power Ability */ 1498 u8 power_desc; 1499 #define ICE_AQ_PWR_CLASS_M 0x3 1500 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1501 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1502 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1503 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1504 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1505 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1506 __le16 link_speed; 1507 #define ICE_AQ_LINK_SPEED_M 0x7FF 1508 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1509 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1510 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1511 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1512 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1513 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1514 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1515 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1516 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1517 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1518 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1519 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1520 __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1521 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1522 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1523 }; 1524 1525 /* Set event mask command (direct 0x0613) */ 1526 struct ice_aqc_set_event_mask { 1527 u8 lport_num; 1528 u8 reserved[7]; 1529 __le16 event_mask; 1530 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1531 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1532 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1533 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1534 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1535 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1536 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1537 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1538 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1539 #define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10) 1540 #define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11) 1541 u8 reserved1[6]; 1542 }; 1543 1544 /* Set PHY Loopback command (direct 0x0619) */ 1545 struct ice_aqc_set_phy_lb { 1546 u8 lport_num; 1547 u8 lport_num_valid; 1548 #define ICE_AQ_PHY_LB_PORT_NUM_VALID BIT(0) 1549 u8 phy_index; 1550 u8 lb_mode; 1551 #define ICE_AQ_PHY_LB_EN BIT(0) 1552 #define ICE_AQ_PHY_LB_TYPE_M BIT(1) 1553 #define ICE_AQ_PHY_LB_TYPE_LOCAL 0 1554 #define ICE_AQ_PHY_LB_TYPE_REMOTE ICE_AQ_PHY_LB_TYPE_M 1555 #define ICE_AQ_PHY_LB_LEVEL_M BIT(2) 1556 #define ICE_AQ_PHY_LB_LEVEL_PMD 0 1557 #define ICE_AQ_PHY_LB_LEVEL_PCS ICE_AQ_PHY_LB_LEVEL_M 1558 u8 reserved2[12]; 1559 }; 1560 1561 /* Set MAC Loopback command (direct 0x0620) */ 1562 struct ice_aqc_set_mac_lb { 1563 u8 lb_mode; 1564 #define ICE_AQ_MAC_LB_EN BIT(0) 1565 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1566 u8 reserved[15]; 1567 }; 1568 1569 /* DNL Get Status command (indirect 0x0680) 1570 * Structure used for the response, the command uses the generic 1571 * ice_aqc_generic struct to pass a buffer address to the FW. 1572 */ 1573 struct ice_aqc_dnl_get_status { 1574 u8 ctx; 1575 u8 status; 1576 #define ICE_AQ_DNL_STATUS_IDLE 0x0 1577 #define ICE_AQ_DNL_STATUS_RESERVED 0x1 1578 #define ICE_AQ_DNL_STATUS_STOPPED 0x2 1579 #define ICE_AQ_DNL_STATUS_FATAL 0x3 /* Fatal DNL engine error */ 1580 #define ICE_AQ_DNL_SRC_S 3 1581 #define ICE_AQ_DNL_SRC_M (0x3 << ICE_AQ_DNL_SRC_S) 1582 #define ICE_AQ_DNL_SRC_NVM (0x0 << ICE_AQ_DNL_SRC_S) 1583 #define ICE_AQ_DNL_SRC_NVM_SCRATCH (0x1 << ICE_AQ_DNL_SRC_S) 1584 u8 stack_ptr; 1585 #define ICE_AQ_DNL_ST_PTR_S 0x0 1586 #define ICE_AQ_DNL_ST_PTR_M (0x7 << ICE_AQ_DNL_ST_PTR_S) 1587 u8 engine_flags; 1588 #define ICE_AQ_DNL_FLAGS_ERROR BIT(2) 1589 #define ICE_AQ_DNL_FLAGS_NEGATIVE BIT(3) 1590 #define ICE_AQ_DNL_FLAGS_OVERFLOW BIT(4) 1591 #define ICE_AQ_DNL_FLAGS_ZERO BIT(5) 1592 #define ICE_AQ_DNL_FLAGS_CARRY BIT(6) 1593 #define ICE_AQ_DNL_FLAGS_JUMP BIT(7) 1594 __le16 pc; 1595 __le16 activity_id; 1596 __le32 addr_high; 1597 __le32 addr_low; 1598 }; 1599 1600 struct ice_aqc_dnl_get_status_data { 1601 __le16 activity_err_code; 1602 __le16 act_err_code; 1603 #define ICE_AQ_DNL_ACT_ERR_SUCCESS 0x0000 /* no error */ 1604 #define ICE_AQ_DNL_ACT_ERR_PARSE 0x8001 /* NVM parse error */ 1605 #define ICE_AQ_DNL_ACT_ERR_UNSUPPORTED 0x8002 /* unsupported action */ 1606 #define ICE_AQ_DNL_ACT_ERR_NOT_FOUND 0x8003 /* activity not found */ 1607 #define ICE_AQ_DNL_ACT_ERR_BAD_JUMP 0x8004 /* an illegal jump */ 1608 #define ICE_AQ_DNL_ACT_ERR_PSTO_OVER 0x8005 /* persistent store overflow */ 1609 #define ICE_AQ_DNL_ACT_ERR_ST_OVERFLOW 0x8006 /* stack overflow */ 1610 #define ICE_AQ_DNL_ACT_ERR_TIMEOUT 0x8007 /* activity timeout */ 1611 #define ICE_AQ_DNL_ACT_ERR_BREAK 0x0008 /* stopped at breakpoint */ 1612 #define ICE_AQ_DNL_ACT_ERR_INVAL_ARG 0x0101 /* invalid action argument */ 1613 __le32 execution_time; /* in nanoseconds */ 1614 __le16 lib_ver; 1615 u8 psto_local_sz; 1616 u8 psto_global_sz; 1617 u8 stack_sz; 1618 #define ICE_AQ_DNL_STACK_SZ_S 0 1619 #define ICE_AQ_DNL_STACK_SZ_M (0xF << ICE_AQ_DNL_STACK_SZ_S) 1620 u8 port_count; 1621 #define ICE_AQ_DNL_PORT_CNT_S 0 1622 #define ICE_AQ_DNL_PORT_CNT_M (0x1F << ICE_AQ_DNL_PORT_CNT_S) 1623 __le16 act_cache_cntr; 1624 u32 i2c_clk_cntr; 1625 u32 mdio_clk_cntr; 1626 u32 sb_iosf_clk_cntr; 1627 }; 1628 1629 /* DNL run command (direct 0x0681) */ 1630 struct ice_aqc_dnl_run_command { 1631 u8 reserved0; 1632 u8 command; 1633 #define ICE_AQ_DNL_CMD_S 0 1634 #define ICE_AQ_DNL_CMD_M (0x7 << ICE_AQ_DNL_CMD_S) 1635 #define ICE_AQ_DNL_CMD_RESET 0x0 1636 #define ICE_AQ_DNL_CMD_RUN 0x1 1637 #define ICE_AQ_DNL_CMD_STEP 0x3 1638 #define ICE_AQ_DNL_CMD_ABORT 0x4 1639 #define ICE_AQ_DNL_CMD_SET_PC 0x7 1640 #define ICE_AQ_DNL_CMD_SRC_S 3 1641 #define ICE_AQ_DNL_CMD_SRC_M (0x3 << ICE_AQ_DNL_CMD_SRC_S) 1642 #define ICE_AQ_DNL_CMD_SRC_DNL 0x0 1643 #define ICE_AQ_DNL_CMD_SRC_SCRATCH 0x1 1644 __le16 new_pc; 1645 u8 reserved1[12]; 1646 }; 1647 1648 /* DNL call command (indirect 0x0682) 1649 * Struct is used for both command and response 1650 */ 1651 struct ice_aqc_dnl_call_command { 1652 u8 ctx; /* Used in command, reserved in response */ 1653 u8 reserved; 1654 __le16 activity_id; 1655 __le32 reserved1; 1656 __le32 addr_high; 1657 __le32 addr_low; 1658 }; 1659 1660 /* DNL call command/response buffer (indirect 0x0682) */ 1661 struct ice_aqc_dnl_call { 1662 __le32 stores[4]; 1663 }; 1664 1665 /* Used for both commands: 1666 * DNL read sto command (indirect 0x0683) 1667 * DNL write sto command (indirect 0x0684) 1668 */ 1669 struct ice_aqc_dnl_read_write_command { 1670 u8 ctx; 1671 u8 sto_sel; /* STORE select */ 1672 #define ICE_AQC_DNL_STORE_SELECT_STORE 0x0 1673 #define ICE_AQC_DNL_STORE_SELECT_PSTO 0x1 1674 #define ICE_AQC_DNL_STORE_SELECT_STACK 0x2 1675 __le16 offset; 1676 __le32 data; /* Used for write sto only */ 1677 __le32 addr_high; /* Used for read sto only */ 1678 __le32 addr_low; /* Used for read sto only */ 1679 }; 1680 1681 /* Used for both command responses: 1682 * DNL read sto response (indirect 0x0683) 1683 * DNL write sto response (indirect 0x0684) 1684 */ 1685 struct ice_aqc_dnl_read_write_response { 1686 u8 reserved; 1687 u8 status; /* Reserved for read command */ 1688 __le16 size; /* Reserved for write command */ 1689 __le32 data; /* Reserved for write command */ 1690 __le32 addr_high; /* Reserved for write command */ 1691 __le32 addr_low; /* Reserved for write command */ 1692 }; 1693 1694 /* DNL set breakpoints command (indirect 0x0686) */ 1695 struct ice_aqc_dnl_set_breakpoints_command { 1696 __le32 reserved[2]; 1697 __le32 addr_high; 1698 __le32 addr_low; 1699 }; 1700 1701 /* DNL set breakpoints data buffer structure (indirect 0x0686) */ 1702 struct ice_aqc_dnl_set_breakpoints { 1703 u8 ctx; 1704 u8 ena; /* 0- disabled, 1- enabled */ 1705 __le16 offset; 1706 __le16 activity_id; 1707 }; 1708 1709 /* DNL read log data command(indirect 0x0687) */ 1710 struct ice_aqc_dnl_read_log_command { 1711 __le16 reserved0; 1712 __le16 offset; 1713 __le32 reserved1; 1714 __le32 addr_high; 1715 __le32 addr_low; 1716 1717 }; 1718 1719 /* DNL read log data response(indirect 0x0687) */ 1720 struct ice_aqc_dnl_read_log_response { 1721 __le16 reserved; 1722 __le16 size; 1723 __le32 data; 1724 __le32 addr_high; 1725 __le32 addr_low; 1726 1727 }; 1728 1729 struct ice_aqc_link_topo_addr { 1730 u8 lport_num; 1731 u8 lport_num_valid; 1732 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 1733 u8 node_type_ctx; 1734 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 1735 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 1736 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 1737 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1738 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1739 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1740 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 1741 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 1742 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 1743 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 1744 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1745 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 1746 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 1747 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 1748 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 1749 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 1750 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 1751 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 1752 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 1753 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 1754 u8 index; 1755 __le16 handle; 1756 #define ICE_AQC_LINK_TOPO_HANDLE_S 0 1757 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 1758 /* Used to decode the handle field */ 1759 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1760 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 1761 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 1762 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 1763 /* In case of a Mezzanine type */ 1764 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1765 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1766 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 1767 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 1768 /* In case of a LOM type */ 1769 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 1770 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1771 }; 1772 1773 /* Get Link Topology Handle (direct, 0x06E0) */ 1774 struct ice_aqc_get_link_topo { 1775 struct ice_aqc_link_topo_addr addr; 1776 u8 node_part_num; 1777 u8 rsvd[9]; 1778 }; 1779 1780 /* Get Link Topology Pin (direct, 0x06E1) */ 1781 struct ice_aqc_get_link_topo_pin { 1782 struct ice_aqc_link_topo_addr addr; 1783 u8 input_io_params; 1784 #define ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_S 0 1785 #define ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_M \ 1786 (0x1F << ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_S) 1787 #define ICE_AQC_LINK_TOPO_IO_FUNC_GPIO 0 1788 #define ICE_AQC_LINK_TOPO_IO_FUNC_RESET_N 1 1789 #define ICE_AQC_LINK_TOPO_IO_FUNC_INT_N 2 1790 #define ICE_AQC_LINK_TOPO_IO_FUNC_PRESENT_N 3 1791 #define ICE_AQC_LINK_TOPO_IO_FUNC_TX_DIS 4 1792 #define ICE_AQC_LINK_TOPO_IO_FUNC_MODSEL_N 5 1793 #define ICE_AQC_LINK_TOPO_IO_FUNC_LPMODE 6 1794 #define ICE_AQC_LINK_TOPO_IO_FUNC_TX_FAULT 7 1795 #define ICE_AQC_LINK_TOPO_IO_FUNC_RX_LOSS 8 1796 #define ICE_AQC_LINK_TOPO_IO_FUNC_RS0 9 1797 #define ICE_AQC_LINK_TOPO_IO_FUNC_RS1 10 1798 #define ICE_AQC_LINK_TOPO_IO_FUNC_EEPROM_WP 11 1799 /* 12 repeats intentionally due to two different uses depending on context */ 1800 #define ICE_AQC_LINK_TOPO_IO_FUNC_LED 12 1801 #define ICE_AQC_LINK_TOPO_IO_FUNC_RED_LED 12 1802 #define ICE_AQC_LINK_TOPO_IO_FUNC_GREEN_LED 13 1803 #define ICE_AQC_LINK_TOPO_IO_FUNC_BLUE_LED 14 1804 #define ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S 5 1805 #define ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_M \ 1806 (0x7 << ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S) 1807 /* Use ICE_AQC_LINK_TOPO_NODE_TYPE_* for the type values */ 1808 u8 output_io_params; 1809 #define ICE_AQC_LINK_TOPO_OUTPUT_IO_FUNC_S 0 1810 #define ICE_AQC_LINK_TOPO_OUTPUT_IO_FUNC_M \ 1811 (0x1F << \ ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_NUM_S) 1812 /* Use ICE_AQC_LINK_TOPO_IO_FUNC_* for the non-numerical options */ 1813 #define ICE_AQC_LINK_TOPO_OUTPUT_IO_TYPE_S 5 1814 #define ICE_AQC_LINK_TOPO_OUTPUT_IO_TYPE_M \ 1815 (0x7 << ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S) 1816 /* Use ICE_AQC_LINK_TOPO_NODE_TYPE_* for the type values */ 1817 u8 output_io_flags; 1818 #define ICE_AQC_LINK_TOPO_OUTPUT_SPEED_S 0 1819 #define ICE_AQC_LINK_TOPO_OUTPUT_SPEED_M \ 1820 (0x7 << ICE_AQC_LINK_TOPO_OUTPUT_SPEED_S) 1821 #define ICE_AQC_LINK_TOPO_OUTPUT_INT_S 3 1822 #define ICE_AQC_LINK_TOPO_OUTPUT_INT_M \ 1823 (0x3 << ICE_AQC_LINK_TOPO_OUTPUT_INT_S) 1824 #define ICE_AQC_LINK_TOPO_OUTPUT_POLARITY BIT(5) 1825 #define ICE_AQC_LINK_TOPO_OUTPUT_VALUE BIT(6) 1826 #define ICE_AQC_LINK_TOPO_OUTPUT_DRIVEN BIT(7) 1827 u8 rsvd[7]; 1828 }; 1829 1830 /* Read/Write I2C (direct, 0x06E2/0x06E3) */ 1831 struct ice_aqc_i2c { 1832 struct ice_aqc_link_topo_addr topo_addr; 1833 __le16 i2c_addr; 1834 u8 i2c_params; 1835 #define ICE_AQC_I2C_DATA_SIZE_S 0 1836 #define ICE_AQC_I2C_DATA_SIZE_M (0xF << ICE_AQC_I2C_DATA_SIZE_S) 1837 #define ICE_AQC_I2C_ADDR_TYPE_M BIT(4) 1838 #define ICE_AQC_I2C_ADDR_TYPE_7BIT 0 1839 #define ICE_AQC_I2C_ADDR_TYPE_10BIT ICE_AQC_I2C_ADDR_TYPE_M 1840 #define ICE_AQC_I2C_DATA_OFFSET_S 5 1841 #define ICE_AQC_I2C_DATA_OFFSET_M (0x3 << ICE_AQC_I2C_DATA_OFFSET_S) 1842 #define ICE_AQC_I2C_USE_REPEATED_START BIT(7) 1843 u8 rsvd; 1844 __le16 i2c_bus_addr; 1845 #define ICE_AQC_I2C_ADDR_7BIT_MASK 0x7F 1846 #define ICE_AQC_I2C_ADDR_10BIT_MASK 0x3FF 1847 u8 i2c_data[4]; /* Used only by write command, reserved in read. */ 1848 }; 1849 1850 /* Read I2C Response (direct, 0x06E2) */ 1851 struct ice_aqc_read_i2c_resp { 1852 u8 i2c_data[16]; 1853 }; 1854 1855 /* Read/Write MDIO (direct, 0x06E4/0x06E5) */ 1856 struct ice_aqc_mdio { 1857 struct ice_aqc_link_topo_addr topo_addr; 1858 u8 mdio_device_addr; 1859 #define ICE_AQC_MDIO_DEV_S 0 1860 #define ICE_AQC_MDIO_DEV_M (0x1F << ICE_AQC_MDIO_DEV_S) 1861 #define ICE_AQC_MDIO_CLAUSE_22 BIT(5) 1862 #define ICE_AQC_MDIO_CLAUSE_45 BIT(6) 1863 u8 rsvd; 1864 __le16 offset; 1865 __le16 data; /* Input in write cmd, output in read cmd. */ 1866 u8 rsvd1[4]; 1867 }; 1868 1869 /* Set/Get GPIO By Function (direct, 0x06E6/0x06E7) */ 1870 struct ice_aqc_gpio_by_func { 1871 struct ice_aqc_link_topo_addr topo_addr; 1872 u8 io_func_num; 1873 #define ICE_AQC_GPIO_FUNC_S 0 1874 #define ICE_AQC_GPIO_FUNC_M (0x1F << ICE_AQC_GPIO_IO_FUNC_NUM_S) 1875 u8 io_value; /* Input in write cmd, output in read cmd. */ 1876 #define ICE_AQC_GPIO_ON BIT(0) 1877 #define ICE_AQC_GPIO_OFF 0 1878 u8 rsvd[8]; 1879 }; 1880 1881 /* Set LED (direct, 0x06E8) */ 1882 struct ice_aqc_set_led { 1883 struct ice_aqc_link_topo_addr topo_addr; 1884 u8 color_and_blink; 1885 #define ICE_AQC_LED_COLOR_S 0 1886 #define ICE_AQC_LED_COLOR_M (0x7 << ICE_AQC_LED_COLOR_S) 1887 #define ICE_AQC_LED_COLOR_SKIP 0 1888 #define ICE_AQC_LED_COLOR_RED 1 1889 #define ICE_AQC_LED_COLOR_ORANGE 2 1890 #define ICE_AQC_LED_COLOR_YELLOW 3 1891 #define ICE_AQC_LED_COLOR_GREEN 4 1892 #define ICE_AQC_LED_COLOR_BLUE 5 1893 #define ICE_AQC_LED_COLOR_PURPLE 6 1894 #define ICE_AQC_LED_BLINK_S 3 1895 #define ICE_AQC_LED_BLINK_M (0x7 << ICE_AQC_LED_BLINK_S) 1896 #define ICE_AQC_LED_BLINK_NONE 0 1897 #define ICE_AQC_LED_BLINK_SLOW 1 1898 #define ICE_AQC_LED_BLINK_SLOW_MAC 2 1899 #define ICE_AQC_LED_BLINK_SLOW_FLTR 3 1900 #define ICE_AQC_LED_BLINK_FAST 5 1901 #define ICE_AQC_LED_BLINK_FAST_MAC 6 1902 #define ICE_AQC_LED_BLINK_FAST_FLTR 7 1903 u8 rsvd[9]; 1904 }; 1905 1906 /* Set Port Identification LED (direct, 0x06E9) */ 1907 struct ice_aqc_set_port_id_led { 1908 u8 lport_num; 1909 u8 lport_num_valid; 1910 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0) 1911 u8 ident_mode; 1912 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 1913 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 1914 u8 rsvd[13]; 1915 }; 1916 1917 /* Get Port Options (indirect, 0x06EA) */ 1918 struct ice_aqc_get_port_options { 1919 u8 lport_num; 1920 u8 lport_num_valid; 1921 #define ICE_AQC_PORT_OPT_PORT_NUM_VALID BIT(0) 1922 u8 port_options_count; 1923 #define ICE_AQC_PORT_OPT_COUNT_S 0 1924 #define ICE_AQC_PORT_OPT_COUNT_M (0xF << ICE_AQC_PORT_OPT_COUNT_S) 1925 u8 innermost_phy_index; 1926 u8 port_options; 1927 #define ICE_AQC_PORT_OPT_ACTIVE_S 0 1928 #define ICE_AQC_PORT_OPT_ACTIVE_M (0xF << ICE_AQC_PORT_OPT_ACTIVE_S) 1929 #define ICE_AQC_PORT_OPT_FORCED BIT(6) 1930 #define ICE_AQC_PORT_OPT_VALID BIT(7) 1931 u8 rsvd[3]; 1932 __le32 addr_high; 1933 __le32 addr_low; 1934 }; 1935 1936 struct ice_aqc_get_port_options_elem { 1937 u8 pmd; 1938 #define ICE_AQC_PORT_INV_PORT_OPT 4 1939 #define ICE_AQC_PORT_OPT_PMD_COUNT_S 0 1940 #define ICE_AQC_PORT_OPT_PMD_COUNT_M (0xF << ICE_AQC_PORT_OPT_PMD_COUNT_S) 1941 #define ICE_AQC_PORT_OPT_PMD_WIDTH_S 4 1942 #define ICE_AQC_PORT_OPT_PMD_WIDTH_M (0xF << ICE_AQC_PORT_OPT_PMD_WIDTH_S) 1943 u8 max_lane_speed; 1944 #define ICE_AQC_PORT_OPT_MAX_LANE_S 0 1945 #define ICE_AQC_PORT_OPT_MAX_LANE_M (0xF << ICE_AQC_PORT_OPT_MAX_LANE_S) 1946 #define ICE_AQC_PORT_OPT_MAX_LANE_100M 0 1947 #define ICE_AQC_PORT_OPT_MAX_LANE_1G 1 1948 #define ICE_AQC_PORT_OPT_MAX_LANE_2500M 2 1949 #define ICE_AQC_PORT_OPT_MAX_LANE_5G 3 1950 #define ICE_AQC_PORT_OPT_MAX_LANE_10G 4 1951 #define ICE_AQC_PORT_OPT_MAX_LANE_25G 5 1952 #define ICE_AQC_PORT_OPT_MAX_LANE_50G 6 1953 #define ICE_AQC_PORT_OPT_MAX_LANE_100G 7 1954 u8 global_scid[2]; 1955 u8 phy_scid[2]; 1956 }; 1957 1958 /* Set Port Option (direct, 0x06EB) */ 1959 struct ice_aqc_set_port_option { 1960 u8 lport_num; 1961 u8 lport_num_valid; 1962 #define ICE_AQC_SET_PORT_OPT_PORT_NUM_VALID BIT(0) 1963 u8 selected_port_option; 1964 u8 rsvd[13]; 1965 }; 1966 1967 /* Set/Get GPIO (direct, 0x06EC/0x06ED) */ 1968 struct ice_aqc_gpio { 1969 __le16 gpio_ctrl_handle; 1970 #define ICE_AQC_GPIO_HANDLE_S 0 1971 #define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S) 1972 u8 gpio_num; 1973 u8 gpio_val; 1974 u8 rsvd[12]; 1975 }; 1976 1977 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 1978 struct ice_aqc_sff_eeprom { 1979 u8 lport_num; 1980 u8 lport_num_valid; 1981 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 1982 __le16 i2c_bus_addr; 1983 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 1984 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 1985 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 1986 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 1987 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 1988 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 1989 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 1990 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 1991 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 1992 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 1993 #define ICE_AQC_SFF_IS_WRITE BIT(15) 1994 __le16 i2c_mem_addr; 1995 __le16 eeprom_page; 1996 #define ICE_AQC_SFF_EEPROM_BANK_S 0 1997 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 1998 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 1999 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 2000 __le32 addr_high; 2001 __le32 addr_low; 2002 }; 2003 2004 /* NVM Read command (indirect 0x0701) 2005 * NVM Erase commands (direct 0x0702) 2006 * NVM Write commands (indirect 0x0703) 2007 * NVM Write Activate commands (direct 0x0707) 2008 * NVM Shadow RAM Dump commands (direct 0x0707) 2009 */ 2010 struct ice_aqc_nvm { 2011 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 2012 __le16 offset_low; 2013 u8 offset_high; /* For Write Activate offset_high is used as flags2 */ 2014 u8 cmd_flags; 2015 #define ICE_AQC_NVM_LAST_CMD BIT(0) 2016 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */ 2017 #define ICE_AQC_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */ 2018 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 2019 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 2020 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 2021 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 2022 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 2023 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 2024 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) 2025 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) 2026 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) 2027 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 2028 #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3) 2029 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 2030 __le16 module_typeid; 2031 __le16 length; 2032 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 2033 __le32 addr_high; 2034 __le32 addr_low; 2035 }; 2036 2037 /* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */ 2038 #define ICE_AQC_NVM_SECTOR_UNIT 4096 /* In Bytes */ 2039 #define ICE_AQC_NVM_WORD_UNIT 2 /* In Bytes */ 2040 2041 #define ICE_AQC_NVM_START_POINT 0 2042 #define ICE_AQC_NVM_EMP_SR_PTR_OFFSET 0x90 2043 #define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN 2 /* In Bytes */ 2044 #define ICE_AQC_NVM_EMP_SR_PTR_M MAKEMASK(0x7FFF, 0) 2045 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S 15 2046 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M BIT(15) 2047 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR 1 2048 2049 #define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET 0x46 2050 #define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN 2 /* In Bytes */ 2051 #define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */ 2052 2053 #define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129 2054 #define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */ 2055 #define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0) 2056 #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */ 2057 #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */ 2058 2059 /* The result of netlist NVM read comes in a TLV format. The actual data 2060 * (netlist header) starts from word offset 1 (byte 2). The FW strips 2061 * out the type field from the TLV header so all the netlist fields 2062 * should adjust their offset value by 1 word (2 bytes) in order to map 2063 * their correct location. 2064 */ 2065 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_MOD_ID 0x11B 2066 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN_OFFSET 1 2067 #define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN 2 /* In bytes */ 2068 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_OFFSET 2 2069 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_LEN 2 /* In bytes */ 2070 #define ICE_AQC_NVM_NETLIST_NODE_COUNT_M MAKEMASK(0x3FF, 0) 2071 #define ICE_AQC_NVM_NETLIST_ID_BLK_START_OFFSET 5 2072 #define ICE_AQC_NVM_NETLIST_ID_BLK_LEN 0x30 /* In words */ 2073 2074 /* netlist ID block field offsets (word offsets) */ 2075 #define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_LOW 2 2076 #define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_HIGH 3 2077 #define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_LOW 4 2078 #define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_HIGH 5 2079 #define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_LOW 6 2080 #define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_HIGH 7 2081 #define ICE_AQC_NVM_NETLIST_ID_BLK_REV_LOW 8 2082 #define ICE_AQC_NVM_NETLIST_ID_BLK_REV_HIGH 9 2083 #define ICE_AQC_NVM_NETLIST_ID_BLK_SHA_HASH 0xA 2084 #define ICE_AQC_NVM_NETLIST_ID_BLK_CUST_VER 0x2F 2085 2086 /* Used for 0x0704 as well as for 0x0705 commands */ 2087 struct ice_aqc_nvm_cfg { 2088 u8 cmd_flags; 2089 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0) 2090 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1) 2091 #define ICE_AQC_ANVM_NEW_CFG BIT(2) 2092 u8 reserved; 2093 __le16 count; 2094 __le16 id; 2095 u8 reserved1[2]; 2096 __le32 addr_high; 2097 __le32 addr_low; 2098 }; 2099 2100 struct ice_aqc_nvm_cfg_data { 2101 __le16 field_id; 2102 __le16 field_options; 2103 __le16 field_value; 2104 }; 2105 2106 /* NVM Checksum Command (direct, 0x0706) */ 2107 struct ice_aqc_nvm_checksum { 2108 u8 flags; 2109 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 2110 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 2111 u8 rsvd; 2112 __le16 checksum; /* Used only by response */ 2113 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 2114 u8 rsvd2[12]; 2115 }; 2116 2117 /** 2118 * Send to PF command (indirect 0x0801) ID is only used by PF 2119 * 2120 * Send to VF command (indirect 0x0802) ID is only used by PF 2121 * 2122 */ 2123 struct ice_aqc_pf_vf_msg { 2124 __le32 id; 2125 u32 reserved; 2126 __le32 addr_high; 2127 __le32 addr_low; 2128 }; 2129 2130 /* Write/Read Alternate - Direct (direct 0x0900/0x0902) */ 2131 struct ice_aqc_read_write_alt_direct { 2132 __le32 dword0_addr; 2133 __le32 dword0_value; 2134 __le32 dword1_addr; 2135 __le32 dword1_value; 2136 }; 2137 2138 /* Write/Read Alternate - Indirect (indirect 0x0901/0x0903) */ 2139 struct ice_aqc_read_write_alt_indirect { 2140 __le32 base_dword_addr; 2141 __le32 num_dwords; 2142 __le32 addr_high; 2143 __le32 addr_low; 2144 }; 2145 2146 /* Done Alternate Write (direct 0x0904) */ 2147 struct ice_aqc_done_alt_write { 2148 u8 flags; 2149 #define ICE_AQC_CMD_UEFI_BIOS_MODE BIT(0) 2150 #define ICE_AQC_RESP_RESET_NEEDED BIT(1) 2151 u8 reserved[15]; 2152 }; 2153 2154 /* Clear Port Alternate Write (direct 0x0906) */ 2155 struct ice_aqc_clear_port_alt_write { 2156 u8 reserved[16]; 2157 }; 2158 2159 /* Get LLDP MIB (indirect 0x0A00) 2160 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 2161 * as the format is the same. 2162 */ 2163 struct ice_aqc_lldp_get_mib { 2164 u8 type; 2165 #define ICE_AQ_LLDP_MIB_TYPE_S 0 2166 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 2167 #define ICE_AQ_LLDP_MIB_LOCAL 0 2168 #define ICE_AQ_LLDP_MIB_REMOTE 1 2169 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 2170 #define ICE_AQ_LLDP_BRID_TYPE_S 2 2171 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 2172 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 2173 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 2174 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 2175 #define ICE_AQ_LLDP_TX_S 0x4 2176 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 2177 #define ICE_AQ_LLDP_TX_ACTIVE 0 2178 #define ICE_AQ_LLDP_TX_SUSPENDED 1 2179 #define ICE_AQ_LLDP_TX_FLUSHED 3 2180 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 2181 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 2182 * Get LLDP MIB (0x0A00) response only. 2183 */ 2184 u8 reserved1; 2185 __le16 local_len; 2186 __le16 remote_len; 2187 u8 reserved2[2]; 2188 __le32 addr_high; 2189 __le32 addr_low; 2190 }; 2191 2192 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 2193 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 2194 struct ice_aqc_lldp_set_mib_change { 2195 u8 command; 2196 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2197 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 2198 u8 reserved[15]; 2199 }; 2200 2201 /* Add LLDP TLV (indirect 0x0A02) 2202 * Delete LLDP TLV (indirect 0x0A04) 2203 */ 2204 struct ice_aqc_lldp_add_delete_tlv { 2205 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2206 u8 reserved1[1]; 2207 __le16 len; 2208 u8 reserved2[4]; 2209 __le32 addr_high; 2210 __le32 addr_low; 2211 }; 2212 2213 /* Update LLDP TLV (indirect 0x0A03) */ 2214 struct ice_aqc_lldp_update_tlv { 2215 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2216 u8 reserved; 2217 __le16 old_len; 2218 __le16 new_offset; 2219 __le16 new_len; 2220 __le32 addr_high; 2221 __le32 addr_low; 2222 }; 2223 2224 /* Stop LLDP (direct 0x0A05) */ 2225 struct ice_aqc_lldp_stop { 2226 u8 command; 2227 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 2228 #define ICE_AQ_LLDP_AGENT_STOP 0x0 2229 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 2230 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 2231 u8 reserved[15]; 2232 }; 2233 2234 /* Start LLDP (direct 0x0A06) */ 2235 struct ice_aqc_lldp_start { 2236 u8 command; 2237 #define ICE_AQ_LLDP_AGENT_START BIT(0) 2238 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 2239 u8 reserved[15]; 2240 }; 2241 2242 /* Get CEE DCBX Oper Config (0x0A07) 2243 * The command uses the generic descriptor struct and 2244 * returns the struct below as an indirect response. 2245 */ 2246 struct ice_aqc_get_cee_dcb_cfg_resp { 2247 u8 oper_num_tc; 2248 u8 oper_prio_tc[4]; 2249 u8 oper_tc_bw[8]; 2250 u8 oper_pfc_en; 2251 __le16 oper_app_prio; 2252 #define ICE_AQC_CEE_APP_FCOE_S 0 2253 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 2254 #define ICE_AQC_CEE_APP_ISCSI_S 3 2255 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 2256 #define ICE_AQC_CEE_APP_FIP_S 8 2257 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 2258 __le32 tlv_status; 2259 #define ICE_AQC_CEE_PG_STATUS_S 0 2260 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 2261 #define ICE_AQC_CEE_PFC_STATUS_S 3 2262 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 2263 #define ICE_AQC_CEE_FCOE_STATUS_S 8 2264 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 2265 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 2266 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 2267 #define ICE_AQC_CEE_FIP_STATUS_S 16 2268 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 2269 u8 reserved[12]; 2270 }; 2271 2272 /* Set Local LLDP MIB (indirect 0x0A08) 2273 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 2274 */ 2275 struct ice_aqc_lldp_set_local_mib { 2276 u8 type; 2277 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 2278 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 2279 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 2280 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 2281 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 2282 u8 reserved0; 2283 __le16 length; 2284 u8 reserved1[4]; 2285 __le32 addr_high; 2286 __le32 addr_low; 2287 }; 2288 2289 struct ice_aqc_lldp_set_local_mib_resp { 2290 u8 status; 2291 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0) 2292 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0 2293 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT SET_LOCAL_MIB_RESP_EVENT_M 2294 u8 reserved[15]; 2295 }; 2296 2297 /* Stop/Start LLDP Agent (direct 0x0A09) 2298 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 2299 * The same structure is used for the response, with the command field 2300 * being used as the status field. 2301 */ 2302 struct ice_aqc_lldp_stop_start_specific_agent { 2303 u8 command; 2304 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 2305 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 2306 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 2307 u8 reserved[15]; 2308 }; 2309 2310 /* LLDP Filter Control (direct 0x0A0A) */ 2311 struct ice_aqc_lldp_filter_ctrl { 2312 u8 cmd_flags; 2313 #define ICE_AQC_LLDP_FILTER_ACTION_M MAKEMASK(3, 0) 2314 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0 2315 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1 2316 #define ICE_AQC_LLDP_FILTER_ACTION_UPDATE 0x2 2317 u8 reserved1; 2318 __le16 vsi_num; 2319 u8 reserved2[12]; 2320 }; 2321 2322 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 2323 struct ice_aqc_get_set_rss_key { 2324 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 2325 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 2326 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 2327 __le16 vsi_id; 2328 u8 reserved[6]; 2329 __le32 addr_high; 2330 __le32 addr_low; 2331 }; 2332 2333 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 2334 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 2335 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 2336 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 2337 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 2338 2339 /** 2340 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer 2341 * @standard_rss_key: 40 most significant bytes of hash key 2342 * @extended_hash_key: 12 least significant bytes of hash key 2343 * 2344 * Set/Get 40 byte hash key using standard_rss_key field, and set 2345 * extended_hash_key field to zero. Set/Get 52 byte hash key using 2346 * standard_rss_key field for 40 most significant bytes and the 2347 * extended_hash_key field for the 12 least significant bytes of hash key. 2348 */ 2349 struct ice_aqc_get_set_rss_keys { 2350 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 2351 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 2352 }; 2353 2354 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 2355 struct ice_aqc_get_set_rss_lut { 2356 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 2357 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 2358 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 2359 __le16 vsi_id; 2360 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 2361 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 2362 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 2363 2364 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0 2365 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1 2366 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2 2367 2368 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 2369 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 2370 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 2371 2372 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128 2373 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0 2374 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512 2375 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 2376 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048 2377 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 2378 2379 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 2380 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 2381 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 2382 2383 __le16 flags; 2384 __le32 reserved; 2385 __le32 addr_high; 2386 __le32 addr_low; 2387 }; 2388 2389 /* Add Tx LAN Queues (indirect 0x0C30) */ 2390 struct ice_aqc_add_txqs { 2391 u8 num_qgrps; 2392 u8 reserved[3]; 2393 __le32 reserved1; 2394 __le32 addr_high; 2395 __le32 addr_low; 2396 }; 2397 2398 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 2399 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 2400 */ 2401 struct ice_aqc_add_txqs_perq { 2402 __le16 txq_id; 2403 u8 rsvd[2]; 2404 __le32 q_teid; 2405 u8 txq_ctx[22]; 2406 u8 rsvd2[2]; 2407 struct ice_aqc_txsched_elem info; 2408 }; 2409 2410 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 2411 * is an array of the following structs. Please note that the length of 2412 * each struct ice_aqc_add_tx_qgrp is variable due 2413 * to the variable number of queues in each group! 2414 */ 2415 struct ice_aqc_add_tx_qgrp { 2416 __le32 parent_teid; 2417 u8 num_txqs; 2418 u8 rsvd[3]; 2419 struct ice_aqc_add_txqs_perq txqs[STRUCT_HACK_VAR_LEN]; 2420 }; 2421 2422 /* Disable Tx LAN Queues (indirect 0x0C31) */ 2423 struct ice_aqc_dis_txqs { 2424 u8 cmd_type; 2425 #define ICE_AQC_Q_DIS_CMD_S 0 2426 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 2427 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 2428 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 2429 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 2430 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 2431 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 2432 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 2433 u8 num_entries; 2434 __le16 vmvf_and_timeout; 2435 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 2436 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 2437 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 2438 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 2439 __le32 blocked_cgds; 2440 __le32 addr_high; 2441 __le32 addr_low; 2442 }; 2443 2444 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 2445 * contains the following structures, arrayed one after the 2446 * other. 2447 * Note: Since the q_id is 16 bits wide, if the 2448 * number of queues is even, then 2 bytes of alignment MUST be 2449 * added before the start of the next group, to allow correct 2450 * alignment of the parent_teid field. 2451 */ 2452 #pragma pack(1) 2453 struct ice_aqc_dis_txq_item { 2454 __le32 parent_teid; 2455 u8 num_qs; 2456 u8 rsvd; 2457 /* The length of the q_id array varies according to num_qs */ 2458 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 2459 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 2460 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2461 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 2462 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2463 __le16 q_id[STRUCT_HACK_VAR_LEN]; 2464 }; 2465 #pragma pack() 2466 2467 /* Tx LAN Queues Cleanup Event (0x0C31) */ 2468 struct ice_aqc_txqs_cleanup { 2469 __le16 caller_opc; 2470 __le16 cmd_tag; 2471 u8 reserved[12]; 2472 }; 2473 2474 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */ 2475 struct ice_aqc_move_txqs { 2476 u8 cmd_type; 2477 #define ICE_AQC_Q_CMD_TYPE_S 0 2478 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S) 2479 #define ICE_AQC_Q_CMD_TYPE_MOVE 1 2480 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2 2481 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3 2482 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2) 2483 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3) 2484 u8 num_qs; 2485 u8 rsvd; 2486 u8 timeout; 2487 #define ICE_AQC_Q_CMD_TIMEOUT_S 2 2488 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S) 2489 __le32 blocked_cgds; 2490 __le32 addr_high; 2491 __le32 addr_low; 2492 }; 2493 2494 /* Per-queue data buffer for the Move Tx LAN Queues command/response */ 2495 struct ice_aqc_move_txqs_elem { 2496 __le16 txq_id; 2497 u8 q_cgd; 2498 u8 rsvd; 2499 __le32 q_teid; 2500 }; 2501 2502 /* Indirect data buffer for the Move Tx LAN Queues command/response */ 2503 struct ice_aqc_move_txqs_data { 2504 __le32 src_teid; 2505 __le32 dest_teid; 2506 struct ice_aqc_move_txqs_elem txqs[STRUCT_HACK_VAR_LEN]; 2507 }; 2508 2509 /* Download Package (indirect 0x0C40) */ 2510 /* Also used for Update Package (indirect 0x0C42 and 0x0C41) */ 2511 struct ice_aqc_download_pkg { 2512 u8 flags; 2513 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 2514 u8 reserved[3]; 2515 __le32 reserved1; 2516 __le32 addr_high; 2517 __le32 addr_low; 2518 }; 2519 2520 struct ice_aqc_download_pkg_resp { 2521 __le32 error_offset; 2522 __le32 error_info; 2523 __le32 addr_high; 2524 __le32 addr_low; 2525 }; 2526 2527 /* Get Package Info List (indirect 0x0C43) */ 2528 struct ice_aqc_get_pkg_info_list { 2529 __le32 reserved1; 2530 __le32 reserved2; 2531 __le32 addr_high; 2532 __le32 addr_low; 2533 }; 2534 2535 /* Version format for packages */ 2536 struct ice_pkg_ver { 2537 u8 major; 2538 u8 minor; 2539 u8 update; 2540 u8 draft; 2541 }; 2542 2543 #define ICE_PKG_NAME_SIZE 32 2544 #define ICE_SEG_NAME_SIZE 28 2545 2546 struct ice_aqc_get_pkg_info { 2547 struct ice_pkg_ver ver; 2548 char name[ICE_SEG_NAME_SIZE]; 2549 __le32 track_id; 2550 u8 is_in_nvm; 2551 u8 is_active; 2552 u8 is_active_at_boot; 2553 u8 is_modified; 2554 }; 2555 2556 /* Get Package Info List response buffer format (0x0C43) */ 2557 struct ice_aqc_get_pkg_info_resp { 2558 __le32 count; 2559 struct ice_aqc_get_pkg_info pkg_info[STRUCT_HACK_VAR_LEN]; 2560 }; 2561 2562 /* Driver Shared Parameters (direct, 0x0C90) */ 2563 struct ice_aqc_driver_shared_params { 2564 u8 set_or_get_op; 2565 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0) 2566 #define ICE_AQC_DRIVER_PARAM_SET 0 2567 #define ICE_AQC_DRIVER_PARAM_GET 1 2568 u8 param_indx; 2569 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15 2570 u8 rsvd[2]; 2571 __le32 param_val; 2572 __le32 addr_high; 2573 __le32 addr_low; 2574 }; 2575 2576 /* Lan Queue Overflow Event (direct, 0x1001) */ 2577 struct ice_aqc_event_lan_overflow { 2578 __le32 prtdcb_ruptq; 2579 __le32 qtx_ctl; 2580 u8 reserved[8]; 2581 }; 2582 2583 /* Set Health Status (direct 0xFF20) */ 2584 struct ice_aqc_set_health_status_config { 2585 u8 event_source; 2586 #define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0) 2587 #define ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1) 2588 #define ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2) 2589 u8 reserved[15]; 2590 }; 2591 2592 /* Get Health Status codes (indirect 0xFF21) */ 2593 struct ice_aqc_get_supported_health_status_codes { 2594 __le16 health_code_count; 2595 u8 reserved[6]; 2596 __le32 addr_high; 2597 __le32 addr_low; 2598 }; 2599 2600 /* Get Health Status (indirect 0xFF22) */ 2601 struct ice_aqc_get_health_status { 2602 __le16 health_status_count; 2603 u8 reserved[6]; 2604 __le32 addr_high; 2605 __le32 addr_low; 2606 }; 2607 2608 /* Get Health Status event buffer entry, (0xFF22) 2609 * repeated per reported health status 2610 */ 2611 struct ice_aqc_health_status_elem { 2612 __le16 health_status_code; 2613 __le16 event_source; 2614 #define ICE_AQC_HEALTH_STATUS_PF (0x1) 2615 #define ICE_AQC_HEALTH_STATUS_PORT (0x2) 2616 #define ICE_AQC_HEALTH_STATUS_GLOBAL (0x3) 2617 __le32 internal_data1; 2618 #define ICE_AQC_HEALTH_STATUS_UNDEFINED_DATA (0xDEADBEEF) 2619 __le32 internal_data2; 2620 }; 2621 2622 /* Clear Health Status (direct 0xFF23) */ 2623 struct ice_aqc_clear_health_status { 2624 __le32 reserved[4]; 2625 }; 2626 2627 /** 2628 * struct ice_aq_desc - Admin Queue (AQ) descriptor 2629 * @flags: ICE_AQ_FLAG_* flags 2630 * @opcode: AQ command opcode 2631 * @datalen: length in bytes of indirect/external data buffer 2632 * @retval: return value from firmware 2633 * @cookie_h: opaque data high-half 2634 * @cookie_l: opaque data low-half 2635 * @params: command-specific parameters 2636 * 2637 * Descriptor format for commands the driver posts on the Admin Transmit Queue 2638 * (ATQ). The firmware writes back onto the command descriptor and returns 2639 * the result of the command. Asynchronous events that are not an immediate 2640 * result of the command are written to the Admin Receive Queue (ARQ) using 2641 * the same descriptor format. Descriptors are in little-endian notation with 2642 * 32-bit words. 2643 */ 2644 struct ice_aq_desc { 2645 __le16 flags; 2646 __le16 opcode; 2647 __le16 datalen; 2648 __le16 retval; 2649 __le32 cookie_high; 2650 __le32 cookie_low; 2651 union { 2652 u8 raw[16]; 2653 struct ice_aqc_generic generic; 2654 struct ice_aqc_get_ver get_ver; 2655 struct ice_aqc_driver_ver driver_ver; 2656 struct ice_aqc_q_shutdown q_shutdown; 2657 struct ice_aqc_get_exp_err exp_err; 2658 struct ice_aqc_req_res res_owner; 2659 struct ice_aqc_manage_mac_read mac_read; 2660 struct ice_aqc_manage_mac_write mac_write; 2661 struct ice_aqc_clear_pxe clear_pxe; 2662 struct ice_aqc_config_no_drop_policy no_drop; 2663 struct ice_aqc_add_update_mir_rule add_update_rule; 2664 struct ice_aqc_delete_mir_rule del_rule; 2665 struct ice_aqc_list_caps get_cap; 2666 struct ice_aqc_get_phy_caps get_phy; 2667 struct ice_aqc_set_phy_cfg set_phy; 2668 struct ice_aqc_restart_an restart_an; 2669 struct ice_aqc_dnl_get_status get_status; 2670 struct ice_aqc_dnl_run_command dnl_run; 2671 struct ice_aqc_dnl_call_command dnl_call; 2672 struct ice_aqc_dnl_read_write_command dnl_read_write; 2673 struct ice_aqc_dnl_read_write_response dnl_read_write_resp; 2674 struct ice_aqc_dnl_set_breakpoints_command dnl_set_brk; 2675 struct ice_aqc_dnl_read_log_command dnl_read_log; 2676 struct ice_aqc_dnl_read_log_response dnl_read_log_resp; 2677 struct ice_aqc_i2c read_write_i2c; 2678 struct ice_aqc_mdio read_write_mdio; 2679 struct ice_aqc_gpio_by_func read_write_gpio_by_func; 2680 struct ice_aqc_gpio read_write_gpio; 2681 struct ice_aqc_set_led set_led; 2682 struct ice_aqc_sff_eeprom read_write_sff_param; 2683 struct ice_aqc_set_port_id_led set_port_id_led; 2684 struct ice_aqc_get_port_options get_port_options; 2685 struct ice_aqc_set_port_option set_port_option; 2686 struct ice_aqc_get_sw_cfg get_sw_conf; 2687 struct ice_aqc_set_port_params set_port_params; 2688 struct ice_aqc_sw_rules sw_rules; 2689 struct ice_aqc_storm_cfg storm_conf; 2690 struct ice_aqc_get_topo get_topo; 2691 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 2692 struct ice_aqc_query_txsched_res query_sched_res; 2693 struct ice_aqc_query_node_to_root query_node_to_root; 2694 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd; 2695 struct ice_aqc_query_port_ets port_ets; 2696 struct ice_aqc_rl_profile rl_profile; 2697 struct ice_aqc_nvm nvm; 2698 struct ice_aqc_nvm_cfg nvm_cfg; 2699 struct ice_aqc_nvm_checksum nvm_checksum; 2700 struct ice_aqc_pf_vf_msg virt; 2701 struct ice_aqc_read_write_alt_direct read_write_alt_direct; 2702 struct ice_aqc_read_write_alt_indirect read_write_alt_indirect; 2703 struct ice_aqc_done_alt_write done_alt_write; 2704 struct ice_aqc_clear_port_alt_write clear_port_alt_write; 2705 struct ice_aqc_pfc_ignore pfc_ignore; 2706 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode; 2707 struct ice_aqc_set_dcb_params set_dcb_params; 2708 struct ice_aqc_lldp_get_mib lldp_get_mib; 2709 struct ice_aqc_lldp_set_mib_change lldp_set_event; 2710 struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv; 2711 struct ice_aqc_lldp_update_tlv lldp_update_tlv; 2712 struct ice_aqc_lldp_stop lldp_stop; 2713 struct ice_aqc_lldp_start lldp_start; 2714 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 2715 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 2716 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl; 2717 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 2718 struct ice_aqc_get_set_rss_key get_set_rss_key; 2719 struct ice_aqc_add_txqs add_txqs; 2720 struct ice_aqc_dis_txqs dis_txqs; 2721 struct ice_aqc_move_txqs move_txqs; 2722 struct ice_aqc_txqs_cleanup txqs_cleanup; 2723 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 2724 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 2725 struct ice_aqc_get_vsi_resp get_vsi_resp; 2726 struct ice_aqc_download_pkg download_pkg; 2727 struct ice_aqc_get_pkg_info_list get_pkg_info_list; 2728 struct ice_aqc_driver_shared_params drv_shared_params; 2729 struct ice_aqc_set_mac_lb set_mac_lb; 2730 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 2731 struct ice_aqc_get_res_alloc get_res; 2732 struct ice_aqc_get_allocd_res_desc get_res_desc; 2733 struct ice_aqc_set_mac_cfg set_mac_cfg; 2734 struct ice_aqc_set_event_mask set_event_mask; 2735 struct ice_aqc_get_link_status get_link_status; 2736 struct ice_aqc_event_lan_overflow lan_overflow; 2737 struct ice_aqc_get_link_topo get_link_topo; 2738 struct ice_aqc_set_health_status_config 2739 set_health_status_config; 2740 struct ice_aqc_get_supported_health_status_codes 2741 get_supported_health_status_codes; 2742 struct ice_aqc_get_health_status get_health_status; 2743 struct ice_aqc_clear_health_status clear_health_status; 2744 } params; 2745 }; 2746 2747 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 2748 #define ICE_AQ_LG_BUF 512 2749 2750 /* Flags sub-structure 2751 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 2752 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 2753 */ 2754 2755 /* command flags and offsets */ 2756 #define ICE_AQ_FLAG_DD_S 0 2757 #define ICE_AQ_FLAG_CMP_S 1 2758 #define ICE_AQ_FLAG_ERR_S 2 2759 #define ICE_AQ_FLAG_VFE_S 3 2760 #define ICE_AQ_FLAG_LB_S 9 2761 #define ICE_AQ_FLAG_RD_S 10 2762 #define ICE_AQ_FLAG_VFC_S 11 2763 #define ICE_AQ_FLAG_BUF_S 12 2764 #define ICE_AQ_FLAG_SI_S 13 2765 #define ICE_AQ_FLAG_EI_S 14 2766 #define ICE_AQ_FLAG_FE_S 15 2767 2768 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */ 2769 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */ 2770 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 2771 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */ 2772 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 2773 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 2774 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */ 2775 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 2776 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 2777 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */ 2778 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */ 2779 2780 /* error codes */ 2781 enum ice_aq_err { 2782 ICE_AQ_RC_OK = 0, /* Success */ 2783 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 2784 ICE_AQ_RC_ENOENT = 2, /* No such element */ 2785 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */ 2786 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */ 2787 ICE_AQ_RC_EIO = 5, /* I/O error */ 2788 ICE_AQ_RC_ENXIO = 6, /* No such resource */ 2789 ICE_AQ_RC_E2BIG = 7, /* Arg too long */ 2790 ICE_AQ_RC_EAGAIN = 8, /* Try again */ 2791 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 2792 ICE_AQ_RC_EACCES = 10, /* Permission denied */ 2793 ICE_AQ_RC_EFAULT = 11, /* Bad address */ 2794 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 2795 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 2796 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 2797 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 2798 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 2799 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 2800 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */ 2801 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 2802 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 2803 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 2804 ICE_AQ_RC_EFBIG = 22, /* File too big */ 2805 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */ 2806 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 2807 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 2808 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 2809 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 2810 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 2811 ICE_AQ_RC_EACCES_BMCU = 29, /* BMC Update in progress */ 2812 }; 2813 2814 /* Admin Queue command opcodes */ 2815 enum ice_adminq_opc { 2816 /* AQ commands */ 2817 ice_aqc_opc_get_ver = 0x0001, 2818 ice_aqc_opc_driver_ver = 0x0002, 2819 ice_aqc_opc_q_shutdown = 0x0003, 2820 ice_aqc_opc_get_exp_err = 0x0005, 2821 2822 /* resource ownership */ 2823 ice_aqc_opc_req_res = 0x0008, 2824 ice_aqc_opc_release_res = 0x0009, 2825 2826 /* device/function capabilities */ 2827 ice_aqc_opc_list_func_caps = 0x000A, 2828 ice_aqc_opc_list_dev_caps = 0x000B, 2829 2830 /* manage MAC address */ 2831 ice_aqc_opc_manage_mac_read = 0x0107, 2832 ice_aqc_opc_manage_mac_write = 0x0108, 2833 2834 /* PXE */ 2835 ice_aqc_opc_clear_pxe_mode = 0x0110, 2836 2837 ice_aqc_opc_config_no_drop_policy = 0x0112, 2838 2839 /* internal switch commands */ 2840 ice_aqc_opc_get_sw_cfg = 0x0200, 2841 ice_aqc_opc_set_port_params = 0x0203, 2842 2843 /* Alloc/Free/Get Resources */ 2844 ice_aqc_opc_get_res_alloc = 0x0204, 2845 ice_aqc_opc_alloc_res = 0x0208, 2846 ice_aqc_opc_free_res = 0x0209, 2847 ice_aqc_opc_get_allocd_res_desc = 0x020A, 2848 2849 /* VSI commands */ 2850 ice_aqc_opc_add_vsi = 0x0210, 2851 ice_aqc_opc_update_vsi = 0x0211, 2852 ice_aqc_opc_get_vsi_params = 0x0212, 2853 ice_aqc_opc_free_vsi = 0x0213, 2854 2855 /* Mirroring rules - add/update, delete */ 2856 ice_aqc_opc_add_update_mir_rule = 0x0260, 2857 ice_aqc_opc_del_mir_rule = 0x0261, 2858 2859 /* storm configuration */ 2860 ice_aqc_opc_set_storm_cfg = 0x0280, 2861 ice_aqc_opc_get_storm_cfg = 0x0281, 2862 2863 /* switch rules population commands */ 2864 ice_aqc_opc_add_sw_rules = 0x02A0, 2865 ice_aqc_opc_update_sw_rules = 0x02A1, 2866 ice_aqc_opc_remove_sw_rules = 0x02A2, 2867 ice_aqc_opc_get_sw_rules = 0x02A3, 2868 ice_aqc_opc_clear_pf_cfg = 0x02A4, 2869 2870 /* DCB commands */ 2871 ice_aqc_opc_pfc_ignore = 0x0301, 2872 ice_aqc_opc_query_pfc_mode = 0x0302, 2873 ice_aqc_opc_set_pfc_mode = 0x0303, 2874 ice_aqc_opc_set_dcb_params = 0x0306, 2875 2876 /* transmit scheduler commands */ 2877 ice_aqc_opc_get_dflt_topo = 0x0400, 2878 ice_aqc_opc_add_sched_elems = 0x0401, 2879 ice_aqc_opc_cfg_sched_elems = 0x0403, 2880 ice_aqc_opc_get_sched_elems = 0x0404, 2881 ice_aqc_opc_move_sched_elems = 0x0408, 2882 ice_aqc_opc_suspend_sched_elems = 0x0409, 2883 ice_aqc_opc_resume_sched_elems = 0x040A, 2884 ice_aqc_opc_query_port_ets = 0x040E, 2885 ice_aqc_opc_delete_sched_elems = 0x040F, 2886 ice_aqc_opc_add_rl_profiles = 0x0410, 2887 ice_aqc_opc_query_rl_profiles = 0x0411, 2888 ice_aqc_opc_query_sched_res = 0x0412, 2889 ice_aqc_opc_query_node_to_root = 0x0413, 2890 ice_aqc_opc_cfg_l2_node_cgd = 0x0414, 2891 ice_aqc_opc_remove_rl_profiles = 0x0415, 2892 2893 /* PHY commands */ 2894 ice_aqc_opc_get_phy_caps = 0x0600, 2895 ice_aqc_opc_set_phy_cfg = 0x0601, 2896 ice_aqc_opc_set_mac_cfg = 0x0603, 2897 ice_aqc_opc_restart_an = 0x0605, 2898 ice_aqc_opc_get_link_status = 0x0607, 2899 ice_aqc_opc_set_event_mask = 0x0613, 2900 ice_aqc_opc_set_mac_lb = 0x0620, 2901 ice_aqc_opc_dnl_get_status = 0x0680, 2902 ice_aqc_opc_dnl_run = 0x0681, 2903 ice_aqc_opc_dnl_call = 0x0682, 2904 ice_aqc_opc_dnl_read_sto = 0x0683, 2905 ice_aqc_opc_dnl_write_sto = 0x0684, 2906 ice_aqc_opc_dnl_set_breakpoints = 0x0686, 2907 ice_aqc_opc_dnl_read_log = 0x0687, 2908 ice_aqc_opc_get_link_topo = 0x06E0, 2909 ice_aqc_opc_get_link_topo_pin = 0x06E1, 2910 ice_aqc_opc_read_i2c = 0x06E2, 2911 ice_aqc_opc_write_i2c = 0x06E3, 2912 ice_aqc_opc_read_mdio = 0x06E4, 2913 ice_aqc_opc_write_mdio = 0x06E5, 2914 ice_aqc_opc_set_gpio_by_func = 0x06E6, 2915 ice_aqc_opc_get_gpio_by_func = 0x06E7, 2916 ice_aqc_opc_set_led = 0x06E8, 2917 ice_aqc_opc_set_port_id_led = 0x06E9, 2918 ice_aqc_opc_get_port_options = 0x06EA, 2919 ice_aqc_opc_set_port_option = 0x06EB, 2920 ice_aqc_opc_set_gpio = 0x06EC, 2921 ice_aqc_opc_get_gpio = 0x06ED, 2922 ice_aqc_opc_sff_eeprom = 0x06EE, 2923 2924 /* NVM commands */ 2925 ice_aqc_opc_nvm_read = 0x0701, 2926 ice_aqc_opc_nvm_erase = 0x0702, 2927 ice_aqc_opc_nvm_write = 0x0703, 2928 ice_aqc_opc_nvm_cfg_read = 0x0704, 2929 ice_aqc_opc_nvm_cfg_write = 0x0705, 2930 ice_aqc_opc_nvm_checksum = 0x0706, 2931 ice_aqc_opc_nvm_write_activate = 0x0707, 2932 ice_aqc_opc_nvm_sr_dump = 0x0707, 2933 ice_aqc_opc_nvm_save_factory_settings = 0x0708, 2934 ice_aqc_opc_nvm_update_empr = 0x0709, 2935 ice_aqc_opc_nvm_pkg_data = 0x070A, 2936 ice_aqc_opc_nvm_pass_component_tbl = 0x070B, 2937 2938 /* PF/VF mailbox commands */ 2939 ice_mbx_opc_send_msg_to_pf = 0x0801, 2940 ice_mbx_opc_send_msg_to_vf = 0x0802, 2941 /* Alternate Structure Commands */ 2942 ice_aqc_opc_write_alt_direct = 0x0900, 2943 ice_aqc_opc_write_alt_indirect = 0x0901, 2944 ice_aqc_opc_read_alt_direct = 0x0902, 2945 ice_aqc_opc_read_alt_indirect = 0x0903, 2946 ice_aqc_opc_done_alt_write = 0x0904, 2947 ice_aqc_opc_clear_port_alt_write = 0x0906, 2948 /* LLDP commands */ 2949 ice_aqc_opc_lldp_get_mib = 0x0A00, 2950 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 2951 ice_aqc_opc_lldp_add_tlv = 0x0A02, 2952 ice_aqc_opc_lldp_update_tlv = 0x0A03, 2953 ice_aqc_opc_lldp_delete_tlv = 0x0A04, 2954 ice_aqc_opc_lldp_stop = 0x0A05, 2955 ice_aqc_opc_lldp_start = 0x0A06, 2956 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 2957 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 2958 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 2959 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A, 2960 2961 /* RSS commands */ 2962 ice_aqc_opc_set_rss_key = 0x0B02, 2963 ice_aqc_opc_set_rss_lut = 0x0B03, 2964 ice_aqc_opc_get_rss_key = 0x0B04, 2965 ice_aqc_opc_get_rss_lut = 0x0B05, 2966 2967 /* Tx queue handling commands/events */ 2968 ice_aqc_opc_add_txqs = 0x0C30, 2969 ice_aqc_opc_dis_txqs = 0x0C31, 2970 ice_aqc_opc_txqs_cleanup = 0x0C31, 2971 ice_aqc_opc_move_recfg_txqs = 0x0C32, 2972 2973 /* package commands */ 2974 ice_aqc_opc_download_pkg = 0x0C40, 2975 ice_aqc_opc_upload_section = 0x0C41, 2976 ice_aqc_opc_update_pkg = 0x0C42, 2977 ice_aqc_opc_get_pkg_info_list = 0x0C43, 2978 2979 ice_aqc_opc_driver_shared_params = 0x0C90, 2980 2981 /* Standalone Commands/Events */ 2982 ice_aqc_opc_event_lan_overflow = 0x1001, 2983 2984 /* SystemDiagnostic commands */ 2985 ice_aqc_opc_set_health_status_config = 0xFF20, 2986 ice_aqc_opc_get_supported_health_status_codes = 0xFF21, 2987 ice_aqc_opc_get_health_status = 0xFF22, 2988 ice_aqc_opc_clear_health_status = 0xFF23 2989 }; 2990 2991 #endif /* _ICE_ADMINQ_CMD_H_ */ 2992